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| author | Bin Meng <bmeng@tinylab.org> | 2023-06-27 09:24:56 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-06-27 10:09:51 +0800 |
| commit | 4a3efd71cd858b87527e9478ff51529d39329819 (patch) | |
| tree | d18d6192b5d60e176e98fd2acefbfb580d5bcf1e | |
| parent | 217b6373b57ce815b79f05dddd3203984994ad96 (diff) | |
| download | u-boot-4a3efd71cd858b87527e9478ff51529d39329819.zip u-boot-4a3efd71cd858b87527e9478ff51529d39329819.tar.gz u-boot-4a3efd71cd858b87527e9478ff51529d39329819.tar.bz2 | |
riscv: Fix alignment of RELA sections in the linker scripts
In current linker script both .efi_runtime_rel and .rela.dyn sections
are of RELA type whose entry size is either 12 (RV32) or 24 (RV64).
These two are arranged as a continuous region on purpose so that the
prelink-riscv executable can fix up the PIE addresses in one loop.
However there is an 'ALIGN(8)' between these 2 sections which might
cause a gap to be inserted between these 2 sections to satisfy the
alignment requirement on RV32. This would break the assumption of
the prelink process and generate an unbootable image.
Fixes: 9a6569a043d3 ("riscv: Update alignment for some sections in linker scripts")
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Rick Chen <rick@andestech.com>
| -rw-r--r-- | arch/riscv/cpu/u-boot.lds | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index 15b5cbc..2ffe6ba 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -48,7 +48,7 @@ SECTIONS KEEP(*(SORT(__u_boot_list*))); } - . = ALIGN(4); + . = ALIGN(8); .efi_runtime_rel : { __efi_runtime_rel_start = .; @@ -57,8 +57,6 @@ SECTIONS __efi_runtime_rel_stop = .; } - . = ALIGN(8); - /DISCARD/ : { *(.rela.plt*) } .rela.dyn : { __rel_dyn_start = .; |