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authorBin Meng <bmeng.cn@gmail.com>2021-08-07 13:00:02 +0800
committerStefan Roese <sr@denx.de>2021-08-11 10:36:10 +0200
commitd248627f9d4218688e7430bc714405a23885abfa (patch)
treef02fdc81d46d7a088da53526377c873ef1e48c57
parent74773a4f85221dceccbe92b0b3ae6daef75a141c (diff)
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riscv: qemu: Enable MTD NOR flash support
Enable support to the 2 NOR flashes on the QEMU RISC-V virt machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
-rw-r--r--board/emulation/qemu-riscv/Kconfig2
-rw-r--r--include/configs/qemu-riscv.h2
2 files changed, 4 insertions, 0 deletions
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 0818048..a7de82d 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -64,5 +64,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
imply VIRTIO_PCI
imply VIRTIO_NET
imply VIRTIO_BLK
+ imply MTD_NOR_FLASH
+ imply CFI_FLASH
endif
diff --git a/include/configs/qemu-riscv.h b/include/configs/qemu-riscv.h
index 5291de8..bbeea96 100644
--- a/include/configs/qemu-riscv.h
+++ b/include/configs/qemu-riscv.h
@@ -29,6 +29,8 @@
#define CONFIG_STANDALONE_LOAD_ADDR 0x80200000
+#define CONFIG_SYS_MAX_FLASH_BANKS 2
+
#define RISCV_MMODE_TIMERBASE 0x2000000
#define RISCV_MMODE_TIMER_FREQ 1000000