diff options
| author | Tom Rini <trini@konsulko.com> | 2023-07-10 14:29:14 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-07-10 14:29:14 -0400 |
| commit | 146a82c017d51eb2c3b8be33854f200f1e52a1cb (patch) | |
| tree | c2bb134d105bcc9855e6c39ac5b422e5416735ff | |
| parent | 05aa6516c6bb419d01d69fac457c0de563bfd694 (diff) | |
| parent | 76c61f29d63163d178b1584ecc9fc2c96c538ff0 (diff) | |
| download | u-boot-WIP/10Jul2023.zip u-boot-WIP/10Jul2023.tar.gz u-boot-WIP/10Jul2023.tar.bz2 | |
Merge branch 'next'WIP/10Jul2023
632 files changed, 17423 insertions, 15611 deletions
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml index 96b2ab4..06c46b6 100644 --- a/.azure-pipelines.yml +++ b/.azure-pipelines.yml @@ -391,12 +391,12 @@ stages: grub-mkimage --prefix=\"\" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd grub-mkimage --prefix=\"\" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi # the below corresponds to .gitlab-ci.yml "script" cd ${WORK_DIR} diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index e6c6ab3..cfd5851 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -29,12 +29,12 @@ stages: - grub-mkimage --prefix="" -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage --prefix="" -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - if [[ "${TEST_PY_BD}" == "qemu-riscv32_spl" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/ilp32/generic/firmware/fw_dynamic.bin; fi - if [[ "${TEST_PY_BD}" == "qemu-riscv64_spl" ]] || [[ "${TEST_PY_BD}" == "sifive_unleashed" ]]; then - wget -O - https://github.com/riscv/opensbi/releases/download/v0.9/opensbi-0.9-rv-bin.tar.xz | tar -C /tmp -xJ; - export OPENSBI=/tmp/opensbi-0.9-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; + wget -O - https://github.com/riscv-software-src/opensbi/releases/download/v1.2/opensbi-1.2-rv-bin.tar.xz | tar -C /tmp -xJ; + export OPENSBI=/tmp/opensbi-1.2-rv-bin/share/opensbi/lp64/generic/firmware/fw_dynamic.bin; fi after_script: diff --git a/MAINTAINERS b/MAINTAINERS index 3bf60c4..2477923 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -343,6 +343,7 @@ F: drivers/rtc/armada38x.c F: drivers/spi/kirkwood_spi.c F: drivers/spi/mvebu_a3700_spi.c F: drivers/pci/pcie_dw_mvebu.c +F: drivers/pci/pcie-xilinx-nwl.c F: drivers/watchdog/armada-37xx-wdt.c F: drivers/watchdog/orion_wdt.c F: include/configs/mv-common.h @@ -755,6 +756,7 @@ F: drivers/spi/zynq_qspi.c F: drivers/spi/zynq_spi.c F: drivers/timer/cadence-ttc.c F: drivers/video/seps525.c +F: drivers/video/zynqmp/ F: drivers/watchdog/cdns_wdt.c F: include/zynqmppl.h F: include/zynqmp_firmware.h @@ -423,7 +423,8 @@ DTC_MIN_VERSION := 010406 CHECK = sparse CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \ - -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF) + -Wbitwise -Wno-return-void -Wno-unknown-attribute \ + -D__CHECK_ENDIAN__ $(CF) KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__ @@ -1032,6 +1033,9 @@ ifeq ($(CONFIG_ARC)$(CONFIG_NIOS2)$(CONFIG_X86)$(CONFIG_XTENSA),) LDFLAGS_u-boot += -Ttext $(CONFIG_TEXT_BASE) endif +# make the checker run with the right architecture +CHECKFLAGS += --arch=$(ARCH) + # insure the checker run with the right endianness CHECKFLAGS += $(if $(CONFIG_CPU_BIG_ENDIAN),-mbig-endian,-mlittle-endian) @@ -1808,7 +1812,7 @@ quiet_cmd_gen_envp = ENVP $@ rm -f $@; \ touch $@ ; \ fi -include/generated/env.in: include/generated/env.txt FORCE +include/generated/env.in: include/generated/env.txt $(call cmd,gen_envp) # Regenerate the environment if it changes @@ -1826,7 +1830,7 @@ quiet_cmd_envc = ENVC $@ touch $@ ; \ fi -include/generated/env.txt: $(wildcard $(ENV_FILE)) FORCE +include/generated/env.txt: $(wildcard $(ENV_FILE)) $(call cmd,envc) # Write out the resulting environment, converted to a C string @@ -2148,7 +2152,7 @@ CHANGELOG: # Directories & files removed with 'make clean' CLEAN_DIRS += $(MODVERDIR) \ - $(foreach d, spl tpl, $(patsubst %,$d/%, \ + $(foreach d, spl tpl vpl, $(patsubst %,$d/%, \ $(filter-out include, $(shell ls -1 $d 2>/dev/null)))) CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ @@ -2163,7 +2167,7 @@ CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \ idbloader-spi.img lib/efi_loader/helloworld_efi.S # Directories & files removed with 'make mrproper' -MRPROPER_DIRS += include/config include/generated spl tpl \ +MRPROPER_DIRS += include/config include/generated spl tpl vpl \ .tmp_objdiff doc/output include/asm # Remove include/asm symlink created by U-Boot before v2014.01 diff --git a/arch/Kconfig.nxp b/arch/Kconfig.nxp index 6e1c44b..5a8c382 100644 --- a/arch/Kconfig.nxp +++ b/arch/Kconfig.nxp @@ -45,7 +45,7 @@ config ESBC_HDR_LS config ESBC_ADDR_64BIT def_bool y - depends on ESBC_HDR_LS && FSL_LAYERSCAPE + depends on FSL_LAYERSCAPE help For Layerscape based platforms, ESBC image Address in Header is 64bit. @@ -90,7 +90,7 @@ config SPL_UBOOT_KEY_HASH default "" help Set the key hash for U-Boot here if public/private key pair used to - sign U-boot are different from the SRK hash put in the fuse. Example + sign U-Boot are different from the SRK hash put in the fuse. Example of a key hash is 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b. Otherwise leave this empty. diff --git a/arch/arc/include/asm/io.h b/arch/arc/include/asm/io.h index 6adc0ed..c818b8b 100644 --- a/arch/arc/include/asm/io.h +++ b/arch/arc/include/asm/io.h @@ -80,7 +80,7 @@ static inline void sync(void) /* * We add memory barriers for __raw_readX / __raw_writeX accessors same way as - * it is done for readX and writeX accessors as lots of U-boot driver uses + * it is done for readX and writeX accessors as lots of U-Boot driver uses * __raw_readX / __raw_writeX instead of proper accessor with barrier. */ #define __raw_writeb(v, c) ({ __iowmb(); __arch_putb(v, c); }) diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index e33e536..ccc2f20 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -110,7 +110,7 @@ config ARMV7_LPAE config ARMV7_SET_CORTEX_SMPEN bool help - Enable the ARM Cortex ACTLR.SMP enable bit in U-boot. + Enable the ARM Cortex ACTLR.SMP enable bit in U-Boot. config SPL_ARMV7_SET_CORTEX_SMPEN bool diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 6c066e5..4142872 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -311,11 +311,11 @@ ENTRY(psci_cpu_entry) bl psci_arch_cpu_entry bl psci_get_cpu_id @ CPU ID => r0 - mov r2, r0 @ CPU ID => r2 bl psci_get_context_id @ context id => r0 - mov r1, r0 @ context id => r1 - mov r0, r2 @ CPU ID => r0 + push {r0} @ save context id + bl psci_get_cpu_id @ CPU ID => r0 bl psci_get_target_pc @ target PC => r0 + pop {r1} @ context id => r1 b _do_nonsec_entry ENDPROC(psci_cpu_entry) diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 7d5cf15..9f0fb36 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -145,7 +145,7 @@ config ARMV8_PSCI bool "Enable PSCI support" if EXPERT help PSCI is Power State Coordination Interface defined by ARM. - The PSCI in U-boot provides a general framework and each platform + The PSCI in U-Boot provides a general framework and each platform can implement their own specific PSCI functions. Say Y here to enable PSCI support on ARMv8 platform. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 index 6f3fe7c..1ddf947 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 +++ b/arch/arm/cpu/armv8/fsl-layerscape/doc/README.lsch3 @@ -125,7 +125,7 @@ mcinitcmd: This environment variable is defined to initiate MC and DPL deploymen from the location where it is stored(NOR, NAND, SD, SATA, USB)during u-boot booting.If this variable is not defined then MC_BOOT_ENV_VAR will be null and MC will not be booted and DPL will not be applied - during U-boot booting.However the MC, DPC and DPL can be applied from + during U-Boot booting.However the MC, DPC and DPL can be applied from console independently. The variable needs to be set from the console once and then on rebooting the parameters set in the variable will automatically be diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 480269f..17f506a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -187,8 +187,10 @@ dtb-$(CONFIG_ARCH_S5P4418) += \ s5p4418-nanopi2.dtb dtb-$(CONFIG_ARCH_MESON) += \ + meson-a1-ad401.dtb \ meson-axg-s400.dtb \ meson-axg-jethome-jethub-j100.dtb \ + meson-gxbb-kii-pro.dtb \ meson-gxbb-nanopi-k2.dtb \ meson-gxbb-odroidc2.dtb \ meson-gxbb-nanopi-k2.dtb \ @@ -451,7 +453,6 @@ dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \ am4372-generic.dtb \ am437x-cm-t43.dtb dtb-$(CONFIG_TARGET_AM3517_EVM) += am3517-evm.dtb -dtb-$(CONFIG_TI816X) += dm8168-evm.dtb dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ @@ -1053,7 +1054,9 @@ dtb-$(CONFIG_RCAR_GEN3) += \ r8a77965-ulcb-u-boot.dtb \ r8a77965-salvator-x-u-boot.dtb \ r8a77970-eagle-u-boot.dtb \ + r8a77970-v3msk-u-boot.dtb \ r8a77980-condor-u-boot.dtb \ + r8a77980-v3hsk-u-boot.dtb \ r8a77990-ebisu-u-boot.dtb \ r8a77995-draak-u-boot.dtb diff --git a/arch/arm/dts/am335x-igep0033.dtsi b/arch/arm/dts/am335x-igep0033.dtsi index ad57c74..4488dcc 100644 --- a/arch/arm/dts/am335x-igep0033.dtsi +++ b/arch/arm/dts/am335x-igep0033.dtsi @@ -175,7 +175,7 @@ }; partition@1 { - label = "U-boot"; + label = "U-Boot"; reg = <0x00080000 0x001e0000>; }; diff --git a/arch/arm/dts/armada-3720-db.dts b/arch/arm/dts/armada-3720-db.dts index 3e5789f..1ee9240 100644 --- a/arch/arm/dts/armada-3720-db.dts +++ b/arch/arm/dts/armada-3720-db.dts @@ -180,7 +180,7 @@ reg = <0x0 0x200000>; }; partition@200000 { - label = "U-boot Env"; + label = "U-Boot Env"; reg = <0x200000 0x10000>; }; partition@210000 { diff --git a/arch/arm/dts/corstone1000.dtsi b/arch/arm/dts/corstone1000.dtsi index 533dfdf..1e0ec07 100644 --- a/arch/arm/dts/corstone1000.dtsi +++ b/arch/arm/dts/corstone1000.dtsi @@ -38,7 +38,7 @@ reg = <0x88200000 0x77e00000>; }; - nvmxip-qspi@08000000 { + nvmxip: nvmxip-qspi@08000000 { compatible = "nvmxip,qspi"; reg = <0x08000000 0x2000000>; lba_shift = <9>; @@ -106,6 +106,11 @@ method = "smc"; }; + fwu-mdata { + compatible = "u-boot,fwu-mdata-gpt"; + fwu-mdata-store = <&nvmxip>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/dts/dm8168-evm-u-boot.dtsi b/arch/arm/dts/dm8168-evm-u-boot.dtsi deleted file mode 100644 index f939df2..0000000 --- a/arch/arm/dts/dm8168-evm-u-boot.dtsi +++ /dev/null @@ -1,12 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * dm8168-evm U-Boot Additions - * - * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> - */ - -/ { - ocp { - bootph-all; - }; -}; diff --git a/arch/arm/dts/dm8168-evm.dts b/arch/arm/dts/dm8168-evm.dts deleted file mode 100644 index 70255ab..0000000 --- a/arch/arm/dts/dm8168-evm.dts +++ /dev/null @@ -1,171 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/dts-v1/; - -#include "dm816x.dtsi" -#include <dt-bindings/interrupt-controller/irq.h> - -/ { - model = "DM8168 EVM"; - compatible = "ti,dm8168-evm", "ti,dm8168"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x40000000 /* 1 GB */ - 0xc0000000 0x40000000>; /* 1 GB */ - }; - - /* FDC6331L controlled by SD_POW pin */ - vmmcsd_fixed: fixedregulator0 { - compatible = "regulator-fixed"; - regulator-name = "vmmcsd_fixed"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; -}; - -&dm816x_pinmux { - mcspi1_pins: pinmux_mcspi1_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0a94, MUX_MODE0) /* SPI_SCLK */ - DM816X_IOPAD(0x0a98, MUX_MODE0) /* SPI_SCS0 */ - DM816X_IOPAD(0x0aa8, MUX_MODE0) /* SPI_D0 */ - DM816X_IOPAD(0x0aac, MUX_MODE0) /* SPI_D1 */ - >; - }; - - mmc_pins: pinmux_mmc_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0a70, MUX_MODE0) /* SD_POW */ - DM816X_IOPAD(0x0a74, MUX_MODE0) /* SD_CLK */ - DM816X_IOPAD(0x0a78, MUX_MODE0) /* SD_CMD */ - DM816X_IOPAD(0x0a7C, MUX_MODE0) /* SD_DAT0 */ - DM816X_IOPAD(0x0a80, MUX_MODE0) /* SD_DAT1 */ - DM816X_IOPAD(0x0a84, MUX_MODE0) /* SD_DAT2 */ - DM816X_IOPAD(0x0a88, MUX_MODE0) /* SD_DAT2 */ - DM816X_IOPAD(0x0a8c, MUX_MODE2) /* GP1[7] */ - DM816X_IOPAD(0x0a90, MUX_MODE2) /* GP1[8] */ - >; - }; - - usb0_pins: pinmux_usb0_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB0_DRVVBUS */ - >; - }; - - usb1_pins: pinmux_usb1_pins { - pinctrl-single,pins = < - DM816X_IOPAD(0x0d08, MUX_MODE0) /* USB1_DRVVBUS */ - >; - }; -}; - -&i2c1 { - extgpio0: pcf8575@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&i2c2 { - extgpio1: pcf8575@20 { - compatible = "nxp,pcf8575"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; -}; - -&gpmc { - ranges = <0 0 0x04000000 0x01000000>; /* CS0: 16MB for NAND */ - - nand@0,0 { - compatible = "ti,omap2-nand"; - linux,mtd-name= "micron,mt29f2g16aadwp"; - reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ - interrupt-parent = <&gpmc>; - interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ - <1 IRQ_TYPE_NONE>; /* termcount */ - #address-cells = <1>; - #size-cells = <1>; - ti,nand-ecc-opt = "bch8"; - nand-bus-width = <16>; - gpmc,device-width = <2>; - gpmc,sync-clk-ps = <0>; - gpmc,cs-on-ns = <0>; - gpmc,cs-rd-off-ns = <44>; - gpmc,cs-wr-off-ns = <44>; - gpmc,adv-on-ns = <6>; - gpmc,adv-rd-off-ns = <34>; - gpmc,adv-wr-off-ns = <44>; - gpmc,we-on-ns = <0>; - gpmc,we-off-ns = <40>; - gpmc,oe-on-ns = <0>; - gpmc,oe-off-ns = <54>; - gpmc,access-ns = <64>; - gpmc,rd-cycle-ns = <82>; - gpmc,wr-cycle-ns = <82>; - gpmc,bus-turnaround-ns = <0>; - gpmc,cycle2cycle-delay-ns = <0>; - gpmc,clk-activation-ns = <0>; - gpmc,wr-access-ns = <40>; - gpmc,wr-data-mux-bus-ns = <0>; - partition@0 { - label = "X-Loader"; - reg = <0 0x80000>; - }; - partition@80000 { - label = "U-Boot"; - reg = <0x80000 0x1c0000>; - }; - partition@1c0000 { - label = "Environment"; - reg = <0x240000 0x40000>; - }; - partition@280000 { - label = "Kernel"; - reg = <0x280000 0x500000>; - }; - partition@780000 { - label = "Filesystem"; - reg = <0x780000 0xf880000>; - }; - }; -}; - -&mcspi1 { - pinctrl-names = "default"; - pinctrl-0 = <&mcspi1_pins>; - - flash@0 { - compatible = "w25x32"; - spi-max-frequency = <48000000>; - reg = <0>; - #address-cells = <1>; - #size-cells = <1>; - }; -}; - -&mmc1 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc_pins>; - vmmc-supply = <&vmmcsd_fixed>; - bus-width = <4>; - cd-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; -}; - -/* At least dm8168-evm rev c won't support multipoint, later may */ -&usb0 { - pinctrl-names = "default"; - pinctrl-0 = <&usb0_pins>; - mentor,multipoint = <0>; -}; - -&usb1 { - pinctrl-names = "default"; - pinctrl-0 = <&usb1_pins>; - mentor,multipoint = <0>; -}; diff --git a/arch/arm/dts/dm816x-clocks.dtsi b/arch/arm/dts/dm816x-clocks.dtsi deleted file mode 100644 index f7a839d..0000000 --- a/arch/arm/dts/dm816x-clocks.dtsi +++ /dev/null @@ -1,246 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -&scrm { - main_fapll: main_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x400 0x40>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>, <5>, - <6>, <7>; - clock-output-names = "main_pll_clk1", - "main_pll_clk2", - "main_pll_clk3", - "main_pll_clk4", - "main_pll_clk5", - "main_pll_clk6", - "main_pll_clk7"; - }; - - ddr_fapll: ddr_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x440 0x30>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>; - clock-output-names = "ddr_pll_clk1", - "ddr_pll_clk2", - "ddr_pll_clk3", - "ddr_pll_clk4"; - }; - - video_fapll: video_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x470 0x30>; - clocks = <&sys_clkin_ck &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>; - clock-output-names = "video_pll_clk1", - "video_pll_clk2", - "video_pll_clk3"; - }; - - audio_fapll: audio_fapll { - #clock-cells = <1>; - compatible = "ti,dm816-fapll-clock"; - reg = <0x4a0 0x30>; - clocks = <&main_fapll 7>, < &sys_clkin_ck>; - clock-indices = <1>, <2>, <3>, <4>, <5>; - clock-output-names = "audio_pll_clk1", - "audio_pll_clk2", - "audio_pll_clk3", - "audio_pll_clk4", - "audio_pll_clk5"; - }; -}; - -&scrm_clocks { - secure_32k_ck: secure_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_32k_ck: sys_32k_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - tclkin_ck: tclkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - sys_clkin_ck: sys_clkin_ck { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <27000000>; - }; -}; - -/* 0x48180000 */ -&prcm_clocks { - clkout_pre_ck: clkout_pre_ck@100 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&main_fapll 5 &ddr_fapll 1 &video_fapll 1 - &audio_fapll 1>; - reg = <0x100>; - }; - - clkout_div_ck: clkout_div_ck@100 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&clkout_pre_ck>; - ti,bit-shift = <3>; - ti,max-div = <8>; - reg = <0x100>; - }; - - clkout_ck: clkout_ck@100 { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&clkout_div_ck>; - ti,bit-shift = <7>; - reg = <0x100>; - }; - - /* CM_DPLL clocks p1795 */ - sysclk1_ck: sysclk1_ck@300 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 1>; - ti,max-div = <7>; - reg = <0x0300>; - }; - - sysclk2_ck: sysclk2_ck@304 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 2>; - ti,max-div = <7>; - reg = <0x0304>; - }; - - sysclk3_ck: sysclk3_ck@308 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 3>; - ti,max-div = <7>; - reg = <0x0308>; - }; - - sysclk4_ck: sysclk4_ck@30c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 4>; - ti,max-div = <1>; - reg = <0x030c>; - }; - - sysclk5_ck: sysclk5_ck@310 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&sysclk4_ck>; - ti,max-div = <1>; - reg = <0x0310>; - }; - - sysclk6_ck: sysclk6_ck@314 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 4>; - ti,dividers = <2>, <4>; - reg = <0x0314>; - }; - - sysclk10_ck: sysclk10_ck@324 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&ddr_fapll 2>; - ti,max-div = <7>; - reg = <0x0324>; - }; - - sysclk24_ck: sysclk24_ck@3b4 { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&main_fapll 5>; - ti,max-div = <7>; - reg = <0x03b4>; - }; - - mpu_ck: mpu_ck@15dc { - #clock-cells = <0>; - compatible = "ti,gate-clock"; - clocks = <&sysclk2_ck>; - ti,bit-shift = <1>; - reg = <0x15dc>; - }; - - audio_pll_a_ck: audio_pll_a_ck@35c { - #clock-cells = <0>; - compatible = "ti,divider-clock"; - clocks = <&audio_fapll 1>; - ti,max-div = <7>; - reg = <0x035c>; - }; - - sysclk18_ck: sysclk18_ck@378 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&sys_32k_ck>, <&audio_pll_a_ck>; - reg = <0x0378>; - }; - - timer1_fck: timer1_fck@390 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0390>; - }; - - timer2_fck: timer2_fck@394 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0394>; - }; - - timer3_fck: timer3_fck@398 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x0398>; - }; - - timer4_fck: timer4_fck@39c { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x039c>; - }; - - timer5_fck: timer5_fck@3a0 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a0>; - }; - - timer6_fck: timer6_fck@3a4 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a4>; - }; - - timer7_fck: timer7_fck@3a8 { - #clock-cells = <0>; - compatible = "ti,mux-clock"; - clocks = <&tclkin_ck>, <&sysclk18_ck>, <&sys_clkin_ck>; - reg = <0x03a8>; - }; -}; diff --git a/arch/arm/dts/dm816x.dtsi b/arch/arm/dts/dm816x.dtsi deleted file mode 100644 index c4a8653..0000000 --- a/arch/arm/dts/dm816x.dtsi +++ /dev/null @@ -1,517 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -#include <dt-bindings/gpio/gpio.h> -#include <dt-bindings/pinctrl/omap.h> - -/ { - compatible = "ti,dm816"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - chosen { }; - - aliases { - i2c0 = &i2c1; - i2c1 = &i2c2; - serial0 = &uart1; - serial1 = &uart2; - serial2 = &uart3; - ethernet0 = ð0; - ethernet1 = ð1; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu@0 { - compatible = "arm,cortex-a8"; - device_type = "cpu"; - reg = <0>; - }; - }; - - pmu { - compatible = "arm,cortex-a8-pmu"; - interrupts = <3>; - }; - - /* - * The soc node represents the soc top level view. It is used for IPs - * that are not memory mapped in the MPU view or for the MPU itself. - */ - soc { - compatible = "ti,omap-infra"; - mpu { - compatible = "ti,omap3-mpu"; - ti,hwmods = "mpu"; - }; - }; - - /* - * XXX: Use a flat representation of the dm816x interconnect. - * The real dm816x interconnect network is quite complex. Since - * it will not bring real advantage to represent that in DT - * for the moment, just use a fake OCP bus entry to represent - * the whole bus hierarchy. - */ - ocp { - compatible = "simple-bus"; - reg = <0x44000000 0x10000>; - interrupts = <9 10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - prcm: prcm@48180000 { - compatible = "ti,dm816-prcm", "simple-bus"; - reg = <0x48180000 0x4000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x48180000 0x4000>; - - prcm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - prcm_clockdomains: clockdomains { - }; - }; - - scrm: scrm@48140000 { - compatible = "ti,dm816-scrm", "simple-bus"; - reg = <0x48140000 0x21000>; - #address-cells = <1>; - #size-cells = <1>; - #pinctrl-cells = <1>; - ranges = <0 0x48140000 0x21000>; - - dm816x_pinmux: pinmux@800 { - compatible = "pinctrl-single"; - reg = <0x800 0x50a>; - #address-cells = <1>; - #size-cells = <0>; - #pinctrl-cells = <1>; - pinctrl-single,register-width = <16>; - pinctrl-single,function-mask = <0xf>; - }; - - /* Device Configuration Registers */ - scm_conf: syscon@600 { - compatible = "syscon", "simple-bus"; - reg = <0x600 0x110>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x600 0x110>; - - usb_phy0: usb-phy@20 { - compatible = "ti,dm8168-usb-phy"; - reg = <0x20 0x8>; - reg-names = "phy"; - clocks = <&main_fapll 6>; - clock-names = "refclk"; - #phy-cells = <0>; - syscon = <&scm_conf>; - }; - - usb_phy1: usb-phy@28 { - compatible = "ti,dm8168-usb-phy"; - reg = <0x28 0x8>; - reg-names = "phy"; - clocks = <&main_fapll 6>; - clock-names = "refclk"; - #phy-cells = <0>; - syscon = <&scm_conf>; - }; - }; - - scrm_clocks: clocks { - #address-cells = <1>; - #size-cells = <0>; - }; - - scrm_clockdomains: clockdomains { - }; - }; - - edma: edma@49000000 { - compatible = "ti,edma3"; - ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2", "tptc3"; - reg = <0x49000000 0x10000>, - <0x44e10f90 0x40>; - interrupts = <12 13 14>; - #dma-cells = <1>; - }; - - elm: elm@48080000 { - compatible = "ti,816-elm"; - ti,hwmods = "elm"; - reg = <0x48080000 0x2000>; - interrupts = <4>; - }; - - gpio1: gpio@48032000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio1"; - ti,gpio-always-on; - reg = <0x48032000 0x1000>; - interrupts = <96>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpio2: gpio@4804c000 { - compatible = "ti,omap4-gpio"; - ti,hwmods = "gpio2"; - ti,gpio-always-on; - reg = <0x4804c000 0x1000>; - interrupts = <98>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpmc: gpmc@50000000 { - compatible = "ti,am3352-gpmc"; - ti,hwmods = "gpmc"; - reg = <0x50000000 0x2000>; - #address-cells = <2>; - #size-cells = <1>; - interrupts = <100>; - dmas = <&edma 52>; - dma-names = "rxtx"; - gpmc,num-cs = <6>; - gpmc,num-waitpins = <2>; - interrupt-controller; - #interrupt-cells = <2>; - gpio-controller; - #gpio-cells = <2>; - }; - - i2c1: i2c@48028000 { - compatible = "ti,omap4-i2c"; - ti,hwmods = "i2c1"; - reg = <0x48028000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <70>; - dmas = <&edma 58 &edma 59>; - dma-names = "tx", "rx"; - }; - - i2c2: i2c@4802a000 { - compatible = "ti,omap4-i2c"; - ti,hwmods = "i2c2"; - reg = <0x4802a000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <71>; - dmas = <&edma 60 &edma 61>; - dma-names = "tx", "rx"; - }; - - intc: interrupt-controller@48200000 { - compatible = "ti,dm816-intc"; - interrupt-controller; - #interrupt-cells = <1>; - reg = <0x48200000 0x1000>; - }; - - rtc: rtc@480c0000 { - compatible = "ti,am3352-rtc", "ti,da830-rtc"; - reg = <0x480c0000 0x1000>; - interrupts = <75 76>; - ti,hwmods = "rtc"; - }; - - mailbox: mailbox@480c8000 { - compatible = "ti,omap4-mailbox"; - reg = <0x480c8000 0x2000>; - interrupts = <77>; - ti,hwmods = "mailbox"; - #mbox-cells = <1>; - ti,mbox-num-users = <4>; - ti,mbox-num-fifos = <12>; - mbox_dsp: mbox-dsp { - ti,mbox-tx = <3 0 0>; - ti,mbox-rx = <0 0 0>; - }; - }; - - spinbox: spinbox@480ca000 { - compatible = "ti,omap4-hwspinlock"; - reg = <0x480ca000 0x2000>; - ti,hwmods = "spinbox"; - #hwlock-cells = <1>; - }; - - mdio: mdio@4a100800 { - compatible = "ti,davinci_mdio"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x4a100800 0x100>; - ti,hwmods = "davinci_mdio"; - bus_freq = <1000000>; - phy0: ethernet-phy@0 { - reg = <1>; - }; - phy1: ethernet-phy@1 { - reg = <2>; - }; - }; - - eth0: ethernet@4a100000 { - compatible = "ti,dm816-emac"; - ti,hwmods = "emac0"; - reg = <0x4a100000 0x800 - 0x4a100900 0x3700>; - clocks = <&sysclk24_ck>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0>; - ti,davinci-ctrl-mod-reg-offset = <0x900>; - ti,davinci-ctrl-ram-offset = <0x2000>; - ti,davinci-ctrl-ram-size = <0x2000>; - interrupts = <40 41 42 43>; - phy-handle = <&phy0>; - }; - - eth1: ethernet@4a120000 { - compatible = "ti,dm816-emac"; - ti,hwmods = "emac1"; - reg = <0x4a120000 0x4000>; - clocks = <&sysclk24_ck>; - syscon = <&scm_conf>; - ti,davinci-ctrl-reg-offset = <0>; - ti,davinci-ctrl-mod-reg-offset = <0x900>; - ti,davinci-ctrl-ram-offset = <0x2000>; - ti,davinci-ctrl-ram-size = <0x2000>; - interrupts = <44 45 46 47>; - phy-handle = <&phy1>; - }; - - mcspi1: spi@48030000 { - compatible = "ti,omap4-mcspi"; - reg = <0x48030000 0x1000>; - #address-cells = <1>; - #size-cells = <0>; - interrupts = <65>; - ti,spi-num-cs = <4>; - ti,hwmods = "mcspi1"; - dmas = <&edma 16 &edma 17 - &edma 18 &edma 19 - &edma 20 &edma 21 - &edma 22 &edma 23>; - dma-names = "tx0", "rx0", "tx1", "rx1", - "tx2", "rx2", "tx3", "rx3"; - }; - - mmc1: mmc@48060000 { - compatible = "ti,omap4-hsmmc"; - reg = <0x48060000 0x11000>; - ti,hwmods = "mmc1"; - interrupts = <64>; - dmas = <&edma 24 &edma 25>; - dma-names = "tx", "rx"; - }; - - timer1: timer@4802e000 { - compatible = "ti,dm816-timer"; - reg = <0x4802e000 0x2000>; - interrupts = <67>; - ti,hwmods = "timer1"; - ti,timer-alwon; - }; - - timer2: timer@48040000 { - compatible = "ti,dm816-timer"; - reg = <0x48040000 0x2000>; - interrupts = <68>; - ti,hwmods = "timer2"; - }; - - timer3: timer@48042000 { - compatible = "ti,dm816-timer"; - reg = <0x48042000 0x2000>; - interrupts = <69>; - ti,hwmods = "timer3"; - }; - - timer4: timer@48044000 { - compatible = "ti,dm816-timer"; - reg = <0x48044000 0x2000>; - interrupts = <92>; - ti,hwmods = "timer4"; - ti,timer-pwm; - }; - - timer5: timer@48046000 { - compatible = "ti,dm816-timer"; - reg = <0x48046000 0x2000>; - interrupts = <93>; - ti,hwmods = "timer5"; - ti,timer-pwm; - }; - - timer6: timer@48048000 { - compatible = "ti,dm816-timer"; - reg = <0x48048000 0x2000>; - interrupts = <94>; - ti,hwmods = "timer6"; - ti,timer-pwm; - }; - - timer7: timer@4804a000 { - compatible = "ti,dm816-timer"; - reg = <0x4804a000 0x2000>; - interrupts = <95>; - ti,hwmods = "timer7"; - ti,timer-pwm; - }; - - uart1: serial@48020000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart1"; - reg = <0x48020000 0x2000>; - clock-frequency = <48000000>; - interrupts = <72>; - dmas = <&edma 26 &edma 27>; - dma-names = "tx", "rx"; - }; - - uart2: serial@48022000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart2"; - reg = <0x48022000 0x2000>; - clock-frequency = <48000000>; - interrupts = <73>; - dmas = <&edma 28 &edma 29>; - dma-names = "tx", "rx"; - }; - - uart3: serial@48024000 { - compatible = "ti,am3352-uart", "ti,omap3-uart"; - ti,hwmods = "uart3"; - reg = <0x48024000 0x2000>; - clock-frequency = <48000000>; - interrupts = <74>; - dmas = <&edma 30 &edma 31>; - dma-names = "tx", "rx"; - }; - - /* NOTE: USB needs a transceiver driver for phys to work */ - usb: usb_otg_hs@47401000 { - compatible = "ti,am33xx-usb"; - reg = <0x47401000 0x400000>; - ranges; - #address-cells = <1>; - #size-cells = <1>; - ti,hwmods = "usb_otg_hs"; - - usb0: usb@47401000 { - compatible = "ti,musb-dm816"; - reg = <0x47401400 0x400 - 0x47401000 0x200>; - reg-names = "mc", "control"; - interrupts = <18>; - interrupt-names = "mc"; - dr_mode = "host"; - interface-type = <0>; - phys = <&usb_phy0>; - phy-names = "usb2-phy"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - - dmas = <&cppi41dma 0 0 &cppi41dma 1 0 - &cppi41dma 2 0 &cppi41dma 3 0 - &cppi41dma 4 0 &cppi41dma 5 0 - &cppi41dma 6 0 &cppi41dma 7 0 - &cppi41dma 8 0 &cppi41dma 9 0 - &cppi41dma 10 0 &cppi41dma 11 0 - &cppi41dma 12 0 &cppi41dma 13 0 - &cppi41dma 14 0 &cppi41dma 0 1 - &cppi41dma 1 1 &cppi41dma 2 1 - &cppi41dma 3 1 &cppi41dma 4 1 - &cppi41dma 5 1 &cppi41dma 6 1 - &cppi41dma 7 1 &cppi41dma 8 1 - &cppi41dma 9 1 &cppi41dma 10 1 - &cppi41dma 11 1 &cppi41dma 12 1 - &cppi41dma 13 1 &cppi41dma 14 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - usb1: usb@47401800 { - compatible = "ti,musb-dm816"; - reg = <0x47401c00 0x400 - 0x47401800 0x200>; - reg-names = "mc", "control"; - interrupts = <19>; - interrupt-names = "mc"; - dr_mode = "host"; - interface-type = <0>; - phys = <&usb_phy1>; - phy-names = "usb2-phy"; - mentor,multipoint = <1>; - mentor,num-eps = <16>; - mentor,ram-bits = <12>; - mentor,power = <500>; - - dmas = <&cppi41dma 15 0 &cppi41dma 16 0 - &cppi41dma 17 0 &cppi41dma 18 0 - &cppi41dma 19 0 &cppi41dma 20 0 - &cppi41dma 21 0 &cppi41dma 22 0 - &cppi41dma 23 0 &cppi41dma 24 0 - &cppi41dma 25 0 &cppi41dma 26 0 - &cppi41dma 27 0 &cppi41dma 28 0 - &cppi41dma 29 0 &cppi41dma 15 1 - &cppi41dma 16 1 &cppi41dma 17 1 - &cppi41dma 18 1 &cppi41dma 19 1 - &cppi41dma 20 1 &cppi41dma 21 1 - &cppi41dma 22 1 &cppi41dma 23 1 - &cppi41dma 24 1 &cppi41dma 25 1 - &cppi41dma 26 1 &cppi41dma 27 1 - &cppi41dma 28 1 &cppi41dma 29 1>; - dma-names = - "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7", - "rx8", "rx9", "rx10", "rx11", "rx12", "rx13", - "rx14", "rx15", - "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", - "tx8", "tx9", "tx10", "tx11", "tx12", "tx13", - "tx14", "tx15"; - }; - - cppi41dma: dma-controller@47402000 { - compatible = "ti,am3359-cppi41"; - reg = <0x47400000 0x1000 - 0x47402000 0x1000 - 0x47403000 0x1000 - 0x47404000 0x4000>; - reg-names = "glue", "controller", "scheduler", "queuemgr"; - interrupts = <17>; - interrupt-names = "glue"; - #dma-cells = <2>; - #dma-channels = <30>; - #dma-requests = <256>; - }; - }; - - wd_timer2: wd_timer@480c2000 { - compatible = "ti,omap3-wdt"; - ti,hwmods = "wd_timer"; - reg = <0x480c2000 0x1000>; - interrupts = <0>; - }; - }; -}; - -#include "dm816x-clocks.dtsi" diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 06b36cc..dde0c40 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -51,7 +51,7 @@ idle-states { /* - * PSCI node is not added default, U-boot will add missing + * PSCI node is not added default, U-Boot will add missing * parts if it determines to use PSCI. */ entry-method = "psci"; diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi index 884bdad..5e02cd9 100644 --- a/arch/arm/dts/fsl-ls1043a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi @@ -7,7 +7,7 @@ * Mingkai Hu <Mingkai.hu@freescale.com> */ -/include/ "fsl-ls1043a.dtsi" +#include "fsl-ls1043a.dtsi" / { model = "LS1043A QDS Board"; diff --git a/arch/arm/dts/fsl-ls1043a-rdb-u-boot.dtsi b/arch/arm/dts/fsl-ls1043a-rdb-u-boot.dtsi new file mode 100644 index 0000000..ef31c79 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-rdb-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2023 NXP */ + +#include "fsl-ls1043a-u-boot.dtsi" + diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts index 9e7c79f..f5b3bb6 100644 --- a/arch/arm/dts/fsl-ls1043a-rdb.dts +++ b/arch/arm/dts/fsl-ls1043a-rdb.dts @@ -9,13 +9,17 @@ */ /dts-v1/; -/include/ "fsl-ls1043a.dtsi" +#include "fsl-ls1043a.dtsi" / { model = "LS1043A RDB Board"; aliases { spi1 = &dspi0; + serial0 = &duart0; + serial1 = &duart1; + serial2 = &duart2; + serial3 = &duart3; }; }; diff --git a/arch/arm/dts/fsl-ls1043a-u-boot.dtsi b/arch/arm/dts/fsl-ls1043a-u-boot.dtsi new file mode 100644 index 0000000..65a8705 --- /dev/null +++ b/arch/arm/dts/fsl-ls1043a-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2023 NXP */ + +&duart0 { + bootph-all; +}; + +&duart1 { + bootph-all; +}; + +&duart2 { + bootph-all; +}; + +&duart3 { + bootph-all; +}; + diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi index 4960973..21643a1 100644 --- a/arch/arm/dts/fsl-ls1043a.dtsi +++ b/arch/arm/dts/fsl-ls1043a.dtsi @@ -8,7 +8,9 @@ * Mingkai Hu <Mingkai.hu@freescale.com> */ -/include/ "skeleton64.dtsi" +#include "skeleton64.dtsi" +#include <dt-bindings/clock/fsl,qoriq-clockgen.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "fsl,ls1043a"; @@ -223,28 +225,32 @@ compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; interrupts = <0 54 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; }; duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0600 0x0 0x100>; interrupts = <0 54 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; }; duart2: serial@21d0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0500 0x0 0x100>; interrupts = <0 55 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; }; duart3: serial@21d0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0600 0x0 0x100>; interrupts = <0 55 0x4>; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(1)>; }; lpuart0: serial@2950000 { diff --git a/arch/arm/dts/fsl-ls1046a-frwy-u-boot.dtsi b/arch/arm/dts/fsl-ls1046a-frwy-u-boot.dtsi new file mode 100644 index 0000000..ce204e6 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-frwy-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2023 NXP */ + +#include "fsl-ls1046a-u-boot.dtsi" + diff --git a/arch/arm/dts/fsl-ls1046a-frwy.dts b/arch/arm/dts/fsl-ls1046a-frwy.dts index cda0541..ba10d21 100644 --- a/arch/arm/dts/fsl-ls1046a-frwy.dts +++ b/arch/arm/dts/fsl-ls1046a-frwy.dts @@ -2,22 +2,42 @@ /* * Device Tree Include file for NXP Layerscape-1046A family SoC. * - * Copyright 2019 NXP + * Copyright 2019-2023 NXP * */ /dts-v1/; -/include/ "fsl-ls1046a.dtsi" +#include "fsl-ls1046a.dtsi" / { model = "LS1046A FRWY Board"; aliases { spi0 = &qspi; + serial0 = &duart0; + serial1 = &duart1; + serial2 = &duart2; + serial3 = &duart3; }; }; +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&duart2 { + status = "okay"; +}; + +&duart3 { + status = "okay"; +}; + &qspi { status = "okay"; @@ -34,3 +54,49 @@ &i2c0 { status = "okay"; }; + +#include "fsl-ls1046-post.dtsi" + +&fman0 { + ethernet@e0000 { + phy-handle = <&qsgmii_phy4>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + ethernet@e8000 { + phy-handle = <&qsgmii_phy2>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + ethernet@ea000 { + phy-handle = <&qsgmii_phy1>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + ethernet@f2000 { + phy-handle = <&qsgmii_phy3>; + phy-connection-type = "qsgmii"; + status = "okay"; + }; + + mdio@fd000 { + qsgmii_phy1: ethernet-phy@1c { + reg = <0x1c>; + }; + + qsgmii_phy2: ethernet-phy@1d { + reg = <0x1d>; + }; + + qsgmii_phy3: ethernet-phy@1e { + reg = <0x1e>; + }; + + qsgmii_phy4: ethernet-phy@1f { + reg = <0x1f>; + }; + }; +}; diff --git a/arch/arm/dts/fsl-ls1046a-qds.dtsi b/arch/arm/dts/fsl-ls1046a-qds.dtsi index fec5c8d..d668249 100644 --- a/arch/arm/dts/fsl-ls1046a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1046a-qds.dtsi @@ -7,7 +7,7 @@ * Mingkai Hu <Mingkai.hu@nxp.com> */ -/include/ "fsl-ls1046a.dtsi" +#include "fsl-ls1046a.dtsi" / { model = "LS1046A QDS Board"; diff --git a/arch/arm/dts/fsl-ls1046a-rdb-u-boot.dtsi b/arch/arm/dts/fsl-ls1046a-rdb-u-boot.dtsi new file mode 100644 index 0000000..ce204e6 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-rdb-u-boot.dtsi @@ -0,0 +1,5 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2023 NXP */ + +#include "fsl-ls1046a-u-boot.dtsi" + diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts index 4641292..66d7189 100644 --- a/arch/arm/dts/fsl-ls1046a-rdb.dts +++ b/arch/arm/dts/fsl-ls1046a-rdb.dts @@ -9,17 +9,29 @@ */ /dts-v1/; -/include/ "fsl-ls1046a.dtsi" +#include "fsl-ls1046a.dtsi" / { model = "LS1046A RDB Board"; aliases { spi0 = &qspi; + serial0 = &duart0; + serial1 = &duart1; + serial2 = &duart2; + serial3 = &duart3; }; }; +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + &qspi { status = "okay"; diff --git a/arch/arm/dts/fsl-ls1046a-u-boot.dtsi b/arch/arm/dts/fsl-ls1046a-u-boot.dtsi new file mode 100644 index 0000000..65a8705 --- /dev/null +++ b/arch/arm/dts/fsl-ls1046a-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* Copyright 2023 NXP */ + +&duart0 { + bootph-all; +}; + +&duart1 { + bootph-all; +}; + +&duart2 { + bootph-all; +}; + +&duart3 { + bootph-all; +}; + diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi index 060dc39..44ee4c5 100644 --- a/arch/arm/dts/fsl-ls1046a.dtsi +++ b/arch/arm/dts/fsl-ls1046a.dtsi @@ -8,7 +8,9 @@ * Mingkai Hu <mingkai.hu@nxp.com> */ -/include/ "skeleton64.dtsi" +#include "skeleton64.dtsi" +#include <dt-bindings/clock/fsl,qoriq-clockgen.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> / { compatible = "fsl,ls1046a"; @@ -222,29 +224,37 @@ duart0: serial@21c0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0500 0x0 0x100>; - interrupts = <0 54 0x4>; - clocks = <&clockgen 4 0>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + status = "disabled"; }; duart1: serial@21c0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x00 0x21c0600 0x0 0x100>; - interrupts = <0 54 0x4>; - clocks = <&clockgen 4 0>; + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + status = "disabled"; }; duart2: serial@21d0500 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0500 0x0 0x100>; - interrupts = <0 55 0x4>; - clocks = <&clockgen 4 0>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + status = "disabled"; }; duart3: serial@21d0600 { compatible = "fsl,ns16550", "ns16550a"; reg = <0x0 0x21d0600 0x0 0x100>; - interrupts = <0 55 0x4>; - clocks = <&clockgen 4 0>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + status = "disabled"; }; lpuart0: serial@2950000 { diff --git a/arch/arm/dts/meson-a1-ad401.dts b/arch/arm/dts/meson-a1-ad401.dts new file mode 100644 index 0000000..69c25c6 --- /dev/null +++ b/arch/arm/dts/meson-a1-ad401.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +/dts-v1/; + +#include "meson-a1.dtsi" + +/ { + compatible = "amlogic,ad401", "amlogic,a1"; + model = "Amlogic Meson A1 AD401 Development Board"; + + aliases { + serial0 = &uart_AO_B; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x8000000>; + }; +}; + +&uart_AO_B { + status = "okay"; +}; diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi new file mode 100644 index 0000000..6509329 --- /dev/null +++ b/arch/arm/dts/meson-a1.dtsi @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + */ + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/gpio/meson-a1-gpio.h> + +/ { + compatible = "amlogic,a1"; + + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a35"; + reg = <0x0 0x1>; + enable-method = "psci"; + next-level-cache = <&l2>; + }; + + l2: l2-cache0 { + compatible = "cache"; + cache-level = <2>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x0 0x800000>; + alignment = <0x0 0x400000>; + linux,cma-default; + }; + }; + + sm: secure-monitor { + compatible = "amlogic,meson-gxbb-sm"; + + pwrc: power-controller { + compatible = "amlogic,meson-a1-pwrc"; + #power-domain-cells = <1>; + status = "okay"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + apb: bus@fe000000 { + compatible = "simple-bus"; + reg = <0x0 0xfe000000 0x0 0x1000000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; + + reset: reset-controller@0 { + compatible = "amlogic,meson-a1-reset"; + reg = <0x0 0x0 0x0 0x8c>; + #reset-cells = <1>; + }; + + periphs_pinctrl: pinctrl@400 { + compatible = "amlogic,meson-a1-periphs-pinctrl"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gpio: bank@400 { + reg = <0x0 0x0400 0x0 0x003c>, + <0x0 0x0480 0x0 0x0118>; + reg-names = "mux", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&periphs_pinctrl 0 0 62>; + }; + + }; + + uart_AO: serial@1c00 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x1c00 0x0 0x18>; + interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + + uart_AO_B: serial@2000 { + compatible = "amlogic,meson-gx-uart", + "amlogic,meson-ao-uart"; + reg = <0x0 0x2000 0x0 0x18>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; + clocks = <&xtal>, <&xtal>, <&xtal>; + clock-names = "xtal", "pclk", "baud"; + status = "disabled"; + }; + }; + + gic: interrupt-controller@ff901000 { + compatible = "arm,gic-400"; + reg = <0x0 0xff901000 0x0 0x1000>, + <0x0 0xff902000 0x0 0x2000>, + <0x0 0xff904000 0x0 0x2000>, + <0x0 0xff906000 0x0 0x2000>; + interrupt-controller; + interrupts = <GIC_PPI 9 + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; + }; + + xtal: xtal-clk { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xtal"; + #clock-cells = <0>; + }; +}; diff --git a/arch/arm/dts/meson-g12-common-u-boot.dtsi b/arch/arm/dts/meson-g12-common-u-boot.dtsi index efa6a05..8070b62 100644 --- a/arch/arm/dts/meson-g12-common-u-boot.dtsi +++ b/arch/arm/dts/meson-g12-common-u-boot.dtsi @@ -5,7 +5,7 @@ */ / { - /* Keep HW order from U-boot */ + /* Keep HW order from U-Boot */ aliases { /delete-property/ mmc0; /delete-property/ mmc1; diff --git a/arch/arm/dts/meson-gx-u-boot.dtsi b/arch/arm/dts/meson-gx-u-boot.dtsi index 9f123ab..9e0620f 100644 --- a/arch/arm/dts/meson-gx-u-boot.dtsi +++ b/arch/arm/dts/meson-gx-u-boot.dtsi @@ -5,7 +5,7 @@ */ / { - /* Keep HW order from U-boot */ + /* Keep HW order from U-Boot */ aliases { /delete-property/ mmc0; /delete-property/ mmc1; diff --git a/arch/arm/dts/meson-gxbb-kii-pro-u-boot.dtsi b/arch/arm/dts/meson-gxbb-kii-pro-u-boot.dtsi new file mode 100644 index 0000000..191c519 --- /dev/null +++ b/arch/arm/dts/meson-gxbb-kii-pro-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong <narmstrong@baylibre.com> + */ + +#include "meson-gx-u-boot.dtsi" + +ðmac { + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0>, <10000>, <1000000>; + snps,reset-active-low; +}; diff --git a/arch/arm/dts/meson-gxbb-kii-pro.dts b/arch/arm/dts/meson-gxbb-kii-pro.dts new file mode 100644 index 0000000..e238f1f --- /dev/null +++ b/arch/arm/dts/meson-gxbb-kii-pro.dts @@ -0,0 +1,140 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Mohammad Rasim <mohammad.rasim96@gmail.com> + */ + +/dts-v1/; + +#include "meson-gxbb-p20x.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/sound/meson-aiu.h> + +/ { + compatible = "videostrong,kii-pro", "amlogic,meson-gxbb"; + model = "Videostrong KII Pro"; + + spdif_dit: audio-codec-0 { + #sound-dai-cells = <0>; + compatible = "linux,spdif-dit"; + status = "okay"; + sound-name-prefix = "DIT"; + }; + + leds { + compatible = "gpio-leds"; + led { + gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_STATUS; + default-state = "off"; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <20>; + + button-reset { + label = "reset"; + linux,code = <KEY_POWER>; + gpios = <&gpio_ao GPIOAO_3 GPIO_ACTIVE_HIGH>; + }; + }; + + sound { + compatible = "amlogic,gx-sound-card"; + model = "KII-PRO"; + assigned-clocks = <&clkc CLKID_MPLL0>, + <&clkc CLKID_MPLL1>, + <&clkc CLKID_MPLL2>; + assigned-clock-parents = <0>, <0>, <0>; + assigned-clock-rates = <294912000>, + <270950400>, + <393216000>; + + dai-link-0 { + sound-dai = <&aiu AIU_CPU CPU_I2S_FIFO>; + }; + + dai-link-1 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_FIFO>; + }; + + dai-link-2 { + sound-dai = <&aiu AIU_CPU CPU_I2S_ENCODER>; + dai-format = "i2s"; + mclk-fs = <256>; + + codec-0 { + sound-dai = <&aiu AIU_HDMI CTRL_I2S>; + }; + }; + + dai-link-3 { + sound-dai = <&aiu AIU_CPU CPU_SPDIF_ENCODER>; + + codec-0 { + sound-dai = <&spdif_dit>; + }; + }; + + dai-link-4 { + sound-dai = <&aiu AIU_HDMI CTRL_OUT>; + + codec-0 { + sound-dai = <&hdmi_tx>; + }; + }; + }; +}; + +&aiu { + status = "okay"; + pinctrl-0 = <&spdif_out_y_pins>; + pinctrl-names = "default"; +}; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rmii_pins>; + pinctrl-names = "default"; + + phy-handle = <ð_phy0>; + phy-mode = "rmii"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy@0 { + /* IC Plus IP101GR (0x02430c54) */ + reg = <0>; + reset-assert-us = <10000>; + reset-deassert-us = <10000>; + reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ir { + linux,rc-map-name = "rc-videostrong-kii-pro"; +}; + +&uart_A { + status = "okay"; + pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>; + pinctrl-names = "default"; + uart-has-rtscts; + + bluetooth { + compatible = "brcm,bcm4335a0"; + shutdown-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpio GPIOX_21 GPIO_ACTIVE_HIGH>; + max-speed = <2000000>; + clocks = <&wifi32k>; + clock-names = "lpo"; + }; +}; diff --git a/arch/arm/dts/r7s72100-gr-peach.dts b/arch/arm/dts/r7s72100-gr-peach.dts index fe1a4aa..70d034c 100644 --- a/arch/arm/dts/r7s72100-gr-peach.dts +++ b/arch/arm/dts/r7s72100-gr-peach.dts @@ -126,6 +126,8 @@ phy-handle = <&phy0>; phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c0f0", + "ethernet-phy-ieee802.3-c22"; reg = <0>; reset-gpios = <&port4 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/dts/r8a77970-v3msk-u-boot.dts b/arch/arm/dts/r8a77970-v3msk-u-boot.dts new file mode 100644 index 0000000..6ee06d7 --- /dev/null +++ b/arch/arm/dts/r8a77970-v3msk-u-boot.dts @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the V3MSK board + * + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#include "r8a77970-v3msk.dts" +#include "r8a77970-u-boot.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + aliases { + spi0 = &rpc; + }; + + cpld { + compatible = "renesas,v3msk-cpld"; + status = "okay"; + gpio-mdc = <&gpio1 21 0>; + gpio-mosi = <&gpio1 22 0>; + gpio-miso = <&gpio1 23 0>; + gpio-enablez = <&gpio1 19 0>; + /* Disable V3MSK Videobox Mini CANFD PHY */ + gpios = <&gpio0 12 0>, <&gpio0 14 0>; + }; +}; + +&avb { + pinctrl-0 = <&avb0_pins>; + pinctrl-names = "default"; + +}; + +&phy0 { + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; +}; + +&pfc { + avb0_pins: avb { + mux { + groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + }; +}; + +&rpc { + num-cs = <1>; + status = "okay"; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + status = "okay"; + }; +}; diff --git a/arch/arm/dts/r8a77970-v3msk.dts b/arch/arm/dts/r8a77970-v3msk.dts new file mode 100644 index 0000000..c2b65f8 --- /dev/null +++ b/arch/arm/dts/r8a77970-v3msk.dts @@ -0,0 +1,303 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the V3M Starter Kit board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * Copyright (C) 2017 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a77970.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Renesas V3M Starter Kit board"; + compatible = "renesas,v3msk", "renesas,r8a77970"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + serial0 = &scif0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + lvds-decoder { + compatible = "thine,thc63lvd1024"; + vcc-supply = <&vcc_d3_3v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + thc63lvd1024_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@2 { + reg = <2>; + thc63lvd1024_out: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x0 0x78000000>; + }; + + osc5_clk: osc5-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + vcc_d1_8v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VCC_D1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_d3_3v: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC_D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_vddq_vin0: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "VCC_VDDQ_VIN0"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + renesas,no-ether-link; + phy-handle = <&phy0>; + rx-internal-delay-ps = <1800>; + tx-internal-delay-ps = <2000>; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio1>; + interrupts = <17 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&osc5_clk>; + clock-names = "du.0", "dclkin.0"; + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + hdmi@39{ + compatible = "adi,adv7511w"; + #sound-dai-cells = <0>; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + avdd-supply = <&vcc_d1_8v>; + dvdd-supply = <&vcc_d1_8v>; + pvdd-supply = <&vcc_d1_8v>; + bgvdd-supply = <&vcc_d1_8v>; + dvdd-3v-supply = <&vcc_d3_3v>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&thc63lvd1024_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&thc63lvd1024_in>; + }; + }; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-names = "default"; + + vmmc-supply = <&vcc_d3_3v>; + vqmmc-supply = <&vcc_vddq_vin0>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +&pfc { + avb_pins: avb0 { + groups = "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; + function = "avb0"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + mmc_pins: mmc_3_3v { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + power-source = <3300>; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + cr7@40000 { + reg = <0x00040000 0x080000>; + read-only; + }; + cert_header_sa3@c0000 { + reg = <0x000c0000 0x080000>; + read-only; + }; + bl2@140000 { + reg = <0x00140000 0x040000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x460000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x0c0000>; + read-only; + }; + uboot-env@700000 { + reg = <0x00700000 0x040000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; diff --git a/arch/arm/dts/r8a77980-v3hsk-u-boot.dts b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts new file mode 100644 index 0000000..d083df6 --- /dev/null +++ b/arch/arm/dts/r8a77980-v3hsk-u-boot.dts @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source extras for U-Boot for the Eagle board + * + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#include "r8a77980-v3hsk.dts" +#include "r8a77980-u-boot.dtsi" + +/ { + aliases { + spi0 = &rpc; + }; +}; + +&rpc { + num-cs = <1>; + status = "okay"; + spi-max-frequency = <50000000>; + #address-cells = <1>; + #size-cells = <0>; + + flash0: spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "s25fs512s", "spi-flash", "jedec,spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + reg = <0>; + status = "okay"; + }; +}; + +&i2c0 { + cpld { + compatible = "renesas,v3hsk-cpld"; + reg = <0x70>; + u-boot,i2c-offset-len = <2>; + }; +}; diff --git a/arch/arm/dts/r8a77980-v3hsk.dts b/arch/arm/dts/r8a77980-v3hsk.dts new file mode 100644 index 0000000..d168b0e --- /dev/null +++ b/arch/arm/dts/r8a77980-v3hsk.dts @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the V3H Starter Kit board + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ + +/dts-v1/; +#include "r8a77980.dtsi" +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Renesas V3H Starter Kit board"; + compatible = "renesas,v3hsk", "renesas,r8a77980"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &scif0; + ethernet0 = &gether; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + lvds-decoder { + compatible = "thine,thc63lvd1024"; + vcc-supply = <&vcc3v3_d5>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + thc63lvd1024_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@2 { + reg = <2>; + thc63lvd1024_out: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0 0x48000000 0 0x78000000>; + }; + + osc1_clk: osc1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; + + vcc1v8_d4: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8_D4"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc3v3_d5: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_D5"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&osc1_clk>; + clock-names = "du.0", "dclkin.0"; + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&gether { + pinctrl-0 = <&gether_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii"; + phy-handle = <&phy0>; + renesas,no-ether-link; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + hdmi@39 { + compatible = "adi,adv7511w"; + #sound-dai-cells = <0>; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + avdd-supply = <&vcc1v8_d4>; + dvdd-supply = <&vcc1v8_d4>; + pvdd-supply = <&vcc1v8_d4>; + bgvdd-supply = <&vcc1v8_d4>; + dvdd-3v-supply = <&vcc3v3_d5>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&thc63lvd1024_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&thc63lvd1024_in>; + }; + }; + }; +}; + +&pfc { + gether_pins: gether { + groups = "gether_mdio_a", "gether_rgmii", + "gether_txcrefclk", "gether_txcrefclk_mega"; + function = "gether"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_b"; + function = "scif_clk"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + cr7@40000 { + reg = <0x00040000 0x080000>; + read-only; + }; + cert_header_sa3@c0000 { + reg = <0x000c0000 0x080000>; + read-only; + }; + bl2@140000 { + reg = <0x00140000 0x040000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x460000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x0c0000>; + read-only; + }; + uboot-env@700000 { + reg = <0x00700000 0x040000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; diff --git a/arch/arm/dts/rk3328-evb-u-boot.dtsi b/arch/arm/dts/rk3328-evb-u-boot.dtsi index 4bfa0c2..95e4979 100644 --- a/arch/arm/dts/rk3328-evb-u-boot.dtsi +++ b/arch/arm/dts/rk3328-evb-u-boot.dtsi @@ -41,7 +41,7 @@ }; &gmac2phy { - /* Integrated PHY unsupported by U-boot */ + /* Integrated PHY unsupported by U-Boot */ status = "broken"; }; diff --git a/arch/arm/dts/rk3328.dtsi b/arch/arm/dts/rk3328.dtsi index 27e45d5..e8d8f00 100644 --- a/arch/arm/dts/rk3328.dtsi +++ b/arch/arm/dts/rk3328.dtsi @@ -984,7 +984,7 @@ }; /* - * U-boot Specific Change + * U-Boot Specific Change * * The OTG controller must come after the USB host pair for it * to work. This is likely due to lack of support for the USB diff --git a/arch/arm/dts/stm32f769-disco-u-boot.dtsi b/arch/arm/dts/stm32f769-disco-u-boot.dtsi index b5198fd..2c823cc 100644 --- a/arch/arm/dts/stm32f769-disco-u-boot.dtsi +++ b/arch/arm/dts/stm32f769-disco-u-boot.dtsi @@ -28,11 +28,6 @@ button-gpio = <&gpioa 0 0>; }; - dsi_host: dsi_host { - compatible = "synopsys,dw-mipi-dsi"; - status = "okay"; - }; - led1 { compatible = "st,led1"; led-gpio = <&gpioj 5 0>; diff --git a/arch/arm/dts/stm32mp13-pinctrl.dtsi b/arch/arm/dts/stm32mp13-pinctrl.dtsi index d2472cd..b2dce3a 100644 --- a/arch/arm/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp13-pinctrl.dtsi @@ -6,6 +6,114 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { + pins { + pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ + <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ + }; + }; + + i2c1_pins_a: i2c1-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ + <STM32_PINMUX('E', 8, AF5)>; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c1_sleep_pins_a: i2c1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ + <STM32_PINMUX('E', 8, ANALOG)>; /* I2C1_SDA */ + }; + }; + + i2c5_pins_a: i2c5-0 { + pins { + pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ + <STM32_PINMUX('H', 6, AF4)>; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + i2c5_sleep_pins_a: i2c5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ + <STM32_PINMUX('H', 6, ANALOG)>; /* I2C5_SDA */ + }; + }; + + mcp23017_pins_a: mcp23017-0 { + pins { + pinmux = <STM32_PINMUX('G', 12, GPIO)>; + bias-pull-up; + }; + }; + + pwm3_pins_a: pwm3-0 { + pins { + pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_a: pwm3-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */ + }; + }; + + pwm4_pins_a: pwm4-0 { + pins { + pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ + }; + }; + + pwm8_pins_a: pwm8-0 { + pins { + pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_a: pwm8-sleep-0 { + pins { + pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */ + }; + }; + + pwm14_pins_a: pwm14-0 { + pins { + pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm14_sleep_pins_a: pwm14-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -108,6 +216,36 @@ }; }; + spi5_pins_a: spi5-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */ + <STM32_PINMUX('H', 3, AF5)>; /* SPI5_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF5)>; /* SPI5_MISO */ + bias-disable; + }; + }; + + spi5_sleep_pins_a: spi5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */ + <STM32_PINMUX('A', 8, ANALOG)>, /* SPI5_MISO */ + <STM32_PINMUX('H', 3, ANALOG)>; /* SPI5_MOSI */ + }; + }; + + stm32g0_intn_pins_a: stm32g0-intn-0 { + pins { + pinmux = <STM32_PINMUX('I', 2, GPIO)>; + bias-pull-up; + }; + }; + uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ diff --git a/arch/arm/dts/stm32mp131.dtsi b/arch/arm/dts/stm32mp131.dtsi index 6d82bf6..d94ba25 100644 --- a/arch/arm/dts/stm32mp131.dtsi +++ b/arch/arm/dts/stm32mp131.dtsi @@ -77,6 +77,28 @@ always-on; }; + /* PWR 1v1, 1v8 and 3v3 regulators defined as fixed, waiting for SCMI */ + reg11: reg11 { + compatible = "regulator-fixed"; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + compatible = "regulator-fixed"; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + compatible = "regulator-fixed"; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + soc { compatible = "simple-bus"; #address-cells = <1>; @@ -97,6 +119,284 @@ }; }; + timers2: timer@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32h7-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers3: timer@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32h7-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers4: timer@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32h7-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers5: timer@40003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40003000 0x400>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32h7-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers6: timer@40004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40004000 0x400>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32h7-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + + timers7: timer@40005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40005000 0x400>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32h7-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + lptimer1: timer@40009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4000b000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi2: spi@4000b000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000b000 0x400>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI2_K>; + resets = <&rcc SPI2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4000c000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi3: spi@4000c000 { + compatible = "st,stm32h7-spi"; + reg = <0x4000c000 0x400>; + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI3_K>; + resets = <&rcc SPI3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + reg = <0x4000d000 0x400>; + #sound-dai-cells = <0>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + status = "disabled"; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; @@ -106,6 +406,241 @@ status = "disabled"; }; + i2c1: i2c@40012000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40012000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C1_K>; + resets = <&rcc I2C1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 33 0x400 0x1>, + <&dmamux1 34 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x1>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c2: i2c@40013000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x40013000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C2_K>; + resets = <&rcc I2C2_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 35 0x400 0x1>, + <&dmamux1 36 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x2>; + i2c-analog-filter; + status = "disabled"; + }; + + timers1: timer@44000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44000000 0x400>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32h7-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers8: timer@44001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44001000 0x400>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32h7-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + i2s1: audio-controller@44004000 { + compatible = "st,stm32h7-i2s"; + reg = <0x44004000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi1: spi@44004000 { + compatible = "st,stm32h7-spi"; + reg = <0x44004000 0x400>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI1_K>; + resets = <&rcc SPI1_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai1: sai@4400a000 { + compatible = "st,stm32h7-sai"; + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + ranges = <0 0x4400a000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI1_R>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; + status = "disabled"; + }; + + sai1b: audio-controller@4400a024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; + status = "disabled"; + }; + }; + + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + ranges = <0 0x4400b000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + resets = <&rcc SAI2_R>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; + status = "disabled"; + }; + + sai2b: audio-controller@4400b024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; + status = "disabled"; + }; + }; + + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + reg = <0>; + #io-channel-cells = <1>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + reg = <1>; + #io-channel-cells = <1>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + }; + dma1: dma-controller@48000000 { compatible = "st,stm32-dma"; reg = <0x48000000 0x400>; @@ -153,6 +688,314 @@ dma-channels = <16>; }; + adc_2: adc@48004000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48004000 0x400>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc ADC2>, <&rcc ADC2_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc2: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_2>; + interrupts = <0>; + dmas = <&dmamux1 10 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@13 { + reg = <13>; + label = "vrefint"; + }; + channel@14 { + reg = <14>; + label = "vddcore"; + }; + channel@16 { + reg = <16>; + label = "vddcpu"; + }; + channel@17 { + reg = <17>; + label = "vddq_ddr"; + }; + }; + }; + + usbotg_hs: usb@49000000 { + compatible = "st,stm32mp15-hsotg", "snps,dwc2"; + reg = <0x49000000 0x40000>; + clocks = <&rcc USBO_K>; + clock-names = "otg"; + resets = <&rcc USBO_R>; + reset-names = "dwc2"; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + g-rx-fifo-size = <512>; + g-np-tx-fifo-size = <32>; + g-tx-fifo-size = <256 16 16 16 16 16 16 16>; + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; + status = "disabled"; + }; + + i2s4: audio-controller@4c002000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4c002000 0x400>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi4: spi@4c002000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c002000 0x400>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI4_K>; + resets = <&rcc SPI4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi5: spi@4c003000 { + compatible = "st,stm32h7-spi"; + reg = <0x4c003000 0x400>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc SPI5_K>; + resets = <&rcc SPI5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + i2c3: i2c@4c004000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c004000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C3_K>; + resets = <&rcc I2C3_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 73 0x400 0x1>, + <&dmamux1 74 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c4: i2c@4c005000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c005000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C4_K>; + resets = <&rcc I2C4_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 75 0x400 0x1>, + <&dmamux1 76 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; + status = "disabled"; + }; + + i2c5: i2c@4c006000 { + compatible = "st,stm32mp13-i2c"; + reg = <0x4c006000 0x400>; + interrupt-names = "event", "error"; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc I2C5_K>; + resets = <&rcc I2C5_R>; + #address-cells = <1>; + #size-cells = <0>; + dmas = <&dmamux1 115 0x400 0x1>, + <&dmamux1 116 0x400 0x1>; + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; + status = "disabled"; + }; + + timers12: timer@4c007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c007000 0x400>; + interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timer@4c008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c008000 0x400>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; + }; + + timers14: timer@4c009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c009000 0x400>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; + }; + + timers15: timer@4c00a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00a000 0x400>; + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@4c00b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00b000 0x400>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@4c00c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00c000 0x400>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "global"; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp13-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -181,6 +1024,111 @@ clocks = <&rcc SYSCFG>; }; + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -261,13 +1209,31 @@ clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; resets = <&rcc SDMMC2_R>; - cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; status = "disabled"; }; + usbh_ohci: usb@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + usbh_ehci: usb@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&usbphyc>, <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; + companion = <&usbh_ohci>; + status = "disabled"; + }; + iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; @@ -276,6 +1242,29 @@ status = "disabled"; }; + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; @@ -294,6 +1283,7 @@ part_number_otp: part_number_otp@4 { reg = <0x4 0x2>; + bits = <0 12>; }; ts_cal1: calib@5c { reg = <0x5c 0x2>; @@ -314,7 +1304,6 @@ ranges = <0 0x50002000 0x8400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; gpioa: gpio@50002000 { gpio-controller; diff --git a/arch/arm/dts/stm32mp133.dtsi b/arch/arm/dts/stm32mp133.dtsi index 531c263..df451c3 100644 --- a/arch/arm/dts/stm32mp133.dtsi +++ b/arch/arm/dts/stm32mp133.dtsi @@ -33,5 +33,36 @@ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; }; + + adc_1: adc@48003000 { + compatible = "st,stm32mp13-adc-core"; + reg = <0x48003000 0x400>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc ADC1>, <&rcc ADC1_K>; + clock-names = "bus", "adc"; + interrupt-controller; + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + adc1: adc@0 { + compatible = "st,stm32mp13-adc"; + #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + interrupt-parent = <&adc_1>; + interrupts = <0>; + dmas = <&dmamux1 9 0x400 0x80000001>; + dma-names = "rx"; + status = "disabled"; + + channel@18 { + reg = <18>; + label = "vrefint"; + }; + }; + }; }; }; diff --git a/arch/arm/dts/stm32mp135f-dk.dts b/arch/arm/dts/stm32mp135f-dk.dts index 52f8659..c40686c 100644 --- a/arch/arm/dts/stm32mp135f-dk.dts +++ b/arch/arm/dts/stm32mp135f-dk.dts @@ -40,7 +40,7 @@ gpio-keys { compatible = "gpio-keys"; - user-pa13 { + button-user { label = "User-PA13"; linux,code = <BTN_1>; gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; @@ -59,6 +59,22 @@ }; }; + v3v3_sw: v3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "v3v3_sw"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_adc: vdd-adc { + compatible = "regulator-fixed"; + regulator-name = "vdd_adc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vdd_sd: vdd-sd { compatible = "regulator-fixed"; regulator-name = "vdd_sd"; @@ -66,6 +82,101 @@ regulator-max-microvolt = <2900000>; regulator-always-on; }; + + vdd_usb: vdd-usb { + compatible = "regulator-fixed"; + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_usb_cc_pins_a>; + vdda-supply = <&vdd_adc>; + vref-supply = <&vdd_adc>; + status = "okay"; + adc1: adc@0 { + status = "okay"; + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in6 & in12. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. + * Use arbitrary margin here (e.g. 5us). + */ + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + }; + channel@12 { + reg = <12>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <1000000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + mcp23017: pinctrl@21 { + compatible = "microchip,mcp23017"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpiog>; + pinctrl-names = "default"; + pinctrl-0 = <&mcp23017_pins_a>; + interrupt-controller; + #interrupt-cells = <2>; + microchip,irq-mirror; + }; + + typec@53 { + compatible = "st,stm32g0-typec"; + reg = <0x53>; + /* Alert pin on PI2 */ + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent = <&gpioi>; + /* Internal pull-up on PI2 */ + pinctrl-names = "default"; + pinctrl-0 = <&stm32g0_intn_pins_a>; + firmware-name = "stm32g0-ucsi.mp135f-dk.fw"; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + con_usb_c_g0_ep: endpoint { + remote-endpoint = <&usbotg_hs_ep>; + }; + }; + }; + }; +}; + +&i2c5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_a>; + pinctrl-1 = <&i2c5_sleep_pins_a>; + i2c-scl-rising-time-ns = <170>; + i2c-scl-falling-time-ns = <5>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; }; &iwdg2 { @@ -90,8 +201,130 @@ status = "okay"; }; +&spi5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_pins_a>; + pinctrl-1 = <&spi5_sleep_pins_a>; + status = "disabled"; +}; + +&timers3 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm3_pins_a>; + pinctrl-1 = <&pwm3_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm4_pins_a>; + pinctrl-1 = <&pwm4_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@3 { + status = "okay"; + }; +}; + +&timers8 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm8_pins_a>; + pinctrl-1 = <&pwm8_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@7 { + status = "okay"; + }; +}; + +&timers14 { + status = "disabled"; + pwm { + pinctrl-0 = <&pwm14_pins_a>; + pinctrl-1 = <&pwm14_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@13 { + status = "okay"; + }; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; status = "okay"; }; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + /* onboard HUB */ + hub@1 { + compatible = "usb424,2514"; + reg = <1>; + vdd-supply = <&v3v3_sw>; + }; +}; + +&usbotg_hs { + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb-role-switch; + status = "okay"; + port { + usbotg_hs_ep: endpoint { + remote-endpoint = <&con_usb_c_g0_ep>; + }; + }; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; +}; diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi b/arch/arm/dts/stm32mp15-pinctrl.dtsi index 2cc9341..a9d2bec 100644 --- a/arch/arm/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi @@ -1261,7 +1261,7 @@ }; qspi_bk1_pins_a: qspi-bk1-0 { - pins1 { + pins { pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ @@ -1270,12 +1270,6 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { - pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; }; qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { @@ -1283,13 +1277,12 @@ pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ - <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ - <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ + <STM32_PINMUX('F', 6, ANALOG)>; /* QSPI_BK1_IO3 */ }; }; qspi_bk2_pins_a: qspi-bk2-0 { - pins1 { + pins { pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ @@ -1298,7 +1291,34 @@ drive-push-pull; slew-rate = <1>; }; - pins2 { + }; + + qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ + <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ + <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ + <STM32_PINMUX('G', 7, ANALOG)>; /* QSPI_BK2_IO3 */ + }; + }; + + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ + }; + }; + + qspi_cs2_pins_a: qspi-cs2-0 { + pins { pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ bias-pull-up; drive-push-pull; @@ -1306,13 +1326,9 @@ }; }; - qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { + qspi_cs2_sleep_pins_a: qspi-cs2-sleep-0 { pins { - pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ - <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ - <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ - <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ - <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ + pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ }; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 5d178b5..b3baacb 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -1693,7 +1693,6 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; gpioa: gpio@50002000 { gpio-controller; @@ -1822,7 +1821,6 @@ #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; ranges = <0 0x54004000 0x400>; - pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index cff3f49..2623ceb 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -12,6 +12,7 @@ i2c3 = &i2c4; usb0 = &usbotg_hs; }; + config { u-boot,boot-led = "heartbeat"; u-boot,error-led = "error"; diff --git a/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi index 5a8fc15..ae93497 100644 --- a/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi @@ -4,3 +4,10 @@ */ #include "stm32mp157a-dk1-scmi-u-boot.dtsi" + +/ { + fwu-mdata { + compatible = "u-boot,fwu-mdata-gpt"; + fwu-mdata-store = <&sdmmc1>; + }; +}; diff --git a/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi index 71a94f9..9768db8d 100644 --- a/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi @@ -14,4 +14,129 @@ spi0 = &qspi; usb0 = &usbotg_hs; }; + + fwu-mdata { + compatible = "u-boot,fwu-mdata-gpt"; + fwu-mdata-store = <&sdmmc1>; + }; +}; + +&flash0 { + bootph-pre-ram; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00040000>; + }; + partition@40000 { + label = "fsbl2"; + reg = <0x00040000 0x00040000>; + }; + partition@80000 { + label = "metadata1"; + reg = <0x00080000 0x00040000>; + }; + partition@c0000 { + label = "metadata2"; + reg = <0x000c0000 0x00040000>; + }; + partition@100000 { + label = "fip-a"; + reg = <0x00100000 0x00400000>; + }; + partition@500000 { + label = "fip-b"; + reg = <0x00500000 0x00400000>; + }; + partition@900000 { + label = "u-boot-env"; + reg = <0x00900000 0x00080000>; + }; + partition@980000 { + label = "nor-user"; + reg = <0x00980000 0x03680000>; + }; + }; +}; + +&fmc { + nand-controller@4,0 { + nand@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00080000>; + }; + partition@80000 { + label = "fsbl2"; + reg = <0x00080000 0x00080000>; + }; + partition@100000 { + label = "metadata1"; + reg = <0x00100000 0x00080000>; + }; + partition@180000 { + label = "metadata2"; + reg = <0x00180000 0x00080000>; + }; + partition@200000 { + label = "fip-a1"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "fip-a2"; + reg = <0x00600000 0x00400000>; + }; + partition@a00000 { + label = "fip-b1"; + reg = <0x00a00000 0x00400000>; + }; + partition@e00000 { + label = "fip-b2"; + reg = <0x00e00000 0x00400000>; + }; + partition@1200000 { + label = "UBI"; + reg = <0x01200000 0x3ee00000>; + }; + }; + }; + }; +}; + +&qspi { + bootph-pre-ram; +}; + +&qspi_clk_pins_a { + bootph-pre-ram; + pins { + bootph-pre-ram; + }; +}; + +&qspi_bk1_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; +}; + +&qspi_bk2_pins_a { + bootph-pre-ram; + pins1 { + bootph-pre-ram; + }; + pins2 { + bootph-pre-ram; + }; }; diff --git a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi index cb32c30..1f7fdbc 100644 --- a/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi @@ -23,6 +23,103 @@ &flash0 { bootph-pre-ram; + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + +#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL) + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00040000>; + }; + partition@80000 { + label = "fsbl2"; + reg = <0x00040000 0x00040000>; + }; + partition@100000 { + label = "ssbl"; + reg = <0x00080000 0x00200000>; + }; + partition@280000 { + label = "u-boot-env"; + reg = <0x00280000 0x00080000>; + }; + partition@300000 { + label = "nor-user"; + reg = <0x00300000 0x03d00000>; + }; +#else + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00040000>; + }; + partition@40000 { + label = "fsbl2"; + reg = <0x00040000 0x00040000>; + }; + partition@100000 { + label = "fip"; + reg = <0x00080000 0x00400000>; + }; + partition@480000 { + label = "u-boot-env"; + reg = <0x00480000 0x00080000>; + }; + partition@500000 { + label = "nor-user"; + reg = <0x00500000 0x03b00000>; + }; +#endif + }; +}; + +&fmc { + nand-controller@4,0 { + nand@0 { + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + +#if defined(CONFIG_STM32MP15x_STM32IMAGE) || defined(CONFIG_SPL) + partition@0 { + label = "fsbl"; + reg = <0x00000000 0x00200000>; + }; + partition@200000 { + label = "ssbl1"; + reg = <0x00200000 0x00200000>; + }; + partition@400000 { + label = "ssbl2"; + reg = <0x00400000 0x00200000>; + }; + partition@600000 { + label = "UBI"; + reg = <0x00600000 0x3fa00000>; + }; +#else + partition@0 { + label = "fsbl"; + reg = <0x00000000 0x00200000>; + }; + partition@200000 { + label = "fip1"; + reg = <0x00200000 0x00400000>; + }; + partition@600000 { + label = "fip2"; + reg = <0x00600000 0x00400000>; + }; + partition@1200000 { + label = "UBI"; + reg = <0x00a00000 0x3f600000>; + }; +#endif + }; + }; + }; }; &qspi { @@ -55,4 +152,3 @@ bootph-pre-ram; }; }; - diff --git a/arch/arm/dts/stm32mp157c-ev1.dts b/arch/arm/dts/stm32mp157c-ev1.dts index 2d5db41..542226c 100644 --- a/arch/arm/dts/stm32mp157c-ev1.dts +++ b/arch/arm/dts/stm32mp157c-ev1.dts @@ -8,6 +8,7 @@ #include "stm32mp157c-ed1.dts" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> +#include <dt-bindings/media/video-interfaces.h> / { model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; @@ -90,7 +91,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov5640_0>; - bus-type = <5>; + bus-type = <MEDIA_BUS_TYPE_PARALLEL>; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; @@ -144,7 +145,7 @@ max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; @@ -255,8 +256,16 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a + &qspi_bk2_pins_a + &qspi_cs2_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a + &qspi_bk2_sleep_pins_a + &qspi_cs2_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; @@ -393,6 +402,7 @@ st,tune-squelch-level = <3>; st,tune-hs-rx-offset = <2>; st,no-lsfs-sc; + connector { compatible = "usb-a-connector"; vbus-supply = <&vbus_sw>; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi index 83e2c87..de76174 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-som.dtsi @@ -429,8 +429,12 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi index bc0730c..a808620 100644 --- a/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi @@ -92,6 +92,33 @@ &flash0 { bootph-pre-ram; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00040000>; + }; + partition@40000 { + label = "fsbl2"; + reg = <0x00040000 0x00040000>; + }; + partition@500000 { + label = "uboot"; + reg = <0x00080000 0x00160000>; + }; + partition@900000 { + label = "env1"; + reg = <0x001E0000 0x00010000>; + }; + partition@980000 { + label = "env2"; + reg = <0x001F0000 0x00010000>; + }; + }; }; &qspi { diff --git a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi index 98033b5..f36eec1 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-som.dtsi @@ -191,8 +191,12 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x200000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi index 804c662..eb905ad 100644 --- a/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15xx-dhcor-u-boot.dtsi @@ -28,6 +28,33 @@ &flash0 { bootph-pre-ram; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "fsbl1"; + reg = <0x00000000 0x00040000>; + }; + partition@40000 { + label = "fsbl2"; + reg = <0x00040000 0x00040000>; + }; + partition@500000 { + label = "uboot"; + reg = <0x00080000 0x00160000>; + }; + partition@900000 { + label = "env1"; + reg = <0x001E0000 0x00010000>; + }; + partition@980000 { + label = "env2"; + reg = <0x001F0000 0x00010000>; + }; + }; }; &i2c4 { diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 34af901..49b3e76 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -72,7 +72,7 @@ sound { compatible = "audio-graph-card"; - label = "STM32MP1-DK"; + label = "STM32MP15-DK"; routing = "Playback" , "MCLK", "Capture" , "MCLK", @@ -149,7 +149,7 @@ max-speed = <1000>; phy-handle = <&phy0>; - mdio0 { + mdio { #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; @@ -509,14 +509,12 @@ sai2a: audio-controller@4400b004 { #clock-cells = <0>; dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; status = "okay"; sai2a_port: port { sai2a_endpoint: endpoint { remote-endpoint = <&cs42l51_tx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; @@ -534,7 +532,7 @@ sai2b_port: port { sai2b_endpoint: endpoint { remote-endpoint = <&cs42l51_rx_endpoint>; - format = "i2s"; + dai-format = "i2s"; mclk-fs = <256>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <32>; diff --git a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi index 9f9837b..9957646 100644 --- a/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi +++ b/arch/arm/dts/synquacer-sc2a11-developerbox-u-boot.dtsi @@ -21,7 +21,7 @@ #size-cells = <0>; status = "okay"; - flash@0 { + flash0: flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; @@ -74,8 +74,24 @@ }; partition@500000 { - label = "Ex-OPTEE"; - reg = <0x500000 0x200000>; + label = "MDATA-Pri"; + reg = <0x500000 0x1000>; + }; + + partition@530000 { + label = "MDATA-Sec"; + reg = <0x530000 0x1000>; + }; + + /* FWU Multi bank update partitions */ + partition@600000 { + label = "FIP-Bank0"; + reg = <0x600000 0x400000>; + }; + + partition@a00000 { + label = "FIP-Bank1"; + reg = <0xa00000 0x400000>; }; }; }; @@ -102,6 +118,33 @@ optee { status = "okay"; }; + + fwu-mdata { + compatible = "u-boot,fwu-mdata-mtd"; + fwu-mdata-store = <&flash0>; + mdata-parts = "MDATA-Pri", "MDATA-Sec"; + + fwu-bank0 { + id = <0>; + label = "FIP-Bank0"; + fwu-image0 { + id = <0>; + offset = <0x0>; + size = <0x400000>; + uuid = "5a66a702-99fd-4fef-a392-c26e261a2828"; + }; + }; + fwu-bank1 { + id = <1>; + label = "FIP-Bank1"; + fwu-image0 { + id = <0>; + offset = <0x0>; + size = <0x400000>; + uuid = "a8f868a1-6e5c-4757-878d-ce63375ef2c0"; + }; + }; + }; }; }; diff --git a/arch/arm/include/asm/arch-am33xx/clock.h b/arch/arm/include/asm/arch-am33xx/clock.h index ad25b3e..67400c2 100644 --- a/arch/arm/include/asm/arch-am33xx/clock.h +++ b/arch/arm/include/asm/arch-am33xx/clock.h @@ -13,10 +13,6 @@ #include <asm/arch/clocks_am33xx.h> #include <asm/arch/hardware.h> -#if defined(CONFIG_TI816X) -#include <asm/arch/clock_ti81xx.h> -#endif - #define LDELAY 1000000 /*CM_<clock_domain>__CLKCTRL */ diff --git a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h b/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h deleted file mode 100644 index d22d958..0000000 --- a/arch/arm/include/asm/arch-am33xx/clock_ti81xx.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * ti81xx.h - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - * - * This file is released under the terms of GPL v2 and any later version. - * See the file COPYING in the root directory of the source tree for details. - */ - -#ifndef _CLOCK_TI81XX_H_ -#define _CLOCK_TI81XX_H_ - -#define PRCM_MOD_EN 0x2 - -#define CM_DEFAULT_BASE (PRCM_BASE + 0x0500) -#define CM_ALWON_BASE (PRCM_BASE + 0x1400) - -struct cm_def { - unsigned int resv0[2]; - unsigned int l3fastclkstctrl; - unsigned int resv1[1]; - unsigned int pciclkstctrl; - unsigned int resv2[1]; - unsigned int ducaticlkstctrl; - unsigned int resv3[1]; - unsigned int emif0clkctrl; - unsigned int emif1clkctrl; - unsigned int dmmclkctrl; - unsigned int fwclkctrl; - unsigned int resv4[10]; - unsigned int usbclkctrl; - unsigned int resv5[1]; - unsigned int sataclkctrl; - unsigned int resv6[4]; - unsigned int ducaticlkctrl; - unsigned int pciclkctrl; -}; - -struct cm_alwon { - unsigned int l3slowclkstctrl; - unsigned int ethclkstctrl; - unsigned int l3medclkstctrl; - unsigned int mmu_clkstctrl; - unsigned int mmucfg_clkstctrl; - unsigned int ocmc0clkstctrl; -#if defined(CONFIG_TI816X) - unsigned int ocmc1clkstctrl; -#endif - unsigned int mpuclkstctrl; - unsigned int sysclk4clkstctrl; - unsigned int sysclk5clkstctrl; - unsigned int sysclk6clkstctrl; - unsigned int rtcclkstctrl; - unsigned int l3fastclkstctrl; - unsigned int resv0[67]; - unsigned int mcasp0clkctrl; - unsigned int mcasp1clkctrl; - unsigned int mcasp2clkctrl; - unsigned int mcbspclkctrl; - unsigned int uart0clkctrl; - unsigned int uart1clkctrl; - unsigned int uart2clkctrl; - unsigned int gpio0clkctrl; - unsigned int gpio1clkctrl; - unsigned int i2c0clkctrl; - unsigned int i2c1clkctrl; -#if defined(CONFIG_TI816X) - unsigned int resv1[1]; - unsigned int timer1clkctrl; - unsigned int timer2clkctrl; - unsigned int timer3clkctrl; - unsigned int timer4clkctrl; - unsigned int timer5clkctrl; - unsigned int timer6clkctrl; - unsigned int timer7clkctrl; -#endif - unsigned int wdtimerclkctrl; - unsigned int spiclkctrl; - unsigned int mailboxclkctrl; - unsigned int spinboxclkctrl; - unsigned int mmudataclkctrl; - unsigned int resv2[2]; - unsigned int mmucfgclkctrl; -#if defined(CONFIG_TI816X) - unsigned int resv3[1]; - unsigned int sdioclkctrl; -#endif - unsigned int ocmc0clkctrl; -#if defined(CONFIG_TI816X) - unsigned int ocmc1clkctrl; -#endif - unsigned int resv4[2]; - unsigned int controlclkctrl; - unsigned int resv5[2]; - unsigned int gpmcclkctrl; - unsigned int ethernet0clkctrl; - unsigned int ethernet1clkctrl; - unsigned int mpuclkctrl; -#if defined(CONFIG_TI816X) - unsigned int resv6[1]; -#endif - unsigned int l3clkctrl; - unsigned int l4hsclkctrl; - unsigned int l4lsclkctrl; - unsigned int rtcclkctrl; - unsigned int tpccclkctrl; - unsigned int tptc0clkctrl; - unsigned int tptc1clkctrl; - unsigned int tptc2clkctrl; - unsigned int tptc3clkctrl; -#if defined(CONFIG_TI816X) - unsigned int sr0clkctrl; - unsigned int sr1clkctrl; -#endif -}; - -#endif /* _CLOCK_TI81XX_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 15a5b64..1a03107 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -369,15 +369,9 @@ struct ddr_ctrl { unsigned int ddrckectrl; }; -#ifdef CONFIG_TI816X -void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, - const struct emif_regs *regs, - const struct dmm_lisa_map_regs *lisa_regs, int nrs); -#else void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, const struct ddr_data *data, const struct cmd_control *ctrl, const struct emif_regs *regs, int nr); -#endif void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); #endif /* _DDR_DEFS_H */ diff --git a/arch/arm/include/asm/arch-am33xx/emac_defs.h b/arch/arm/include/asm/arch-am33xx/emac_defs.h deleted file mode 100644 index eb6516d..0000000 --- a/arch/arm/include/asm/arch-am33xx/emac_defs.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 Texas Instruments - * - * Based on: - * - * ---------------------------------------------------------------------------- - * - * dm644x_emac.h - * - * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM - * - * Copyright (C) 2005 Texas Instruments. - * - * ---------------------------------------------------------------------------- - * - */ - -#ifndef _EMAC_DEFS_H_ -#define _EMAC_DEFS_H_ - -#ifdef CONFIG_TI816X -#define EMAC_BASE_ADDR (0x4A100000) -#define EMAC_WRAPPER_BASE_ADDR (0x4A100900) -#define EMAC_WRAPPER_RAM_ADDR (0x4A102000) -#define EMAC_MDIO_BASE_ADDR (0x4A100800) -#define EMAC_MDIO_BUS_FREQ (250000000UL) -#define EMAC_MDIO_CLOCK_FREQ (2000000UL) - -typedef volatile unsigned int dv_reg; -typedef volatile unsigned int *dv_reg_p; - -#define DAVINCI_EMAC_VERSION2 -#define DAVINCI_EMAC_GIG_ENABLE -#endif - -#endif /* _EMAC_DEFS_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/hardware.h b/arch/arm/include/asm/arch-am33xx/hardware.h index 2d7f9da..387f053 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware.h +++ b/arch/arm/include/asm/arch-am33xx/hardware.h @@ -14,8 +14,6 @@ #include <asm/arch/omap.h> #ifdef CONFIG_AM33XX #include <asm/arch/hardware_am33xx.h> -#elif defined(CONFIG_TI816X) -#include <asm/arch/hardware_ti816x.h> #elif defined(CONFIG_AM43XX) #include <asm/arch/hardware_am43xx.h> #endif diff --git a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h b/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h deleted file mode 100644 index 78b7948..0000000 --- a/arch/arm/include/asm/arch-am33xx/hardware_ti816x.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * hardware_ti816x.h - * - * TI816x hardware specific header - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - * Based on TI-PSP-04.00.02.14 - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __AM33XX_HARDWARE_TI816X_H -#define __AM33XX_HARDWARE_TI816X_H - -/* UART */ -#define UART0_BASE 0x48020000 -#define UART1_BASE 0x48022000 -#define UART2_BASE 0x48024000 - -/* Watchdog Timer */ -#define WDT_BASE 0x480C2000 - -/* Control Module Base Address */ -#define CTRL_BASE 0x48140000 -#define CTRL_DEVICE_BASE 0x48140600 - -/* PRCM Base Address */ -#define PRCM_BASE 0x48180000 - -#define PRM_RSTCTRL (PRCM_BASE + 0x00A0) -#define PRM_RSTST (PRM_RSTCTRL + 8) - -/* VTP Base address */ -#define VTP0_CTRL_ADDR 0x48198358 -#define VTP1_CTRL_ADDR 0x4819A358 - -/* DDR Base address */ -#define DDR_PHY_CMD_ADDR 0x48198000 -#define DDR_PHY_DATA_ADDR 0x481980C8 -#define DDR_PHY_CMD_ADDR2 0x4819A000 -#define DDR_PHY_DATA_ADDR2 0x4819A0C8 -#define DDR_DATA_REGS_NR 4 - - -#define DDRPHY_0_CONFIG_BASE 0x48198000 -#define DDRPHY_1_CONFIG_BASE 0x4819A000 -#define DDRPHY_CONFIG_BASE ((emif == 0) ? \ - DDRPHY_0_CONFIG_BASE : DDRPHY_1_CONFIG_BASE) - -/* RTC base address */ -#define RTC_BASE 0x480C0000 - -#endif /* __AM33XX_HARDWARE_TI816X_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index ed15d15..b1b1896 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -24,9 +24,4 @@ #define OMAP_HSMMC1_BASE 0x48060000 #define OMAP_HSMMC2_BASE 0x481D8000 -#if defined(CONFIG_TI816X) -#undef MMC_CLOCK_REFERENCE -#define MMC_CLOCK_REFERENCE 48 /* MHz */ -#endif - #endif /* MMC_HOST_DEF_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mux.h b/arch/arm/include/asm/arch-am33xx/mux.h index 7cf9737..ebb2d30 100644 --- a/arch/arm/include/asm/arch-am33xx/mux.h +++ b/arch/arm/include/asm/arch-am33xx/mux.h @@ -20,8 +20,6 @@ #ifdef CONFIG_AM33XX #include <asm/arch/mux_am33xx.h> -#elif defined(CONFIG_TI816X) -#include <asm/arch/mux_ti816x.h> #elif defined(CONFIG_AM43XX) #include <asm/arch/mux_am43xx.h> #endif diff --git a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h b/arch/arm/include/asm/arch-am33xx/mux_ti816x.h deleted file mode 100644 index a6a8a98..0000000 --- a/arch/arm/include/asm/arch-am33xx/mux_ti816x.h +++ /dev/null @@ -1,362 +0,0 @@ -/* - * mux_ti816x.h - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. - * - * This program is distributed "as is" WITHOUT ANY WARRANTY of any - * kind, whether express or implied; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MUX_TI816X_H_ -#define _MUX_TI816X_H_ - -#include <asm/io.h> - -#define MUX_CFG(value, offset) \ - __raw_writel(value, (CTRL_BASE + offset)); - -#define PULLDOWN_EN (0x0 << 4) /* Pull Down Selection */ -#define PULLUP_EN (0x1 << 4) /* Pull Up Selection */ -#define PULLUDEN (0x0 << 3) /* Pull up enabled */ -#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ -#define MODE(val) (val) /* used for Readability */ - - -/* - * PAD CONTROL OFFSETS - * Field names corresponds to the pad signal name - */ -struct pad_signals { - int pincntl1; - int pincntl2; - int pincntl3; - int pincntl4; - int pincntl5; - int pincntl6; - int pincntl7; - int pincntl8; - int pincntl9; - int pincntl10; - int pincntl11; - int pincntl12; - int pincntl13; - int pincntl14; - int pincntl15; - int pincntl16; - int pincntl17; - int pincntl18; - int pincntl19; - int pincntl20; - int pincntl21; - int pincntl22; - int pincntl23; - int pincntl24; - int pincntl25; - int pincntl26; - int pincntl27; - int pincntl28; - int pincntl29; - int pincntl30; - int pincntl31; - int pincntl32; - int pincntl33; - int pincntl34; - int pincntl35; - int pincntl36; - int pincntl37; - int pincntl38; - int pincntl39; - int pincntl40; - int pincntl41; - int pincntl42; - int pincntl43; - int pincntl44; - int pincntl45; - int pincntl46; - int pincntl47; - int pincntl48; - int pincntl49; - int pincntl50; - int pincntl51; - int pincntl52; - int pincntl53; - int pincntl54; - int pincntl55; - int pincntl56; - int pincntl57; - int pincntl58; - int pincntl59; - int pincntl60; - int pincntl61; - int pincntl62; - int pincntl63; - int pincntl64; - int pincntl65; - int pincntl66; - int pincntl67; - int pincntl68; - int pincntl69; - int pincntl70; - int pincntl71; - int pincntl72; - int pincntl73; - int pincntl74; - int pincntl75; - int pincntl76; - int pincntl77; - int pincntl78; - int pincntl79; - int pincntl80; - int pincntl81; - int pincntl82; - int pincntl83; - int pincntl84; - int pincntl85; - int pincntl86; - int pincntl87; - int pincntl88; - int pincntl89; - int pincntl90; - int pincntl91; - int pincntl92; - int pincntl93; - int pincntl94; - int pincntl95; - int pincntl96; - int pincntl97; - int pincntl98; - int pincntl99; - int pincntl100; - int pincntl101; - int pincntl102; - int pincntl103; - int pincntl104; - int pincntl105; - int pincntl106; - int pincntl107; - int pincntl108; - int pincntl109; - int pincntl110; - int pincntl111; - int pincntl112; - int pincntl113; - int pincntl114; - int pincntl115; - int pincntl116; - int pincntl117; - int pincntl118; - int pincntl119; - int pincntl120; - int pincntl121; - int pincntl122; - int pincntl123; - int pincntl124; - int pincntl125; - int pincntl126; - int pincntl127; - int pincntl128; - int pincntl129; - int pincntl130; - int pincntl131; - int pincntl132; - int pincntl133; - int pincntl134; - int pincntl135; - int pincntl136; - int pincntl137; - int pincntl138; - int pincntl139; - int pincntl140; - int pincntl141; - int pincntl142; - int pincntl143; - int pincntl144; - int pincntl145; - int pincntl146; - int pincntl147; - int pincntl148; - int pincntl149; - int pincntl150; - int pincntl151; - int pincntl152; - int pincntl153; - int pincntl154; - int pincntl155; - int pincntl156; - int pincntl157; - int pincntl158; - int pincntl159; - int pincntl160; - int pincntl161; - int pincntl162; - int pincntl163; - int pincntl164; - int pincntl165; - int pincntl166; - int pincntl167; - int pincntl168; - int pincntl169; - int pincntl170; - int pincntl171; - int pincntl172; - int pincntl173; - int pincntl174; - int pincntl175; - int pincntl176; - int pincntl177; - int pincntl178; - int pincntl179; - int pincntl180; - int pincntl181; - int pincntl182; - int pincntl183; - int pincntl184; - int pincntl185; - int pincntl186; - int pincntl187; - int pincntl188; - int pincntl189; - int pincntl190; - int pincntl191; - int pincntl192; - int pincntl193; - int pincntl194; - int pincntl195; - int pincntl196; - int pincntl197; - int pincntl198; - int pincntl199; - int pincntl200; - int pincntl201; - int pincntl202; - int pincntl203; - int pincntl204; - int pincntl205; - int pincntl206; - int pincntl207; - int pincntl208; - int pincntl209; - int pincntl210; - int pincntl211; - int pincntl212; - int pincntl213; - int pincntl214; - int pincntl215; - int pincntl216; - int pincntl217; - int pincntl218; - int pincntl219; - int pincntl220; - int pincntl221; - int pincntl222; - int pincntl223; - int pincntl224; - int pincntl225; - int pincntl226; - int pincntl227; - int pincntl228; - int pincntl229; - int pincntl230; - int pincntl231; - int pincntl232; - int pincntl233; - int pincntl234; - int pincntl235; - int pincntl236; - int pincntl237; - int pincntl238; - int pincntl239; - int pincntl240; - int pincntl241; - int pincntl242; - int pincntl243; - int pincntl244; - int pincntl245; - int pincntl246; - int pincntl247; - int pincntl248; - int pincntl249; - int pincntl250; - int pincntl251; - int pincntl252; - int pincntl253; - int pincntl254; - int pincntl255; - int pincntl256; - int pincntl257; - int pincntl258; - int pincntl259; - int pincntl260; - int pincntl261; - int pincntl262; - int pincntl263; - int pincntl264; - int pincntl265; - int pincntl266; - int pincntl267; - int pincntl268; - int pincntl269; - int pincntl270; - int pincntl271; - int pincntl272; - int pincntl273; - int pincntl274; - int pincntl275; - int pincntl276; - int pincntl277; - int pincntl278; - int pincntl279; - int pincntl280; - int pincntl281; - int pincntl282; - int pincntl283; - int pincntl284; - int pincntl285; - int pincntl286; - int pincntl287; - int pincntl288; - int pincntl289; - int pincntl290; - int pincntl291; - int pincntl292; - int pincntl293; - int pincntl294; - int pincntl295; - int pincntl296; - int pincntl297; - int pincntl298; - int pincntl299; - int pincntl300; - int pincntl301; - int pincntl302; - int pincntl303; - int pincntl304; - int pincntl305; - int pincntl306; - int pincntl307; - int pincntl308; - int pincntl309; - int pincntl310; - int pincntl311; - int pincntl312; - int pincntl313; - int pincntl314; - int pincntl315; - int pincntl316; - int pincntl317; - int pincntl318; - int pincntl319; - int pincntl320; - int pincntl321; - int pincntl322; - int pincntl323; -}; - -#endif /* endif _MUX_TI816X_H_ */ diff --git a/arch/arm/include/asm/arch-am33xx/omap.h b/arch/arm/include/asm/arch-am33xx/omap.h index 4c71dbf..53046de 100644 --- a/arch/arm/include/asm/arch-am33xx/omap.h +++ b/arch/arm/include/asm/arch-am33xx/omap.h @@ -20,10 +20,6 @@ #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40310000 #define NON_SECURE_SRAM_IMG_END 0x4030B800 -#elif defined(CONFIG_TI816X) -#define NON_SECURE_SRAM_START 0x40300000 -#define NON_SECURE_SRAM_END 0x40320000 -#define NON_SECURE_SRAM_IMG_END 0x4031B800 #elif defined(CONFIG_AM43XX) #define NON_SECURE_SRAM_START 0x402F0400 #define NON_SECURE_SRAM_END 0x40340000 diff --git a/arch/arm/include/asm/arch-am33xx/spl.h b/arch/arm/include/asm/arch-am33xx/spl.h index 6bd3ca0..9ddb346 100644 --- a/arch/arm/include/asm/arch-am33xx/spl.h +++ b/arch/arm/include/asm/arch-am33xx/spl.h @@ -9,19 +9,7 @@ #define BOOT_DEVICE_NONE 0x00 #define BOOT_DEVICE_MMC2_2 0xFF -#if defined(CONFIG_TI816X) -#define BOOT_DEVICE_XIP 0x01 -#define BOOT_DEVICE_XIPWAIT 0x02 -#define BOOT_DEVICE_NAND 0x03 -#define BOOT_DEVICE_ONENAND 0x04 -#define BOOT_DEVICE_MMC2 0x05 /* ROM only supports 2nd instance. */ -#define BOOT_DEVICE_MMC1 0x06 -#define BOOT_DEVICE_UART 0x43 -#define BOOT_DEVICE_USB 0x45 - -#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2 -#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1 -#elif defined(CONFIG_AM33XX) +#if defined(CONFIG_AM33XX) #define BOOT_DEVICE_XIP 0x01 #define BOOT_DEVICE_XIPWAIT 0x02 #define BOOT_DEVICE_NAND 0x05 diff --git a/arch/arm/include/asm/arch-bcmcygnus/configs.h b/arch/arm/include/asm/arch-bcmcygnus/configs.h deleted file mode 100644 index fd8dad3..0000000 --- a/arch/arm/include/asm/arch-bcmcygnus/configs.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014-2017 Broadcom. - */ - -#ifndef __ARCH_CONFIGS_H -#define __ARCH_CONFIGS_H - -#include <asm/iproc-common/configs.h> - -/* uArchitecture specifics */ - -/* Serial Info */ -#define CFG_SYS_NS16550_CLK 100000000 -#define CFG_SYS_NS16550_CLK_DIV 54 -#define CFG_SYS_NS16550_COM3 0x18023000 - -#endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-bcmnsp/configs.h b/arch/arm/include/asm/arch-bcmnsp/configs.h deleted file mode 100644 index 0d4baf3..0000000 --- a/arch/arm/include/asm/arch-bcmnsp/configs.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#ifndef __ARCH_CONFIGS_H -#define __ARCH_CONFIGS_H - -#include <asm/iproc-common/configs.h> - -/* uArchitecture specifics */ - -/* Serial Info */ -#define CFG_SYS_NS16550_CLK 0x03b9aca0 -#define CFG_SYS_NS16550_COM1 0x18000300 - -#endif /* __ARCH_CONFIGS_H */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h index 1b02d48..c18c51e 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h @@ -22,7 +22,7 @@ * * -PCIe * -there is a range of stream IDs set aside for PCI in this - * file. U-boot will scan the PCI bus and for each device discovered: + * file. U-Boot will scan the PCI bus and for each device discovered: * -allocate a streamID * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' * -set a msi-map entry in the PEXn controller node in the diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index b36b6d38..140849d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -23,7 +23,7 @@ * * -PCIe * -there is a range of stream IDs set aside for PCI in this - * file. U-boot will scan the PCI bus and for each device discovered: + * file. U-Boot will scan the PCI bus and for each device discovered: * -allocate a streamID * -set a PEXn LUT table entry mapping 'requester ID' to 'stream ID' * -set a msi-map entry in the PEXn controller node in the diff --git a/arch/arm/include/asm/arch-imx8m/sys_proto.h b/arch/arm/include/asm/arch-imx8m/sys_proto.h index 55b46af..4ed8e95 100644 --- a/arch/arm/include/asm/arch-imx8m/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8m/sys_proto.h @@ -4,7 +4,7 @@ */ #ifndef __ARCH_IMX8M_SYS_PROTO_H -#define __ARCH_NMX8M_SYS_PROTO_H +#define __ARCH_IMX8M_SYS_PROTO_H #include <asm/mach-imx/sys_proto.h> #include <asm/arch/imx-regs.h> diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index 5bbae21..95bf753 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -4,7 +4,7 @@ */ #ifndef __ARCH_IMX8ULP_SYS_PROTO_H -#define __ARCH_NMX8ULP_SYS_PROTO_H +#define __ARCH_IMX8ULP_SYS_PROTO_H #include <asm/mach-imx/sys_proto.h> diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h index ba97f92..2f7a129 100644 --- a/arch/arm/include/asm/arch-imx9/sys_proto.h +++ b/arch/arm/include/asm/arch-imx9/sys_proto.h @@ -4,7 +4,7 @@ */ #ifndef __ARCH_IMX9_SYS_PROTO_H -#define __ARCH_NMX9_SYS_PROTO_H +#define __ARCH_IMX9_SYS_PROTO_H #include <asm/mach-imx/sys_proto.h> diff --git a/arch/arm/include/asm/arch-imxrt/imxrt.h b/arch/arm/include/asm/arch-imxrt/imxrt.h deleted file mode 100644 index 14f7c76..0000000 --- a/arch/arm/include/asm/arch-imxrt/imxrt.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2019 - * Author(s): Giulio Benetti <giulio.benetti@benettiengineering.com> - */ - -#ifndef _ASM_ARCH_IMXRT_H -#define _ASM_ARCH_IMXRT_H - -#endif /* _ASM_ARCH_IMXRT_H */ diff --git a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h b/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h deleted file mode 100644 index 762bbee..0000000 --- a/arch/arm/include/asm/arch-lpc32xx/gpio_grp.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * LPC32xx GPIO interface macro for pin mapping. - * - * (C) Copyright 2015 DENX Software Engineering GmbH - * Written-by: Sylvain Lemieux <slemieux@@tycoint.com> - */ - -#ifndef _LPC32XX_GPIO_GRP_H -#define _LPC32XX_GPIO_GRP_H - -/* - * Macro to map the pin for the lpc32xx_gpio driver. - * Note: - GPIOS are considered here as homogeneous and linear from 0 to 159; - * mapping is done per register, as group of 32. - * (see drivers/gpio/lpc32xx_gpio.c for details). - * - macros can be use with the following pins: - * P0.0 - P0.7 - * P1.0 - P1.23 - * P2.0 - P2.12 - * P3 GPI_0 - GPI_9 / GPI_15 - GPI_23 / GPI_25 / GPI_27 - GPI_28 - * P3 GPO_0 - GPO_23 - * P3 GPIO_0 - GPIO_5 (output register only) - */ -#define LPC32XX_GPIO_P0_GRP 0 -#define LPC32XX_GPIO_P1_GRP 32 -#define LPC32XX_GPIO_P2_GRP 64 -#define LPC32XX_GPO_P3_GRP 96 -#define LPC32XX_GPIO_P3_GRP (LPC32XX_GPO_P3_GRP + 25) -#define LPC32XX_GPI_P3_GRP 128 - -/* - * A specific GPIO can be selected with this macro - * ie, GPIO P0.1 can be selected with LPC32XX_GPIO(LPC32XX_GPIO_P0_GRP, 1) - * See the LPC32x0 User's guide for GPIO group numbers - */ -#define LPC32XX_GPIO(x, y) ((x) + (y)) - -#endif /* _LPC32XX_GPIO_GRP_H */ diff --git a/arch/arm/include/asm/arch-meson/a1.h b/arch/arm/include/asm/arch-meson/a1.h new file mode 100644 index 0000000..86d1a68 --- /dev/null +++ b/arch/arm/include/asm/arch-meson/a1.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2023 SberDevices, Inc. + * Author: Igor Prusov <ivprusov@sberdevices.ru> + */ + +#ifndef __MESON_A1_H__ +#define __MESON_A1_H__ + +#define A1_SYSCTRL_BASE 0xfe005800 + +/* SYSCTRL registers */ +#define A1_SYSCTRL_ADDR(off) (A1_SYSCTRL_BASE + ((off) << 2)) + +#define A1_SYSCTRL_SEC_STATUS_REG4 A1_SYSCTRL_ADDR(0xc4) + +#define A1_SYSCTRL_MEM_SIZE_MASK 0xFFFF0000 +#define A1_SYSCTRL_MEM_SIZE_SHIFT 16 + +#endif /* __MESON_A1_H__ */ diff --git a/arch/arm/include/asm/arch-meson/sm.h b/arch/arm/include/asm/arch-meson/sm.h index 53b7517..4b1d564 100644 --- a/arch/arm/include/asm/arch-meson/sm.h +++ b/arch/arm/include/asm/arch-meson/sm.h @@ -58,4 +58,34 @@ enum { */ int meson_sm_get_reboot_reason(void); +#define PWRDM_OFF 0 +#define PWRDM_ON 1 + +/** + * meson_sm_pwrdm_set - do command at specified power domain. + * + * @index: power domain index. + * @cmd: command index. + * @return: zero on success or error code on failure. + */ +int meson_sm_pwrdm_set(size_t index, int cmd); + +/** + * meson_sm_pwrdm_off - disable specified power domain. + * + * @index: power domain index. + * @return: zero on success or error code on failure. + */ +#define meson_sm_pwrdm_off(index) \ + meson_sm_pwrdm_set(index, PWRDM_OFF) + +/** + * meson_sm_pwrdm_on - enable specified power domain. + * + * @index: power domain index. + * @return: zero on success or error code on failure. + */ +#define meson_sm_pwrdm_on(index) \ + meson_sm_pwrdm_set(index, PWRDM_ON) + #endif /* __MESON_SM_H__ */ diff --git a/arch/arm/include/asm/arch-mx27/mxcmmc.h b/arch/arm/include/asm/arch-mx27/mxcmmc.h deleted file mode 100644 index 52fb0ab..0000000 --- a/arch/arm/include/asm/arch-mx27/mxcmmc.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com> - */ - -#ifndef ASM_ARCH_MXCMMC_H -#define ASM_ARCH_MXCMMC_H - -int mxc_mmc_init(struct bd_info *bis); - -#endif diff --git a/arch/arm/include/asm/arch-mx6/opos6ul.h b/arch/arm/include/asm/arch-mx6/opos6ul.h deleted file mode 100644 index b55a54c..0000000 --- a/arch/arm/include/asm/arch-mx6/opos6ul.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2017 Armadeus Systems - */ - -#ifndef __ARCH_ARM_MX6UL_OPOS6UL_H__ -#define __ARCH_ARM_MX6UL_OPOS6UL_H__ - -int opos6ul_board_late_init(void); - -#endif diff --git a/arch/arm/include/asm/arch-mxs/regs-uartapp.h b/arch/arm/include/asm/arch-mxs/regs-uartapp.h deleted file mode 100644 index d89cf27..0000000 --- a/arch/arm/include/asm/arch-mxs/regs-uartapp.h +++ /dev/null @@ -1,219 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Freescale MXS UARTAPP Register Definitions - * - * Copyright (C) 2013 Andreas Wass <andreas.wass@dalelven.com> - * - * Based on code from LTIB: - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ARCH_ARM___MXS_UARTAPP_H -#define __ARCH_ARM___MXS_UARTAPP_H - -#include <asm/mach-imx/regs-common.h> - -#ifndef __ASSEMBLY__ -struct mxs_uartapp_regs { - mxs_reg_32(hw_uartapp_ctrl0) - mxs_reg_32(hw_uartapp_ctrl1) - mxs_reg_32(hw_uartapp_ctrl2) - mxs_reg_32(hw_uartapp_linectrl) - mxs_reg_32(hw_uartapp_linectrl2) - mxs_reg_32(hw_uartapp_intr) - mxs_reg_32(hw_uartapp_data) - mxs_reg_32(hw_uartapp_stat) - mxs_reg_32(hw_uartapp_debug) - mxs_reg_32(hw_uartapp_version) - mxs_reg_32(hw_uartapp_autobaud) -}; -#endif - -#define UARTAPP_CTRL0_SFTRST_MASK (1 << 31) -#define UARTAPP_CTRL0_CLKGATE_MASK (1 << 30) -#define UARTAPP_CTRL0_RUN_MASK (1 << 29) -#define UARTAPP_CTRL0_RX_SOURCE_MASK (1 << 28) -#define UARTAPP_CTRL0_RXTO_ENABLE_MASK (1 << 27) -#define UARTAPP_CTRL0_RXTIMEOUT_OFFSET 16 -#define UARTAPP_CTRL0_RXTIMEOUT_MASK (0x7FF << 16) -#define UARTAPP_CTRL0_XFER_COUNT_OFFSET 0 -#define UARTAPP_CTRL0_XFER_COUNT_MASK 0xFFFF - -#define UARTAPP_CTRL1_RUN_MASK (1 << 28) - -#define UARTAPP_CTRL1_XFER_COUNT_OFFSET 0 -#define UARTAPP_CTRL1_XFER_COUNT_MASK 0xFFFF - -#define UARTAPP_CTRL2_INVERT_RTS_MASK (1 << 31) -#define UARTAPP_CTRL2_INVERT_CTS_MASK (1 << 30) -#define UARTAPP_CTRL2_INVERT_TX_MASK (1 << 29) -#define UARTAPP_CTRL2_INVERT_RX_MASK (1 << 28) -#define UARTAPP_CTRL2_RTS_SEMAPHORE_MASK (1 << 27) -#define UARTAPP_CTRL2_DMAONERR_MASK (1 << 26) -#define UARTAPP_CTRL2_TXDMAE_MASK (1 << 25) -#define UARTAPP_CTRL2_RXDMAE_MASK (1 << 24) -#define UARTAPP_CTRL2_RXIFLSEL_OFFSET 20 -#define UARTAPP_CTRL2_RXIFLSEL_MASK (0x7 << 20) - -#define UARTAPP_CTRL2_RXIFLSEL_NOT_EMPTY (0x0 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_ONE_QUARTER (0x1 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_ONE_HALF (0x2 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_THREE_QUARTERS (0x3 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_SEVEN_EIGHTHS (0x4 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID5 (0x5 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID6 (0x6 << 20) -#define UARTAPP_CTRL2_RXIFLSEL_INVALID7 (0x7 << 20) -#define UARTAPP_CTRL2_TXIFLSEL_OFFSET 16 -#define UARTAPP_CTRL2_TXIFLSEL_MASK (0x7 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_EMPTY (0x0 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_ONE_QUARTER (0x1 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_ONE_HALF (0x2 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_THREE_QUARTERS (0x3 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_SEVEN_EIGHTHS (0x4 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID5 (0x5 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID6 (0x6 << 16) -#define UARTAPP_CTRL2_TXIFLSEL_INVALID7 (0x7 << 16) -#define UARTAPP_CTRL2_CTSEN_MASK (1 << 15) -#define UARTAPP_CTRL2_RTSEN_MASK (1 << 14) -#define UARTAPP_CTRL2_OUT2_MASK (1 << 13) -#define UARTAPP_CTRL2_OUT1_MASK (1 << 12) -#define UARTAPP_CTRL2_RTS_MASK (1 << 11) -#define UARTAPP_CTRL2_DTR_MASK (1 << 10) -#define UARTAPP_CTRL2_RXE_MASK (1 << 9) -#define UARTAPP_CTRL2_TXE_MASK (1 << 8) -#define UARTAPP_CTRL2_LBE_MASK (1 << 7) -#define UARTAPP_CTRL2_USE_LCR2_MASK (1 << 6) - -#define UARTAPP_CTRL2_SIRLP_MASK (1 << 2) -#define UARTAPP_CTRL2_SIREN_MASK (1 << 1) -#define UARTAPP_CTRL2_UARTEN_MASK 0x01 - -#define UARTAPP_LINECTRL_BAUD_DIVINT_OFFSET 16 -#define UARTAPP_LINECTRL_BAUD_DIVINT_MASK (0xFFFF << 16) -#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVINT_OFFSET 6 - -#define UARTAPP_LINECTRL_BAUD_DIVFRAC_OFFSET 8 -#define UARTAPP_LINECTRL_BAUD_DIVFRAC_MASK (0x3F << 8) -#define UARTAPP_LINECTRL_EXTRACT_BAUD_DIVFRAC_MASK 0x3F - -#define UARTAPP_LINECTRL_SPS_MASK (1 << 7) -#define UARTAPP_LINECTRL_WLEN_OFFSET 5 -#define UARTAPP_LINECTRL_WLEN_MASK (0x03 << 5) -#define UARTAPP_LINECTRL_WLEN_5BITS (0x00 << 5) -#define UARTAPP_LINECTRL_WLEN_6BITS (0x01 << 5) -#define UARTAPP_LINECTRL_WLEN_7BITS (0x02 << 5) -#define UARTAPP_LINECTRL_WLEN_8BITS (0x03 << 5) - -#define UARTAPP_LINECTRL_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL_PEN_MASK (1 << 1) -#define UARTAPP_LINECTRL_BRK_MASK 1 - -#define UARTAPP_LINECTRL2_BAUD_DIVINT_OFFSET 16 -#define UARTAPP_LINECTRL2_BAUD_DIVINT_MASK (0xFFFF << 16) -#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVINT_OFFSET 6 - -#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_OFFSET 8 -#define UARTAPP_LINECTRL2_BAUD_DIVFRAC_MASK (0x3F << 8) -#define UARTAPP_LINECTRL2_EXTRACT_BAUD_DIVFRAC_MASK 0x3F - -#define UARTAPP_LINECTRL2_SPS_MASK (1 << 7) -#define UARTAPP_LINECTRL2_WLEN_OFFSET 5 -#define UARTAPP_LINECTRL2_WLEN_MASK (0x03 << 5) -#define UARTAPP_LINECTRL2_WLEN_5BITS (0x00 << 5) -#define UARTAPP_LINECTRL2_WLEN_6BITS (0x01 << 5) -#define UARTAPP_LINECTRL2_WLEN_7BITS (0x02 << 5) -#define UARTAPP_LINECTRL2_WLEN_8BITS (0x03 << 5) - -#define UARTAPP_LINECTRL2_FEN_MASK (1 << 4) -#define UARTAPP_LINECTRL2_STP2_MASK (1 << 3) -#define UARTAPP_LINECTRL2_EPS_MASK (1 << 2) -#define UARTAPP_LINECTRL2_PEN_MASK (1 << 1) - -#define UARTAPP_INTR_ABDIEN_MASK (1 << 27) -#define UARTAPP_INTR_OEIEN_MASK (1 << 26) -#define UARTAPP_INTR_BEIEN_MASK (1 << 25) -#define UARTAPP_INTR_PEIEN_MASK (1 << 24) -#define UARTAPP_INTR_FEIEN_MASK (1 << 23) -#define UARTAPP_INTR_RTIEN_MASK (1 << 22) -#define UARTAPP_INTR_TXIEN_MASK (1 << 21) -#define UARTAPP_INTR_RXIEN_MASK (1 << 20) -#define UARTAPP_INTR_DSRMIEN_MASK (1 << 19) -#define UARTAPP_INTR_DCDMIEN_MASK (1 << 18) -#define UARTAPP_INTR_CTSMIEN_MASK (1 << 17) -#define UARTAPP_INTR_RIMIEN_MASK (1 << 16) - -#define UARTAPP_INTR_ABDIS_MASK (1 << 11) -#define UARTAPP_INTR_OEIS_MASK (1 << 10) -#define UARTAPP_INTR_BEIS_MASK (1 << 9) -#define UARTAPP_INTR_PEIS_MASK (1 << 8) -#define UARTAPP_INTR_FEIS_MASK (1 << 7) -#define UARTAPP_INTR_RTIS_MASK (1 << 6) -#define UARTAPP_INTR_TXIS_MASK (1 << 5) -#define UARTAPP_INTR_RXIS_MASK (1 << 4) -#define UARTAPP_INTR_DSRMIS_MASK (1 << 3) -#define UARTAPP_INTR_DCDMIS_MASK (1 << 2) -#define UARTAPP_INTR_CTSMIS_MASK (1 << 1) -#define UARTAPP_INTR_RIMIS_MASK 0x1 - -#define UARTAPP_DATA_DATA_OFFSET 0 -#define UARTAPP_DATA_DATA_MASK 0xFFFFFFFF -#define UARTAPP_STAT_PRESENT_MASK (1 << 31) -#define UARTAPP_STAT_PRESENT_UNAVAILABLE (0x0 << 31) -#define UARTAPP_STAT_PRESENT_AVAILABLE (0x1 << 31) - -#define UARTAPP_STAT_HISPEED_MASK (1 << 30) -#define UARTAPP_STAT_HISPEED_UNAVAILABLE (0x0 << 30) -#define UARTAPP_STAT_HISPEED_AVAILABLE (0x1 << 30) - -#define UARTAPP_STAT_BUSY_MASK (1 << 29) -#define UARTAPP_STAT_CTS_MASK (1 << 28) -#define UARTAPP_STAT_TXFE_MASK (1 << 27) -#define UARTAPP_STAT_RXFF_MASK (1 << 26) -#define UARTAPP_STAT_TXFF_MASK (1 << 25) -#define UARTAPP_STAT_RXFE_MASK (1 << 24) -#define UARTAPP_STAT_RXBYTE_INVALID_OFFSET 20 -#define UARTAPP_STAT_RXBYTE_INVALID_MASK (0xF << 20) - -#define UARTAPP_STAT_OERR_MASK (1 << 19) -#define UARTAPP_STAT_BERR_MASK (1 << 18) -#define UARTAPP_STAT_PERR_MASK (1 << 17) -#define UARTAPP_STAT_FERR_MASK (1 << 16) -#define UARTAPP_STAT_RXCOUNT_OFFSET 0 -#define UARTAPP_STAT_RXCOUNT_MASK 0xFFFF - -#define UARTAPP_DEBUG_RXIBAUD_DIV_OFFSET 16 -#define UARTAPP_DEBUG_RXIBAUD_DIV_MASK (0xFFFF << 16) - -#define UARTAPP_DEBUG_RXFBAUD_DIV_OFFSET 10 -#define UARTAPP_DEBUG_RXFBAUD_DIV_MASK (0x3F << 10) - -#define UARTAPP_DEBUG_TXDMARUN_MASK (1 << 5) -#define UARTAPP_DEBUG_RXDMARUN_MASK (1 << 4) -#define UARTAPP_DEBUG_TXCMDEND_MASK (1 << 3) -#define UARTAPP_DEBUG_RXCMDEND_MASK (1 << 2) -#define UARTAPP_DEBUG_TXDMARQ_MASK (1 << 1) -#define UARTAPP_DEBUG_RXDMARQ_MASK 0x01 - -#define UARTAPP_VERSION_MAJOR_OFFSET 24 -#define UARTAPP_VERSION_MAJOR_MASK (0xFF << 24) - -#define UARTAPP_VERSION_MINOR_OFFSET 16 -#define UARTAPP_VERSION_MINOR_MASK (0xFF << 16) - -#define UARTAPP_VERSION_STEP_OFFSET 0 -#define UARTAPP_VERSION_STEP_MASK 0xFFFF - -#define UARTAPP_AUTOBAUD_REFCHAR1_OFFSET 24 -#define UARTAPP_AUTOBAUD_REFCHAR1_MASK (0xFF << 24) - -#define UARTAPP_AUTOBAUD_REFCHAR0_OFFSET 16 -#define UARTAPP_AUTOBAUD_REFCHAR0_MASK (0xFF << 16) - -#define UARTAPP_AUTOBAUD_UPDATE_TX_MASK (1 << 4) -#define UARTAPP_AUTOBAUD_TWO_REF_CHARS_MASK (1 << 3) -#define UARTAPP_AUTOBAUD_START_WITH_RUNBIT_MASK (1 << 2) -#define UARTAPP_AUTOBAUD_START_BAUD_DETECT_MASK (1 << 1) -#define UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE_MASK 0x01 -#endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/arch/arm/include/asm/arch-omap3/omap3-regs.h b/arch/arm/include/asm/arch-omap3/omap3-regs.h deleted file mode 100644 index 7b3c6c7..0000000 --- a/arch/arm/include/asm/arch-omap3/omap3-regs.h +++ /dev/null @@ -1,78 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (c) 2011 Comelit Group SpA, Luca Ceresoli <luca.ceresoli@comelit.it> - */ - -#ifndef _OMAP3_REGS_H -#define _OMAP3_REGS_H - -/* - * Register definitions for OMAP3 processors. - */ - -/* - * GPMC_CONFIG1 - GPMC_CONFIG7 - */ - -/* Values for GPMC_CONFIG1 - signal control parameters */ -#define WRAPBURST (1 << 31) -#define READMULTIPLE (1 << 30) -#define READTYPE (1 << 29) -#define WRITEMULTIPLE (1 << 28) -#define WRITETYPE (1 << 27) -#define CLKACTIVATIONTIME(x) (((x) & 3) << 25) -#define ATTACHEDDEVICEPAGELENGTH(x) (((x) & 3) << 23) -#define WAITREADMONITORING (1 << 22) -#define WAITWRITEMONITORING (1 << 21) -#define WAITMONITORINGTIME(x) (((x) & 3) << 18) -#define WAITPINSELECT(x) (((x) & 3) << 16) -#define DEVICESIZE(x) (((x) & 3) << 12) -#define DEVICESIZE_8BIT DEVICESIZE(0) -#define DEVICESIZE_16BIT DEVICESIZE(1) -#define DEVICETYPE(x) (((x) & 3) << 10) -#define DEVICETYPE_NOR DEVICETYPE(0) -#define DEVICETYPE_NAND DEVICETYPE(2) -#define MUXADDDATA (1 << 9) -#define TIMEPARAGRANULARITY (1 << 4) -#define GPMCFCLKDIVIDER(x) (((x) & 3) << 0) - -/* Values for GPMC_CONFIG2 - CS timing */ -#define CSWROFFTIME(x) (((x) & 0x1f) << 16) -#define CSRDOFFTIME(x) (((x) & 0x1f) << 8) -#define CSEXTRADELAY (1 << 7) -#define CSONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG3 - nADV timing */ -#define ADVWROFFTIME(x) (((x) & 0x1f) << 16) -#define ADVRDOFFTIME(x) (((x) & 0x1f) << 8) -#define ADVEXTRADELAY (1 << 7) -#define ADVONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG4 - nWE and nOE timing */ -#define WEOFFTIME(x) (((x) & 0x1f) << 24) -#define WEEXTRADELAY (1 << 23) -#define WEONTIME(x) (((x) & 0xf) << 16) -#define OEOFFTIME(x) (((x) & 0x1f) << 8) -#define OEEXTRADELAY (1 << 7) -#define OEONTIME(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG5 - RdAccessTime and CycleTime timing */ -#define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24) -#define RDACCESSTIME(x) (((x) & 0x1f) << 16) -#define WRCYCLETIME(x) (((x) & 0x1f) << 8) -#define RDCYCLETIME(x) (((x) & 0x1f) << 0) - -/* Values for GPMC_CONFIG6 - misc timings */ -#define WRACCESSTIME(x) (((x) & 0x1f) << 24) -#define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16) -#define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8) -#define CYCLE2CYCLESAMECSEN (1 << 7) -#define CYCLE2CYCLEDIFFCSEN (1 << 6) -#define BUSTURNAROUND(x) (((x) & 0xf) << 0) - -/* Values for GPMC_CONFIG7 - CS address mapping configuration */ -#define MASKADDRESS(x) (((x) & 0xf) << 8) -#define CSVALID (1 << 6) -#define BASEADDRESS(x) (((x) & 0x3f) << 0) - -#endif /* _OMAP3_REGS_H */ diff --git a/arch/arm/include/asm/arch-omap5/mux_omap5.h b/arch/arm/include/asm/arch-omap5/mux_omap5.h deleted file mode 100644 index 2460646..0000000 --- a/arch/arm/include/asm/arch-omap5/mux_omap5.h +++ /dev/null @@ -1,317 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2004-2009 - * Texas Instruments Incorporated - * Richard Woodruff <r-woodruff2@ti.com> - * Aneesh V <aneesh@ti.com> - * Balaji Krishnamoorthy <balajitk@ti.com> - */ -#ifndef _MUX_OMAP5_H_ -#define _MUX_OMAP5_H_ - -#include <asm/types.h> - -#ifdef CONFIG_OFF_PADCONF -#define OFF_PD (1 << 12) -#define OFF_PU (3 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (2 << 10) -#define OFF_IN (1 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (1 << 9) -#else -#define OFF_PD (0 << 12) -#define OFF_PU (0 << 12) -#define OFF_OUT_PTD (0 << 10) -#define OFF_OUT_PTU (0 << 10) -#define OFF_IN (0 << 10) -#define OFF_OUT (0 << 10) -#define OFF_EN (0 << 9) -#endif - -#define IEN (1 << 8) -#define IDIS (0 << 8) -#define PTU (3 << 3) -#define PTD (1 << 3) -#define EN (1 << 3) -#define DIS (0 << 3) - -#define M0 0 -#define M1 1 -#define M2 2 -#define M3 3 -#define M4 4 -#define M5 5 -#define M6 6 -#define M7 7 - -#define SAFE_MODE M7 - -#ifdef CONFIG_OFF_PADCONF -#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) -#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) -#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) -#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) -#else -#define OFF_IN_PD 0 -#define OFF_IN_PU 0 -#define OFF_OUT_PD 0 -#define OFF_OUT_PU 0 -#endif - -#define CORE_REVISION 0x0000 -#define CORE_HWINFO 0x0004 -#define CORE_SYSCONFIG 0x0010 -#define EMMC_CLK 0x0040 -#define EMMC_CMD 0x0042 -#define EMMC_DATA0 0x0044 -#define EMMC_DATA1 0x0046 -#define EMMC_DATA2 0x0048 -#define EMMC_DATA3 0x004a -#define EMMC_DATA4 0x004c -#define EMMC_DATA5 0x004e -#define EMMC_DATA6 0x0050 -#define EMMC_DATA7 0x0052 -#define C2C_CLKOUT0 0x0054 -#define C2C_CLKOUT1 0x0056 -#define C2C_CLKIN0 0x0058 -#define C2C_CLKIN1 0x005a -#define C2C_DATAIN0 0x005c -#define C2C_DATAIN1 0x005e -#define C2C_DATAIN2 0x0060 -#define C2C_DATAIN3 0x0062 -#define C2C_DATAIN4 0x0064 -#define C2C_DATAIN5 0x0066 -#define C2C_DATAIN6 0x0068 -#define C2C_DATAIN7 0x006a -#define C2C_DATAOUT0 0x006c -#define C2C_DATAOUT1 0x006e -#define C2C_DATAOUT2 0x0070 -#define C2C_DATAOUT3 0x0072 -#define C2C_DATAOUT4 0x0074 -#define C2C_DATAOUT5 0x0076 -#define C2C_DATAOUT6 0x0078 -#define C2C_DATAOUT7 0x007a -#define C2C_DATA8 0x007c -#define C2C_DATA9 0x007e -#define C2C_DATA10 0x0080 -#define C2C_DATA11 0x0082 -#define C2C_DATA12 0x0084 -#define C2C_DATA13 0x0086 -#define C2C_DATA14 0x0088 -#define C2C_DATA15 0x008a -#define LLIA_WAKEREQOUT 0x008c -#define LLIB_WAKEREQOUT 0x008e -#define HSI1_ACREADY 0x0090 -#define HSI1_CAREADY 0x0092 -#define HSI1_ACWAKE 0x0094 -#define HSI1_CAWAKE 0x0096 -#define HSI1_ACFLAG 0x0098 -#define HSI1_ACDATA 0x009a -#define HSI1_CAFLAG 0x009c -#define HSI1_CADATA 0x009e -#define UART1_TX 0x00a0 -#define UART1_CTS 0x00a2 -#define UART1_RX 0x00a4 -#define UART1_RTS 0x00a6 -#define HSI2_CAREADY 0x00a8 -#define HSI2_ACREADY 0x00aa -#define HSI2_CAWAKE 0x00ac -#define HSI2_ACWAKE 0x00ae -#define HSI2_CAFLAG 0x00b0 -#define HSI2_CADATA 0x00b2 -#define HSI2_ACFLAG 0x00b4 -#define HSI2_ACDATA 0x00b6 -#define UART2_RTS 0x00b8 -#define UART2_CTS 0x00ba -#define UART2_RX 0x00bc -#define UART2_TX 0x00be -#define USBB1_HSIC_STROBE 0x00c0 -#define USBB1_HSIC_DATA 0x00c2 -#define USBB2_HSIC_STROBE 0x00c4 -#define USBB2_HSIC_DATA 0x00c6 -#define TIMER10_PWM_EVT 0x00c8 -#define DSIPORTA_TE0 0x00ca -#define DSIPORTA_LANE0X 0x00cc -#define DSIPORTA_LANE0Y 0x00ce -#define DSIPORTA_LANE1X 0x00d0 -#define DSIPORTA_LANE1Y 0x00d2 -#define DSIPORTA_LANE2X 0x00d4 -#define DSIPORTA_LANE2Y 0x00d6 -#define DSIPORTA_LANE3X 0x00d8 -#define DSIPORTA_LANE3Y 0x00da -#define DSIPORTA_LANE4X 0x00dc -#define DSIPORTA_LANE4Y 0x00de -#define DSIPORTC_LANE0X 0x00e0 -#define DSIPORTC_LANE0Y 0x00e2 -#define DSIPORTC_LANE1X 0x00e4 -#define DSIPORTC_LANE1Y 0x00e6 -#define DSIPORTC_LANE2X 0x00e8 -#define DSIPORTC_LANE2Y 0x00ea -#define DSIPORTC_LANE3X 0x00ec -#define DSIPORTC_LANE3Y 0x00ee -#define DSIPORTC_LANE4X 0x00f0 -#define DSIPORTC_LANE4Y 0x00f2 -#define DSIPORTC_TE0 0x00f4 -#define TIMER9_PWM_EVT 0x00f6 -#define I2C4_SCL 0x00f8 -#define I2C4_SDA 0x00fa -#define MCSPI2_CLK 0x00fc -#define MCSPI2_SIMO 0x00fe -#define MCSPI2_SOMI 0x0100 -#define MCSPI2_CS0 0x0102 -#define RFBI_DATA15 0x0104 -#define RFBI_DATA14 0x0106 -#define RFBI_DATA13 0x0108 -#define RFBI_DATA12 0x010a -#define RFBI_DATA11 0x010c -#define RFBI_DATA10 0x010e -#define RFBI_DATA9 0x0110 -#define RFBI_DATA8 0x0112 -#define RFBI_DATA7 0x0114 -#define RFBI_DATA6 0x0116 -#define RFBI_DATA5 0x0118 -#define RFBI_DATA4 0x011a -#define RFBI_DATA3 0x011c -#define RFBI_DATA2 0x011e -#define RFBI_DATA1 0x0120 -#define RFBI_DATA0 0x0122 -#define RFBI_WE 0x0124 -#define RFBI_CS0 0x0126 -#define RFBI_A0 0x0128 -#define RFBI_RE 0x012a -#define RFBI_HSYNC0 0x012c -#define RFBI_TE_VSYNC0 0x012e -#define GPIO6_182 0x0130 -#define GPIO6_183 0x0132 -#define GPIO6_184 0x0134 -#define GPIO6_185 0x0136 -#define GPIO6_186 0x0138 -#define GPIO6_187 0x013a -#define HDMI_CEC 0x013c -#define HDMI_HPD 0x013e -#define HDMI_DDC_SCL 0x0140 -#define HDMI_DDC_SDA 0x0142 -#define CSIPORTC_LANE0X 0x0144 -#define CSIPORTC_LANE0Y 0x0146 -#define CSIPORTC_LANE1X 0x0148 -#define CSIPORTC_LANE1Y 0x014a -#define CSIPORTB_LANE0X 0x014c -#define CSIPORTB_LANE0Y 0x014e -#define CSIPORTB_LANE1X 0x0150 -#define CSIPORTB_LANE1Y 0x0152 -#define CSIPORTB_LANE2X 0x0154 -#define CSIPORTB_LANE2Y 0x0156 -#define CSIPORTA_LANE0X 0x0158 -#define CSIPORTA_LANE0Y 0x015a -#define CSIPORTA_LANE1X 0x015c -#define CSIPORTA_LANE1Y 0x015e -#define CSIPORTA_LANE2X 0x0160 -#define CSIPORTA_LANE2Y 0x0162 -#define CSIPORTA_LANE3X 0x0164 -#define CSIPORTA_LANE3Y 0x0166 -#define CSIPORTA_LANE4X 0x0168 -#define CSIPORTA_LANE4Y 0x016a -#define CAM_SHUTTER 0x016c -#define CAM_STROBE 0x016e -#define CAM_GLOBALRESET 0x0170 -#define TIMER11_PWM_EVT 0x0172 -#define TIMER5_PWM_EVT 0x0174 -#define TIMER6_PWM_EVT 0x0176 -#define TIMER8_PWM_EVT 0x0178 -#define I2C3_SCL 0x017a -#define I2C3_SDA 0x017c -#define GPIO8_233 0x017e -#define GPIO8_234 0x0180 -#define ABE_CLKS 0x0182 -#define ABEDMIC_DIN1 0x0184 -#define ABEDMIC_DIN2 0x0186 -#define ABEDMIC_DIN3 0x0188 -#define ABEDMIC_CLK1 0x018a -#define ABEDMIC_CLK2 0x018c -#define ABEDMIC_CLK3 0x018e -#define ABESLIMBUS1_CLOCK 0x0190 -#define ABESLIMBUS1_DATA 0x0192 -#define ABEMCBSP2_DR 0x0194 -#define ABEMCBSP2_DX 0x0196 -#define ABEMCBSP2_FSX 0x0198 -#define ABEMCBSP2_CLKX 0x019a -#define ABEMCPDM_UL_DATA 0x019c -#define ABEMCPDM_DL_DATA 0x019e -#define ABEMCPDM_FRAME 0x01a0 -#define ABEMCPDM_LB_CLK 0x01a2 -#define WLSDIO_CLK 0x01a4 -#define WLSDIO_CMD 0x01a6 -#define WLSDIO_DATA0 0x01a8 -#define WLSDIO_DATA1 0x01aa -#define WLSDIO_DATA2 0x01ac -#define WLSDIO_DATA3 0x01ae -#define UART5_RX 0x01b0 -#define UART5_TX 0x01b2 -#define UART5_CTS 0x01b4 -#define UART5_RTS 0x01b6 -#define I2C2_SCL 0x01b8 -#define I2C2_SDA 0x01ba -#define MCSPI1_CLK 0x01bc -#define MCSPI1_SOMI 0x01be -#define MCSPI1_SIMO 0x01c0 -#define MCSPI1_CS0 0x01c2 -#define MCSPI1_CS1 0x01c4 -#define I2C5_SCL 0x01c6 -#define I2C5_SDA 0x01c8 -#define PERSLIMBUS2_CLOCK 0x01ca -#define PERSLIMBUS2_DATA 0x01cc -#define UART6_TX 0x01ce -#define UART6_RX 0x01d0 -#define UART6_CTS 0x01d2 -#define UART6_RTS 0x01d4 -#define UART3_CTS_RCTX 0x01d6 -#define UART3_RTS_IRSD 0x01d8 -#define UART3_TX_IRTX 0x01da -#define UART3_RX_IRRX 0x01dc -#define USBB3_HSIC_STROBE 0x01de -#define USBB3_HSIC_DATA 0x01e0 -#define SDCARD_CLK 0x01e2 -#define SDCARD_CMD 0x01e4 -#define SDCARD_DATA2 0x01e6 -#define SDCARD_DATA3 0x01e8 -#define SDCARD_DATA0 0x01ea -#define SDCARD_DATA1 0x01ec -#define USBD0_HS_DP 0x01ee -#define USBD0_HS_DM 0x01f0 -#define I2C1_PMIC_SCL 0x01f2 -#define I2C1_PMIC_SDA 0x01f4 -#define USBD0_SS_RX 0x01f6 - -#define LLIA_WAKEREQIN 0x0040 -#define LLIB_WAKEREQIN 0x0042 -#define DRM_EMU0 0x0044 -#define DRM_EMU1 0x0046 -#define JTAG_NTRST 0x0048 -#define JTAG_TCK 0x004a -#define JTAG_RTCK 0x004c -#define JTAG_TMSC 0x004e -#define JTAG_TDI 0x0050 -#define JTAG_TDO 0x0052 -#define SYS_32K 0x0054 -#define FREF_CLK_IOREQ 0x0056 -#define FREF_CLK0_OUT 0x0058 -#define FREF_CLK1_OUT 0x005a -#define FREF_CLK2_OUT 0x005c -#define FREF_CLK2_REQ 0x005e -#define FREF_CLK1_REQ 0x0060 -#define SYS_NRESPWRON 0x0062 -#define SYS_NRESWARM 0x0064 -#define SYS_PWR_REQ 0x0066 -#define SYS_NIRQ1 0x0068 -#define SYS_NIRQ2 0x006a -#define SR_PMIC_SCL 0x006c -#define SR_PMIC_SDA 0x006e -#define SYS_BOOT0 0x0070 -#define SYS_BOOT1 0x0072 -#define SYS_BOOT2 0x0074 -#define SYS_BOOT3 0x0076 -#define SYS_BOOT4 0x0078 -#define SYS_BOOT5 0x007a - -#endif /* _MUX_OMAP5_H_ */ diff --git a/arch/arm/include/asm/boot0-linux-kernel-header.h b/arch/arm/include/asm/boot0-linux-kernel-header.h index c6cd76f..c930fea 100644 --- a/arch/arm/include/asm/boot0-linux-kernel-header.h +++ b/arch/arm/include/asm/boot0-linux-kernel-header.h @@ -31,8 +31,6 @@ .long \sym\()_hi32 .endm -.globl _start -_start: /* * DO NOT MODIFY. Image header expected by Linux boot-loaders. */ diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h deleted file mode 100644 index ce831bc..0000000 --- a/arch/arm/include/asm/iproc-common/configs.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2014 Broadcom Corporation. - */ - -#ifndef __IPROC_COMMON_CONFIGS_H -#define __IPROC_COMMON_CONFIGS_H - -#include <linux/stringify.h> - -/* Memory Info */ -#define CFG_SYS_SDRAM_BASE 0x61000000 - -#endif /* __IPROC_COMMON_CONFIGS_H */ diff --git a/arch/arm/include/asm/iproc-common/iproc_sdhci.h b/arch/arm/include/asm/iproc-common/iproc_sdhci.h deleted file mode 100644 index 4e29921..0000000 --- a/arch/arm/include/asm/iproc-common/iproc_sdhci.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: <SPDX License Expression> */ -/* - * Copyright 2019 Broadcom - * - */ - -#ifndef __IPROC_SDHCI_H -#define __IPROC_SDHCI_H - -int iproc_sdhci_init(int dev_index, u32 quirks); - -#endif diff --git a/arch/arm/include/asm/kona-common/kona_sdhci.h b/arch/arm/include/asm/kona-common/kona_sdhci.h deleted file mode 100644 index 22db651..0000000 --- a/arch/arm/include/asm/kona-common/kona_sdhci.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2013 Broadcom Corporation. - */ - -#ifndef __KONA_SDHCI_H -#define __KONA_SDHCI_H - -int kona_sdhci_init(int dev_index, u32 min_clk, u32 quirks); - -#endif diff --git a/arch/arm/include/asm/linkage.h b/arch/arm/include/asm/linkage.h index dbe4b4e..73bf25b 100644 --- a/arch/arm/include/asm/linkage.h +++ b/arch/arm/include/asm/linkage.h @@ -1,7 +1,7 @@ #ifndef __ASM_LINKAGE_H #define __ASM_LINKAGE_H -#define __ALIGN .align 0 -#define __ALIGN_STR ".align 0" +#define __ALIGN .p2align 2 +#define __ALIGN_STR ".p2align 2" #endif diff --git a/arch/arm/include/asm/unaligned.h b/arch/arm/include/asm/unaligned.h index 0a228fb..7fb482a 100644 --- a/arch/arm/include/asm/unaligned.h +++ b/arch/arm/include/asm/unaligned.h @@ -1,19 +1,2 @@ -#ifndef _ASM_ARM_UNALIGNED_H -#define _ASM_ARM_UNALIGNED_H - -#include <linux/unaligned/le_byteshift.h> -#include <linux/unaligned/be_byteshift.h> -#include <linux/unaligned/generic.h> - -/* - * Select endianness - */ -#if __BYTE_ORDER == __LITTLE_ENDIAN -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#else -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#endif - -#endif /* _ASM_ARM_UNALIGNED_H */ +/* SPDX-License-Identifier: GPL-2.0 */ +#include <asm-generic/unaligned.h> diff --git a/arch/arm/mach-at91/include/mach/at91_rtt.h b/arch/arm/mach-at91/include/mach/at91_rtt.h deleted file mode 100644 index ba88c44..0000000 --- a/arch/arm/mach-at91/include/mach/at91_rtt.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * - * Real-time Timer - * Based on AT91SAM9XE datasheet - */ - -#ifndef AT91_RTT_H -#define AT91_RTT_H - -#ifndef __ASSEMBLY__ - -typedef struct at91_rtt { - u32 mr; /* Mode Register RW 0x00008000 */ - u32 ar; /* Alarm Register RW 0xFFFFFFFF */ - u32 vr; /* Value Register RO 0x00000000 */ - u32 sr; /* Status Register RO 0x00000000 */ -} at91_rtt_t; - -#endif /* __ASSEMBLY__ */ - -#define AT91_RTT_MR_RTPRES 0x0000ffff -#define AT91_RTT_MR_ALMIEN 0x00010000 -#define AT91_RTT_RTTINCIEN 0x00020000 -#define AT91_RTT_RTTRST 0x00040000 - -#define AT91_RTT_SR_ALMS 0x00000001 -#define AT91_RTT_SR_RTTINC 0x00000002 - -#endif diff --git a/arch/arm/mach-davinci/include/mach/aintc_defs.h b/arch/arm/mach-davinci/include/mach/aintc_defs.h deleted file mode 100644 index 7419a58..0000000 --- a/arch/arm/mach-davinci/include/mach/aintc_defs.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - */ -#ifndef _DV_AINTC_DEFS_H_ -#define _DV_AINTC_DEFS_H_ - -struct dv_aintc_regs { - unsigned int fiq0; /* 0x00 */ - unsigned int fiq1; /* 0x04 */ - unsigned int irq0; /* 0x08 */ - unsigned int irq1; /* 0x0c */ - unsigned int fiqentry; /* 0x10 */ - unsigned int irqentry; /* 0x14 */ - unsigned int eint0; /* 0x18 */ - unsigned int eint1; /* 0x1c */ - unsigned int intctl; /* 0x20 */ - unsigned int eabase; /* 0x24 */ - unsigned char rsvd0[8]; /* 0x28 */ - unsigned int intpri0; /* 0x30 */ - unsigned int intpri1; /* 0x34 */ - unsigned int intpri2; /* 0x38 */ - unsigned int intpri3; /* 0x3c */ - unsigned int intpri4; /* 0x40 */ - unsigned int intpri5; /* 0x44 */ - unsigned int intpri6; /* 0x48 */ - unsigned int intpri7; /* 0x4c */ -}; - -#define dv_aintc_regs ((struct dv_aintc_regs *)DAVINCI_ARM_INTC_BASE) - -#define DV_AINTC_INTCTL_IDMODE (1 << 2) - -#endif /* _DV_AINTC_DEFS_H_ */ diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 906f538..00d6ad8 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -54,7 +54,7 @@ obj-$(CONFIG_IMX_RDC) += rdc-sema.o ifneq ($(CONFIG_SPL_BUILD),y) obj-$(CONFIG_IMX_BOOTAUX) += imx_bootaux.o endif -obj-$(CONFIG_SATA) += sata.o +obj-$(CONFIG_$(SPL_)SATA) += sata.o obj-$(CONFIG_IMX_HAB) += hab.o obj-$(CONFIG_SYSCOUNTER_TIMER) += syscounter.o endif diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index 026c4f9..787fe92 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -15,6 +15,15 @@ #include <dm/uclass-internal.h> #include <dm/pinctrl.h> +#define RTC_BASE_ADDRESS 0x2b1f0000 +#define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18) +#define REG_K3RTC_KICK0 (RTC_BASE_ADDRESS + 0x70) +#define REG_K3RTC_KICK1 (RTC_BASE_ADDRESS + 0x74) + +/* Magic values for lock/unlock */ +#define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13 +#define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0 + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -71,6 +80,42 @@ static __maybe_unused void enable_mcu_esm_reset(void) writel(stat, CTRLMMR_MCU_RST_CTRL); } +#if defined(CONFIG_CPU_V7R) + +/* + * RTC Erratum i2327 Workaround for Silicon Revision 1 + * + * Due to a bug in initial synchronization out of cold power on, + * IRQ status can get locked infinitely if we do not unlock RTC + * + * This workaround *must* be applied within 1 second of power on, + * So, this is closest point to be able to guarantee the max + * timing. + * + * https://www.ti.com/lit/er/sprz487c/sprz487c.pdf + */ +void rtc_erratumi2327_init(void) +{ + u32 counter; + + /* + * If counter has gone past 1, nothing we can do, leave + * system locked! This is the only way we know if RTC + * can be used for all practical purposes. + */ + counter = readl(REG_K3RTC_S_CNT_LSW); + if (counter > 1) + return; + /* + * Need to set this up at the very start + * MUST BE DONE under 1 second of boot. + */ + writel(K3RTC_KICK0_UNLOCK_VALUE, REG_K3RTC_KICK0); + writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1); + return; +} +#endif + void board_init_f(ulong dummy) { struct udevice *dev; @@ -78,6 +123,7 @@ void board_init_f(ulong dummy) #if defined(CONFIG_CPU_V7R) setup_k3_mpu_regions(); + rtc_erratumi2327_init(); #endif /* diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 88687c2..f8087d2 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -222,14 +222,13 @@ struct mm_region *mem_map = j721s2_mem_map; #endif /* CONFIG_SOC_K3_J721S2 */ -#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) || \ - defined(CONFIG_SOC_K3_AM62A7) +#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7) /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) +#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) /* ToDo: Add 64bit IO */ -struct mm_region am64_mem_map[NR_MMU_REGIONS] = { +struct mm_region am62_mem_map[NR_MMU_REGIONS] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -240,10 +239,65 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, + .size = 0x1E780000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xA0000000UL, + .phys = 0xA0000000UL, + .size = 0x60000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + + }, { + .virt = 0x880000000UL, + .phys = 0x880000000UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { + .virt = 0x500000000UL, + .phys = 0x500000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = am62_mem_map; +#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ + +#ifdef CONFIG_SOC_K3_AM642 + +/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ +#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) + +/* ToDo: Add 64bit IO */ +struct mm_region am64_mem_map[NR_MMU_REGIONS] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x1E800000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xA0000000UL, + .phys = 0xA0000000UL, + .size = 0x60000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { .virt = 0x880000000UL, .phys = 0x880000000UL, .size = 0x80000000UL, @@ -263,4 +317,4 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = { }; struct mm_region *mem_map = am64_mem_map; -#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ +#endif /* CONFIG_SOC_K3_AM642 */ diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 34737a4..bda0152 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -568,39 +568,51 @@ void disable_linefill_optimization(void) } #endif -void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) +static void remove_fwl_regions(struct fwl_data fwl_data, size_t num_regions, + enum k3_firewall_region_type fwl_type) { - struct ti_sci_msg_fwl_region region; struct ti_sci_fwl_ops *fwl_ops; struct ti_sci_handle *ti_sci; - size_t i, j; + struct ti_sci_msg_fwl_region region; + size_t j; ti_sci = get_ti_sci_handle(); fwl_ops = &ti_sci->ops.fwl_ops; - for (i = 0; i < fwl_data_size; i++) { - for (j = 0; j < fwl_data[i].regions; j++) { - region.fwl_id = fwl_data[i].fwl_id; - region.region = j; - region.n_permission_regs = 3; - - fwl_ops->get_fwl_region(ti_sci, ®ion); - - /* Don't disable the background regions */ - if (region.control != 0 && - ((region.control & K3_BACKGROUND_FIREWALL_BIT) == - 0)) { - pr_debug("Attempting to disable firewall %5d (%25s)\n", - region.fwl_id, fwl_data[i].name); - region.control = 0; - - if (fwl_ops->set_fwl_region(ti_sci, ®ion)) - pr_err("Could not disable firewall %5d (%25s)\n", - region.fwl_id, fwl_data[i].name); - } + + for (j = 0; j < fwl_data.regions; j++) { + region.fwl_id = fwl_data.fwl_id; + region.region = j; + region.n_permission_regs = 3; + + fwl_ops->get_fwl_region(ti_sci, ®ion); + + /* Don't disable the background regions */ + if (region.control != 0 && + ((region.control & K3_FIREWALL_BACKGROUND_BIT) == + fwl_type)) { + pr_debug("Attempting to disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data.name); + region.control = 0; + + if (fwl_ops->set_fwl_region(ti_sci, ®ion)) + pr_err("Could not disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data.name); } } } +void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) +{ + size_t i; + + for (i = 0; i < fwl_data_size; i++) { + remove_fwl_regions(fwl_data[i], fwl_data[i].regions, + K3_FIREWALL_REGION_FOREGROUND); + remove_fwl_regions(fwl_data[i], fwl_data[i].regions, + K3_FIREWALL_REGION_BACKGROUND); + } +} + void spl_enable_dcache(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index 899be64..6cffbd4 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -9,9 +9,7 @@ #include <asm/armv7_mpu.h> #include <asm/hardware.h> -#define J721E 0xbb64 -#define J7200 0xbb6d -#define K3_BACKGROUND_FIREWALL_BIT BIT(8) +#define K3_FIREWALL_BACKGROUND_BIT BIT(8) struct fwl_data { const char *name; @@ -19,6 +17,11 @@ struct fwl_data { u16 regions; }; +enum k3_firewall_region_type { + K3_FIREWALL_REGION_FOREGROUND, + K3_FIREWALL_REGION_BACKGROUND +}; + enum k3_device_type { K3_DEVICE_TYPE_BAD, K3_DEVICE_TYPE_GP, diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c index 0437e30..9b45786 100644 --- a/arch/arm/mach-k3/j7200/clk-data.c +++ b/arch/arm/mach-k3/j7200/clk-data.c @@ -379,6 +379,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out1", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c4, 0, 2, 0, 0, 48000000), CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), @@ -534,6 +535,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"), + DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"), DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), @@ -546,7 +549,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata j7200_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 108, + .clk_list_cnt = 109, .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 127, + .soc_dev_clk_data_cnt = 129, }; diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c index d3194ae..c1a4dab 100644 --- a/arch/arm/mach-k3/j7200/dev-data.c +++ b/arch/arm/mach-k3/j7200/dev-data.c @@ -53,6 +53,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(92, &soc_lpsc_list[5]), PSC_DEV(91, &soc_lpsc_list[6]), PSC_DEV(146, &soc_lpsc_list[7]), + PSC_DEV(278, &soc_lpsc_list[7]), PSC_DEV(4, &soc_lpsc_list[8]), PSC_DEV(4, &soc_lpsc_list[9]), PSC_DEV(202, &soc_lpsc_list[10]), @@ -77,5 +78,5 @@ const struct ti_k3_pd_platdata j7200_pd_platdata = { .num_psc = 2, .num_pd = 6, .num_lpsc = 17, - .num_devs = 22, + .num_devs = 23, }; diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c index 5ab7951..e451109 100644 --- a/arch/arm/mach-k3/j721e/clk-data.c +++ b/arch/arm/mach-k3/j721e/clk-data.c @@ -553,6 +553,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0, 48000000), CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), @@ -760,6 +761,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(279, 0, "usart_programmable_clock_divider_out2"), + DEV_CLK(279, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"), DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), @@ -780,7 +783,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata j721e_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 156, + .clk_list_cnt = 157, .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 171, + .soc_dev_clk_data_cnt = 173, }; diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c index 300d998..f0afa35 100644 --- a/arch/arm/mach-k3/j721e/dev-data.c +++ b/arch/arm/mach-k3/j721e/dev-data.c @@ -46,6 +46,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(30, &soc_lpsc_list[0]), PSC_DEV(61, &soc_lpsc_list[0]), PSC_DEV(146, &soc_lpsc_list[1]), + PSC_DEV(279, &soc_lpsc_list[1]), PSC_DEV(90, &soc_lpsc_list[2]), PSC_DEV(47, &soc_lpsc_list[3]), PSC_DEV(288, &soc_lpsc_list[4]), @@ -75,5 +76,5 @@ const struct ti_k3_pd_platdata j721e_pd_platdata = { .num_psc = 2, .num_pd = 5, .num_lpsc = 16, - .num_devs = 22, + .num_devs = 23, }; diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 0c5d41a..b616457 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -294,7 +294,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { switch (boot_device) { case BOOT_DEVICE_MMC1: - return MMCSD_MODE_EMMCBOOT; + return (spl_mmc_emmc_boot_partition(mmc) ? MMCSD_MODE_EMMCBOOT : MMCSD_MODE_FS); case BOOT_DEVICE_MMC2: return MMCSD_MODE_FS; default: diff --git a/arch/arm/mach-k3/j721s2/clk-data.c b/arch/arm/mach-k3/j721s2/clk-data.c index ad6bd99..0c5c321 100644 --- a/arch/arm/mach-k3/j721s2/clk-data.c +++ b/arch/arm/mach-k3/j721s2/clk-data.c @@ -247,6 +247,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0), CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0), CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0), @@ -383,6 +384,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"), DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"), + DEV_CLK(354, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(354, 3, "usart_programmable_clock_divider_out5"), DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"), DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), @@ -397,7 +400,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata j721s2_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 104, + .clk_list_cnt = 105, .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 122, + .soc_dev_clk_data_cnt = 124, }; diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/j721s2/dev-data.c index e36f1ed..35e8b17 100644 --- a/arch/arm/mach-k3/j721s2/dev-data.c +++ b/arch/arm/mach-k3/j721s2/dev-data.c @@ -67,6 +67,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(99, &soc_lpsc_list[12]), PSC_DEV(98, &soc_lpsc_list[13]), PSC_DEV(146, &soc_lpsc_list[14]), + PSC_DEV(354, &soc_lpsc_list[15]), PSC_DEV(357, &soc_lpsc_list[15]), PSC_DEV(4, &soc_lpsc_list[16]), PSC_DEV(202, &soc_lpsc_list[17]), @@ -81,5 +82,5 @@ const struct ti_k3_pd_platdata j721s2_pd_platdata = { .num_psc = 2, .num_pd = 6, .num_lpsc = 19, - .num_devs = 24, + .num_devs = 25, }; diff --git a/arch/arm/mach-keystone/include/mach/xhci-keystone.h b/arch/arm/mach-keystone/include/mach/xhci-keystone.h deleted file mode 100644 index 989b0c3..0000000 --- a/arch/arm/mach-keystone/include/mach/xhci-keystone.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * USB 3.0 DRD Controller - * - * (C) Copyright 2012-2014 - * Texas Instruments Incorporated, <www.ti.com> - */ - -#ifndef __ASSEMBLY__ -#include <linux/bitops.h> -#endif - -#define USB3_PHY_REF_SSP_EN BIT(29) -#define USB3_PHY_OTG_VBUSVLDECTSEL BIT(16) - -/* KEYSTONE2 XHCI PHY register structure */ -struct keystone_xhci_phy { - unsigned int phy_utmi; /* ctl0 */ - unsigned int phy_pipe; /* ctl1 */ - unsigned int phy_param_ctrl_1; /* ctl2 */ - unsigned int phy_param_ctrl_2; /* ctl3 */ - unsigned int phy_clock; /* ctl4 */ - unsigned int phy_pll; /* ctl5 */ -}; diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index 6cba2c4..669ca09 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -51,6 +51,12 @@ config MESON_G12A help Select this if your SoC is an S905X/D2 +config MESON_A1 + bool "A1" + select MESON64_COMMON + help + Select this if your SoC is an A113L + endchoice config SYS_SOC @@ -69,6 +75,7 @@ config SYS_VENDOR config SYS_BOARD string "Board name" + default "ad401" if MESON_A1 default "p200" if MESON_GXBB default "p212" if MESON_GXL default "q200" if MESON_GXM diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile index a9e4046..535b087 100644 --- a/arch/arm/mach-meson/Makefile +++ b/arch/arm/mach-meson/Makefile @@ -6,3 +6,4 @@ obj-y += board-common.o sm.o board-info.o obj-$(CONFIG_MESON_GX) += board-gx.o obj-$(CONFIG_MESON_AXG) += board-axg.o obj-$(CONFIG_MESON_G12A) += board-g12a.o +obj-$(CONFIG_MESON_A1) += board-a1.o diff --git a/arch/arm/mach-meson/board-a1.c b/arch/arm/mach-meson/board-a1.c new file mode 100644 index 0000000..967bb67 --- /dev/null +++ b/arch/arm/mach-meson/board-a1.c @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 SberDevices, Inc. + */ + +#include <common.h> +#include <asm/arch/a1.h> +#include <asm/arch/boot.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <linux/compiler.h> +#include <linux/sizes.h> + +phys_size_t get_effective_memsize(void) +{ + return ((readl(A1_SYSCTRL_SEC_STATUS_REG4) & A1_SYSCTRL_MEM_SIZE_MASK) + >> A1_SYSCTRL_MEM_SIZE_SHIFT) * SZ_1M; +} + +void meson_init_reserved_memory(__maybe_unused void *fdt) +{ +} + +int meson_get_boot_device(void) +{ + return -ENOSYS; +} + +static struct mm_region a1_mem_map[] = { + { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x7FE00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* + * This mem region contains in/out shared memory with bl31, + * hence it's marked as NORMAL memory type + */ + .virt = 0xFFE00000UL, + .phys = 0xFFE00000UL, + .size = 0x00200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = a1_mem_map; diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c index f2ca7e7..d600c64d 100644 --- a/arch/arm/mach-meson/sm.c +++ b/arch/arm/mach-meson/sm.c @@ -24,6 +24,7 @@ #define FN_EFUSE_READ 0x82000030 #define FN_EFUSE_WRITE 0x82000031 #define FN_CHIP_ID 0x82000044 +#define FN_PWRDM_SET 0x82000093 static void *shmem_input; static void *shmem_output; @@ -137,3 +138,16 @@ int meson_sm_get_reboot_reason(void) /* The SMC call is not used, we directly use AO_SEC_SD_CFG15 */ return FIELD_GET(REBOOT_REASON_MASK, reason); } + +int meson_sm_pwrdm_set(size_t index, int cmd) +{ + struct pt_regs regs; + + regs.regs[0] = FN_PWRDM_SET; + regs.regs[1] = index; + regs.regs[2] = cmd; + + smc_call(®s); + + return regs.regs[0]; +} diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig index 309b967..8465b54 100644 --- a/arch/arm/mach-omap2/Kconfig +++ b/arch/arm/mach-omap2/Kconfig @@ -77,16 +77,6 @@ config OMAP54XX imply SPL_SERIAL imply SYS_I2C_OMAP24XX -config TI816X - bool "TI816X SoC" - select SPECIFY_CONSOLE_INDEX - imply NAND_OMAP_ELM - imply NAND_OMAP_GPMC - help - Support for AM335x SOC from Texas Instruments. - The AM335x high performance SOC features a Cortex-A8 - ARM core and more. - config AM43XX bool "AM43XX SoC" select SPECIFY_CONSOLE_INDEX @@ -203,7 +193,6 @@ source "board/BuR/brppt1/Kconfig" source "board/siemens/draco/Kconfig" source "board/siemens/pxm2/Kconfig" source "board/siemens/rut/Kconfig" -source "board/ti/ti816x/Kconfig" source "board/ti/am43xx/Kconfig" source "board/ti/am335x/Kconfig" source "board/compulab/cm_t43/Kconfig" diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig index 1299aec..8cb0c57 100644 --- a/arch/arm/mach-omap2/am33xx/Kconfig +++ b/arch/arm/mach-omap2/am33xx/Kconfig @@ -1,13 +1,3 @@ -if TI816X - -config TARGET_TI816X_EVM - bool "Support ti816x_evm" - help - This option specifies support for the TI8168 EVM development platform - with PG2.0 silicon and DDR3 DRAM. - -endif - if AM33XX config AM33XX_CHILISOM diff --git a/arch/arm/mach-omap2/am33xx/Makefile b/arch/arm/mach-omap2/am33xx/Makefile index bf94d34..2aa8013 100644 --- a/arch/arm/mach-omap2/am33xx/Makefile +++ b/arch/arm/mach-omap2/am33xx/Makefile @@ -9,13 +9,11 @@ ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),) obj-y += clock.o endif -obj-$(CONFIG_TI816X) += clock_ti816x.o obj-y += sys_info.o obj-y += ddr.o -ifeq ($(CONFIG_TI816X)$(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) +ifeq ($(CONFIG_$(SPL_)SKIP_LOWLEVEL_INIT),) obj-y += emif4.o endif -obj-$(CONFIG_TI816X) += ti816x_emif4.o obj-y += board.o obj-y += mux.o obj-y += prcm-regs.o diff --git a/arch/arm/mach-omap2/am33xx/clock_ti816x.c b/arch/arm/mach-omap2/am33xx/clock_ti816x.c deleted file mode 100644 index ec4cc75..0000000 --- a/arch/arm/mach-omap2/am33xx/clock_ti816x.c +++ /dev/null @@ -1,407 +0,0 @@ -/* - * clock_ti816x.c - * - * Clocks for TI816X based boards - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - * - * Based on TI-PSP-04.00.02.14 : - * - * Copyright (C) 2009, Texas Instruments, Incorporated - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <common.h> -#include <asm/arch/ddr_defs.h> -#include <asm/arch/cpu.h> -#include <asm/arch/clock.h> -#include <asm/arch/hardware.h> -#include <asm/io.h> -#include <linux/bitops.h> - -#include <asm/emif.h> - -#define CM_PLL_BASE (CTRL_BASE + 0x0400) - -/* Main PLL */ -#define MAIN_N 64 -#define MAIN_P 0x1 -#define MAIN_INTFREQ1 0x8 -#define MAIN_FRACFREQ1 0x800000 -#define MAIN_MDIV1 0x2 -#define MAIN_INTFREQ2 0xE -#define MAIN_FRACFREQ2 0x0 -#define MAIN_MDIV2 0x1 -#define MAIN_INTFREQ3 0x8 -#define MAIN_FRACFREQ3 0xAAAAB0 -#define MAIN_MDIV3 0x3 -#define MAIN_INTFREQ4 0x9 -#define MAIN_FRACFREQ4 0x55554F -#define MAIN_MDIV4 0x3 -#define MAIN_INTFREQ5 0x9 -#define MAIN_FRACFREQ5 0x374BC6 -#define MAIN_MDIV5 0xC -#define MAIN_MDIV6 0x48 -#define MAIN_MDIV7 0x4 - -/* DDR PLL */ -#define DDR_N 59 -#define DDR_P 0x1 -#define DDR_MDIV1 0x2 -#define DDR_INTFREQ2 0x8 -#define DDR_FRACFREQ2 0xD99999 -#define DDR_MDIV2 0x1E -#define DDR_INTFREQ3 0x8 -#define DDR_FRACFREQ3 0x0 -#define DDR_MDIV3 0x4 -#define DDR_INTFREQ4 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ4 0x0 -#define DDR_MDIV4 0x4 -#define DDR_INTFREQ5 0xE /* Expansion DDR clk */ -#define DDR_FRACFREQ5 0x0 -#define DDR_MDIV5 0x4 - -#define CONTROL_STATUS (CTRL_BASE + 0x40) -#define DDR_RCD (CTRL_BASE + 0x070C) -#define CM_TIMER1_CLKSEL (PRCM_BASE + 0x390) -#define CM_ALWON_CUST_EFUSE_CLKCTRL (PRCM_BASE + 0x1628) - -#define INTCPS_SYSCONFIG 0x48200010 -#define CM_SYSCLK10_CLKSEL 0x48180324 - -struct cm_pll { - unsigned int mainpll_ctrl; /* offset 0x400 */ - unsigned int mainpll_pwd; - unsigned int mainpll_freq1; - unsigned int mainpll_div1; - unsigned int mainpll_freq2; - unsigned int mainpll_div2; - unsigned int mainpll_freq3; - unsigned int mainpll_div3; - unsigned int mainpll_freq4; - unsigned int mainpll_div4; - unsigned int mainpll_freq5; - unsigned int mainpll_div5; - unsigned int resv0[1]; - unsigned int mainpll_div6; - unsigned int resv1[1]; - unsigned int mainpll_div7; - unsigned int ddrpll_ctrl; /* offset 0x440 */ - unsigned int ddrpll_pwd; - unsigned int resv2[1]; - unsigned int ddrpll_div1; - unsigned int ddrpll_freq2; - unsigned int ddrpll_div2; - unsigned int ddrpll_freq3; - unsigned int ddrpll_div3; - unsigned int ddrpll_freq4; - unsigned int ddrpll_div4; - unsigned int ddrpll_freq5; - unsigned int ddrpll_div5; - unsigned int videopll_ctrl; /* offset 0x470 */ - unsigned int videopll_pwd; - unsigned int videopll_freq1; - unsigned int videopll_div1; - unsigned int videopll_freq2; - unsigned int videopll_div2; - unsigned int videopll_freq3; - unsigned int videopll_div3; - unsigned int resv3[4]; - unsigned int audiopll_ctrl; /* offset 0x4A0 */ - unsigned int audiopll_pwd; - unsigned int resv4[2]; - unsigned int audiopll_freq2; - unsigned int audiopll_div2; - unsigned int audiopll_freq3; - unsigned int audiopll_div3; - unsigned int audiopll_freq4; - unsigned int audiopll_div4; - unsigned int audiopll_freq5; - unsigned int audiopll_div5; -}; - -const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE; -const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE; -const struct cm_pll *cmpll = (struct cm_pll *)CM_PLL_BASE; -const struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; - -void enable_dmm_clocks(void) -{ - writel(PRCM_MOD_EN, &cmdef->dmmclkctrl); - /* Wait for dmm to be fully functional, including OCP */ - while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) - ; -} - -void enable_emif_clocks(void) -{ - writel(PRCM_MOD_EN, &cmdef->fwclkctrl); - writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl); - writel(PRCM_MOD_EN, &cmdef->emif0clkctrl); - writel(PRCM_MOD_EN, &cmdef->emif1clkctrl); - - /* Wait for clocks to be active */ - while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) - ; - /* Wait for emif0 to be fully functional, including OCP */ - while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) - ; - /* Wait for emif1 to be fully functional, including OCP */ - while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) - ; -} - -/* assume delay is aprox at least 1us */ -static void ddr_delay(int d) -{ - int i; - - /* - * read a control register. - * this is a bit more delay and cannot be optimized by the compiler - * assuming one read takes 200 cycles and A8 is runing 1 GHz - * somewhat conservative setting - */ - for (i = 0; i < 50*d; i++) - readl(CONTROL_STATUS); -} - -static void main_pll_init_ti816x(void) -{ - u32 main_pll_ctrl = 0; - - /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFFFFFFFB; - main_pll_ctrl |= BIT(2); - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); - - /* Enable PLL by setting BIT3 in its ctrl reg */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFFFFFFF7; - main_pll_ctrl |= BIT(3); - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); - - /* Write the values of N,P in the CTRL reg */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFF; - main_pll_ctrl |= (MAIN_N<<16 | MAIN_P<<8); - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); - - /* Power up clock1-7 */ - writel(0x0, &cmpll->mainpll_pwd); - - /* Program the freq and divider values for clock1-7 */ - writel((1<<31 | 1<<28 | (MAIN_INTFREQ1<<24) | MAIN_FRACFREQ1), - &cmpll->mainpll_freq1); - writel(((1<<8) | MAIN_MDIV1), &cmpll->mainpll_div1); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ2<<24) | MAIN_FRACFREQ2), - &cmpll->mainpll_freq2); - writel(((1<<8) | MAIN_MDIV2), &cmpll->mainpll_div2); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ3<<24) | MAIN_FRACFREQ3), - &cmpll->mainpll_freq3); - writel(((1<<8) | MAIN_MDIV3), &cmpll->mainpll_div3); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ4<<24) | MAIN_FRACFREQ4), - &cmpll->mainpll_freq4); - writel(((1<<8) | MAIN_MDIV4), &cmpll->mainpll_div4); - - writel((1<<31 | 1<<28 | (MAIN_INTFREQ5<<24) | MAIN_FRACFREQ5), - &cmpll->mainpll_freq5); - writel(((1<<8) | MAIN_MDIV5), &cmpll->mainpll_div5); - - writel((1<<8 | MAIN_MDIV6), &cmpll->mainpll_div6); - - writel((1<<8 | MAIN_MDIV7), &cmpll->mainpll_div7); - - /* Wait for PLL to lock */ - while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) - ; - - /* Put the PLL in normal mode, disable bypass */ - main_pll_ctrl = readl(&cmpll->mainpll_ctrl); - main_pll_ctrl &= 0xFFFFFFFB; - writel(main_pll_ctrl, &cmpll->mainpll_ctrl); -} - -static void ddr_pll_bypass_ti816x(void) -{ - u32 ddr_pll_ctrl = 0; - - /* Put the PLL in bypass mode by setting BIT2 in its ctrl reg */ - ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); - ddr_pll_ctrl &= 0xFFFFFFFB; - ddr_pll_ctrl |= BIT(2); - writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); -} - -static void ddr_pll_init_ti816x(void) -{ - u32 ddr_pll_ctrl = 0; - /* Enable PLL by setting BIT3 in its ctrl reg */ - ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); - ddr_pll_ctrl &= 0xFFFFFFF7; - ddr_pll_ctrl |= BIT(3); - writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); - - /* Write the values of N,P in the CTRL reg */ - ddr_pll_ctrl = readl(&cmpll->ddrpll_ctrl); - ddr_pll_ctrl &= 0xFF; - ddr_pll_ctrl |= (DDR_N<<16 | DDR_P<<8); - writel(ddr_pll_ctrl, &cmpll->ddrpll_ctrl); - - ddr_delay(10); - - /* Power up clock1-5 */ - writel(0x0, &cmpll->ddrpll_pwd); - - /* Program the freq and divider values for clock1-3 */ - writel(((0<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); - ddr_delay(1); - writel(((1<<8) | DDR_MDIV1), &cmpll->ddrpll_div1); - writel((1<<31 | 1<<28 | (DDR_INTFREQ2<<24) | DDR_FRACFREQ2), - &cmpll->ddrpll_freq2); - writel(((1<<8) | DDR_MDIV2), &cmpll->ddrpll_div2); - writel(((0<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); - ddr_delay(1); - writel(((1<<8) | DDR_MDIV3), &cmpll->ddrpll_div3); - ddr_delay(1); - writel((0<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), - &cmpll->ddrpll_freq3); - ddr_delay(1); - writel((1<<31 | 1<<28 | (DDR_INTFREQ3<<24) | DDR_FRACFREQ3), - &cmpll->ddrpll_freq3); - - ddr_delay(5); - - /* Wait for PLL to lock */ - while ((readl(&cmpll->ddrpll_ctrl) & BIT(7)) != BIT(7)) - ; - - /* Power up RCD */ - writel(BIT(0), DDR_RCD); -} - -static void peripheral_enable(void) -{ - /* Wake-up the l3_slow clock */ - writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl); - - /* - * Note on Timers: - * There are 8 timers(0-7) out of which timer 0 is a secure timer. - * Timer 0 mux should not be changed - * - * To access the timer registers we need the to be - * enabled which is what we do in the first step - */ - - /* Enable timer1 */ - writel(PRCM_MOD_EN, &cmalwon->timer1clkctrl); - /* Select timer1 clock to be CLKIN (27MHz) */ - writel(BIT(1), CM_TIMER1_CLKSEL); - - /* Wait for timer1 to be ON-ACTIVE */ - while (((readl(&cmalwon->l3slowclkstctrl) - & (0x80000<<1))>>20) != 1) - ; - /* Wait for timer1 to be enabled */ - while (((readl(&cmalwon->timer1clkctrl) & 0x30000)>>16) != 0) - ; - /* Active posted mode */ - writel(PRCM_MOD_EN, (DM_TIMER1_BASE + 0x54)); - while (readl(DM_TIMER1_BASE + 0x10) & BIT(0)) - ; - /* Start timer1 */ - writel(BIT(0), (DM_TIMER1_BASE + 0x38)); - - /* eFuse */ - writel(PRCM_MOD_EN, CM_ALWON_CUST_EFUSE_CLKCTRL); - while (readl(CM_ALWON_CUST_EFUSE_CLKCTRL) != PRCM_MOD_EN) - ; - - /* Enable gpio0 */ - writel(PRCM_MOD_EN, &cmalwon->gpio0clkctrl); - while (readl(&cmalwon->gpio0clkctrl) != PRCM_MOD_EN) - ; - writel((BIT(1) | BIT(8)), &cmalwon->gpio0clkctrl); - - /* Enable gpio1 */ - writel(PRCM_MOD_EN, &cmalwon->gpio1clkctrl); - while (readl(&cmalwon->gpio1clkctrl) != PRCM_MOD_EN) - ; - writel((BIT(1) | BIT(8)), &cmalwon->gpio1clkctrl); - - /* Enable spi */ - writel(PRCM_MOD_EN, &cmalwon->spiclkctrl); - while (readl(&cmalwon->spiclkctrl) != PRCM_MOD_EN) - ; - - /* Enable i2c0 */ - writel(PRCM_MOD_EN, &cmalwon->i2c0clkctrl); - while (readl(&cmalwon->i2c0clkctrl) != PRCM_MOD_EN) - ; - - /* Enable ethernet0 */ - writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl); - writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl); - writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl); - - /* Enable hsmmc */ - writel(PRCM_MOD_EN, &cmalwon->sdioclkctrl); - while (readl(&cmalwon->sdioclkctrl) != PRCM_MOD_EN) - ; -} - -void setup_clocks_for_console(void) -{ - /* Fix ROM code bug - from TI-PSP-04.00.02.14 */ - writel(0x0, CM_SYSCLK10_CLKSEL); - - ddr_pll_bypass_ti816x(); - - /* Enable uart0-2 */ - writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl); - while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmalwon->uart1clkctrl); - while (readl(&cmalwon->uart1clkctrl) != PRCM_MOD_EN) - ; - writel(PRCM_MOD_EN, &cmalwon->uart2clkctrl); - while (readl(&cmalwon->uart2clkctrl) != PRCM_MOD_EN) - ; - while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100) - ; -} - -void setup_early_clocks(void) -{ - setup_clocks_for_console(); -} - -void prcm_init(void) -{ - /* Enable the control */ - writel(PRCM_MOD_EN, &cmalwon->controlclkctrl); - - main_pll_init_ti816x(); - ddr_pll_init_ti816x(); - - /* - * With clk freqs setup to desired values, - * enable the required peripherals - */ - peripheral_enable(); -} diff --git a/arch/arm/mach-omap2/am33xx/ddr.c b/arch/arm/mach-omap2/am33xx/ddr.c index f8434ec..5f970d9 100644 --- a/arch/arm/mach-omap2/am33xx/ddr.c +++ b/arch/arm/mach-omap2/am33xx/ddr.c @@ -182,14 +182,6 @@ void config_sdram_emif4d5(const struct emif_regs *regs, int nr) */ void config_sdram(const struct emif_regs *regs, int nr) { -#ifdef CONFIG_TI816X - writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); - writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1); - writel(regs->emif_ddr_phy_ctlr_1, &emif_reg[nr]->emif_ddr_phy_ctrl_1_shdw); - writel(0x0000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* initially a large refresh period */ - writel(0x1000613B, &emif_reg[nr]->emif_sdram_ref_ctrl); /* trigger initialization */ - writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); -#else if (regs->zq_config) { writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); writel(regs->sdram_config, &cstat->secure_emif_sdram_config); @@ -211,7 +203,6 @@ void config_sdram(const struct emif_regs *regs, int nr) /* Write REG_COS_COUNT_1, REG_COS_COUNT_2, and REG_PR_OLD_COUNT. */ if (regs->ocp_config) writel(regs->ocp_config, &emif_reg[nr]->emif_l3_config); -#endif } /** diff --git a/arch/arm/mach-omap2/am33xx/ti816x_emif4.c b/arch/arm/mach-omap2/am33xx/ti816x_emif4.c deleted file mode 100644 index 707ea80..0000000 --- a/arch/arm/mach-omap2/am33xx/ti816x_emif4.c +++ /dev/null @@ -1,165 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * ti816x_emif4.c - * - * TI816x emif4 configuration file - * - * Copyright (C) 2017, Konsulko Group - */ - -#include <common.h> -#include <asm/arch/cpu.h> -#include <asm/arch/ddr_defs.h> -#include <asm/arch/hardware.h> -#include <asm/arch/clock.h> -#include <asm/arch/sys_proto.h> -#include <asm/io.h> -#include <asm/emif.h> -#include <linux/delay.h> - -/********************************************************************* - * Init DDR3 on TI816X EVM - *********************************************************************/ -static void ddr_init_settings(const struct cmd_control *ctrl, int emif) -{ - /* - * setup use_rank_delays to 1. This is only necessary when - * multiple ranks are in use. Though the EVM does not have - * multiple ranks, this is a good value to set. - */ - writel(1, DDRPHY_CONFIG_BASE + 0x134); // DATA0_REG_PHY_USE_RANK0_DELAYS - writel(1, DDRPHY_CONFIG_BASE + 0x1d8); // DATA1_REG_PHY_USE_RANK0_DELAYS - writel(1, DDRPHY_CONFIG_BASE + 0x27c); // DATA2_REG_PHY_USE_RANK0_DELAYS - writel(1, DDRPHY_CONFIG_BASE + 0x320); // DATA3_REG_PHY_USE_RANK0_DELAYS - - config_cmd_ctrl(ctrl, emif); - - /* for ddr3 this needs to be set to 1 */ - writel(0x1, DDRPHY_CONFIG_BASE + 0x0F8); /* init mode */ - writel(0x1, DDRPHY_CONFIG_BASE + 0x104); - writel(0x1, DDRPHY_CONFIG_BASE + 0x19C); - writel(0x1, DDRPHY_CONFIG_BASE + 0x1A8); - writel(0x1, DDRPHY_CONFIG_BASE + 0x240); - writel(0x1, DDRPHY_CONFIG_BASE + 0x24C); - writel(0x1, DDRPHY_CONFIG_BASE + 0x2E4); - writel(0x1, DDRPHY_CONFIG_BASE + 0x2F0); - - /* - * This represents the initial value for the leveling process. The - * value is a ratio - so 0x100 represents one cycle. The real delay - * is determined through the leveling process. - * - * During the leveling process, 0x20 is subtracted from the value, so - * we have added that to the value we want to set. We also set the - * values such that byte3 completes leveling after byte2 and byte1 - * after byte0. - */ - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0F0); /* data0 writelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x0F4); /* */ - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x194); /* data1 writelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x198); /* */ - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x238); /* data2 writelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x23c); /* */ - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2dc); /* data3 writelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x2e0); /* */ - - - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x0FC); /* data0 gatelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x100); - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x1A0); /* data1 gatelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x1A4); - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x244); /* data2 gatelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x248); - writel((0x20 << 10) | 0x20, DDRPHY_CONFIG_BASE + 0x2E8); /* data3 gatelvl init ratio */ - writel(0x0, DDRPHY_CONFIG_BASE + 0x2EC); - - writel(0x5, DDRPHY_CONFIG_BASE + 0x00C); /* cmd0 io config - output impedance of pad */ - writel(0x5, DDRPHY_CONFIG_BASE + 0x010); /* cmd0 io clk config - output impedance of pad */ - writel(0x5, DDRPHY_CONFIG_BASE + 0x040); /* cmd1 io config - output impedance of pad */ - writel(0x5, DDRPHY_CONFIG_BASE + 0x044); /* cmd1 io clk config - output impedance of pad */ - writel(0x5, DDRPHY_CONFIG_BASE + 0x074); /* cmd2 io config - output impedance of pad */ - writel(0x5, DDRPHY_CONFIG_BASE + 0x078); /* cmd2 io clk config - output impedance of pad */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x0A8); /* data0 io config - output impedance of pad */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x0AC); /* data0 io clk config - output impedance of pad */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x14C); /* data1 io config - output impedance of pa */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x150); /* data1 io clk config - output impedance of pad */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x1F0); /* data2 io config - output impedance of pa */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x1F4); /* data2 io clk config - output impedance of pad */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x294); /* data3 io config - output impedance of pa */ - writel(0x4, DDRPHY_CONFIG_BASE + 0x298); /* data3 io clk config - output impedance of pad */ -} - -static void ddr3_sw_levelling(const struct ddr_data *data, int emif) -{ - /* Set the correct value to DDR_VTP_CTRL_0 */ - writel(0x6, (DDRPHY_CONFIG_BASE + 0x358)); - - writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x108)); - writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x1AC)); - writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x250)); - writel(data->datafwsratio0, (DDRPHY_CONFIG_BASE + 0x2F4)); - - writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x0DC)); - writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x180)); - writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x224)); - writel(data->datawdsratio0, (DDRPHY_CONFIG_BASE + 0x2C8)); - - writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x120)); - writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x1C4)); - writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x268)); - writel(data->datawrsratio0, (DDRPHY_CONFIG_BASE + 0x30C)); - - writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x0C8)); - writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x16C)); - writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x210)); - writel(data->datardsratio0, (DDRPHY_CONFIG_BASE + 0x2B4)); -} - -static struct dmm_lisa_map_regs *hw_lisa_map_regs = - (struct dmm_lisa_map_regs *)DMM_BASE; - -#define DMM_PAT_BASE_ADDR (DMM_BASE + 0x420) -void config_dmm(const struct dmm_lisa_map_regs *regs) -{ - writel(0, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(0, &hw_lisa_map_regs->dmm_lisa_map_0); - - writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3); - writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2); - writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1); - writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0); - - /* Enable Tiled Access */ - writel(0x80000000, DMM_PAT_BASE_ADDR); -} - -void config_ddr(const struct ddr_data *data, const struct cmd_control *ctrl, - const struct emif_regs *regs, - const struct dmm_lisa_map_regs *lisa_regs, int nrs) -{ - int i; - - enable_emif_clocks(); - - for (i = 0; i < nrs; i++) - ddr_init_settings(ctrl, i); - - enable_dmm_clocks(); - - /* Program the DMM to for non-interleaved configuration */ - config_dmm(lisa_regs); - - /* Program EMIF CFG Registers */ - for (i = 0; i < nrs; i++) { - set_sdram_timings(regs, i); - config_sdram(regs, i); - } - - udelay(1000); - for (i = 0; i < nrs; i++) - ddr3_sw_levelling(data, i); - - udelay(50000); /* Some delay needed */ -} diff --git a/arch/arm/mach-omap2/boot-common.c b/arch/arm/mach-omap2/boot-common.c index 9a342a1..a2dd5f6 100644 --- a/arch/arm/mach-omap2/boot-common.c +++ b/arch/arm/mach-omap2/boot-common.c @@ -75,23 +75,6 @@ void save_omap_boot_params(void) if (boot_device == BOOT_DEVICE_QSPI_4) boot_device = BOOT_DEVICE_SPI; #endif -#ifdef CONFIG_TI816X - /* - * On PG2.0 and later TI816x the values we get when booting are not the - * same as on PG1.0, which is what the defines are based on. Update - * them as needed. - */ - if (get_cpu_rev() != 1) { - if (boot_device == 0x05) { - omap_boot_params->boot_device = BOOT_DEVICE_NAND; - boot_device = BOOT_DEVICE_NAND; - } - if (boot_device == 0x08) { - omap_boot_params->boot_device = BOOT_DEVICE_MMC1; - boot_device = BOOT_DEVICE_MMC1; - } - } -#endif /* * When booting from peripheral booting, the boot device is not usable * as-is (unless there is support for it), so the boot device is instead @@ -183,8 +166,7 @@ void save_omap_boot_params(void) gd->arch.omap_boot_mode = boot_mode; -#if !defined(CONFIG_TI816X) && \ - !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) +#if !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX) /* CH flags */ diff --git a/arch/arm/mach-rmobile/Kconfig.rcar3 b/arch/arm/mach-rmobile/Kconfig.rcar3 index 5f33821..ad35d10 100644 --- a/arch/arm/mach-rmobile/Kconfig.rcar3 +++ b/arch/arm/mach-rmobile/Kconfig.rcar3 @@ -99,6 +99,11 @@ config TARGET_CONDOR help Support for Renesas R-Car Gen3 Condor platform +config TARGET_V3HSK + bool "V3HSK board" + help + Support for Renesas R-Car Gen3 V3HSK platform + config TARGET_DRAAK bool "Draak board" imply R8A77995 @@ -111,6 +116,11 @@ config TARGET_EAGLE help Support for Renesas R-Car Gen3 Eagle platform +config TARGET_V3MSK + bool "V3MSK board" + help + Support for Renesas R-Car Gen3 V3MSK platform + config TARGET_EBISU bool "Ebisu board" imply R8A77990 @@ -166,6 +176,8 @@ source "board/renesas/eagle/Kconfig" source "board/renesas/ebisu/Kconfig" source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" +source "board/renesas/v3hsk/Kconfig" +source "board/renesas/v3msk/Kconfig" source "board/beacon/beacon-rzg2m/Kconfig" source "board/hoperun/hihope-rzg2/Kconfig" source "board/silinux/ek874/Kconfig" diff --git a/arch/arm/mach-rockchip/board.c b/arch/arm/mach-rockchip/board.c index 45d9eae..8d7b39b 100644 --- a/arch/arm/mach-rockchip/board.c +++ b/arch/arm/mach-rockchip/board.c @@ -41,7 +41,7 @@ static bool updatable_image(struct disk_partition *info) uuid_str_to_bin(info->type_guid, image_type_guid.b, UUID_STR_FORMAT_GUID); - for (i = 0; i < num_image_type_guids; i++) { + for (i = 0; i < update_info.num_images; i++) { if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) { ret = true; break; @@ -59,7 +59,7 @@ static void set_image_index(struct disk_partition *info, int index) uuid_str_to_bin(info->type_guid, image_type_guid.b, UUID_STR_FORMAT_GUID); - for (i = 0; i < num_image_type_guids; i++) { + for (i = 0; i < update_info.num_images; i++) { if (!guidcmp(&fw_images[i].image_type_id, &image_type_guid)) { fw_images[i].image_index = index; break; diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index f5f4b20..0dc1e5c 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -622,7 +622,7 @@ static int stm32mp_bsec_read(struct udevice *dev, int offset, shadow = false; } - if ((offs % 4) || (size % 4)) + if ((offs % 4) || (size % 4) || !size) return -EINVAL; if (IS_ENABLED(CONFIG_OPTEE) && priv->tee) { @@ -678,7 +678,7 @@ static int stm32mp_bsec_write(struct udevice *dev, int offset, shadow = false; } - if ((offs % 4) || (size % 4)) + if ((offs % 4) || (size % 4) || !size) return -EINVAL; if (IS_ENABLED(CONFIG_OPTEE) && priv->tee) { diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c index cfafa53..c695cc1 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/cmd_stm32prog.c @@ -180,15 +180,6 @@ U_BOOT_CMD(stm32prog, 5, 0, do_stm32prog, " <size> = size of flashlayout (optional for image with STM32 header)\n" ); -#ifdef CONFIG_STM32MP15x_STM32IMAGE -bool stm32prog_get_tee_partitions(void) -{ - if (stm32prog_data) - return stm32prog_data->tee_detected; - - return false; -} -#endif bool stm32prog_get_fsbl_nor(void) { diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c index 6f3641c..9ba94be 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.c @@ -63,6 +63,12 @@ static const efi_guid_t uuid_mmc[3] = { ROOTFS_MMC2_UUID }; +/* + * GUID value defined in the FWU specification for identification + * of the FWU metadata partition. + */ +#define FWU_MDATA_UUID "8a7a84a0-8387-40f6-ab41-a8b9a5a60d23" + /* FIP type partition UUID used by TF-A*/ #define FIP_TYPE_UUID "19D5DF83-11B0-457B-BE2C-7559C13142A5" @@ -208,11 +214,6 @@ static int optee_ta_invoke(struct stm32prog_data *data, int cmd, int type, return rc; } -/* partition handling routines : CONFIG_CMD_MTDPARTS */ -int mtdparts_init(void); -int find_dev_and_part(const char *id, struct mtd_device **dev, - u8 *part_num, struct part_info **part); - char *stm32prog_get_error(struct stm32prog_data *data) { static const char error_msg[] = "Unspecified"; @@ -430,8 +431,14 @@ static int parse_type(struct stm32prog_data *data, } } else if (!strcmp(p, "FIP")) { part->part_type = PART_FIP; + } else if (!strcmp(p, "FWU_MDATA")) { + part->part_type = PART_FWU_MDATA; + } else if (!strcmp(p, "ENV")) { + part->part_type = PART_ENV; } else if (!strcmp(p, "System")) { part->part_type = PART_SYSTEM; + } else if (!strcmp(p, "ESP")) { + part->part_type = PART_ESP; } else if (!strcmp(p, "FileSystem")) { part->part_type = PART_FILESYSTEM; } else if (!strcmp(p, "RawImage")) { @@ -514,7 +521,7 @@ static int parse_offset(struct stm32prog_data *data, stm32prog_err("Layout line %d: invalid part '%s'", i, p); } else { - part->addr = simple_strtoull(p, &tail, 0); + part->addr = simple_strtoull(p, &tail, 10); if (tail == p || *tail != '\0') { stm32prog_err("Layout line %d: invalid offset '%s'", i, p); @@ -741,6 +748,7 @@ static int init_device(struct stm32prog_data *data, struct mmc *mmc = NULL; struct blk_desc *block_dev = NULL; struct mtd_info *mtd = NULL; + struct mtd_info *partition; char mtd_id[16]; int part_id; int ret; @@ -749,6 +757,7 @@ static int init_device(struct stm32prog_data *data, u64 part_addr, part_size; bool part_found; const char *part_name; + u8 i; switch (dev->target) { case STM32PROG_MMC: @@ -793,10 +802,11 @@ static int init_device(struct stm32prog_data *data, stm32prog_err("unknown device type = %d", dev->target); return -ENODEV; } + /* register partitions with MTDIDS/MTDPARTS or OF fallback */ + mtd_probe_devices(); get_mtd_by_target(mtd_id, dev->target, dev->dev_id); log_debug("%s\n", mtd_id); - mtdparts_init(); mtd = get_mtd_device_nm(mtd_id); if (IS_ERR(mtd)) { stm32prog_err("MTD device %s not found", mtd_id); @@ -943,25 +953,23 @@ static int init_device(struct stm32prog_data *data, } if (IS_ENABLED(CONFIG_MTD) && mtd) { - char mtd_part_id[32]; - struct part_info *mtd_part; - struct mtd_device *mtd_dev; - u8 part_num; - - sprintf(mtd_part_id, "%s,%d", mtd_id, - part->part_id - 1); - ret = find_dev_and_part(mtd_part_id, &mtd_dev, - &part_num, &mtd_part); - if (ret != 0) { - stm32prog_err("%s (0x%x): Invalid MTD partition %s", - part->name, part->id, - mtd_part_id); + i = 0; + list_for_each_entry(partition, &mtd->partitions, node) { + if ((part->part_id - 1) == i) { + part_found = true; + break; + } + i++; + } + if (part_found) { + part_addr = partition->offset; + part_size = partition->size; + part_name = partition->name; + } else { + stm32prog_err("%s (0x%x):Couldn't find part %d on device mtd %s", + part->name, part->id, part->part_id, mtd_id); return -ENODEV; } - part_addr = mtd_part->offset; - part_size = mtd_part->size; - part_name = mtd_part->name; - part_found = true; } /* no partition for this device */ @@ -999,9 +1007,6 @@ static int treat_partition_list(struct stm32prog_data *data) INIT_LIST_HEAD(&data->dev[j].part_list); } -#ifdef CONFIG_STM32MP15x_STM32IMAGE - data->tee_detected = false; -#endif data->fsbl_nor_detected = false; for (i = 0; i < data->part_nb; i++) { part = &data->part_array[i]; @@ -1053,14 +1058,6 @@ static int treat_partition_list(struct stm32prog_data *data) !strncmp(part->name, "fsbl", 4)) data->fsbl_nor_detected = true; /* fallthrough */ - case STM32PROG_NAND: - case STM32PROG_SPI_NAND: -#ifdef CONFIG_STM32MP15x_STM32IMAGE - if (!data->tee_detected && - !strncmp(part->name, "tee", 3)) - data->tee_detected = true; - break; -#endif default: break; } @@ -1130,10 +1127,20 @@ static int create_gpt_partitions(struct stm32prog_data *data) case PART_BINARY: type_str = LINUX_RESERVED_UUID; break; + case PART_ENV: + type_str = "u-boot-env"; + break; case PART_FIP: type_str = FIP_TYPE_UUID; break; - default: + case PART_FWU_MDATA: + type_str = FWU_MDATA_UUID; + break; + case PART_ESP: + /* EFI System Partition */ + type_str = "system"; + break; + default: /* PART_FILESYSTEM or PART_SYSTEM for distro */ type_str = "linux"; break; } @@ -1439,8 +1446,11 @@ int stm32prog_otp_write(struct stm32prog_data *data, u32 offset, u8 *buffer, if (!data->otp_part) { data->otp_part = memalign(CONFIG_SYS_CACHELINE_SIZE, otp_size); - if (!data->otp_part) + if (!data->otp_part) { + stm32prog_err("OTP write issue %d", -ENOMEM); + return -ENOMEM; + } } if (!offset) @@ -1503,6 +1513,8 @@ int stm32prog_otp_read(struct stm32prog_data *data, u32 offset, u8 *buffer, memcpy(buffer, (void *)((uintptr_t)data->otp_part + offset), *size); end_otp_read: + if (result) + stm32prog_err("OTP read issue %d", result); log_debug("%s: result %i\n", __func__, result); return result; @@ -1556,6 +1568,8 @@ int stm32prog_otp_start(struct stm32prog_data *data) free(data->otp_part); data->otp_part = NULL; + if (result) + stm32prog_err("OTP write issue %d", result); log_debug("%s: result %i\n", __func__, result); return result; diff --git a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h index 58f4b96..feba295 100644 --- a/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h +++ b/arch/arm/mach-stm32mp/cmd_stm32prog/stm32prog.h @@ -96,12 +96,20 @@ struct stm32_header_v2 { u8 extension_padding[376]; }; -/* partition type in flashlayout file */ +/* + * partition type in flashlayout file + * SYSTEM = linux partition, bootable + * FILESYSTEM = linux partition + * ESP = EFI system partition + */ enum stm32prog_part_type { PART_BINARY, PART_FIP, + PART_FWU_MDATA, + PART_ENV, PART_SYSTEM, PART_FILESYSTEM, + PART_ESP, RAW_IMAGE, }; @@ -149,9 +157,6 @@ struct stm32prog_data { struct stm32prog_dev_t dev[STM32PROG_MAX_DEV]; /* array of device */ int part_nb; /* nb of partition */ struct stm32prog_part_t *part_array; /* array of partition */ -#ifdef CONFIG_STM32MP15x_STM32IMAGE - bool tee_detected; -#endif bool fsbl_nor_detected; /* command internal information */ diff --git a/arch/arm/mach-stm32mp/ecdsa_romapi.c b/arch/arm/mach-stm32mp/ecdsa_romapi.c index 12b42b9..93c561c 100644 --- a/arch/arm/mach-stm32mp/ecdsa_romapi.c +++ b/arch/arm/mach-stm32mp/ecdsa_romapi.c @@ -5,6 +5,7 @@ * Implements ECDSA signature verification via the STM32MP ROM. */ #include <asm/system.h> +#include <asm/arch/sys_proto.h> #include <dm/device.h> #include <linux/types.h> #include <u-boot/ecdsa.h> diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index c85ae6a..1cdc5e3 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -21,8 +21,10 @@ #define STM32_DBGMCU_BASE 0x50081000 #endif #define STM32_FMC2_BASE 0x58002000 +#define STM32_IWDG2_BASE 0x5A002000 #define STM32_DDRCTRL_BASE 0x5A003000 #define STM32_DDRPHYC_BASE 0x5A004000 +#define STM32_IWDG1_BASE 0x5C003000 #define STM32_TZC_BASE 0x5C006000 #define STM32_ETZPC_BASE 0x5C007000 #define STM32_STGEN_BASE 0x5C008000 diff --git a/arch/arm/mach-stm32mp/include/mach/stm32prog.h b/arch/arm/mach-stm32mp/include/mach/stm32prog.h index 99be4e1..23d1adf 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32prog.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32prog.h @@ -11,8 +11,4 @@ int stm32prog_read_medium_virt(struct dfu_entity *dfu, u64 offset, void *buf, long *len); int stm32prog_get_medium_size_virt(struct dfu_entity *dfu, u64 *size); -#ifdef CONFIG_STM32MP15x_STM32IMAGE -bool stm32prog_get_tee_partitions(void); -#endif - bool stm32prog_get_fsbl_nor(void); diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 0d39b67..83fb32a 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -44,6 +44,7 @@ u32 get_cpu_dev(void); #define CPU_REV1_2 0x1003 #define CPU_REV2 0x2000 #define CPU_REV2_1 0x2001 +#define CPU_REV2_2 0x2003 /* return Silicon revision = REV_ID[15:0] of Device Version */ u32 get_cpu_rev(void); diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c index 1e69673..39b5200 100644 --- a/arch/arm/mach-stm32mp/psci.c +++ b/arch/arm/mach-stm32mp/psci.c @@ -161,6 +161,12 @@ #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) #define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) +/* IWDG */ +#define IWDG_KR 0x00 +#define IWDG_KR_RELOAD_KEY 0xaaaa +#define IWDG_EWCR 0x14 +#define IWDG_EWCR_EWIC BIT(14) + #define STM32MP1_PSCI_NR_CPUS 2 #if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS" @@ -696,7 +702,18 @@ void __secure psci_system_suspend(u32 __always_unused function_id, u32 ep, u32 context_id) { u32 saved_mcudivr, saved_pll3cr, saved_pll4cr, saved_mssckselr; + u32 gicd_addr = stm32mp_get_gicd_base_address(); + bool iwdg1_wake = false; + bool iwdg2_wake = false; + bool other_wake = false; u32 saved_pwrctl, reg; + u32 gic_enabled[8]; + u32 irqs; + int i; + + /* Cache enable mask of all 256 SPI */ + for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) + gic_enabled[i] = readl(gicd_addr + GICD_ISENABLERn + 0x4 + 4 * i); /* Disable IO compensation */ @@ -725,11 +742,57 @@ void __secure psci_system_suspend(u32 __always_unused function_id, setbits_le32(STM32_PWR_BASE + PWR_CR3, PWR_CR3_DDRSREN); writel(0x3, STM32_RCC_BASE + RCC_MP_SREQSETR); - /* Zzz, enter stop mode */ - asm volatile( - "isb\n" - "dsb\n" - "wfi\n"); + /* Ping the IWDG before entering suspend */ + iwdg1_wake = !!(gic_enabled[4] & BIT(22)); /* SPI 150 */ + iwdg2_wake = !!(gic_enabled[4] & BIT(23)); /* SPI 151 */ + + for (;;) { + /* Ping IWDG1 and ACK pretimer IRQ */ + if (iwdg1_wake) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG1_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG1_BASE + IWDG_EWCR); + } + + /* Ping IWDG2 and ACK pretimer IRQ */ + if (iwdg2_wake) { + writel(IWDG_KR_RELOAD_KEY, STM32_IWDG2_BASE + IWDG_KR); + writel(IWDG_EWCR_EWIC, STM32_IWDG2_BASE + IWDG_EWCR); + } + + iwdg1_wake = false; + iwdg2_wake = false; + + /* Zzz, enter stop mode */ + asm volatile( + "isb\n" + "dsb\n" + "wfi\n"); + + /* Determine the wake up source */ + for (i = 0; i < ARRAY_SIZE(gic_enabled); i++) { + irqs = readl(gicd_addr + GICR_IGROUPMODRn + 0x4 + 4 * i); + irqs &= gic_enabled[i]; + if (!irqs) + continue; + + /* Test whether IWDG pretimeout triggered the wake up. */ + if (i == 4) { /* SPI Num 128..159 */ + iwdg1_wake = !!(irqs & BIT(22)); /* SPI 150 */ + iwdg2_wake = !!(irqs & BIT(23)); /* SPI 151 */ + irqs &= ~(BIT(22) | BIT(23)); + } + + /* Test whether there is any other wake up trigger. */ + if (irqs) { + other_wake = true; + break; + } + } + + /* Other wake up triggers pending, let OS deal with all of it. */ + if (other_wake) + break; + } writel(0x3, STM32_RCC_BASE + RCC_MP_SREQCLRR); ddr_sw_self_refresh_exit(); diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp15x.c index 660c907..afc56b0 100644 --- a/arch/arm/mach-stm32mp/stm32mp15x.c +++ b/arch/arm/mach-stm32mp/stm32mp15x.c @@ -266,7 +266,7 @@ static const char * const soc_type[] = { }; static const char * const soc_pkg[] = { "??", "AD", "AC", "AB", "AA" }; -static const char * const soc_rev[] = { "?", "A", "B", "Z" }; +static const char * const soc_rev[] = { "?", "A", "B", "Z", "Y"}; static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, unsigned int *rev) @@ -307,6 +307,9 @@ static void get_cpu_string_offsets(unsigned int *type, unsigned int *pkg, case CPU_REV2_1: *rev = 3; break; + case CPU_REV2_2: + *rev = 4; + break; default: *rev = 0; break; diff --git a/arch/arm/mach-uniphier/dram/ddrphy-init.h b/arch/arm/mach-uniphier/dram/ddrphy-init.h index 09981f6..4431f5c 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-init.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-init.h @@ -4,7 +4,7 @@ */ #ifndef ARCH_DDRPHY_INIT_H -#define ARCH_DDRPHY_INTT_H +#define ARCH_DDRPHY_INIT_H #include <linux/compiler.h> #include <linux/types.h> diff --git a/arch/arm/mach-versal-net/include/mach/hardware.h b/arch/arm/mach-versal-net/include/mach/hardware.h index c5e4e22..3f04104 100644 --- a/arch/arm/mach-versal-net/include/mach/hardware.h +++ b/arch/arm/mach-versal-net/include/mach/hardware.h @@ -27,7 +27,13 @@ struct iou_scntrs_regs { u32 base_frequency_id_register; /* 0x20 */ }; +struct crp_regs { + u32 reserved0[128]; + u32 boot_mode_usr; /* 0x200 */ +}; + #define VERSAL_NET_CRL_APB_BASEADDR 0xEB5E0000 +#define VERSAL_NET_CRP_BASEADDR 0xF1260000 #define VERSAL_NET_IOU_SCNTR_SECURE 0xEC920000 #define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT BIT(25) @@ -36,6 +42,7 @@ struct iou_scntrs_regs { #define IOU_SCNTRS_CONTROL_EN 1 #define crlapb_base ((struct crlapb_regs *)VERSAL_NET_CRL_APB_BASEADDR) +#define crp_base ((struct crp_regs *)VERSAL_NET_CRP_BASEADDR) #define iou_scntr_secure ((struct iou_scntrs_regs *)VERSAL_NET_IOU_SCNTR_SECURE) #define PMC_TAP 0xF11A0000 @@ -44,11 +51,26 @@ struct iou_scntrs_regs { #define PMC_TAP_VERSION (PMC_TAP + 0x4) # define PMC_VERSION_MASK GENMASK(7, 0) # define PS_VERSION_MASK GENMASK(15, 8) +# define PS_VERSION_PRODUCTION 0x20 # define RTL_VERSION_MASK GENMASK(23, 16) # define PLATFORM_MASK GENMASK(27, 24) # define PLATFORM_VERSION_MASK GENMASK(31, 28) #define PMC_TAP_USERCODE (PMC_TAP + 0x8) +/* Bootmode setting values */ +#define BOOT_MODES_MASK 0x0000000F +#define QSPI_MODE_24BIT 0x00000001 +#define QSPI_MODE_32BIT 0x00000002 +#define SD_MODE 0x00000003 /* sd 0 */ +#define SD_MODE1 0x00000005 /* sd 1 */ +#define EMMC_MODE 0x00000006 +#define USB_MODE 0x00000007 +#define OSPI_MODE 0x00000008 +#define SD1_LSHFT_MODE 0x0000000E /* SD1 Level shifter */ +#define JTAG_MODE 0x00000000 +#define BOOT_MODE_USE_ALT 0x100 +#define BOOT_MODE_ALT_SHIFT 12 + enum versal_net_platform { VERSAL_NET_SILICON = 0, VERSAL_NET_SPP = 1, diff --git a/arch/arm/mach-versal/include/mach/sys_proto.h b/arch/arm/mach-versal/include/mach/sys_proto.h index 3f01508..433f9ba 100644 --- a/arch/arm/mach-versal/include/mach/sys_proto.h +++ b/arch/arm/mach-versal/include/mach/sys_proto.h @@ -10,6 +10,7 @@ enum { TCM_SPLIT, }; +void initialize_tcm(bool mode); void tcm_init(u8 mode); void mem_map_fill(void); diff --git a/arch/arm/mach-versal/mp.c b/arch/arm/mach-versal/mp.c index 9b0518d..5b850f3 100644 --- a/arch/arm/mach-versal/mp.c +++ b/arch/arm/mach-versal/mp.c @@ -23,7 +23,7 @@ #define VERSAL_CRL_RST_CPU_R5_RESET_PGE_MASK 0x10 #define VERSAL_CRLAPB_CPU_R5_CTRL_CLKACT_MASK 0x1000000 -void set_r5_halt_mode(u8 halt, u8 mode) +static void set_r5_halt_mode(u8 halt, u8 mode) { u32 tmp; @@ -44,7 +44,7 @@ void set_r5_halt_mode(u8 halt, u8 mode) } } -void set_r5_tcm_mode(u8 mode) +static void set_r5_tcm_mode(u8 mode) { u32 tmp; @@ -62,7 +62,7 @@ void set_r5_tcm_mode(u8 mode) writel(tmp, &rpu_base->rpu_glbl_ctrl); } -void release_r5_reset(u8 mode) +static void release_r5_reset(u8 mode) { u32 tmp; @@ -77,7 +77,7 @@ void release_r5_reset(u8 mode) writel(tmp, &crlapb_base->rst_cpu_r5); } -void enable_clock_r5(void) +static void enable_clock_r5(void) { u32 tmp; diff --git a/arch/arm/mach-zynqmp/handoff.c b/arch/arm/mach-zynqmp/handoff.c index b9e0c6c..511b241 100644 --- a/arch/arm/mach-zynqmp/handoff.c +++ b/arch/arm/mach-zynqmp/handoff.c @@ -9,6 +9,7 @@ #include <asm/io.h> #include <asm/arch/hardware.h> #include <asm/arch/sys_proto.h> +#include <spl.h> /* * atfhandoffparams diff --git a/arch/arm/mach-zynqmp/mp.c b/arch/arm/mach-zynqmp/mp.c index 7a12f4b..b06c867 100644 --- a/arch/arm/mach-zynqmp/mp.c +++ b/arch/arm/mach-zynqmp/mp.c @@ -326,6 +326,10 @@ int cpu_release(u32 nr, int argc, char *const argv[]) flush_dcache_all(); if (!strncmp(argv[1], "lockstep", 8)) { + if (nr != ZYNQMP_CORE_RPU0) { + printf("Lockstep mode should run on ZYNQMP_CORE_RPU0\n"); + return 1; + } printf("R5 lockstep mode\n"); set_r5_reset(nr, LOCK); set_r5_tcm_mode(LOCK); diff --git a/arch/m68k/include/asm/unaligned.h b/arch/m68k/include/asm/unaligned.h index 328aa0c..7fb482a 100644 --- a/arch/m68k/include/asm/unaligned.h +++ b/arch/m68k/include/asm/unaligned.h @@ -1,15 +1,2 @@ -#ifndef _ASM_M68K_UNALIGNED_H -#define _ASM_M68K_UNALIGNED_H - -#ifdef CONFIG_COLDFIRE -#include <linux/unaligned/be_byteshift.h> -#else -#include <linux/unaligned/access_ok.h> -#endif - -#include <linux/unaligned/generic.h> - -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be - -#endif /* _ASM_M68K_UNALIGNED_H */ +/* SPDX-License-Identifier: GPL-2.0 */ +#include <asm-generic/unaligned.h> diff --git a/arch/mips/include/asm/unaligned.h b/arch/mips/include/asm/unaligned.h index debb9cf..7fb482a 100644 --- a/arch/mips/include/asm/unaligned.h +++ b/arch/mips/include/asm/unaligned.h @@ -1,23 +1,2 @@ /* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org) - */ -#ifndef _ASM_MIPS_UNALIGNED_H -#define _ASM_MIPS_UNALIGNED_H - -#include <linux/compiler.h> -#if defined(__MIPSEB__) -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#elif defined(__MIPSEL__) -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#else -#error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???" -#endif - -#include <linux/unaligned/le_byteshift.h> -#include <linux/unaligned/be_byteshift.h> -#include <linux/unaligned/generic.h> - -#endif /* _ASM_MIPS_UNALIGNED_H */ +#include <asm-generic/unaligned.h> diff --git a/arch/powerpc/include/asm/mc146818rtc.h b/arch/powerpc/include/asm/mc146818rtc.h deleted file mode 100644 index 5f806c4..0000000 --- a/arch/powerpc/include/asm/mc146818rtc.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Machine dependent access functions for RTC registers. - */ -#ifndef __ASM_PPC_MC146818RTC_H -#define __ASM_PPC_MC146818RTC_H - -#include <asm/io.h> - -#ifndef RTC_PORT -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */ -#endif - -/* - * The yet supported machines all access the RTC index register via - * an ISA port access but the way to access the date register differs ... - */ -#define CMOS_READ(addr) ({ \ -outb_p((addr),RTC_PORT(0)); \ -inb_p(RTC_PORT(1)); \ -}) -#define CMOS_WRITE(val, addr) ({ \ -outb_p((addr),RTC_PORT(0)); \ -outb_p((val),RTC_PORT(1)); \ -}) - -#endif /* __ASM_PPC_MC146818RTC_H */ diff --git a/arch/powerpc/include/asm/pci_io.h b/arch/powerpc/include/asm/pci_io.h deleted file mode 100644 index 9b738c3..0000000 --- a/arch/powerpc/include/asm/pci_io.h +++ /dev/null @@ -1,43 +0,0 @@ -/* originally from linux source (asm-ppc/io.h). - * Sanity added by Rob Taylor, Flying Pig Systems, 2000 - */ -#ifndef _PCI_IO_H_ -#define _PCI_IO_H_ - -#include "io.h" - - -#define pci_read_le16(addr, dest) \ - __asm__ __volatile__("lhbrx %0,0,%1" : "=r" (dest) : \ - "r" (addr), "m" (*addr)); - -#define pci_write_le16(addr, val) \ - __asm__ __volatile__("sthbrx %1,0,%2" : "=m" (*addr) : \ - "r" (val), "r" (addr)); - - -#define pci_read_le32(addr, dest) \ - __asm__ __volatile__("lwbrx %0,0,%1" : "=r" (dest) : \ - "r" (addr), "m" (*addr)); - -#define pci_write_le32(addr, val) \ -__asm__ __volatile__("stwbrx %1,0,%2" : "=m" (*addr) : \ - "r" (val), "r" (addr)); - -#define pci_readb(addr,b) ((b) = *(volatile u8 *) (addr)) -#define pci_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b)) - -#if !defined(__BIG_ENDIAN) -#define pci_readw(addr,b) ((b) = *(volatile u16 *) (addr)) -#define pci_readl(addr,b) ((b) = *(volatile u32 *) (addr)) -#define pci_writew(b,addr) ((*(volatile u16 *) (addr)) = (b)) -#define pci_writel(b,addr) ((*(volatile u32 *) (addr)) = (b)) -#else -#define pci_readw(addr,b) pci_read_le16((volatile u16 *)(addr),(b)) -#define pci_readl(addr,b) pci_read_le32((volatile u32 *)(addr),(b)) -#define pci_writew(b,addr) pci_write_le16((volatile u16 *)(addr),(b)) -#define pci_writel(b,addr) pci_write_le32((volatile u32 *)(addr),(b)) -#endif - - -#endif /* _PCI_IO_H_ */ diff --git a/arch/powerpc/include/asm/unaligned.h b/arch/powerpc/include/asm/unaligned.h index 5f1b1e3..7fb482a 100644 --- a/arch/powerpc/include/asm/unaligned.h +++ b/arch/powerpc/include/asm/unaligned.h @@ -1,16 +1,2 @@ -#ifndef _ASM_POWERPC_UNALIGNED_H -#define _ASM_POWERPC_UNALIGNED_H - -#ifdef __KERNEL__ - -/* - * The PowerPC can do unaligned accesses itself in big endian mode. - */ -#include <linux/unaligned/access_ok.h> -#include <linux/unaligned/generic.h> - -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be - -#endif /* __KERNEL__ */ -#endif /* _ASM_POWERPC_UNALIGNED_H */ +/* SPDX-License-Identifier: GPL-2.0 */ +#include <asm-generic/unaligned.h> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a5869..1d61eb8 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0+ dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb -dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb +dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts deleted file mode 100644 index c3f58e2..0000000 --- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts +++ /dev/null @@ -1,136 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2021-2022 Microchip Technology Inc. - * Padmarao Begari <padmarao.begari@microchip.com> - */ - -/dts-v1/; - -#include "microchip-mpfs.dtsi" - -/* Clock frequency (in Hz) of the rtcclk */ -#define RTCCLK_FREQ 1000000 - -/ { - model = "Microchip PolarFire-SoC Icicle Kit"; - compatible = "microchip,mpfs-icicle-reference-rtlv2210", - "microchip,mpfs-icicle-kit", "microchip,mpfs"; - - aliases { - serial1 = &uart1; - ethernet0 = &mac1; - spi0 = &qspi; - }; - - chosen { - stdout-path = "serial1"; - }; - - cpus { - timebase-frequency = <RTCCLK_FREQ>; - }; - - ddrc_cache_lo: memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x0 0x40000000>; - status = "okay"; - }; - - ddrc_cache_hi: memory@1040000000 { - device_type = "memory"; - reg = <0x10 0x40000000 0x0 0x40000000>; - status = "okay"; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - hss_payload: region@BFC00000 { - reg = <0x0 0xBFC00000 0x0 0x400000>; - no-map; - }; - }; -}; - -&refclk { - clock-frequency = <125000000>; -}; - -&uart1 { - status = "okay"; -}; - -&mmc { - status = "okay"; - - bus-width = <4>; - disable-wp; - cap-mmc-highspeed; - cap-sd-highspeed; - card-detect-delay = <200>; - mmc-ddr-1_8v; - mmc-hs200-1_8v; - sd-uhs-sdr12; - sd-uhs-sdr25; - sd-uhs-sdr50; - sd-uhs-sdr104; -}; - -&i2c1 { - status = "okay"; - clock-frequency = <100000>; - - pac193x: pac193x@10 { - compatible = "microchip,pac1934"; - reg = <0x10>; - samp-rate = <64>; - status = "okay"; - ch1: channel0 { - uohms-shunt-res = <10000>; - rail-name = "VDDREG"; - channel_enabled; - }; - ch2: channel1 { - uohms-shunt-res = <10000>; - rail-name = "VDDA25"; - channel_enabled; - }; - ch3: channel2 { - uohms-shunt-res = <10000>; - rail-name = "VDD25"; - channel_enabled; - }; - ch4: channel3 { - uohms-shunt-res = <10000>; - rail-name = "VDDA_REG"; - channel_enabled; - }; - }; -}; - -&mac1 { - status = "okay"; - phy-mode = "sgmii"; - phy-handle = <&phy1>; - phy1: ethernet-phy@9 { - reg = <9>; - ti,fifo-depth = <0x1>; - }; -}; - -&qspi { - status = "okay"; - num-cs = <1>; - - flash0: flash@0 { - compatible = "spi-nand"; - reg = <0x0>; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - spi-max-frequency = <20000000>; - spi-cpol; - spi-cpha; - }; -}; diff --git a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi new file mode 100644 index 0000000..1069134 --- /dev/null +++ b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/ { + compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", + "microchip,mpfs"; + + core_pwm0: pwm@40000000 { + compatible = "microchip,corepwm-rtl-v4"; + reg = <0x0 0x40000000 0x0 0xF0>; + microchip,sync-update-mask = /bits/ 32 <0>; + #pwm-cells = <3>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; + status = "disabled"; + }; + + i2c2: i2c@40000200 { + compatible = "microchip,corei2c-rtl-v7"; + reg = <0x0 0x40000200 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; + interrupt-parent = <&plic>; + interrupts = <122>; + clock-frequency = <100000>; + status = "disabled"; + }; + + pcie: pcie@3000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>; + clock-names = "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + refclk_ccc: cccrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; +}; + +&ccc_nw { + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status = "okay"; +}; diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi index f60283f..f60283f 100644 --- a/arch/riscv/dts/microchip-mpfs-icicle-kit-u-boot.dtsi +++ b/arch/riscv/dts/mpfs-icicle-kit-u-boot.dtsi diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts b/arch/riscv/dts/mpfs-icicle-kit.dts new file mode 100644 index 0000000..8aa5fb1 --- /dev/null +++ b/arch/riscv/dts/mpfs-icicle-kit.dts @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2021-2022 Microchip Technology Inc. + * Padmarao Begari <padmarao.begari@microchip.com> + */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-icicle-kit-fabric.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + model = "Microchip PolarFire-SoC Icicle Kit"; + compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", + "microchip,mpfs"; + + aliases { + ethernet0 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + leds { + compatible = "gpio-leds"; + + led-1 { + gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + label = "led1"; + }; + + led-2 { + gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_RED>; + label = "led2"; + }; + + led-3 { + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_AMBER>; + label = "led3"; + }; + + led-4 { + gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>; + color = <LED_COLOR_ID_AMBER>; + label = "led4"; + }; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1040000000 { + device_type = "memory"; + reg = <0x10 0x40000000 0x0 0x40000000>; + status = "okay"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss_payload: region@BFC00000 { + reg = <0x0 0xBFC00000 0x0 0x400000>; + no-map; + }; + }; +}; + +&core_pwm0 { + status = "okay"; +}; + +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + +&mac0 { + phy-mode = "sgmii"; + phy-handle = <&phy0>; + status = "enabled"; +}; + +&mac1 { + phy-mode = "sgmii"; + phy-handle = <&phy1>; + status = "okay"; + + phy1: ethernet-phy@9 { + reg = <9>; + }; + + phy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&mmuart2 { + status = "okay"; +}; + +&mmuart3 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&refclk_ccc { + clock-frequency = <50000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/riscv/dts/microchip-mpfs.dtsi b/arch/riscv/dts/mpfs.dtsi index 891dd09..6012a28 100644 --- a/arch/riscv/dts/microchip-mpfs.dtsi +++ b/arch/riscv/dts/mpfs.dtsi @@ -2,8 +2,6 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ #include "dt-bindings/clock/microchip-mpfs-clock.h" -#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h" -#include "dt-bindings/interrupt-controller/riscv-hart.h" / { #address-cells = <2>; @@ -11,9 +9,6 @@ model = "Microchip PolarFire SoC"; compatible = "microchip,mpfs"; - chosen { - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -28,12 +23,7 @@ riscv,isa = "rv64imac"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu0_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -59,13 +49,9 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu1_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -91,13 +77,9 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu2_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -123,13 +105,9 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; + cpu3_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; @@ -155,273 +133,322 @@ riscv,isa = "rv64imafdc"; clocks = <&clkcfg CLK_CPU>; tlb-split; + next-level-cache = <&cctrllr>; status = "okay"; - operating-points = < - /* kHz uV */ - 600000 1100000 - 300000 950000 - 150000 750000 - >; cpu4_intc: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + + core4 { + cpu = <&cpu4>; + }; + }; + }; }; - refclk: refclk { + refclk: mssrefclk { compatible = "fixed-clock"; #clock-cells = <0>; }; + syscontroller: syscontroller { + compatible = "microchip,mpfs-sys-controller"; + mboxes = <&mbox 0>; + }; + soc { #address-cells = <2>; #size-cells = <2>; - compatible = "microchip,mpfs-soc", "simple-bus"; + compatible = "simple-bus"; ranges; - clint: clint@2000000 { - compatible = "sifive,clint0"; - reg = <0x0 0x2000000 0x0 0xC000>; - interrupts-extended = - <&cpu0_intc HART_INT_M_SOFT &cpu0_intc HART_INT_M_TIMER - &cpu1_intc HART_INT_M_SOFT &cpu1_intc HART_INT_M_TIMER - &cpu2_intc HART_INT_M_SOFT &cpu2_intc HART_INT_M_TIMER - &cpu3_intc HART_INT_M_SOFT &cpu3_intc HART_INT_M_TIMER - &cpu4_intc HART_INT_M_SOFT &cpu4_intc HART_INT_M_TIMER>; - }; - - cachecontroller: cache-controller@2010000 { - compatible = "sifive,fu540-c000-ccache", "cache"; + cctrllr: cache-controller@2010000 { + compatible = "microchip,mpfs-ccache", "sifive,fu540-c000-ccache", "cache"; reg = <0x0 0x2010000 0x0 0x1000>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_L2_METADATA_CORR - PLIC_INT_L2_METADATA_UNCORR - PLIC_INT_L2_DATA_CORR>; cache-block-size = <64>; cache-level = <2>; cache-sets = <1024>; cache-size = <2097152>; cache-unified; + interrupt-parent = <&plic>; + interrupts = <1>, <3>, <4>, <2>; }; - pdma: pdma@3000000 { - compatible = "microchip,mpfs-pdma-uio","sifive,fu540-c000-pdma"; - reg = <0x0 0x3000000 0x0 0x8000>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_DMA_CH0_DONE PLIC_INT_DMA_CH0_ERR - PLIC_INT_DMA_CH1_DONE PLIC_INT_DMA_CH1_ERR - PLIC_INT_DMA_CH2_DONE PLIC_INT_DMA_CH2_ERR - PLIC_INT_DMA_CH3_DONE PLIC_INT_DMA_CH3_ERR>; - #dma-cells = <1>; + clint: clint@2000000 { + compatible = "sifive,fu540-c000-clint", "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0xC000>; + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, + <&cpu1_intc 3>, <&cpu1_intc 7>, + <&cpu2_intc 3>, <&cpu2_intc 7>, + <&cpu3_intc 3>, <&cpu3_intc 7>, + <&cpu4_intc 3>, <&cpu4_intc 7>; }; plic: interrupt-controller@c000000 { - compatible = "sifive,plic-1.0.0"; + compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; reg = <0x0 0xc000000 0x0 0x4000000>; + #address-cells = <0>; #interrupt-cells = <1>; - riscv,ndev = <186>; interrupt-controller; - interrupts-extended = <&cpu0_intc HART_INT_M_EXT - &cpu1_intc HART_INT_M_EXT &cpu1_intc HART_INT_S_EXT - &cpu2_intc HART_INT_M_EXT &cpu2_intc HART_INT_S_EXT - &cpu3_intc HART_INT_M_EXT &cpu3_intc HART_INT_S_EXT - &cpu4_intc HART_INT_M_EXT &cpu4_intc HART_INT_S_EXT>; + interrupts-extended = <&cpu0_intc 11>, + <&cpu1_intc 11>, <&cpu1_intc 9>, + <&cpu2_intc 11>, <&cpu2_intc 9>, + <&cpu3_intc 11>, <&cpu3_intc 9>, + <&cpu4_intc 11>, <&cpu4_intc 9>; + riscv,ndev = <186>; + }; + + pdma: dma-controller@3000000 { + compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = <5 6>, <7 8>, <9 10>, <11 12>; + dma-channels = <4>; + #dma-cells = <1>; }; clkcfg: clkcfg@20002000 { compatible = "microchip,mpfs-clkcfg"; reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - reg-names = "mss_sysreg"; clocks = <&refclk>; #clock-cells = <1>; - clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ - "mac0", "mac1", "mmc", "timer", /* 4-7 */ - "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ - "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ - "i2c1", "can0", "can1", "usb", /* 16-19 */ - "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ - "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ - "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ + #reset-cells = <1>; }; - /* Common node entry for eMMC/SD */ - mmc: mmc@20008000 { - compatible = "microchip,mpfs-sd4hc","cdns,sd4hc"; - reg = <0x0 0x20008000 0x0 0x1000>; - clocks = <&clkcfg CLK_MMC>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMC_MAIN PLIC_INT_MMC_WAKEUP>; - max-frequency = <200000000>; + ccc_se: clock-controller@38010000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38010000 0x0 0x1000>, <0x0 0x38020000 0x0 0x1000>, + <0x0 0x39010000 0x0 0x1000>, <0x0 0x39020000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_ne: clock-controller@38040000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38040000 0x0 0x1000>, <0x0 0x38080000 0x0 0x1000>, + <0x0 0x39040000 0x0 0x1000>, <0x0 0x39080000 0x0 0x1000>; + #clock-cells = <1>; status = "disabled"; }; - uart0: serial@20000000 { + ccc_nw: clock-controller@38100000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38100000 0x0 0x1000>, <0x0 0x38200000 0x0 0x1000>, + <0x0 0x39100000 0x0 0x1000>, <0x0 0x39200000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + ccc_sw: clock-controller@38400000 { + compatible = "microchip,mpfs-ccc"; + reg = <0x0 0x38400000 0x0 0x1000>, <0x0 0x38800000 0x0 0x1000>, + <0x0 0x39400000 0x0 0x1000>, <0x0 0x39800000 0x0 0x1000>; + #clock-cells = <1>; + status = "disabled"; + }; + + mmuart0: serial@20000000 { compatible = "ns16550a"; reg = <0x0 0x20000000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMUART0>; + interrupts = <90>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART0>; status = "disabled"; /* Reserved for the HSS */ }; - uart1: serial@20100000 { + mmuart1: serial@20100000 { compatible = "ns16550a"; reg = <0x0 0x20100000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMUART1>; + interrupts = <91>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART1>; status = "disabled"; }; - uart2: serial@20102000 { + mmuart2: serial@20102000 { compatible = "ns16550a"; reg = <0x0 0x20102000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMUART2>; + interrupts = <92>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART2>; status = "disabled"; }; - uart3: serial@20104000 { + mmuart3: serial@20104000 { compatible = "ns16550a"; reg = <0x0 0x20104000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMUART3>; + interrupts = <93>; + current-speed = <115200>; clocks = <&clkcfg CLK_MMUART3>; status = "disabled"; }; - uart4: serial@20106000 { + mmuart4: serial@20106000 { compatible = "ns16550a"; reg = <0x0 0x20106000 0x0 0x400>; reg-io-width = <4>; reg-shift = <2>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MMUART4>; + interrupts = <94>; clocks = <&clkcfg CLK_MMUART4>; + current-speed = <115200>; + status = "disabled"; + }; + + /* Common node entry for emmc/sd */ + mmc: mmc@20008000 { + compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88>; + clocks = <&clkcfg CLK_MMC>; + max-frequency = <200000000>; status = "disabled"; }; spi0: spi@20108000 { compatible = "microchip,mpfs-spi"; - reg = <0x0 0x20108000 0x0 0x1000>; - clocks = <&clkcfg CLK_SPI0>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_SPI0>; - num-cs = <8>; #address-cells = <1>; #size-cells = <0>; + reg = <0x0 0x20108000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <54>; + clocks = <&clkcfg CLK_SPI0>; status = "disabled"; }; spi1: spi@20109000 { compatible = "microchip,mpfs-spi"; + #address-cells = <1>; + #size-cells = <0>; reg = <0x0 0x20109000 0x0 0x1000>; - clocks = <&clkcfg CLK_SPI1>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_SPI1>; - num-cs = <8>; + interrupts = <55>; + clocks = <&clkcfg CLK_SPI1>; + status = "disabled"; + }; + + qspi: spi@21000000 { + compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2"; #address-cells = <1>; #size-cells = <0>; + reg = <0x0 0x21000000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <85>; + clocks = <&clkcfg CLK_QSPI>; status = "disabled"; }; i2c0: i2c@2010a000 { - compatible = "microchip,mpfs-i2c"; + compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; reg = <0x0 0x2010a000 0x0 0x1000>; - clocks = <&clkcfg CLK_I2C0>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_I2C0_MAIN>; #address-cells = <1>; #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <58>; + clocks = <&clkcfg CLK_I2C0>; + clock-frequency = <100000>; status = "disabled"; }; i2c1: i2c@2010b000 { - compatible = "microchip,mpfs-i2c"; + compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7"; reg = <0x0 0x2010b000 0x0 0x1000>; - clocks = <&clkcfg CLK_I2C1>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_I2C1_MAIN>; #address-cells = <1>; #size-cells = <0>; + interrupt-parent = <&plic>; + interrupts = <61>; + clocks = <&clkcfg CLK_I2C1>; + clock-frequency = <100000>; status = "disabled"; }; can0: can@2010c000 { - compatible = "microchip,mpfs-can-uio"; + compatible = "microchip,mpfs-can"; reg = <0x0 0x2010c000 0x0 0x1000>; clocks = <&clkcfg CLK_CAN0>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_CAN0>; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <56>; status = "disabled"; }; can1: can@2010d000 { - compatible = "microchip,mpfs-can-uio"; + compatible = "microchip,mpfs-can"; reg = <0x0 0x2010d000 0x0 0x1000>; clocks = <&clkcfg CLK_CAN1>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_CAN1>; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <57>; status = "disabled"; }; mac0: ethernet@20110000 { - compatible = "cdns,macb"; + compatible = "microchip,mpfs-macb", "cdns,macb"; reg = <0x0 0x20110000 0x0 0x2000>; - clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MAC0_INT - PLIC_INT_MAC0_QUEUE1 - PLIC_INT_MAC0_QUEUE2 - PLIC_INT_MAC0_QUEUE3 - PLIC_INT_MAC0_EMAC - PLIC_INT_MAC0_MMSL>; + interrupts = <64>, <65>, <66>, <67>, <68>, <69>; local-mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + resets = <&clkcfg CLK_MAC0>; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; mac1: ethernet@20112000 { - compatible = "cdns,macb"; + compatible = "microchip,mpfs-macb", "cdns,macb"; reg = <0x0 0x20112000 0x0 0x2000>; - clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; - clock-names = "pclk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_MAC1_INT - PLIC_INT_MAC1_QUEUE1 - PLIC_INT_MAC1_QUEUE2 - PLIC_INT_MAC1_QUEUE3 - PLIC_INT_MAC1_EMAC - PLIC_INT_MAC1_MMSL>; + interrupts = <70>, <71>, <72>, <73>, <74>, <75>; local-mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>; + clock-names = "pclk", "hclk"; + resets = <&clkcfg CLK_MAC1>; status = "disabled"; - #address-cells = <1>; - #size-cells = <0>; }; gpio0: gpio@20120000 { compatible = "microchip,mpfs-gpio"; reg = <0x0 0x20120000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO0>; interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO0>; gpio-controller; #gpio-cells = <2>; status = "disabled"; @@ -429,10 +456,11 @@ gpio1: gpio@20121000 { compatible = "microchip,mpfs-gpio"; - reg = <000 0x20121000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO1>; + reg = <0x0 0x20121000 0x0 0x1000>; interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO1>; gpio-controller; #gpio-cells = <2>; status = "disabled"; @@ -441,9 +469,10 @@ gpio2: gpio@20122000 { compatible = "microchip,mpfs-gpio"; reg = <0x0 0x20122000 0x0 0x1000>; - reg-names = "control"; - clocks = <&clkcfg CLK_GPIO2>; interrupt-parent = <&plic>; + interrupt-controller; + #interrupt-cells = <1>; + clocks = <&clkcfg CLK_GPIO2>; gpio-controller; #gpio-cells = <2>; status = "disabled"; @@ -452,118 +481,31 @@ rtc: rtc@20124000 { compatible = "microchip,mpfs-rtc"; reg = <0x0 0x20124000 0x0 0x1000>; - clocks = <&clkcfg CLK_RTC>; - clock-names = "rtc"; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_RTC_WAKEUP PLIC_INT_RTC_MATCH>; - #address-cells = <1>; - #size-cells = <0>; + interrupts = <80>, <81>; + clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; + clock-names = "rtc", "rtcref"; status = "disabled"; }; usb: usb@20201000 { - compatible = "microchip,mpfs-usb-host"; + compatible = "microchip,mpfs-musb"; reg = <0x0 0x20201000 0x0 0x1000>; - reg-names = "mc","control"; - clocks = <&clkcfg CLK_USB>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_USB_DMA PLIC_INT_USB_MC>; + interrupts = <86>, <87>; + clocks = <&clkcfg CLK_USB>; interrupt-names = "dma","mc"; - dr_mode = "host"; - status = "disabled"; - }; - - qspi: qspi@21000000 { - compatible = "microchip,mpfs-qspi"; - reg = <0x0 0x21000000 0x0 0x1000>; - clocks = <&clkcfg CLK_QSPI>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_QSPI>; - num-cs = <8>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; mbox: mailbox@37020000 { compatible = "microchip,mpfs-mailbox"; - reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; + reg = <0x0 0x37020000 0x0 0x58>, <0x0 0x2000318C 0x0 0x40>, + <0x0 0x37020800 0x0 0x100>; interrupt-parent = <&plic>; - interrupts = <PLIC_INT_G5C_MESSAGE>; + interrupts = <96>; #mbox-cells = <1>; status = "disabled"; }; - - pcie: pcie@2000000000 { - compatible = "microchip,pcie-host-1.0"; - #address-cells = <0x3>; - #interrupt-cells = <0x1>; - #size-cells = <0x2>; - device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; - clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>; - clock-names = "fic0", "fic1", "fic3"; - bus-range = <0x0 0x7f>; - interrupt-parent = <&plic>; - interrupts = <PLIC_INT_FABRIC_F2H_2>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - interrupt-map-mask = <0 0 0 7>; - ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; - msi-parent = <&pcie>; - msi-controller; - mchp,axi-m-atr0 = <0x10 0x0>; - status = "disabled"; - pcie_intc: legacy-interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - - syscontroller: syscontroller { - compatible = "microchip,mpfs-sys-controller"; - #address-cells = <1>; - #size-cells = <1>; - mboxes = <&mbox 0>; - }; - - hwrandom: hwrandom { - compatible = "microchip,mpfs-rng"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - serialnum: serialnum { - compatible = "microchip,mpfs-serial-number"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - fpgadigest: fpgadigest { - compatible = "microchip,mpfs-digest"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - devicecert: cert { - compatible = "microchip,mpfs-device-cert"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; - - signature: signature { - compatible = "microchip,mpfs-signature"; - #address-cells = <1>; - #size-cells = <1>; - syscontroller = <&syscontroller>; - }; }; }; diff --git a/arch/riscv/include/asm/arch-fu740/eeprom.h b/arch/riscv/include/asm/arch-fu740/eeprom.h deleted file mode 100644 index 0e1220e..0000000 --- a/arch/riscv/include/asm/arch-fu740/eeprom.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2021 SiFive, Inc. - * - * Zong Li <zong.li@sifve.com> - */ - -#ifndef _ASM_RISCV_EEPROM_H -#define _ASM_RISCV_EEPROM_H - -#define PCB_REVISION_REV3 0x3 - -u8 get_pcb_revision_from_eeprom(void); - -#endif /* _ASM_RISCV_EEPROM_H */ diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h new file mode 100644 index 0000000..f541fb4 --- /dev/null +++ b/arch/riscv/include/asm/atomic.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2023 SiFive, Inc. + */ + +#ifndef __RISCV_ATOMIC_H +#define __RISCV_ATOMIC_H + +/* use the generic asm/atomic.h until we define a better one */ + +#include <asm/system.h> +#include <asm-generic/atomic.h> + +#endif diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitops.h index 536629b..35f1368 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -158,6 +158,9 @@ static inline unsigned long ffz(unsigned long word) #define hweight16(x) generic_hweight16(x) #define hweight8(x) generic_hweight8(x) +#define test_and_set_bit __test_and_set_bit +#define test_and_clear_bit __test_and_clear_bit + #define ext2_set_bit test_and_set_bit #define ext2_clear_bit test_and_clear_bit #define ext2_test_bit test_bit diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 81fcfe0..7693699 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -28,6 +28,9 @@ enum sbi_ext_id { SBI_EXT_HSM = 0x48534D, SBI_EXT_SRST = 0x53525354, SBI_EXT_PMU = 0x504D55, + SBI_EXT_DBCN = 0x4442434E, + SBI_EXT_SUSP = 0x53555350, + SBI_EXT_CPPC = 0x43505043, }; enum sbi_ext_base_fid { @@ -89,6 +92,12 @@ enum sbi_srst_reset_reason { SBI_SRST_RESET_REASON_SYS_FAILURE, }; +enum sbi_ext_dbcn_fid { + SBI_EXT_DBCN_CONSOLE_WRITE = 0, + SBI_EXT_DBCN_CONSOLE_READ, + SBI_EXT_DBCN_CONSOLE_WRITE_BYTE, +}; + #ifdef CONFIG_SBI_V01 #define SBI_EXT_SET_TIMER SBI_EXT_0_1_SET_TIMER #define SBI_FID_SET_TIMER 0 diff --git a/arch/riscv/include/asm/spl.h b/arch/riscv/include/asm/spl.h index 2898a77..9c0bf975 100644 --- a/arch/riscv/include/asm/spl.h +++ b/arch/riscv/include/asm/spl.h @@ -20,6 +20,7 @@ enum { BOOT_DEVICE_SPI, BOOT_DEVICE_USB, BOOT_DEVICE_SATA, + BOOT_DEVICE_NVME, BOOT_DEVICE_I2C, BOOT_DEVICE_BOARD, BOOT_DEVICE_DFU, diff --git a/arch/riscv/include/asm/system.h b/arch/riscv/include/asm/system.h index 9d8e43e..ffa7649 100644 --- a/arch/riscv/include/asm/system.h +++ b/arch/riscv/include/asm/system.h @@ -7,15 +7,24 @@ #ifndef __ASM_RISCV_SYSTEM_H #define __ASM_RISCV_SYSTEM_H +#include <asm/csr.h> + struct event; /* - * Interrupt configuring macros. - * - * TODO - * + * Interupt configuration macros */ +#define local_irq_save(__flags) \ + do { \ + __flags = csr_read_clear(CSR_SSTATUS, SR_SIE) & SR_SIE; \ + } while (0) + +#define local_irq_restore(__flags) \ + do { \ + csr_set(CSR_SSTATUS, __flags & SR_SIE); \ + } while (0) + /* Hook to set up the CPU (called from SPL too) */ int riscv_cpu_setup(void *ctx, struct event *event); diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c index 324eb44..7518408 100644 --- a/arch/riscv/lib/andes_plicsw.c +++ b/arch/riscv/lib/andes_plicsw.c @@ -2,9 +2,10 @@ /* * Copyright (C) 2019, Rick Chen <rick@andestech.com> * - * U-Boot syscon driver for Andes's Platform Level Interrupt Controller (PLIC). - * The PLIC block holds memory-mapped claim and pending registers - * associated with software interrupt. + * U-Boot syscon driver for Andes' PLICSW + * The PLICSW block is an Andes-specific design for software interrupts, + * contains memory-mapped priority, enable, claim and pending registers + * similar to RISC-V PLIC. */ #include <common.h> @@ -26,9 +27,13 @@ #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80) /* claim register */ #define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000) +/* priority register */ +#define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE) #define ENABLE_HART_IPI (0x01010101) #define SEND_IPI_TO_HART(hart) (0x1 << (hart)) +#define PLICSW_PRIORITY_BASE 0x4 +#define PLICSW_INTERRUPT_PER_HART 0x8 DECLARE_GLOBAL_DATA_PTR; @@ -43,9 +48,21 @@ static int enable_ipi(int hart) return 0; } +static void init_priority_ipi(int hart_num) +{ + uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw); + + for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) { + writel(1, &priority[i]); + } + + return; +} + int riscv_init_ipi(void) { int ret; + int hart_num = 0; long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW); ofnode node; struct udevice *dev; @@ -79,8 +96,10 @@ int riscv_init_ipi(void) ret = ofnode_read_u32(node, "reg", ®); if (ret == 0) enable_ipi(reg); + hart_num++; } + init_priority_ipi(hart_num); return 0; } diff --git a/arch/sandbox/cpu/cpu.c b/arch/sandbox/cpu/cpu.c index 5149633..a1c5c7c 100644 --- a/arch/sandbox/cpu/cpu.c +++ b/arch/sandbox/cpu/cpu.c @@ -286,6 +286,11 @@ void sandbox_set_enable_pci_map(int enable) enable_pci_map = enable; } +int dcache_status(void) +{ + return 1; +} + void flush_dcache_range(unsigned long start, unsigned long stop) { } diff --git a/arch/sandbox/dts/Makefile b/arch/sandbox/dts/Makefile index b6a8847..f810b47 100644 --- a/arch/sandbox/dts/Makefile +++ b/arch/sandbox/dts/Makefile @@ -18,4 +18,4 @@ PHONY += dtbs dtbs: $(addprefix $(obj)/, $(dtb-y)) @: -clean-files := *.dtb +clean-files := *.dtb *.dtbo diff --git a/arch/sandbox/include/asm/axi.h b/arch/sandbox/include/asm/axi.h index d483f7b..5b94bed 100644 --- a/arch/sandbox/include/asm/axi.h +++ b/arch/sandbox/include/asm/axi.h @@ -14,8 +14,8 @@ * @bus: The AXI bus from which to retrieve a emulation device * @address: The address of a transfer that should be handled by a emulation * device - * @length: The data width of a transfer that should be handled by a emulation - * device + * @size: A constant indicating the data width of the transfer that + * should be handled by an emulation device * @emulp: Pointer to a buffer receiving the emulation device that handles * the transfer specified by the address and length parameters * @@ -45,8 +45,8 @@ * Return: 0 of OK, -ENODEV if no device capable of handling the specified * transfer exists or the device could not be retrieved */ -int axi_sandbox_get_emul(struct udevice *bus, ulong address, uint length, - struct udevice **emulp); +int axi_sandbox_get_emul(struct udevice *bus, ulong address, + const enum axi_size_t size, struct udevice **emulp); /** * axi_get_store() - Get address of internal storage of a emulated AXI device * @dev: Emulated AXI device to get the pointer of the internal storage diff --git a/arch/sh/include/asm/mmc.h b/arch/sh/include/asm/mmc.h deleted file mode 100644 index 5732b2b..0000000 --- a/arch/sh/include/asm/mmc.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Renesas SuperH MMCIF driver. - * - * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * Copyright (C) 2012 Renesas Solutions Corp. - * - */ -#ifndef _SH_MMC_H_ -#define _SH_MMC_H_ - -int mmcif_mmc_init(void); - -#endif /* _SH_MMC_H_ */ diff --git a/arch/sh/include/asm/unaligned.h b/arch/sh/include/asm/unaligned.h index 5acf081..7fb482a 100644 --- a/arch/sh/include/asm/unaligned.h +++ b/arch/sh/include/asm/unaligned.h @@ -1,20 +1,2 @@ -#ifndef _ASM_SH_UNALIGNED_H -#define _ASM_SH_UNALIGNED_H - -/* Copy from linux-kernel. */ - -/* Other than SH4A, SH can't handle unaligned accesses. */ -#include <linux/compiler.h> -#if defined(__BIG_ENDIAN__) -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#elif defined(__LITTLE_ENDIAN__) -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#endif - -#include <linux/unaligned/le_byteshift.h> -#include <linux/unaligned/be_byteshift.h> -#include <linux/unaligned/generic.h> - -#endif /* _ASM_SH_UNALIGNED_H */ +/* SPDX-License-Identifier: GPL-2.0 */ +#include <asm-generic/unaligned.h> diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index e54082d..274978c0 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -97,7 +97,7 @@ static void qemu_chipset_init(void) } } -#if !CONFIG_IS_ENABLED(SPL_X86_32BIT_INIT) +#if CONFIG_IS_ENABLED(X86_32BIT_INIT) int arch_cpu_init(void) { post_code(POST_CPU_INIT); diff --git a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c index 4661746..b79a238 100644 --- a/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c +++ b/board/advantech/imx8mp_rsb3720a1/imx8mp_rsb3720a1.c @@ -54,10 +54,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "mmc 2=flash-bin raw 0 0x1B00 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ diff --git a/board/amlogic/ad401/MAINTAINERS b/board/amlogic/ad401/MAINTAINERS new file mode 100644 index 0000000..52a44bd --- /dev/null +++ b/board/amlogic/ad401/MAINTAINERS @@ -0,0 +1,6 @@ +AD401 +M: Neil Armstrong <neil.armstrong@linaro.org> +S: Maintained +L: u-boot-amlogic@groups.io +F: board/amlogic/ad401/ +F: configs/ad401_defconfig diff --git a/board/amlogic/ad401/Makefile b/board/amlogic/ad401/Makefile new file mode 100644 index 0000000..e65c121 --- /dev/null +++ b/board/amlogic/ad401/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0+ +# (C) Copyright 2023 SberDevices, Inc. + +obj-y := ad401.o diff --git a/board/amlogic/ad401/ad401.c b/board/amlogic/ad401/ad401.c new file mode 100644 index 0000000..356b288 --- /dev/null +++ b/board/amlogic/ad401/ad401.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2023 SberDevices, Inc. + * Author: Igor Prusov <ivprusov@sberdevices.ru> + */ + +#include <init.h> +#include <asm/arch/eth.h> + +int misc_init_r(void) +{ + meson_generate_serial_ethaddr(); + + return 0; +} diff --git a/board/amlogic/p200/MAINTAINERS b/board/amlogic/p200/MAINTAINERS index fe451dd..5cf0ce0 100644 --- a/board/amlogic/p200/MAINTAINERS +++ b/board/amlogic/p200/MAINTAINERS @@ -9,8 +9,10 @@ F: configs/odroid-c2_defconfig F: configs/p200_defconfig F: configs/wetek-hub_defconfig F: configs/wetek-play2_defconfig +F: configs/videostrong-kii-pro_defconfig F: doc/board/amlogic/p200.rst F: doc/board/amlogic/nanopi-k2.rst F: doc/board/amlogic/odroid-c2.rst +F: doc/board/amlogic/videostrong-kii-pro.rst F: doc/board/amlogic/wetek-hub.rst F: doc/board/amlogic/wetek-play2.rst diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 770f3d7..4dcf3f3 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -30,7 +30,6 @@ #include <bmp_logo.h> #include <dm/root.h> #include <env.h> -#include <env_internal.h> #include <i2c_eeprom.h> #include <i2c.h> #include <micrel.h> @@ -529,22 +528,3 @@ int embedded_dtb_select(void) return 0; } #endif - -enum env_location env_get_location(enum env_operation op, int prio) -{ - if (op == ENVOP_SAVE || op == ENVOP_ERASE) - return ENVL_SPI_FLASH; - - switch (prio) { - case 0: - return ENVL_NOWHERE; - - case 1: - return ENVL_SPI_FLASH; - - default: - return ENVL_UNKNOWN; - } - - return ENVL_UNKNOWN; -} diff --git a/board/armadeus/opos6uldev/opos6uldev.env b/board/armadeus/opos6uldev/opos6uldev.env index 585f28c..f900297 100644 --- a/board/armadeus/opos6uldev/opos6uldev.env +++ b/board/armadeus/opos6uldev/opos6uldev.env @@ -42,8 +42,8 @@ flash_uboot_spl= setexpr sz ${filesize} / 0x200; setexpr sz ${sz} + 1; if mmc write ${loadaddr} 0x2 ${sz}; then - echo Flashing of U-boot SPL succeed; - else echo Flashing of U-boot SPL failed; + echo Flashing of U-Boot SPL succeed; + else echo Flashing of U-Boot SPL failed; fi; fi; download_uboot_img=tftpboot ${loadaddr} ${board_name}-u-boot.img @@ -52,8 +52,8 @@ flash_uboot_img= setexpr sz ${filesize} / 0x200; setexpr sz ${sz} + 1; if mmc write ${loadaddr} 0x8a ${sz}; then - echo Flashing of U-boot image succeed; - else echo Flashing of U-boot image failed; + echo Flashing of U-Boot image succeed; + else echo Flashing of U-Boot image failed; fi; fi; update_uboot=run download_uboot_spl flash_uboot_spl diff --git a/board/armltd/corstone1000/corstone1000.c b/board/armltd/corstone1000/corstone1000.c index 6ec8e61..01c80aa 100644 --- a/board/armltd/corstone1000/corstone1000.c +++ b/board/armltd/corstone1000/corstone1000.c @@ -5,14 +5,25 @@ * Rui Miguel Silva <rui.silva@linaro.org> */ +#include <blk.h> #include <common.h> #include <cpu_func.h> #include <dm.h> +#include <env.h> +#include <fwu.h> #include <netdev.h> +#include <nvmxip.h> +#include <part.h> #include <dm/platform_data/serial_pl01x.h> #include <asm/armv8/mmu.h> #include <asm/global_data.h> +#define CORSTONE1000_KERNEL_PARTS 2 +#define CORSTONE1000_KERNEL_PRIMARY "kernel_primary" +#define CORSTONE1000_KERNEL_SECONDARY "kernel_secondary" + +static int corstone1000_boot_idx; + static struct mm_region corstone1000_mem_map[] = { { /* CVM */ @@ -87,6 +98,66 @@ int dram_init_banksize(void) return 0; } -void reset_cpu(void) +void fwu_plat_get_bootidx(uint *boot_idx) { + int ret; + + /* + * in our platform, the Secure Enclave is the one who controls + * all the boot tries and status, so, every time we get here + * we know that the we are booting from the active index + */ + ret = fwu_get_active_index(boot_idx); + if (ret < 0) { + *boot_idx = CONFIG_FWU_NUM_BANKS; + log_err("corstone1000: failed to read active index\n"); + } +} + +int board_late_init(void) +{ + struct disk_partition part_info; + struct udevice *dev, *bdev; + struct nvmxip_plat *plat; + struct blk_desc *desc; + int ret; + + ret = uclass_first_device_err(UCLASS_NVMXIP, &dev); + if (ret < 0) { + log_err("Cannot find kernel device\n"); + return ret; + } + + plat = dev_get_plat(dev); + device_find_first_child(dev, &bdev); + desc = dev_get_uclass_plat(bdev); + ret = fwu_get_active_index(&corstone1000_boot_idx); + if (ret < 0) { + log_err("corstone1000: failed to read boot index\n"); + return ret; + } + + if (!corstone1000_boot_idx) + ret = part_get_info_by_name(desc, CORSTONE1000_KERNEL_PRIMARY, + &part_info); + else + ret = part_get_info_by_name(desc, CORSTONE1000_KERNEL_SECONDARY, + &part_info); + + if (ret < 0) { + log_err("failed to fetch kernel partition index: %d\n", + corstone1000_boot_idx); + return ret; + } + + ret = 0; + + ret |= env_set_hex("kernel_addr", plat->phys_base + + (part_info.start * part_info.blksz)); + ret |= env_set_hex("kernel_size", part_info.size * part_info.blksz); + + if (ret < 0) + log_err("failed to setup kernel addr and size\n"); + + return ret; } diff --git a/board/armltd/corstone1000/corstone1000.env b/board/armltd/corstone1000/corstone1000.env index b24ff07..ee318b1 100644 --- a/board/armltd/corstone1000/corstone1000.env +++ b/board/armltd/corstone1000/corstone1000.env @@ -1,13 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0+ */ usb_pgood_delay=250 -boot_bank_flag=0x08002000 -kernel_addr_bank_0=0x083EE000 -kernel_addr_bank_1=0x0936E000 -retrieve_kernel_load_addr= - if itest.l *${boot_bank_flag} == 0; then - setenv kernel_addr $kernel_addr_bank_0; - else - setenv kernel_addr $kernel_addr_bank_1; - fi; +boot_bank_flag=0x08005006 kernel_addr_r=0x88200000 diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c index 4a0603d..7c49b20 100644 --- a/board/bosch/acc/acc.c +++ b/board/bosch/acc/acc.c @@ -12,7 +12,6 @@ #include <dm/platform_data/serial_mxc.h> #include <dm/device-internal.h> #include <env.h> -#include <env_internal.h> #include <hang.h> #include <init.h> #include <linux/delay.h> @@ -236,22 +235,6 @@ static void unset_early_gpio(void) gpio_set_value(GPIO_TOUCH_RESET, 1); } -enum env_location env_get_location(enum env_operation op, int prio) -{ - if (op == ENVOP_SAVE || op == ENVOP_ERASE) - return ENVL_MMC; - - switch (prio) { - case 0: - return ENVL_NOWHERE; - - case 1: - return ENVL_MMC; - } - - return ENVL_UNKNOWN; -} - int board_late_init(void) { struct board_info *binfo = detect_board(); @@ -559,7 +542,7 @@ int board_mmc_init(struct bd_info *bis) gpio_direction_input(USDHC2_CD_GPIO); /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC2 * mmc1 USDHC4 */ diff --git a/board/bosch/shc/README b/board/bosch/shc/README index 2f206e0..74704cd 100644 --- a/board/bosch/shc/README +++ b/board/bosch/shc/README @@ -68,7 +68,7 @@ Netboot - see also doc/SPL/README.am335x-network - set the jumper into netboot mode -- compile the U-boot sources with: +- compile the U-Boot sources with: make am335x_shc_netboot_defconfig make all - copy the images into your tftp boot directory diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c index 1b08a2c..af19a65 100644 --- a/board/compulab/cl-som-imx7/cl-som-imx7.c +++ b/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -86,7 +86,7 @@ int board_mmc_init(struct bd_info *bis) int i, ret; /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC1 * mmc2 USDHC3 (eMMC) */ diff --git a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c index b373e45..af070ec 100644 --- a/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c +++ b/board/compulab/imx8mm-cl-iot-gate/imx8mm-cl-iot-gate.c @@ -50,10 +50,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "mmc 2=flash-bin raw 0x42 0x1D00 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ int board_phys_sdram_size(phys_size_t *size) diff --git a/board/dhelectronics/dh_stm32mp1/board.c b/board/dhelectronics/dh_stm32mp1/board.c index 8d8104a..f9cfabe 100644 --- a/board/dhelectronics/dh_stm32mp1/board.c +++ b/board/dhelectronics/dh_stm32mp1/board.c @@ -184,9 +184,9 @@ int checkboard(void) } #ifdef CONFIG_BOARD_EARLY_INIT_F -static u8 brdcode __section("data"); -static u8 ddr3code __section("data"); -static u8 somcode __section("data"); +static u8 brdcode __section(".data"); +static u8 ddr3code __section(".data"); +static u8 somcode __section(".data"); static u32 opp_voltage_mv __section(".data"); static void board_get_coding_straps(void) diff --git a/board/emulation/qemu-arm/qemu-arm.c b/board/emulation/qemu-arm/qemu-arm.c index 34ed3e8..dfea0d9 100644 --- a/board/emulation/qemu-arm/qemu-arm.c +++ b/board/emulation/qemu-arm/qemu-arm.c @@ -47,10 +47,10 @@ struct efi_fw_image fw_images[] = { }; struct efi_capsule_update_info update_info = { + .num_images = ARRAY_SIZE(fw_images) .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ static struct mm_region qemu_arm64_mem_map[] = { diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index b47ce05..87ed814 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -127,7 +127,7 @@ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr) &img_addr); if (res == 0) - printf("SPL: Validation of U-boot successful\n"); + printf("SPL: Validation of U-Boot successful\n"); } #ifdef CONFIG_SPL_FRAMEWORK diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c index 6dca229..a928882 100644 --- a/board/freescale/common/pfuze.c +++ b/board/freescale/common/pfuze.c @@ -91,7 +91,7 @@ struct pmic *pfuze_common_init(unsigned char i2cbus) return p; } -#else +#elif defined(CONFIG_DM_PMIC) int pfuze_mode_init(struct udevice *dev, u32 mode) { unsigned char offset, i, switch_num; diff --git a/board/freescale/common/vsc3316_3308.h b/board/freescale/common/vsc3316_3308.h index 49a684f..8d343ba 100644 --- a/board/freescale/common/vsc3316_3308.h +++ b/board/freescale/common/vsc3316_3308.h @@ -4,7 +4,7 @@ */ #ifndef __VSC_CROSSBAR_H_ -#define __VSC_CROSSBAR_H 1_ +#define __VSC_CROSSBAR_H_ #include <common.h> #include <i2c.h> diff --git a/board/freescale/ls1012afrdm/README b/board/freescale/ls1012afrdm/README index 382b668..e60ed60 100644 --- a/board/freescale/ls1012afrdm/README +++ b/board/freescale/ls1012afrdm/README @@ -52,7 +52,7 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012aqds/README b/board/freescale/ls1012aqds/README index c1956f9..e9b80ca 100644 --- a/board/freescale/ls1012aqds/README +++ b/board/freescale/ls1012aqds/README @@ -53,7 +53,7 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 diff --git a/board/freescale/ls1012ardb/README b/board/freescale/ls1012ardb/README index 5b6f306..26b0485 100644 --- a/board/freescale/ls1012ardb/README +++ b/board/freescale/ls1012ardb/README @@ -48,8 +48,8 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4020_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4020_0000 PPA FIT image | 2MB | 0x4050_0000 Linux ITB | ~53MB | 0x40A0_0000 @@ -90,8 +90,8 @@ QSPI flash map Images | Size |QSPI Flash Address ------------------------------------------ RCW + PBI | 1MB | 0x4000_0000 -U-boot | 1MB | 0x4010_0000 -U-boot Env | 1MB | 0x4030_0000 +U-Boot | 1MB | 0x4010_0000 +U-Boot Env | 1MB | 0x4030_0000 PPA FIT image | 2MB | 0x4040_0000 PFE firmware | 20K | 0x00a0_0000 Linux ITB | ~53MB | 0x4100_0000 diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c index f6e5c12..899c22a 100644 --- a/board/freescale/ls1046afrwy/ls1046afrwy.c +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -134,6 +134,9 @@ val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK); out_le32(SMMU_NSCR0, val); #endif + if (!IS_ENABLED(CONFIG_SYS_EARLY_PCI_INIT)) + pci_init(); + select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); return 0; } diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c index 533f606..c5dfefe 100644 --- a/board/freescale/lx2160a/eth_lx2160ardb.c +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -8,6 +8,7 @@ #include <netdev.h> #include <exports.h> #include <fsl-mc/fsl_mc.h> +#include "lx2160a.h" DECLARE_GLOBAL_DATA_PTR; @@ -36,3 +37,109 @@ void reset_phy(void) #endif } #endif /* CONFIG_RESET_PHY_R */ + +static int fdt_get_dpmac_node(void *fdt, int dpmac_id) +{ + char dpmac_str[11] = "dpmacs@00"; + int offset, dpmacs_offset; + + /* get the dpmac offset */ + dpmacs_offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs"); + if (dpmacs_offset < 0) + dpmacs_offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs"); + + if (dpmacs_offset < 0) { + printf("dpmacs node not found in device tree\n"); + return dpmacs_offset; + } + + sprintf(dpmac_str, "dpmac@%x", dpmac_id); + offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str); + if (offset < 0) { + sprintf(dpmac_str, "ethernet@%x", dpmac_id); + offset = fdt_subnode_offset(fdt, dpmacs_offset, dpmac_str); + if (offset < 0) { + printf("dpmac@%x/ethernet@%x node not found in device tree\n", + dpmac_id, dpmac_id); + return offset; + } + } + + return offset; +} + +static int fdt_update_phy_addr(void *fdt, int dpmac_id, int phy_addr) +{ + char dpmac_str[] = "dpmacs@00"; + const u32 *phyhandle; + int offset; + int err; + + /* get the dpmac offset */ + offset = fdt_get_dpmac_node(fdt, dpmac_id); + if (offset < 0) + return offset; + + /* get dpmac phy-handle */ + sprintf(dpmac_str, "dpmac@%x", dpmac_id); + phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL); + if (!phyhandle) { + printf("%s node not found in device tree\n", dpmac_str); + return offset; + } + + offset = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyhandle)); + if (offset < 0) { + printf("Could not get the ph node offset for dpmac %d\n", + dpmac_id); + return offset; + } + + phy_addr = cpu_to_fdt32(phy_addr); + err = fdt_setprop(fdt, offset, "reg", &phy_addr, sizeof(phy_addr)); + if (err < 0) { + printf("Could not set phy node's reg for dpmac %d: %s.\n", + dpmac_id, fdt_strerror(err)); + return err; + } + + return 0; +} + +static int fdt_delete_phy_handle(void *fdt, int dpmac_id) +{ + const u32 *phyhandle; + int offset; + + /* get the dpmac offset */ + offset = fdt_get_dpmac_node(fdt, dpmac_id); + if (offset < 0) + return offset; + + /* verify if the node has a phy-handle */ + phyhandle = (u32 *)fdt_getprop(fdt, offset, "phy-handle", NULL); + if (!phyhandle) + return 0; + + return fdt_delprop(fdt, offset, "phy-handle"); +} + +int fdt_fixup_board_phy_revc(void *fdt) +{ + int ret; + + if (get_board_rev() < 'C') + return 0; + + /* DPMACs 3,4 have their Aquantia PHYs at new addresses */ + ret = fdt_update_phy_addr(fdt, 3, AQR113C_PHY_ADDR1); + if (ret) + return ret; + + ret = fdt_update_phy_addr(fdt, 4, AQR113C_PHY_ADDR2); + if (ret) + return ret; + + /* There is no PHY for the DPMAC2, so remove the phy-handle */ + return fdt_delete_phy_handle(fdt, 2); +} diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 2a75205..d631a11 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -133,6 +133,11 @@ int board_fix_fdt(void *fdt) fdt_setprop(fdt, off, "reg-names", reg_names, names_len); } + /* Fixup u-boot's DTS in case this is a revC board and + * we're using DM_ETH. + */ + if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB) && IS_ENABLED(CONFIG_DM_ETH)) + fdt_fixup_board_phy_revc(fdt); return 0; } #endif @@ -487,6 +492,15 @@ int config_board_mux(void) } #endif +#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) +u8 get_board_rev(void) +{ + u8 board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A'; + + return board_rev; +} +#endif + unsigned long get_board_sys_clk(void) { #if defined(CONFIG_TARGET_LX2160AQDS) || defined(CONFIG_TARGET_LX2162AQDS) @@ -627,6 +641,8 @@ void fdt_fixup_board_enet(void *fdt) if (get_mc_boot_status() == 0 && (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) { fdt_status_okay(fdt, offset); + if (IS_ENABLED(CONFIG_TARGET_LX2160ARDB)) + fdt_fixup_board_phy_revc(fdt); } else { fdt_status_fail(fdt, offset); } @@ -760,9 +776,6 @@ int ft_board_setup(void *blob, struct bd_info *bd) u64 mc_memory_size = 0; u16 total_memory_banks; int err; -#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) - u8 board_rev; -#endif err = fdt_increase_size(blob, 512); if (err) { @@ -825,8 +838,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) fdt_fixup_icid(blob); #if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) - board_rev = (QIXIS_READ(arch) & 0xf) - 1 + 'A'; - if (board_rev == 'C') + if (get_board_rev() == 'C') fdt_fixup_i2c_thermal_node(blob); #endif diff --git a/board/freescale/lx2160a/lx2160a.h b/board/freescale/lx2160a/lx2160a.h index 52b0207..61a8bb9 100644 --- a/board/freescale/lx2160a/lx2160a.h +++ b/board/freescale/lx2160a/lx2160a.h @@ -58,4 +58,19 @@ #endif #endif +#if IS_ENABLED(CONFIG_TARGET_LX2160ARDB) +u8 get_board_rev(void); +int fdt_fixup_board_phy_revc(void *fdt); +#else +static inline u8 get_board_rev(void) +{ + return 0; +} + +static inline int fdt_fixup_board_phy_revc(void *fdt) +{ + return 0; +} +#endif + #endif /* __LX2160_H */ diff --git a/board/hisilicon/poplar/README b/board/hisilicon/poplar/README index 99ed6ce..77dcc3b 100644 --- a/board/hisilicon/poplar/README +++ b/board/hisilicon/poplar/README @@ -30,7 +30,7 @@ CONNECTORS One connector for Smart Card One connector for TSI Note of warning: ================ -U-boot has a *strong* dependency with the l-loader and the arm trusted firmware +U-Boot has a *strong* dependency with the l-loader and the arm trusted firmware repositories. The boot sequence is: diff --git a/board/imgtec/boston/checkboard.c b/board/imgtec/boston/checkboard.c index 1b8a47d..c246a7b 100644 --- a/board/imgtec/boston/checkboard.c +++ b/board/imgtec/boston/checkboard.c @@ -16,7 +16,7 @@ int checkboard(void) { u32 changelist; - lowlevel_display("U-boot "); + lowlevel_display("U-Boot "); printf("Board: MIPS Boston\n"); diff --git a/board/isee/igep003x/board.c b/board/isee/igep003x/board.c index 5462a3d..7dbb080 100644 --- a/board/isee/igep003x/board.c +++ b/board/isee/igep003x/board.c @@ -37,7 +37,7 @@ DECLARE_GLOBAL_DATA_PTR; /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards * and control IGEP0034 green and red LEDs. - * U-boot configures these pins as input pullup to detect board revision: + * U-Boot configures these pins as input pullup to detect board revision: * IGEP0034-LITE = 0b00 * IGEP0034 (FULL) = 0b01 * IGEP0033 = 0b1X diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index f159930..0f0a9c5 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -47,7 +47,7 @@ U_BOOT_DRVINFO(igep_uart) = { * IGEP00x0 boards. First of all, it is necessary to reset USB transceiver from * IGEP0030 in order to read GPIO_IGEP00X0_BOARD_DETECTION correctly, because * this functionality is shared by USB HOST. - * Once USB reset is applied, U-boot configures these pins as input pullup to + * Once USB reset is applied, U-Boot configures these pins as input pullup to * detect board and revision: * IGEP0020-RF = 0b00 * IGEP0020-RC = 0b01 diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index bf899d0..c6576aa 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -123,7 +123,7 @@ config SYS_IVM_EEPROM_PAGE_LEN Page size of inventory in EEPROM. config PG_WCOM_UBOOT_UPDATE_SUPPORTED - bool "Enable U-boot Field Fail-Safe Update Functionality" + bool "Enable U-Boot Field Fail-Safe Update Functionality" select EVENT default n help @@ -132,7 +132,7 @@ config PG_WCOM_UBOOT_UPDATE_SUPPORTED from parallel NOR flash. config PG_WCOM_UBOOT_BOOTPACKAGE - bool "U-boot Is Part Of Factory Boot-Package Image" + bool "U-Boot Is Part Of Factory Boot-Package Image" default n help Indicates that u-boot will be a part of the factory programmed @@ -140,7 +140,7 @@ config PG_WCOM_UBOOT_BOOTPACKAGE Has to be set for original u-boot programmed at factory. config PG_WCOM_UBOOT_UPDATE_TEXT_BASE - hex "Text Base For U-boot Programmed Outside Factory" + hex "Text Base For U-Boot Programmed Outside Factory" default 0xFFFFFFFF help Text base of an updated u-boot that is not factory programmed but @@ -148,7 +148,7 @@ config PG_WCOM_UBOOT_UPDATE_TEXT_BASE Has to be set for original u-boot programmed at factory. config PG_WCOM_UBOOT_UPDATE - bool "U-boot Is Part Of Factory Boot-Package Image" + bool "U-Boot Is Part Of Factory Boot-Package Image" default n help Indicates that u-boot will be a part of the embedded software and diff --git a/board/keymile/README b/board/keymile/README index 4e5cfb1..99f27e5 100644 --- a/board/keymile/README +++ b/board/keymile/README @@ -1,4 +1,4 @@ -Field Fail-Save U-boot Update +Field Fail-Save U-Boot Update ----------------------------- Field Fail-Save u-boot update is a feature that allows save u-boot update of FOX and XMC products that are rolled out in the field. diff --git a/board/kontron/pitx_imx8m/pitx_imx8m.c b/board/kontron/pitx_imx8m/pitx_imx8m.c index fcda86b..4548e7c 100644 --- a/board/kontron/pitx_imx8m/pitx_imx8m.c +++ b/board/kontron/pitx_imx8m/pitx_imx8m.c @@ -43,10 +43,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "mmc 0=flash-bin raw 0x42 0x1000 mmcpart 1", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ int board_early_init_f(void) diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c index bae0e70..a9d370b 100644 --- a/board/kontron/sl-mx6ul/spl.c +++ b/board/kontron/sl-mx6ul/spl.c @@ -101,7 +101,7 @@ int board_mmc_init(struct bd_info *bis) /* * According to the board_mmc_init() the following map is done: - * (U-boot device node) (Physical Port) + * (U-Boot device node) (Physical Port) * mmc0 USDHC1 * mmc1 USDHC2 */ diff --git a/board/kontron/sl-mx8mm/sl-mx8mm.c b/board/kontron/sl-mx8mm/sl-mx8mm.c index 2501956..ddb509e 100644 --- a/board/kontron/sl-mx8mm/sl-mx8mm.c +++ b/board/kontron/sl-mx8mm/sl-mx8mm.c @@ -29,10 +29,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "sf 0:0=flash-bin raw 0x400 0x1f0000", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ int board_phys_sdram_size(phys_size_t *size) diff --git a/board/kontron/sl28/sl28.c b/board/kontron/sl28/sl28.c index 89948e0..4ab221c 100644 --- a/board/kontron/sl28/sl28.c +++ b/board/kontron/sl28/sl28.c @@ -40,10 +40,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "sf 0:0=u-boot-bin raw 0x210000 0x1d0000;" "u-boot-env raw 0x3e0000 0x20000", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ int board_early_init_f(void) diff --git a/board/menlo/m53menlo/m53menlo.c b/board/menlo/m53menlo/m53menlo.c index 14324c7..ca3b81c 100644 --- a/board/menlo/m53menlo/m53menlo.c +++ b/board/menlo/m53menlo/m53menlo.c @@ -264,6 +264,7 @@ void board_preboot_os(void) gpio_direction_output(IMX_GPIO_NR(6, 0), 0); } +#if CONFIG_IS_ENABLED(OF_LIBFDT) int ft_board_setup(void *blob, struct bd_info *bd) { if (lvds_compat_string) @@ -272,6 +273,7 @@ int ft_board_setup(void *blob, struct bd_info *bd) return 0; } +#endif struct display_info_t const displays[] = { { diff --git a/board/microchip/mpfs_icicle/mpfs_icicle.c b/board/microchip/mpfs_icicle/mpfs_icicle.c index e74c9fb..0f5f829 100644 --- a/board/microchip/mpfs_icicle/mpfs_icicle.c +++ b/board/microchip/mpfs_icicle/mpfs_icicle.c @@ -80,7 +80,7 @@ int board_late_init(void) char icicle_mac_addr[20]; void *blob = (void *)gd->fdt_blob; - node = fdt_path_offset(blob, "ethernet0"); + node = fdt_path_offset(blob, "/soc/ethernet@20112000"); if (node < 0) { printf("No ethernet0 path offset\n"); return -ENODEV; @@ -88,7 +88,7 @@ int board_late_init(void) ret = fdtdec_get_byte_array(blob, node, "local-mac-address", mac_addr, 6); if (ret) { - printf("No local-mac-address property\n"); + printf("No local-mac-address property for ethernet@20112000\n"); return -EINVAL; } @@ -104,7 +104,7 @@ int board_late_init(void) ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); if (ret) { - printf("Error setting local-mac-address property\n"); + printf("Error setting local-mac-address property for ethernet@20112000\n"); return -ENODEV; } @@ -123,6 +123,15 @@ int board_late_init(void) mac_addr[5] = device_serial_number[0] + 1; + node = fdt_path_offset(blob, "/soc/ethernet@20110000"); + if (node >= 0) { + ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6); + if (ret) { + printf("Error setting local-mac-address property for ethernet@20110000\n"); + return -ENODEV; + } + } + icicle_mac_addr[0] = '['; sprintf(&icicle_mac_addr[1], "%pM", mac_addr); diff --git a/board/phytec/pcm058/README b/board/phytec/pcm058/README index 687366b..4b6984c 100644 --- a/board/phytec/pcm058/README +++ b/board/phytec/pcm058/README @@ -37,12 +37,12 @@ not supported. Flashing U-Boot onto an SD card ------------------------------- -After a successful build, the generated SPL and U-boot binaries can be copied +After a successful build, the generated SPL and U-Boot binaries can be copied to an SD card. Adjust the SD card device as necessary: $ sudo dd if=u-boot-with-spl.imx of=/dev/mmcblk0 bs=1k seek=1 -This is equivalent to separately copying the SPL and U-boot using: +This is equivalent to separately copying the SPL and U-Boot using: $ sudo dd if=SPL of=/dev/mmcblk0 bs=1k seek=1 $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197 @@ -50,11 +50,11 @@ $ sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 bs=1k seek=197 The default bootscripts expect a kernel fit-image file named "fitImage" in the first partition and Linux ext4 rootfs in the second partition. -Flashing U-boot to the SPI Flash, for booting Linux from NAND +Flashing U-Boot to the SPI Flash, for booting Linux from NAND ------------------------------------------------------------- -The SD card created above can also be used to install the SPL and U-boot into -the SPI flash. Boot U-boot from the SD card as above, and stop at the autoboot. +The SD card created above can also be used to install the SPL and U-Boot into +the SPI flash. Boot U-Boot from the SD card as above, and stop at the autoboot. Then, clear the SPI flash: @@ -64,13 +64,13 @@ Then, clear the SPI flash: Load the equivalent of u-boot-with-spl.imx from the raw MMC into memory and copy to the SPI. The SPL is expected at an offset of 0x400, and its size is maximum 392*512-byte blocks in size, therefore 0x188 blocks, totaling 0x31000 -bytes. Assume U-boot should fit into 640KiB, therefore 0x500 512-byte blocks, +bytes. Assume U-Boot should fit into 640KiB, therefore 0x500 512-byte blocks, totalling 0xA0000 bytes. Adding these together: => mmc read ${loadaddr} 0x2 0x688 => sf write ${loadaddr} 0x400 0xD1000 -The SPL is located at offset 0x400, and U-boot at 0x31400 in SPI flash, as to +The SPL is located at offset 0x400, and U-Boot at 0x31400 in SPI flash, as to match the SD Card layout. This would allow, instead of reading from the SD Card above, with networking and TFTP correctly configured, the equivalent of: @@ -84,7 +84,7 @@ image) and "root" (which contains a ubifs root filesystem). The "bootm_size" variable in the environment -------------------------------------------- -By default, U-boot relocates the device tree towards the upper end of the RAM, +By default, U-Boot relocates the device tree towards the upper end of the RAM, which kernels using CONFIG_HIGHMEM=y may not be able to access during early -boot. With the bootm_size variable set to 0x30000000, U-boot relocates the +boot. With the bootm_size variable set to 0x30000000, U-Boot relocates the device tree to below this address instead. diff --git a/board/renesas/condor/Makefile b/board/renesas/condor/Makefile index cf6d566..19e6038 100644 --- a/board/renesas/condor/Makefile +++ b/board/renesas/condor/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_SPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := condor.o ../rcar-common/common.o +obj-y := ../rcar-common/common.o endif diff --git a/board/renesas/condor/condor.c b/board/renesas/condor/condor.c deleted file mode 100644 index 2dd2c15..0000000 --- a/board/renesas/condor/condor.c +++ /dev/null @@ -1,47 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * board/renesas/condor/condor.c - * This file is Condor board support. - * - * Copyright (C) 2019 Marek Vasut <marek.vasut+renesas@gmail.com> - */ - -#include <common.h> -#include <cpu_func.h> -#include <hang.h> -#include <init.h> -#include <asm/global_data.h> -#include <asm/processor.h> -#include <asm/mach-types.h> -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/arch/sys_proto.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} - -#define RST_BASE 0xE6160000 -#define RST_CA57RESCNT (RST_BASE + 0x40) -#define RST_CA53RESCNT (RST_BASE + 0x44) -#define RST_RSTOUTCR (RST_BASE + 0x58) -#define RST_CA57_CODE 0xA5A5000F -#define RST_CA53_CODE 0x5A5A000F - -void reset_cpu(void) -{ - unsigned long midr, cputype; - - asm volatile("mrs %0, midr_el1" : "=r" (midr)); - cputype = (midr >> 4) & 0xfff; - - if (cputype == 0xd03) - writel(RST_CA53_CODE, RST_CA53RESCNT); - else if (cputype == 0xd07) - writel(RST_CA57_CODE, RST_CA57RESCNT); - else - hang(); -} diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index 71efeaf..1ed72d3 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -67,12 +67,3 @@ int board_init(void) return 0; } - -#define RST_BASE 0xE6160000 -#define RST_CA53RESCNT (RST_BASE + 0x44) -#define RST_CA53_CODE 0x5A5A000F - -void reset_cpu(void) -{ - writel(RST_CA53_CODE, RST_CA53RESCNT); -} diff --git a/board/renesas/eagle/Kconfig b/board/renesas/eagle/Kconfig index 1e0710e..4d12843 100644 --- a/board/renesas/eagle/Kconfig +++ b/board/renesas/eagle/Kconfig @@ -10,6 +10,6 @@ config SYS_VENDOR default "renesas" config SYS_CONFIG_NAME - default "eagle" + default "rcar-gen3-common" endif diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile index 062c46b..9fb6a7c 100644 --- a/board/renesas/eagle/Makefile +++ b/board/renesas/eagle/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_SPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := eagle.o ../rcar-common/common.o +obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o endif diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c deleted file mode 100644 index 9af935c..0000000 --- a/board/renesas/eagle/eagle.c +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * board/renesas/eagle/eagle.c - * This file is Eagle board support. - * - * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> - */ - -#include <common.h> -#include <clock_legacy.h> -#include <cpu_func.h> -#include <hang.h> -#include <init.h> -#include <malloc.h> -#include <netdev.h> -#include <dm.h> -#include <asm/global_data.h> -#include <dm/platform_data/serial_sh.h> -#include <asm/processor.h> -#include <asm/mach-types.h> -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/gpio.h> -#include <asm/arch/rmobile.h> -#include <asm/arch/rcar-mstp.h> -#include <asm/arch/sh_sdhi.h> -#include <i2c.h> -#include <mmc.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define CPGWPR 0xE6150900 -#define CPGWPCR 0xE6150904 - -/* PLL */ -#define PLL0CR 0xE61500D8 -#define PLL0_STC_MASK 0x7F000000 -#define PLL0_STC_OFFSET 24 - -#define CLK2MHZ(clk) (clk / 1000 / 1000) -void s_init(void) -{ - struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; - struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; - u32 stc; - - /* Watchdog init */ - writel(0xA5A5A500, &rwdt->rwtcsra); - writel(0xA5A5A500, &swdt->swtcsra); - - /* CPU frequency setting. Set to 0.8GHz */ - stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET; - clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); -} - -int board_early_init_f(void) -{ - /* Unlock CPG access */ - writel(0xA5A5FFFF, CPGWPR); - writel(0x5A5A0000, CPGWPCR); - - return 0; -} - -int board_init(void) -{ - return 0; -} - -#define RST_BASE 0xE6160000 -#define RST_CA57RESCNT (RST_BASE + 0x40) -#define RST_CA53RESCNT (RST_BASE + 0x44) -#define RST_RSTOUTCR (RST_BASE + 0x58) -#define RST_CA57_CODE 0xA5A5000F -#define RST_CA53_CODE 0x5A5A000F - -void reset_cpu(void) -{ - unsigned long midr, cputype; - - asm volatile("mrs %0, midr_el1" : "=r" (midr)); - cputype = (midr >> 4) & 0xfff; - - if (cputype == 0xd03) - writel(RST_CA53_CODE, RST_CA53RESCNT); - else if (cputype == 0xd07) - writel(RST_CA57_CODE, RST_CA57RESCNT); - else - hang(); -} diff --git a/board/renesas/ebisu/Makefile b/board/renesas/ebisu/Makefile index 1fd9a03..956ce8a 100644 --- a/board/renesas/ebisu/Makefile +++ b/board/renesas/ebisu/Makefile @@ -9,5 +9,5 @@ ifdef CONFIG_SPL_BUILD obj-y := ../rcar-common/gen3-spl.o else -obj-y := ebisu.o ../rcar-common/common.o +obj-y := ../rcar-common/common.o endif diff --git a/board/renesas/ebisu/ebisu.c b/board/renesas/ebisu/ebisu.c deleted file mode 100644 index 9a70192..0000000 --- a/board/renesas/ebisu/ebisu.c +++ /dev/null @@ -1,45 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * board/renesas/ebisu/ebisu.c - * This file is Ebisu board support. - * - * Copyright (C) 2018 Marek Vasut <marek.vasut+renesas@gmail.com> - */ - -#include <common.h> -#include <cpu_func.h> -#include <hang.h> -#include <init.h> -#include <malloc.h> -#include <netdev.h> -#include <dm.h> -#include <asm/global_data.h> -#include <dm/platform_data/serial_sh.h> -#include <asm/processor.h> -#include <asm/mach-types.h> -#include <asm/io.h> -#include <linux/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/gpio.h> -#include <asm/arch/gpio.h> -#include <asm/arch/rmobile.h> -#include <asm/arch/rcar-mstp.h> -#include <asm/arch/sh_sdhi.h> -#include <i2c.h> -#include <mmc.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - return 0; -} - -#define RST_BASE 0xE6160000 -#define RST_CA53RESCNT (RST_BASE + 0x44) -#define RST_CA53_CODE 0x5A5A000F - -void reset_cpu(void) -{ - writel(RST_CA53_CODE, RST_CA53RESCNT); -} diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index ab7464d..0aa0f1a 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -84,8 +84,6 @@ int board_early_init_f(void) } #define RST_BASE 0xE6160000 /* Domain0 */ -#define RST_SRESCR0 (RST_BASE + 0x18) -#define RST_SPRES 0x5AA58000 #define RST_WDTRSTCR (RST_BASE + 0x10) #define RST_RWDT 0xA55A8002 @@ -103,8 +101,3 @@ int board_init(void) return 0; } - -void reset_cpu(void) -{ - writel(RST_SPRES, RST_SRESCR0); -} diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index f976c99..ed3f093 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -10,8 +10,10 @@ #include <common.h> #include <dm.h> #include <fdt_support.h> +#include <hang.h> #include <init.h> #include <asm/global_data.h> +#include <asm/io.h> #include <dm/uclass-internal.h> #include <asm/arch/rmobile.h> #include <linux/libfdt.h> @@ -52,6 +54,46 @@ int dram_init_banksize(void) return 0; } +int __weak board_init(void) +{ + return 0; +} + +#if defined(CONFIG_RCAR_GEN3) +#define RST_BASE 0xE6160000 +#define RST_CA57RESCNT (RST_BASE + 0x40) +#define RST_CA53RESCNT (RST_BASE + 0x44) +#define RST_RSTOUTCR (RST_BASE + 0x58) +#define RST_CA57_CODE 0xA5A5000F +#define RST_CA53_CODE 0x5A5A000F + +void __weak reset_cpu(void) +{ + unsigned long midr, cputype; + + asm volatile("mrs %0, midr_el1" : "=r" (midr)); + cputype = (midr >> 4) & 0xfff; + + if (cputype == 0xd03) + writel(RST_CA53_CODE, RST_CA53RESCNT); + else if (cputype == 0xd07) + writel(RST_CA57_CODE, RST_CA57RESCNT); + else + hang(); +} +#elif defined(CONFIG_RCAR_GEN4) +#define RST_BASE 0xE6160000 /* Domain0 */ +#define RST_SRESCR0 (RST_BASE + 0x18) +#define RST_SPRES 0x5AA58000 + +void __weak reset_cpu(void) +{ + writel(RST_SPRES, RST_SRESCR0); +} +#else +#error Neither CONFIG_RCAR_GEN3 nor CONFIG_RCAR_GEN4 are set +#endif + #if defined(CONFIG_OF_BOARD_SETUP) static int is_mem_overlap(void *blob, int first_mem_node, int curr_mem_node) { diff --git a/board/renesas/rcar-common/v3-common.c b/board/renesas/rcar-common/v3-common.c new file mode 100644 index 0000000..7c6202e --- /dev/null +++ b/board/renesas/rcar-common/v3-common.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2017-2023 Marek Vasut <marek.vasut+renesas@mailbox.org> + */ + +#include <common.h> +#include <clock_legacy.h> +#include <asm/io.h> + +#define CPGWPR 0xE6150900 +#define CPGWPCR 0xE6150904 + +/* PLL */ +#define PLL0CR 0xE61500D8 +#define PLL0_STC_MASK 0x7F000000 +#define PLL0_STC_OFFSET 24 + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + u32 stc; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* CPU frequency setting. Set to 0.8GHz */ + stc = ((800 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_OFFSET; + clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); +} + +int board_early_init_f(void) +{ + /* Unlock CPG access */ + writel(0xA5A5FFFF, CPGWPR); + writel(0x5A5A0000, CPGWPCR); + + return 0; +} diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index c27eb3f..939b48e 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -67,21 +67,12 @@ int board_init(void) return 0; } -#define RST_BASE 0xE6160000 -#define RST_CA57RESCNT (RST_BASE + 0x40) -#define RST_CA53RESCNT (RST_BASE + 0x44) -#define RST_RSTOUTCR (RST_BASE + 0x58) -#define RST_CODE 0xA5A5000F - +#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) void reset_cpu(void) { -#if CONFIG_IS_ENABLED(SYS_I2C_LEGACY) && defined(CONFIG_SYS_I2C_SH) i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80); -#else - /* only CA57 ? */ - writel(RST_CODE, RST_CA57RESCNT); -#endif } +#endif #ifdef CONFIG_MULTI_DTB_FIT int board_fit_config_name_match(const char *name) diff --git a/board/renesas/spider/spider.c b/board/renesas/spider/spider.c index caf88dc..fd83a72 100644 --- a/board/renesas/spider/spider.c +++ b/board/renesas/spider/spider.c @@ -65,8 +65,3 @@ int board_init(void) return 0; } - -void reset_cpu(void) -{ - writel(RST_SPRES, RST_SRESCR0); -} diff --git a/board/renesas/v3hsk/Kconfig b/board/renesas/v3hsk/Kconfig new file mode 100644 index 0000000..531ceb7 --- /dev/null +++ b/board/renesas/v3hsk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_V3HSK + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "v3hsk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "v3hsk" + +endif diff --git a/board/renesas/v3hsk/Makefile b/board/renesas/v3hsk/Makefile new file mode 100644 index 0000000..a9d597e --- /dev/null +++ b/board/renesas/v3hsk/Makefile @@ -0,0 +1,15 @@ +# +# board/renesas/v3hsk/Makefile +# +# Copyright (C) 2019 Renesas Electronics Corporation +# Copyright (C) 2019 Cogent Embedded, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o +obj-$(CONFIG_SYSRESET) += cpld.o +endif diff --git a/board/renesas/v3hsk/cpld.c b/board/renesas/v3hsk/cpld.c new file mode 100644 index 0000000..6016f6d --- /dev/null +++ b/board/renesas/v3hsk/cpld.c @@ -0,0 +1,180 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * V3HSK board CPLD access support + * + * Copyright (C) 2019 Renesas Electronics Corporation + * Copyright (C) 2019 Cogent Embedded, Inc. + * + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <i2c.h> +#include <linux/err.h> +#include <sysreset.h> +#include <command.h> + +#define CPLD_ADDR_PRODUCT_0 0x0000 /* R */ +#define CPLD_ADDR_PRODUCT_1 0x0001 /* R */ +#define CPLD_ADDR_PRODUCT_2 0x0002 /* R */ +#define CPLD_ADDR_PRODUCT_3 0x0003 /* R */ +#define CPLD_ADDR_CPLD_VERSION_D 0x0004 /* R */ +#define CPLD_ADDR_CPLD_VERSION_M 0x0005 /* R */ +#define CPLD_ADDR_CPLD_VERSION_Y_0 0x0006 /* R */ +#define CPLD_ADDR_CPLD_VERSION_Y_1 0x0007 /* R */ +#define CPLD_ADDR_MODE_SET_0 0x0008 /* R */ +#define CPLD_ADDR_MODE_SET_1 0x0009 /* R */ +#define CPLD_ADDR_MODE_SET_2 0x000A /* R */ +#define CPLD_ADDR_MODE_SET_3 0x000B /* R */ +#define CPLD_ADDR_MODE_SET_4 0x000C /* R */ +#define CPLD_ADDR_MODE_LAST_0 0x0018 /* R */ +#define CPLD_ADDR_MODE_LAST_1 0x0019 /* R */ +#define CPLD_ADDR_MODE_LAST_2 0x001A /* R */ +#define CPLD_ADDR_MODE_LAST_3 0x001B /* R */ +#define CPLD_ADDR_MODE_LAST_4 0x001C /* R */ +#define CPLD_ADDR_DIPSW4 0x0020 /* R */ +#define CPLD_ADDR_DIPSW5 0x0021 /* R */ +#define CPLD_ADDR_RESET 0x0024 /* R/W */ +#define CPLD_ADDR_POWER_CFG 0x0025 /* R/W */ +#define CPLD_ADDR_PERI_CFG_0 0x0030 /* R/W */ +#define CPLD_ADDR_PERI_CFG_1 0x0031 /* R/W */ +#define CPLD_ADDR_PERI_CFG_2 0x0032 /* R/W */ +#define CPLD_ADDR_PERI_CFG_3 0x0033 /* R/W */ +#define CPLD_ADDR_LEDS 0x0034 /* R/W */ +#define CPLD_ADDR_LEDS_CFG 0x0035 /* R/W */ +#define CPLD_ADDR_UART_CFG 0x0036 /* R/W */ +#define CPLD_ADDR_UART_STATUS 0x0037 /* R */ + +#define CPLD_ADDR_PCB_VERSION_0 0x1000 /* R */ +#define CPLD_ADDR_PCB_VERSION_1 0x1001 /* R */ +#define CPLD_ADDR_SOC_VERSION_0 0x1002 /* R */ +#define CPLD_ADDR_SOC_VERSION_1 0x1003 /* R */ +#define CPLD_ADDR_PCB_SN_0 0x1004 /* R */ +#define CPLD_ADDR_PCB_SN_1 0x1005 /* R */ + +static u16 cpld_read(struct udevice *dev, u16 addr) +{ + u8 data[2]; + + /* Random flash reads require 2 reads: first read is unreliable */ + if (addr >= CPLD_ADDR_PCB_VERSION_0) + dm_i2c_read(dev, addr, data, 2); + + /* Only the second byte read is valid */ + dm_i2c_read(dev, addr, data, 2); + return data[1]; +} + +static void cpld_write(struct udevice *dev, u16 addr, u8 data) +{ + dm_i2c_write(dev, addr, &data, 1); +} + +static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + u16 addr, val; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_SYSRESET, + DM_DRIVER_GET(sysreset_renesas_v3hsk), + &dev); + if (ret) + return ret; + + if (argc == 2 && strcmp(argv[1], "info") == 0) { + printf("Product: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_PRODUCT_3) << 24) | + (cpld_read(dev, CPLD_ADDR_PRODUCT_2) << 16) | + (cpld_read(dev, CPLD_ADDR_PRODUCT_1) << 8) | + cpld_read(dev, CPLD_ADDR_PRODUCT_0)); + printf("CPLD version: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_1) << 24) | + (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y_0) << 16) | + (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_M) << 8) | + cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D)); + printf("Mode setting (MD0..26): 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_MODE_LAST_3) << 24) | + (cpld_read(dev, CPLD_ADDR_MODE_LAST_2) << 16) | + (cpld_read(dev, CPLD_ADDR_MODE_LAST_1) << 8) | + cpld_read(dev, CPLD_ADDR_MODE_LAST_0)); + printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n", + cpld_read(dev, CPLD_ADDR_DIPSW4) ^ 0xff, + (cpld_read(dev, CPLD_ADDR_DIPSW5) ^ 0xff) & 0xf); + printf("Power config: 0x%08x\n", + cpld_read(dev, CPLD_ADDR_POWER_CFG)); + printf("Periferals config: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_PERI_CFG_3) << 24) | + (cpld_read(dev, CPLD_ADDR_PERI_CFG_2) << 16) | + (cpld_read(dev, CPLD_ADDR_PERI_CFG_1) << 8) | + cpld_read(dev, CPLD_ADDR_PERI_CFG_0)); + printf("PCB version: %d.%d\n", + cpld_read(dev, CPLD_ADDR_PCB_VERSION_1), + cpld_read(dev, CPLD_ADDR_PCB_VERSION_0)); + printf("SOC version: %d.%d\n", + cpld_read(dev, CPLD_ADDR_SOC_VERSION_1), + cpld_read(dev, CPLD_ADDR_SOC_VERSION_0)); + printf("PCB S/N: %d\n", + (cpld_read(dev, CPLD_ADDR_PCB_SN_1) << 8) | + cpld_read(dev, CPLD_ADDR_PCB_SN_0)); + return 0; + } + + if (argc < 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[2], NULL, 16); + if (!(addr >= CPLD_ADDR_PRODUCT_0 && addr <= CPLD_ADDR_UART_STATUS)) { + printf("cpld invalid addr\n"); + return CMD_RET_USAGE; + } + + if (argc == 3 && strcmp(argv[1], "read") == 0) { + printf("0x%x\n", cpld_read(dev, addr)); + } else if (argc == 4 && strcmp(argv[1], "write") == 0) { + val = simple_strtoul(argv[3], NULL, 16); + cpld_write(dev, addr, val); + } + + return 0; +} + +U_BOOT_CMD(cpld, 4, 1, do_cpld, + "CPLD access", + "info\n" + "cpld read addr\n" + "cpld write addr val\n" +); + +static int renesas_v3hsk_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + cpld_write(dev, CPLD_ADDR_RESET, 1); + + return -EINPROGRESS; +} + +static int renesas_v3hsk_sysreset_probe(struct udevice *dev) +{ + if (device_get_uclass_id(dev->parent) != UCLASS_I2C) + return -EPROTONOSUPPORT; + + return 0; +} + +static struct sysreset_ops renesas_v3hsk_sysreset = { + .request = renesas_v3hsk_sysreset_request, +}; + +static const struct udevice_id renesas_v3hsk_sysreset_ids[] = { + { .compatible = "renesas,v3hsk-cpld" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sysreset_renesas_v3hsk) = { + .name = "renesas_v3hsk_sysreset", + .id = UCLASS_SYSRESET, + .ops = &renesas_v3hsk_sysreset, + .probe = renesas_v3hsk_sysreset_probe, + .of_match = renesas_v3hsk_sysreset_ids, +}; diff --git a/board/renesas/v3msk/Kconfig b/board/renesas/v3msk/Kconfig new file mode 100644 index 0000000..fe037fd --- /dev/null +++ b/board/renesas/v3msk/Kconfig @@ -0,0 +1,15 @@ +if TARGET_V3MSK + +config SYS_SOC + default "rmobile" + +config SYS_BOARD + default "v3msk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "rcar-gen3-common" + +endif diff --git a/board/renesas/v3msk/MAINTAINERS b/board/renesas/v3msk/MAINTAINERS new file mode 100644 index 0000000..12822a4 --- /dev/null +++ b/board/renesas/v3msk/MAINTAINERS @@ -0,0 +1,6 @@ +V3MSK BOARD +M: Cogent Embedded, Inc. <source@cogentembedded.com> +S: Maintained +F: board/renesas/v3msk/ +F: include/configs/v3msk.h +F: configs/r8a77970_v3msk_defconfig diff --git a/board/renesas/v3msk/Makefile b/board/renesas/v3msk/Makefile new file mode 100644 index 0000000..ec493e5 --- /dev/null +++ b/board/renesas/v3msk/Makefile @@ -0,0 +1,15 @@ +# +# board/renesas/v3msk/Makefile +# +# Copyright (C) 2019 Renesas Electronics Corporation +# Copyright (C) 2019 Cogent Embedded, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifdef CONFIG_SPL_BUILD +obj-y := ../rcar-common/gen3-spl.o +else +obj-y := ../rcar-common/v3-common.o ../rcar-common/common.o +obj-$(CONFIG_SYSRESET) += cpld.o +endif diff --git a/board/renesas/v3msk/cpld.c b/board/renesas/v3msk/cpld.c new file mode 100644 index 0000000..aed616a --- /dev/null +++ b/board/renesas/v3msk/cpld.c @@ -0,0 +1,368 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * V3MSK board CPLD access support + * + * Copyright (C) 2019 Renesas Electronics Corporation + * Copyright (C) 2019 Cogent Embedded, Inc. + * + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <dm.h> +#include <errno.h> +#include <linux/err.h> +#include <sysreset.h> +#include <linux/delay.h> +#include <command.h> + +#define CPLD_ADDR_PRODUCT_L 0x000 /* R */ +#define CPLD_ADDR_PRODUCT_H 0x001 /* R */ +#define CPLD_ADDR_CPLD_VERSION_D 0x002 /* R */ +#define CPLD_ADDR_CPLD_VERSION_Y 0x003 /* R */ +#define CPLD_ADDR_MODE_SET_L 0x004 /* R/W */ +#define CPLD_ADDR_MODE_SET_H 0x005 /* R/W */ +#define CPLD_ADDR_MODE_APPLIED_L 0x006 /* R */ +#define CPLD_ADDR_MODE_APPLIED_H 0x007 /* R */ +#define CPLD_ADDR_DIPSW 0x008 /* R */ +#define CPLD_ADDR_RESET 0x00A /* R/W */ +#define CPLD_ADDR_POWER_CFG 0x00B /* R/W */ +#define CPLD_ADDR_PERI_CFG1 0x00C /* R/W */ +#define CPLD_ADDR_PERI_CFG2 0x00D /* R/W */ +#define CPLD_ADDR_LEDS 0x00E /* R/W */ +#define CPLD_ADDR_PCB_VERSION 0x300 /* R */ +#define CPLD_ADDR_SOC_VERSION 0x301 /* R */ +#define CPLD_ADDR_PCB_SN_L 0x302 /* R */ +#define CPLD_ADDR_PCB_SN_H 0x303 /* R */ + +#define MDIO_DELAY 10 /* microseconds */ + +#define CPLD_MAX_GPIOS 2 + +struct renesas_v3msk_sysreset_priv { + struct gpio_desc miso; + struct gpio_desc mosi; + struct gpio_desc mdc; + struct gpio_desc enablez; + /* + * V3MSK Videobox Mini board has CANFD PHY connected + * we must shutdown this chip to use bb pins + */ + struct gpio_desc gpios[CPLD_MAX_GPIOS]; +}; + +static void mdio_bb_active_mdio(struct renesas_v3msk_sysreset_priv *priv) +{ + dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); +} + +static void mdio_bb_tristate_mdio(struct renesas_v3msk_sysreset_priv *priv) +{ + dm_gpio_set_dir_flags(&priv->mosi, GPIOD_IS_IN); +} + +static void mdio_bb_set_mdio(struct renesas_v3msk_sysreset_priv *priv, int val) +{ + dm_gpio_set_value(&priv->mosi, val); +} + +static int mdio_bb_get_mdio(struct renesas_v3msk_sysreset_priv *priv) +{ + return dm_gpio_get_value(&priv->miso); +} + +static void mdio_bb_set_mdc(struct renesas_v3msk_sysreset_priv *priv, int val) +{ + dm_gpio_set_value(&priv->mdc, val); +} + +static void mdio_bb_delay(void) +{ + udelay(MDIO_DELAY); +} + +/* Send the preamble, address, and register (common to read and write) */ +static void mdio_bb_pre(struct renesas_v3msk_sysreset_priv *priv, + u8 op, u8 addr, u8 reg) +{ + int i; + + /* 32-bit preamble */ + mdio_bb_active_mdio(priv); + mdio_bb_set_mdio(priv, 1); + for (i = 0; i < 32; i++) { + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + } + /* send the ST (2-bits of '01') */ + mdio_bb_set_mdio(priv, 0); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + mdio_bb_set_mdio(priv, 1); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + /* send the OP (2-bits of Opcode: '10'-read, '01'-write) */ + mdio_bb_set_mdio(priv, op >> 1); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + mdio_bb_set_mdio(priv, op & 1); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + /* send the PA5 (5-bits of PHY address) */ + for (i = 0; i < 5; i++) { + mdio_bb_set_mdio(priv, addr & 0x10); /* MSB first */ + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + addr <<= 1; + } + /* send the RA5 (5-bits of register address) */ + for (i = 0; i < 5; i++) { + mdio_bb_set_mdio(priv, reg & 0x10); /* MSB first */ + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + reg <<= 1; + } +} + +static int mdio_bb_read(struct renesas_v3msk_sysreset_priv *priv, + u8 addr, u8 reg) +{ + int i; + u16 data = 0; + + mdio_bb_pre(priv, 2, addr, reg); + /* tri-state MDIO */ + mdio_bb_tristate_mdio(priv); + /* read TA (2-bits of turn-around, last bit must be '0') */ + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + /* check the turnaround bit: the PHY should drive line to zero */ + if (mdio_bb_get_mdio(priv) != 0) { + printf("PHY didn't drive TA low\n"); + for (i = 0; i < 32; i++) { + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + } + /* There is no PHY, set value to 0xFFFF */ + return 0xFFFF; + } + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + /* read 16-bits of data */ + for (i = 0; i < 16; i++) { + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + data <<= 1; + data |= mdio_bb_get_mdio(priv); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + } + + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + + debug("cpld_read(0x%x) @ 0x%x = 0x%04x\n", reg, addr, data); + + return data; +} + +static void mdio_bb_write(struct renesas_v3msk_sysreset_priv *priv, + u8 addr, u8 reg, u16 val) +{ + int i; + + mdio_bb_pre(priv, 1, addr, reg); + /* send the TA (2-bits of turn-around '10') */ + mdio_bb_set_mdio(priv, 1); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + mdio_bb_set_mdio(priv, 0); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + /* write 16-bits of data */ + for (i = 0; i < 16; i++) { + mdio_bb_set_mdio(priv, val & 0x8000); /* MSB first */ + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); + val <<= 1; + } + /* tri-state MDIO */ + mdio_bb_tristate_mdio(priv); + mdio_bb_set_mdc(priv, 0); + mdio_bb_delay(); + mdio_bb_set_mdc(priv, 1); + mdio_bb_delay(); +} + +static u16 cpld_read(struct udevice *dev, u16 addr) +{ + struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev); + + /* random flash reads require 2 reads: first read is unreliable */ + if (addr >= CPLD_ADDR_PCB_VERSION) + mdio_bb_read(priv, addr >> 5, addr & 0x1f); + + return mdio_bb_read(priv, addr >> 5, addr & 0x1f); +} + +static void cpld_write(struct udevice *dev, u16 addr, u16 data) +{ + struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev); + + mdio_bb_write(priv, addr >> 5, addr & 0x1f, data); +} + +static int do_cpld(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) +{ + struct udevice *dev; + u16 addr, val; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_SYSRESET, + DM_DRIVER_GET(sysreset_renesas_v3msk), + &dev); + if (ret) + return ret; + + if (argc == 2 && strcmp(argv[1], "info") == 0) { + printf("Product: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_PRODUCT_H) << 16) | + cpld_read(dev, CPLD_ADDR_PRODUCT_L)); + printf("CPLD version: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_CPLD_VERSION_Y) << 16) | + cpld_read(dev, CPLD_ADDR_CPLD_VERSION_D)); + printf("Mode setting (MD0..26): 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_MODE_APPLIED_H) << 16) | + cpld_read(dev, CPLD_ADDR_MODE_APPLIED_L)); + printf("DIPSW (SW4, SW5): 0x%02x, 0x%x\n", + (cpld_read(dev, CPLD_ADDR_DIPSW) & 0xff) ^ 0xff, + (cpld_read(dev, CPLD_ADDR_DIPSW) >> 8) ^ 0xf); + printf("Power config: 0x%08x\n", + cpld_read(dev, CPLD_ADDR_POWER_CFG)); + printf("Periferals config: 0x%08x\n", + (cpld_read(dev, CPLD_ADDR_PERI_CFG2) << 16) | + cpld_read(dev, CPLD_ADDR_PERI_CFG1)); + printf("PCB version: %d.%d\n", + cpld_read(dev, CPLD_ADDR_PCB_VERSION) >> 8, + cpld_read(dev, CPLD_ADDR_PCB_VERSION) & 0xff); + printf("SOC version: %d.%d\n", + cpld_read(dev, CPLD_ADDR_SOC_VERSION) >> 8, + cpld_read(dev, CPLD_ADDR_SOC_VERSION) & 0xff); + printf("PCB S/N: %d\n", + (cpld_read(dev, CPLD_ADDR_PCB_SN_H) << 16) | + cpld_read(dev, CPLD_ADDR_PCB_SN_L)); + return 0; + } + + if (argc < 3) + return CMD_RET_USAGE; + + addr = simple_strtoul(argv[2], NULL, 16); + if (!(addr >= CPLD_ADDR_PRODUCT_L && addr <= CPLD_ADDR_LEDS)) { + printf("cpld invalid addr\n"); + return CMD_RET_USAGE; + } + + if (argc == 3 && strcmp(argv[1], "read") == 0) { + printf("0x%x\n", cpld_read(dev, addr)); + } else if (argc == 4 && strcmp(argv[1], "write") == 0) { + val = simple_strtoul(argv[3], NULL, 16); + cpld_write(dev, addr, val); + } + + return 0; +} + +U_BOOT_CMD(cpld, 4, 1, do_cpld, + "CPLD access", + "info\n" + "cpld read addr\n" + "cpld write addr val\n" +); + +static int renesas_v3msk_sysreset_request(struct udevice *dev, enum sysreset_t type) +{ + cpld_write(dev, CPLD_ADDR_RESET, 1); + + return -EINPROGRESS; +} + +static int renesas_v3msk_sysreset_probe(struct udevice *dev) +{ + struct renesas_v3msk_sysreset_priv *priv = dev_get_priv(dev); + + if (gpio_request_by_name(dev, "gpio-miso", 0, &priv->miso, + GPIOD_IS_IN)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-mosi", 0, &priv->mosi, + GPIOD_IS_OUT)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-mdc", 0, &priv->mdc, + GPIOD_IS_OUT)) + return -EINVAL; + + if (gpio_request_by_name(dev, "gpio-enablez", 0, &priv->enablez, + GPIOD_IS_OUT)) + return -EINVAL; + + /* V3MSK Videobox Mini board has CANFD PHY connected + * we must shutdown this chip to use bb pins + */ + gpio_request_list_by_name(dev, "gpios", priv->gpios, CPLD_MAX_GPIOS, + GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); + + return 0; +} + +static struct sysreset_ops renesas_v3msk_sysreset = { + .request = renesas_v3msk_sysreset_request, +}; + +static const struct udevice_id renesas_v3msk_sysreset_ids[] = { + { .compatible = "renesas,v3msk-cpld" }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(sysreset_renesas_v3msk) = { + .name = "renesas_v3msk_sysreset", + .id = UCLASS_SYSRESET, + .ops = &renesas_v3msk_sysreset, + .probe = renesas_v3msk_sysreset_probe, + .of_match = renesas_v3msk_sysreset_ids, + .priv_auto = sizeof(struct renesas_v3msk_sysreset_priv), +}; diff --git a/board/renesas/whitehawk/whitehawk.c b/board/renesas/whitehawk/whitehawk.c index 19f09e0..32284b2 100644 --- a/board/renesas/whitehawk/whitehawk.c +++ b/board/renesas/whitehawk/whitehawk.c @@ -65,8 +65,3 @@ int board_init(void) return 0; } - -void reset_cpu(void) -{ - writel(RST_SPRES, RST_SRESCR0); -} diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index c99ffdd..3c773d0 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -18,10 +18,10 @@ static struct efi_fw_image fw_images[ROCKPI4_UPDATABLE_IMAGES] = {0}; struct efi_capsule_update_info update_info = { + .num_images = ROCKPI4_UPDATABLE_IMAGES, .images = fw_images, }; -u8 num_image_type_guids = ROCKPI4_UPDATABLE_IMAGES; #endif #ifndef CONFIG_SPL_BUILD diff --git a/board/sandbox/sandbox.c b/board/sandbox/sandbox.c index 2e44bdf..c7b6cb7 100644 --- a/board/sandbox/sandbox.c +++ b/board/sandbox/sandbox.c @@ -67,10 +67,10 @@ struct efi_fw_image fw_images[] = { struct efi_capsule_update_info update_info = { .dfu_string = "sf 0:0=u-boot-bin raw 0x100000 0x50000;" "u-boot-env raw 0x150000 0x200000", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ #if !CONFIG_IS_ENABLED(OF_PLATDATA) diff --git a/board/socionext/developerbox/Makefile b/board/socionext/developerbox/Makefile index 4a46de9..1acd067 100644 --- a/board/socionext/developerbox/Makefile +++ b/board/socionext/developerbox/Makefile @@ -7,3 +7,4 @@ # obj-y := developerbox.o +obj-$(CONFIG_FWU_MDATA_MTD) += fwu_plat.o diff --git a/board/socionext/developerbox/developerbox.c b/board/socionext/developerbox/developerbox.c index 16e14d4..204e5a4 100644 --- a/board/socionext/developerbox/developerbox.c +++ b/board/socionext/developerbox/developerbox.c @@ -20,6 +20,13 @@ #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT) struct efi_fw_image fw_images[] = { +#if CONFIG_IS_ENABLED(FWU_MULTI_BANK_UPDATE) + { + .image_type_id = DEVELOPERBOX_FIP_IMAGE_GUID, + .fw_name = u"DEVELOPERBOX-FIP", + .image_index = 1, + }, +#else { .image_type_id = DEVELOPERBOX_UBOOT_IMAGE_GUID, .fw_name = u"DEVELOPERBOX-UBOOT", @@ -35,16 +42,17 @@ struct efi_fw_image fw_images[] = { .fw_name = u"DEVELOPERBOX-OPTEE", .image_index = 3, }, +#endif }; struct efi_capsule_update_info update_info = { .dfu_string = "mtd nor1=u-boot.bin raw 200000 100000;" "fip.bin raw 180000 78000;" "optee.bin raw 500000 100000", + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ static struct mm_region sc2a11_mem_map[] = { diff --git a/board/socionext/developerbox/fwu_plat.c b/board/socionext/developerbox/fwu_plat.c new file mode 100644 index 0000000..e724e70 --- /dev/null +++ b/board/socionext/developerbox/fwu_plat.c @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include <efi_loader.h> +#include <fwu.h> +#include <fwu_mdata.h> +#include <memalign.h> +#include <mtd.h> + +#define DFU_ALT_BUF_LEN 256 + +/* Generate dfu_alt_info from partitions */ +void set_dfu_alt_info(char *interface, char *devstr) +{ + ALLOC_CACHE_ALIGN_BUFFER(char, buf, DFU_ALT_BUF_LEN); + struct mtd_info *mtd; + int ret; + + memset(buf, 0, sizeof(buf)); + + mtd_probe_devices(); + + mtd = get_mtd_device_nm("nor1"); + if (IS_ERR_OR_NULL(mtd)) + return; + + ret = fwu_gen_alt_info_from_mtd(buf, DFU_ALT_BUF_LEN, mtd); + if (ret < 0) { + log_err("Error: Failed to generate dfu_alt_info. (%d)\n", ret); + return; + } + log_debug("Make dfu_alt_info: '%s'\n", buf); + + env_set("dfu_alt_info", buf); +} diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index 02e6afb..1d63c81 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -13,7 +13,6 @@ #include <common.h> #include <clock_legacy.h> #include <env.h> -#include <env_internal.h> #include <init.h> #include <pci.h> #include <uuid.h> @@ -222,19 +221,3 @@ int get_serial_clock(void) { return 333333330; } - -enum env_location env_get_location(enum env_operation op, int prio) -{ - if (op == ENVOP_SAVE || op == ENVOP_ERASE) - return ENVL_FLASH; - - switch (prio) { - case 0: - return ENVL_NOWHERE; - case 1: - return ENVL_FLASH; - default: - return ENVL_UNKNOWN; - } - return ENVL_UNKNOWN; -} diff --git a/board/solidrun/mx6cuboxi/mx6cuboxi.c b/board/solidrun/mx6cuboxi/mx6cuboxi.c index cb14c2f..6fa5cf4 100644 --- a/board/solidrun/mx6cuboxi/mx6cuboxi.c +++ b/board/solidrun/mx6cuboxi/mx6cuboxi.c @@ -275,9 +275,8 @@ int board_early_init_f(void) { setup_iomux_uart(); -#ifdef CONFIG_SATA - setup_sata(); -#endif + if (CONFIG_IS_ENABLED(SATA)) + setup_sata(); setup_fec(); return 0; diff --git a/board/st/common/Kconfig b/board/st/common/Kconfig index aba3590..c1c254d 100644 --- a/board/st/common/Kconfig +++ b/board/st/common/Kconfig @@ -6,72 +6,6 @@ config CMD_STBOARD This compile the stboard command to read and write the board in the OTP. -config MTDPARTS_NAND0_BOOT - string "mtd boot partitions for nand0" - default "2m(fsbl),2m(ssbl1),2m(ssbl2)" if STM32MP15x_STM32IMAGE || \ - !TFABOOT - default "2m(fsbl),4m(fip1),4m(fip2)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP - help - This define the partitions of nand0 used to build mtparts dynamically - for boot from nand0. - Each partition need to be aligned with the device erase block size, - 512KB is the max size for the NAND supported by stm32mp1 platform. - The fsbl partition support multiple copy of the same binary, one by - erase block. - -config MTDPARTS_NAND0_TEE - string "mtd tee partitions for nand0" - default "512k(teeh),512k(teed),512k(teex)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE - help - This define the tee partitions added in mtparts dynamically - when tee is supported with boot from nand0. - Each partition need to be aligned with the device erase block size, - 512KB is the max size for the NAND supported by stm32mp1 platform. - -config MTDPARTS_NOR0_BOOT - string "mtd boot partitions for nor0" - default "256k(fsbl1),256k(fsbl2),2m(ssbl),512k(u-boot-env)" if STM32MP15x_STM32IMAGE || \ - !TFABOOT - default "256k(fsbl1),256k(fsbl2),4m(fip),512k(u-boot-env)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP - help - This define the partitions of nand0 used to build mtparts dynamically - for boot from nor0. - Each partition need to be aligned with the device erase block size, - with 256KB we support all the NOR. - U-Boot env partition (512kB) use 2 erase block for redundancy. - -config MTDPARTS_NOR0_TEE - string "mtd tee partitions for nor0" - default "256k(teeh),512k(teed),256k(teex)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE - help - This define the tee partitions added in mtparts dynamically - when tee is supported with boot from nor0. - -config MTDPARTS_SPINAND0_BOOT - string "mtd boot partitions for spi-nand0" - default "2m(fsbl),2m(ssbl1),2m(ssbl2)" if STM32MP15x_STM32IMAGE || !TFABOOT - default "2m(fsbl),4m(fip1),4m(fip2)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP - help - This define the partitions of nand0 used to build mtparts dynamically - for boot from spi-nand0, - 512KB is the max size for the NAND supported by stm32mp1 platform. - The fsbl partition support multiple copy of the same binary, one by - erase block. - -config MTDPARTS_SPINAND0_TEE - string "mtd tee partitions for spi-nand0" - default "512k(teeh),512k(teed),512k(teex)" - depends on SYS_MTDPARTS_RUNTIME && ARCH_STM32MP && STM32MP15x_STM32IMAGE - help - This define the tee partitions added in mtparts dynamically - when tee is supported with boot from spi-nand0, - 512KB is the max size for the NAND supported by stm32mp1 platform. - config DFU_ALT_RAM0 string "dfu for ram0" default "uImage ram 0xc2000000 0x2000000;devicetree.dtb ram 0xc4000000 0x100000;uramdisk.image.gz ram 0xc4400000 0x10000000" diff --git a/board/st/common/Makefile b/board/st/common/Makefile index 65bbebd..c960829 100644 --- a/board/st/common/Makefile +++ b/board/st/common/Makefile @@ -7,7 +7,6 @@ obj-$(CONFIG_CMD_STBOARD) += cmd_stboard.o obj-$(CONFIG_PMIC_STPMIC1) += stpmic1.o ifeq ($(CONFIG_ARCH_STM32MP),y) -obj-$(CONFIG_SYS_MTDPARTS_RUNTIME) += stm32mp_mtdparts.o obj-$(CONFIG_SET_DFU_ALT_INFO) += stm32mp_dfu.o endif diff --git a/board/st/common/stm32mp_mtdparts.c b/board/st/common/stm32mp_mtdparts.c deleted file mode 100644 index 67a56a2..0000000 --- a/board/st/common/stm32mp_mtdparts.c +++ /dev/null @@ -1,177 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause -/* - * Copyright (C) 2020, STMicroelectronics - All Rights Reserved - */ - -#include <common.h> -#include <dfu.h> -#include <dm.h> -#include <env.h> -#include <env_internal.h> -#include <log.h> -#include <mtd.h> -#include <mtd_node.h> -#ifdef CONFIG_STM32MP15x_STM32IMAGE -#include <tee.h> -#endif -#include <asm/arch/stm32prog.h> -#include <asm/arch/sys_proto.h> -#include <asm/global_data.h> - -#define MTDPARTS_LEN 256 -#define MTDIDS_LEN 128 - -/* - * Get a global data pointer - */ -DECLARE_GLOBAL_DATA_PTR; - -/** - * update the variables "mtdids" and "mtdparts" with boot, tee and user strings - */ -static void board_set_mtdparts(const char *dev, - char *mtdids, - char *mtdparts, - const char *boot, -#ifdef CONFIG_STM32MP15x_STM32IMAGE - const char *tee, -#endif - const char *user) -{ - /* mtdids: "<dev>=<dev>, ...." */ - if (mtdids[0] != '\0') - strcat(mtdids, ","); - strcat(mtdids, dev); - strcat(mtdids, "="); - strcat(mtdids, dev); - - /* mtdparts: "mtdparts=<dev>:<mtdparts_<dev>>;..." */ - if (mtdparts[0] != '\0') - strncat(mtdparts, ";", MTDPARTS_LEN); - else - strcat(mtdparts, "mtdparts="); - - strncat(mtdparts, dev, MTDPARTS_LEN); - strncat(mtdparts, ":", MTDPARTS_LEN); - - if (boot) { - strncat(mtdparts, boot, MTDPARTS_LEN); - strncat(mtdparts, ",", MTDPARTS_LEN); - } - -#ifdef CONFIG_STM32MP15x_STM32IMAGE - if (tee) { - strncat(mtdparts, tee, MTDPARTS_LEN); - strncat(mtdparts, ",", MTDPARTS_LEN); - } -#endif - - strncat(mtdparts, user, MTDPARTS_LEN); -} - -void board_mtdparts_default(const char **mtdids, const char **mtdparts) -{ - struct mtd_info *mtd; - struct udevice *dev; - static char parts[3 * MTDPARTS_LEN + 1]; - static char ids[MTDIDS_LEN + 1]; - static bool mtd_initialized; - bool nor, nand, spinand, serial; -#ifdef CONFIG_STM32MP15x_STM32IMAGE - bool tee = false; -#endif - - if (mtd_initialized) { - *mtdids = ids; - *mtdparts = parts; - return; - } - - nor = false; - nand = false; - spinand = false; - serial = false; - - switch (get_bootmode() & TAMP_BOOT_DEVICE_MASK) { - case BOOT_SERIAL_UART: - case BOOT_SERIAL_USB: - serial = true; - if (IS_ENABLED(CONFIG_CMD_STM32PROG)) { -#ifdef CONFIG_STM32MP15x_STM32IMAGE - tee = stm32prog_get_tee_partitions(); -#endif - nor = stm32prog_get_fsbl_nor(); - } - nand = true; - spinand = true; - break; - case BOOT_FLASH_NAND: - nand = true; - break; - case BOOT_FLASH_SPINAND: - spinand = true; - break; - case BOOT_FLASH_NOR: - nor = true; - break; - default: - break; - } - -#ifdef CONFIG_STM32MP15x_STM32IMAGE - if (!serial && tee_find_device(NULL, NULL, NULL, NULL)) - tee = true; -#endif - - memset(parts, 0, sizeof(parts)); - memset(ids, 0, sizeof(ids)); - - /* probe all MTD devices */ - for (uclass_first_device(UCLASS_MTD, &dev); - dev; - uclass_next_device(&dev)) { - log_debug("mtd device = %s\n", dev->name); - } - - if (nand) { - mtd = get_mtd_device_nm("nand0"); - if (!IS_ERR_OR_NULL(mtd)) { - board_set_mtdparts("nand0", ids, parts, - CONFIG_MTDPARTS_NAND0_BOOT, -#ifdef CONFIG_STM32MP15x_STM32IMAGE - !nor && tee ? CONFIG_MTDPARTS_NAND0_TEE : NULL, -#endif - "-(UBI)"); - put_mtd_device(mtd); - } - } - - if (spinand) { - mtd = get_mtd_device_nm("spi-nand0"); - if (!IS_ERR_OR_NULL(mtd)) { - board_set_mtdparts("spi-nand0", ids, parts, - CONFIG_MTDPARTS_SPINAND0_BOOT, -#ifdef CONFIG_STM32MP15x_STM32IMAGE - !nor && tee ? CONFIG_MTDPARTS_SPINAND0_TEE : NULL, -#endif - "-(UBI)"); - put_mtd_device(mtd); - } - } - - if (nor) { - if (!uclass_get_device(UCLASS_SPI_FLASH, 0, &dev)) { - board_set_mtdparts("nor0", ids, parts, - CONFIG_MTDPARTS_NOR0_BOOT, -#ifdef CONFIG_STM32MP15x_STM32IMAGE - tee ? CONFIG_MTDPARTS_NOR0_TEE : NULL, -#endif - "-(nor_user)"); - } - } - - mtd_initialized = true; - *mtdids = ids; - *mtdparts = parts; - log_debug("mtdids=%s & mtdparts=%s\n", ids, parts); -} diff --git a/board/st/stm32mp1/stm32mp1.c b/board/st/stm32mp1/stm32mp1.c index 1a1b184..3205a31 100644 --- a/board/st/stm32mp1/stm32mp1.c +++ b/board/st/stm32mp1/stm32mp1.c @@ -25,7 +25,6 @@ #include <log.h> #include <malloc.h> #include <misc.h> -#include <mtd_node.h> #include <net.h> #include <netdev.h> #include <phy.h> @@ -92,10 +91,10 @@ struct efi_fw_image fw_images[1]; struct efi_capsule_update_info update_info = { + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ int board_early_init_f(void) @@ -915,20 +914,7 @@ int mmc_get_env_dev(void) #if defined(CONFIG_OF_BOARD_SETUP) int ft_board_setup(void *blob, struct bd_info *bd) { - static const struct node_info nodes[] = { - { "jedec,spi-nor", MTD_DEV_TYPE_NOR, }, - { "spi-nand", MTD_DEV_TYPE_SPINAND}, - { "st,stm32mp15-fmc2", MTD_DEV_TYPE_NAND, }, - { "st,stm32mp1-fmc2-nfc", MTD_DEV_TYPE_NAND, }, - }; - char *boot_device; - - /* Check the boot-source and don't update MTD for serial or usb boot */ - boot_device = env_get("boot_device"); - if (!boot_device || - (strcmp(boot_device, "serial") && strcmp(boot_device, "usb"))) - if (IS_ENABLED(CONFIG_FDT_FIXUP_PARTITIONS)) - fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_copy_fixed_partitions(blob); if (IS_ENABLED(CONFIG_FDT_SIMPLEFB)) fdt_simplefb_enable_and_mem_rsv(blob); diff --git a/board/synopsys/hsdk/hsdk.c b/board/synopsys/hsdk/hsdk.c index 4308c7e..6cbc89a 100644 --- a/board/synopsys/hsdk/hsdk.c +++ b/board/synopsys/hsdk/hsdk.c @@ -583,7 +583,7 @@ enum hsdk_axi_masters { * * Please read ARC HS Development IC Specification, section 17.2 for more * information about apertures configuration. - * NOTE: we intentionally modify default settings in U-boot. Default settings + * NOTE: we intentionally modify default settings in U-Boot. Default settings * are specified in "Table 111 CREG Address Decoder register reset values". */ @@ -942,7 +942,7 @@ static int do_hsdk_go(struct cmd_tbl *cmdtp, int flag, int argc, int ret; if (board_mismatch()) { - printf("ERR: U-boot is not configured for this board!\n"); + printf("ERR: U-Boot is not configured for this board!\n"); return CMD_RET_FAILURE; } @@ -983,10 +983,10 @@ U_BOOT_CMD( /* * We may simply use static variable here to store init status, but we also want - * to avoid the situation when we reload U-boot via MDB after previous + * to avoid the situation when we reload U-Boot via MDB after previous * init is done but HW reset (board reset) isn't done. So let's store the * init status in any unused register (i.e CREG_CPU_0_ENTRY) so status will - * survive after U-boot is reloaded via MDB. + * survive after U-Boot is reloaded via MDB. */ #define INIT_MARKER_REGISTER ((void __iomem *)CREG_CPU_0_ENTRY) /* must be equal to INIT_MARKER_REGISTER reset value */ @@ -1008,7 +1008,7 @@ static int do_hsdk_init(struct cmd_tbl *cmdtp, int flag, int argc, int ret; if (board_mismatch()) { - printf("ERR: U-boot is not configured for this board!\n"); + printf("ERR: U-Boot is not configured for this board!\n"); return CMD_RET_FAILURE; } @@ -1258,11 +1258,11 @@ int checkboard(void) printf("Board: Synopsys %s\n", board_name(get_board_type_runtime())); if (board_mismatch()) - printf("WARN: U-boot is configured NOT for this board but for %s!\n", + printf("WARN: U-Boot is configured NOT for this board but for %s!\n", board_name(get_board_type_config())); reg = readl(CREG_AXI_M_HS_CORE_BOOT) & CREG_CORE_BOOT_IMAGE; - printf("U-boot autostart: %s\n", reg ? "enabled" : "disabled"); + printf("U-Boot autostart: %s\n", reg ? "enabled" : "disabled"); return 0; }; diff --git a/board/ti/ti816x/Kconfig b/board/ti/ti816x/Kconfig deleted file mode 100644 index 95973b4..0000000 --- a/board/ti/ti816x/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_TI816X_EVM - -config SYS_BOARD - default "ti816x" - -config SYS_VENDOR - default "ti" - -config SYS_SOC - default "am33xx" - -config SYS_CONFIG_NAME - default "ti816x_evm" - -endif diff --git a/board/ti/ti816x/MAINTAINERS b/board/ti/ti816x/MAINTAINERS deleted file mode 100644 index fd9a98f..0000000 --- a/board/ti/ti816x/MAINTAINERS +++ /dev/null @@ -1,6 +0,0 @@ -TI816X BOARD -M: Tom Rini <trini@konsulko.com> -S: Maintained -F: board/ti/ti816x/ -F: include/configs/ti816x_evm.h -F: configs/ti816x_evm_defconfig diff --git a/board/ti/ti816x/Makefile b/board/ti/ti816x/Makefile deleted file mode 100644 index f12712a..0000000 --- a/board/ti/ti816x/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -# -# Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> -# Antoine Tenart, <atenart@adeneo-embedded.com> -# -# Based on TI-PSP-04.00.02.14 : -# -# Copyright (C) 2009, Texas Instruments, Incorporated - -obj-y := evm.o diff --git a/board/ti/ti816x/evm.c b/board/ti/ti816x/evm.c deleted file mode 100644 index 8c70835..0000000 --- a/board/ti/ti816x/evm.c +++ /dev/null @@ -1,140 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * evm.c - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - */ - -#include <common.h> -#include <env.h> -#include <init.h> -#include <net.h> -#include <spl.h> -#include <asm/cache.h> -#include <asm/global_data.h> -#include <asm/io.h> -#include <asm/arch/clock.h> -#include <asm/arch/cpu.h> -#include <asm/arch/ddr_defs.h> -#include <asm/arch/hardware.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/mmc_host_def.h> -#include <asm/arch/mem.h> -#include <asm/arch/mux.h> - -DECLARE_GLOBAL_DATA_PTR; - -int board_init(void) -{ - gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; -#if defined(CONFIG_MTD_RAW_NAND) - gpmc_init(); -#endif - return 0; -} - -int board_eth_init(struct bd_info *bis) -{ - uint8_t mac_addr[6]; - uint32_t mac_hi, mac_lo; - struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; - - if (!eth_env_get_enetaddr("ethaddr", mac_addr)) { - printf("<ethaddr> not set. Reading from E-fuse\n"); - /* try reading mac address from efuse */ - mac_lo = readl(&cdev->macid0l); - mac_hi = readl(&cdev->macid0h); - mac_addr[0] = mac_hi & 0xFF; - mac_addr[1] = (mac_hi & 0xFF00) >> 8; - mac_addr[2] = (mac_hi & 0xFF0000) >> 16; - mac_addr[3] = (mac_hi & 0xFF000000) >> 24; - mac_addr[4] = mac_lo & 0xFF; - mac_addr[5] = (mac_lo & 0xFF00) >> 8; - - if (is_valid_ethaddr(mac_addr)) - eth_env_set_enetaddr("ethaddr", mac_addr); - else - printf("Unable to read MAC address. Set <ethaddr>\n"); - } - - return 0; -} - -#ifdef CONFIG_SPL_BUILD -static struct module_pin_mux mmc_pin_mux[] = { - { OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) }, - { OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) }, - { OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) }, - { OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) }, - { OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) }, - { OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) }, - { OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) }, - { -1 }, -}; - -void set_uart_mux_conf(void) {} - -void set_mux_conf_regs(void) -{ - configure_module_pin_mux(mmc_pin_mux); -} - -/* - * EMIF Paramters. Refer the EMIF register documentation and the - * memory datasheet for details. This is for 796 MHz. - */ -#define EMIF_TIM1 0x1779C9FE -#define EMIF_TIM2 0x50608074 -#define EMIF_TIM3 0x009F857F -#define EMIF_SDREF 0x10001841 -#define EMIF_SDCFG 0x62A73832 -#define EMIF_PHYCFG 0x00000110 -static const struct emif_regs ddr3_emif_regs = { - .sdram_config = EMIF_SDCFG, - .ref_ctrl = EMIF_SDREF, - .sdram_tim1 = EMIF_TIM1, - .sdram_tim2 = EMIF_TIM2, - .sdram_tim3 = EMIF_TIM3, - .emif_ddr_phy_ctlr_1 = EMIF_PHYCFG, -}; - -static const struct cmd_control ddr3_ctrl = { - .cmd0csratio = 0x100, - .cmd0iclkout = 0x001, - .cmd1csratio = 0x100, - .cmd1iclkout = 0x001, - .cmd2csratio = 0x100, - .cmd2iclkout = 0x001, -}; - -/* These values are obtained from the CCS app */ -#define RD_DQS_GATE (0x1B3) -#define RD_DQS (0x35) -#define WR_DQS (0x93) -static struct ddr_data ddr3_data = { - .datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)), - .datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)), - .datawiratio0 = ((0x20<<10) | 0x20<<0), - .datagiratio0 = ((0x20<<10) | 0x20<<0), - .datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)), - .datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)), -}; - -static const struct dmm_lisa_map_regs evm_lisa_map_regs = { - .dmm_lisa_map_0 = 0x00000000, - .dmm_lisa_map_1 = 0x00000000, - .dmm_lisa_map_2 = 0x80640300, - .dmm_lisa_map_3 = 0xC0640320, -}; - -void sdram_init(void) -{ - /* - * Pass in our DDR3 config information and that we have 2 EMIFs to - * configure. - */ - config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs, - &evm_lisa_map_regs, 2); -} -#endif /* CONFIG_SPL_BUILD */ diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index f335d5b..8f23cda 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -76,17 +76,23 @@ static int baltos_set_console(void) static int read_eeprom(BSP_VS_HWPARAM *header) { - i2c_set_bus_num(1); + int rc; + struct udevice *dev; + struct udevice *bus; + + rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus); + if (rc) + return rc; /* Check if baseboard eeprom is available */ - if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + if (dm_i2c_probe(bus, CONFIG_SYS_I2C_EEPROM_ADDR, 0, &dev)) { puts("Could not probe the EEPROM; something fundamentally " "wrong on the I2C bus.\n"); return -ENODEV; } /* read the eeprom using i2c */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + if (dm_i2c_read(dev, 0, (uchar *)header, sizeof(BSP_VS_HWPARAM))) { puts("Could not read the EEPROM; something fundamentally" " wrong on the I2C bus.\n"); @@ -173,34 +179,28 @@ const struct dpll_params dpll_ddr_baltos = { void am33xx_spl_board_init(void) { - int mpu_vdd; - int sil_rev; + int sil_rev, mpu_vdd; + int freq; + + enable_i2c1_pin_mux(); + i2c_set_bus_num(1); - /* Get the frequency */ - dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + freq = am335x_get_efuse_mpu_max_freq(cdev); /* - * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all * MPU frequencies we support we use a CORE voltage of - * 1.1375V. For MPU voltage we need to switch based on + * 1.1375V. For MPU voltage we need to switch based on * the frequency we are running at. */ - i2c_set_bus_num(1); - - printf("I2C speed: %d Hz\n", CONFIG_SYS_I2C_SPEED); - - if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) { - puts("i2c: cannot access TPS65910\n"); + if (power_tps65910_init(1)) return; - } - /* * Depending on MPU clock and PG we will need a different * VDD to drive at that speed. */ sil_rev = readl(&cdev->deviceid) >> 28; - mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, - dpll_mpu_opp100.m); + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq); /* Tell the TPS65910 to use i2c */ tps65910_set_i2c_control(); @@ -213,12 +213,6 @@ void am33xx_spl_board_init(void) if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) return; - /* Set CORE Frequencies to OPP100 */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - - /* Set MPU Frequency to what we detected now that voltages are set */ - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); - writel(0x000010ff, PRM_DEVICE_INST + 4); } diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index da995dd..4891445 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -352,9 +352,8 @@ static void setup_display(void) int board_early_init_f(void) { setup_iomux_uart(); -#ifdef CONFIG_SATA - setup_sata(); -#endif + if (CONFIG_IS_ENABLED(SATA)) + setup_sata(); return 0; } diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c index d071ebf..0328d68 100644 --- a/board/xilinx/common/board.c +++ b/board/xilinx/common/board.c @@ -52,10 +52,10 @@ struct efi_fw_image fw_images[] = { }; struct efi_capsule_update_info update_info = { + .num_images = ARRAY_SIZE(fw_images), .images = fw_images, }; -u8 num_image_type_guids = ARRAY_SIZE(fw_images); #endif /* EFI_HAVE_CAPSULE_SUPPORT */ #define EEPROM_HEADER_MAGIC 0xdaaddeed diff --git a/board/xilinx/common/board.h b/board/xilinx/common/board.h index 69e6424..922c9d5 100644 --- a/board/xilinx/common/board.h +++ b/board/xilinx/common/board.h @@ -11,4 +11,11 @@ int board_late_init_xilinx(void); int xilinx_read_eeprom(void); +char *board_name_decode(void); + +bool board_detection(void); + +char *soc_name_decode(void); + +bool soc_detection(void); #endif /* BOARD_XILINX_COMMON_BOARD_H */ diff --git a/board/xilinx/versal-net/Kconfig b/board/xilinx/versal-net/Kconfig index 8f94d2b..2484429 100644 --- a/board/xilinx/versal-net/Kconfig +++ b/board/xilinx/versal-net/Kconfig @@ -6,4 +6,12 @@ if ARCH_VERSAL_NET +config CMD_VERSAL_NET + bool "Enable Versal NET specific commands" + default y + depends on ZYNQMP_FIRMWARE + help + Select this to enable Versal NET specific commands. + Commands like versalnet loadpdi are enabled by this. + endif diff --git a/board/xilinx/versal-net/Makefile b/board/xilinx/versal-net/Makefile index 2008d4e..f9ff07c 100644 --- a/board/xilinx/versal-net/Makefile +++ b/board/xilinx/versal-net/Makefile @@ -7,3 +7,4 @@ # obj-y := board.o +obj-$(CONFIG_CMD_VERSAL_NET) += cmds.o diff --git a/board/xilinx/versal-net/board.c b/board/xilinx/versal-net/board.c index 6724c72..a68b608 100644 --- a/board/xilinx/versal-net/board.c +++ b/board/xilinx/versal-net/board.c @@ -10,6 +10,7 @@ #include <cpu_func.h> #include <fdtdec.h> #include <init.h> +#include <env_internal.h> #include <log.h> #include <malloc.h> #include <time.h> @@ -74,32 +75,45 @@ char *soc_name_decode(void) bool soc_detection(void) { - u32 version; + u32 version, ps_version; version = readl(PMC_TAP_VERSION); platform_id = FIELD_GET(PLATFORM_MASK, version); + ps_version = FIELD_GET(PS_VERSION_MASK, version); debug("idcode %x, version %x, usercode %x\n", readl(PMC_TAP_IDCODE), version, readl(PMC_TAP_USERCODE)); - debug("pmc_ver %lx, ps version %lx, rtl version %lx\n", + debug("pmc_ver %lx, ps version %x, rtl version %lx\n", FIELD_GET(PMC_VERSION_MASK, version), - FIELD_GET(PS_VERSION_MASK, version), + ps_version, FIELD_GET(RTL_VERSION_MASK, version)); platform_version = FIELD_GET(PLATFORM_VERSION_MASK, version); if (platform_id == VERSAL_NET_SPP || platform_id == VERSAL_NET_EMU) { - /* - * 9 is diff for - * 0 means 0.9 version - * 1 means 1.0 version - * 2 means 1.1 version - * etc, - */ - platform_version += 9; + if (ps_version == PS_VERSION_PRODUCTION) { + /* + * ES1 version ends at 1.9 version where there was +9 + * used because of IPP/SPP conversion. Production + * version have platform_version started from 0 again + * that's why adding +20 to continue with the same line. + * It means the last ES1 version ends at 1.9 version and + * new PRODUCTION line starts at 2.0. + */ + platform_version += 20; + } else { + /* + * 9 is diff for + * 0 means 0.9 version + * 1 means 1.0 version + * 2 means 1.1 version + * etc, + */ + platform_version += 9; + } } debug("Platform id: %d version: %d.%d\n", platform_id, @@ -165,8 +179,32 @@ int board_early_init_r(void) return 0; } +static u8 versal_net_get_bootmode(void) +{ + u8 bootmode; + u32 reg = 0; + + reg = readl(&crp_base->boot_mode_usr); + + if (reg >> BOOT_MODE_ALT_SHIFT) + reg >>= BOOT_MODE_ALT_SHIFT; + + bootmode = reg & BOOT_MODES_MASK; + + return bootmode; +} + int board_late_init(void) { + u8 bootmode; + struct udevice *dev; + int bootseq = -1; + int bootseq_len = 0; + int env_targets_len = 0; + const char *mode; + char *new_targets; + char *env_targets; + if (!(gd->flags & GD_FLG_ENV_DEFAULT)) { debug("Saved variables - Skipping\n"); return 0; @@ -175,6 +213,95 @@ int board_late_init(void) if (!IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) return 0; + bootmode = versal_net_get_bootmode(); + + puts("Bootmode: "); + switch (bootmode) { + case USB_MODE: + puts("USB_MODE\n"); + mode = "usb_dfu0 usb_dfu1"; + break; + case JTAG_MODE: + puts("JTAG_MODE\n"); + mode = "jtag pxe dhcp"; + break; + case QSPI_MODE_24BIT: + puts("QSPI_MODE_24\n"); + mode = "xspi0"; + break; + case QSPI_MODE_32BIT: + puts("QSPI_MODE_32\n"); + mode = "xspi0"; + break; + case OSPI_MODE: + puts("OSPI_MODE\n"); + mode = "xspi0"; + break; + case EMMC_MODE: + puts("EMMC_MODE\n"); + mode = "mmc"; + bootseq = dev_seq(dev); + break; + case SD_MODE: + puts("SD_MODE\n"); + if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@f1040000", &dev)) { + puts("Boot from SD0 but without SD0 enabled!\n"); + return -1; + } + debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev)); + + mode = "mmc"; + bootseq = dev_seq(dev); + break; + case SD1_LSHFT_MODE: + puts("LVL_SHFT_"); + fallthrough; + case SD_MODE1: + puts("SD_MODE1\n"); + if (uclass_get_device_by_name(UCLASS_MMC, + "mmc@f1050000", &dev)) { + puts("Boot from SD1 but without SD1 enabled!\n"); + return -1; + } + debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev)); + + mode = "mmc"; + bootseq = dev_seq(dev); + break; + default: + mode = ""; + printf("Invalid Boot Mode:0x%x\n", bootmode); + break; + } + + if (bootseq >= 0) { + bootseq_len = snprintf(NULL, 0, "%i", bootseq); + debug("Bootseq len: %x\n", bootseq_len); + } + + /* + * One terminating char + one byte for space between mode + * and default boot_targets + */ + env_targets = env_get("boot_targets"); + if (env_targets) + env_targets_len = strlen(env_targets); + + new_targets = calloc(1, strlen(mode) + env_targets_len + 2 + + bootseq_len); + if (!new_targets) + return -ENOMEM; + + if (bootseq >= 0) + sprintf(new_targets, "%s%x %s", mode, bootseq, + env_targets ? env_targets : ""); + else + sprintf(new_targets, "%s %s", mode, + env_targets ? env_targets : ""); + + env_set("boot_targets", new_targets); + return board_late_init_xilinx(); } diff --git a/board/xilinx/versal-net/cmds.c b/board/xilinx/versal-net/cmds.c new file mode 100644 index 0000000..b18a71f --- /dev/null +++ b/board/xilinx/versal-net/cmds.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023, Advanced Micro Devices, Inc. + * + * Michal Simek <michal.simek@amd.com> + */ + +#include <cpu_func.h> +#include <command.h> +#include <common.h> +#include <log.h> +#include <memalign.h> +#include <versalpl.h> +#include <zynqmp_firmware.h> + +/** + * do_versalnet_load_pdi - Handle the "versalnet load pdi" command-line command + * @cmdtp: Command data struct pointer + * @flag: Command flag + * @argc: Command-line argument count + * @argv: Array of command-line arguments + * + * Processes the Versal NET load pdi command + * + * Return: return 0 on success, Error value if command fails. + * CMD_RET_USAGE incase of incorrect/missing parameters. + */ +static int do_versalnet_load_pdi(struct cmd_tbl *cmdtp, int flag, int argc, + char * const argv[]) +{ + u32 buf_lo, buf_hi; + u32 ret_payload[PAYLOAD_ARG_CNT]; + ulong addr, *pdi_buf; + size_t len; + int ret; + + if (argc != cmdtp->maxargs) { + debug("pdi_load: incorrect parameters passed\n"); + return CMD_RET_USAGE; + } + + addr = simple_strtol(argv[1], NULL, 16); + if (!addr) { + debug("pdi_load: zero pdi_data address\n"); + return CMD_RET_USAGE; + } + + len = hextoul(argv[2], NULL); + if (!len) { + debug("pdi_load: zero size\n"); + return CMD_RET_USAGE; + } + + pdi_buf = (ulong *)ALIGN((ulong)addr, ARCH_DMA_MINALIGN); + if ((ulong)addr != (ulong)pdi_buf) { + memcpy((void *)pdi_buf, (void *)addr, len); + debug("Pdi addr:0x%lx aligned to 0x%lx\n", + addr, (ulong)pdi_buf); + } + + flush_dcache_range((ulong)pdi_buf, (ulong)pdi_buf + len); + + buf_lo = lower_32_bits((ulong)pdi_buf); + buf_hi = upper_32_bits((ulong)pdi_buf); + + ret = xilinx_pm_request(VERSAL_PM_LOAD_PDI, VERSAL_PM_PDI_TYPE, buf_lo, + buf_hi, 0, ret_payload); + if (ret) + printf("PDI load failed with err: 0x%08x\n", ret); + + return cmd_process_error(cmdtp, ret); +} + +static char versalnet_help_text[] = + "loadpdi addr len - Load pdi image\n" + "load pdi image at ddr address 'addr' with pdi image size 'len'\n" +; + +U_BOOT_CMD_WITH_SUBCMDS(versalnet, "Versal NET sub-system", versalnet_help_text, + U_BOOT_SUBCMD_MKENT(loadpdi, 3, 1, + do_versalnet_load_pdi)); diff --git a/board/xilinx/zynqmp/cmds.c b/board/xilinx/zynqmp/cmds.c index e20030e..dd1ad66 100644 --- a/board/xilinx/zynqmp/cmds.c +++ b/board/xilinx/zynqmp/cmds.c @@ -187,6 +187,11 @@ static int do_zynqmp_tcm_init(struct cmd_tbl *cmdtp, int flag, int argc, if (argc != cmdtp->maxargs) return CMD_RET_USAGE; + if (strcmp(argv[2], "lockstep") && strcmp(argv[2], "split")) { + printf("mode param should be lockstep or split\n"); + return CMD_RET_FAILURE; + } + mode = hextoul(argv[2], NULL); if (mode != TCM_LOCK && mode != TCM_SPLIT) { printf("Mode should be either 0(lock)/1(split)\n"); @@ -211,15 +216,24 @@ static int do_zynqmp_pmufw(struct cmd_tbl *cmdtp, int flag, int argc, if (!strncmp(argv[2], "node", 4)) { u32 id; + int ret; if (!strncmp(argv[3], "close", 5)) return zynqmp_pmufw_config_close(); id = dectoul(argv[3], NULL); + if (!id) { + printf("Incorrect ID passed\n"); + return CMD_RET_USAGE; + } printf("Enable permission for node ID %d\n", id); - return zynqmp_pmufw_node(id); + ret = zynqmp_pmufw_node(id); + if (ret == -ENODEV) + ret = 0; + + return ret; } addr = hextoul(argv[2], NULL); @@ -390,17 +404,17 @@ static int do_zynqmp(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct cmd_tbl *c; + int ret = CMD_RET_USAGE; if (argc < 2) return CMD_RET_USAGE; c = find_cmd_tbl(argv[1], &cmd_zynqmp_sub[0], ARRAY_SIZE(cmd_zynqmp_sub)); - if (c) - return c->cmd(c, flag, argc, argv); - else - return CMD_RET_USAGE; + ret = c->cmd(c, flag, argc, argv); + + return cmd_process_error(c, ret); } /***************************************************/ @@ -429,7 +443,7 @@ static char zynqmp_help_text[] = " lock(0)/split(1)\n" #endif "zynqmp pmufw address size - load PMU FW configuration object\n" - "zynqmp pmufw node <id> - load PMU FW configuration object\n" + "zynqmp pmufw node <id> - load PMU FW configuration object, <id> in dec\n" "zynqmp pmufw node close - disable config object loading\n" " node: keyword, id: NODE_ID in decimal format\n" "zynqmp rsa srcaddr srclen mod exp rsaop -\n" diff --git a/boot/boot_fit.c b/boot/boot_fit.c index 4a493b3..9d39412 100644 --- a/boot/boot_fit.c +++ b/boot/boot_fit.c @@ -67,7 +67,7 @@ void *locate_dtb_in_fit(const void *fit) header = (struct legacy_img_hdr *)fit; if (image_get_magic(header) != FDT_MAGIC) { - debug("No FIT image appended to U-boot\n"); + debug("No FIT image appended to U-Boot\n"); return NULL; } diff --git a/cmd/Kconfig b/cmd/Kconfig index 02e54f1..c194184 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1228,6 +1228,7 @@ config LOADS_ECHO config CMD_SAVES bool "saves - Save a file over serial in S-Record format" + depends on CMD_LOADS help Provides a way to save a binary file using the Motorola S-Record format over the serial line. @@ -733,7 +733,7 @@ static int do_fdt(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) gd->fdt_blob = blob; cfg_noffset = fit_conf_get_node(working_fdt, NULL); - if (!cfg_noffset) { + if (cfg_noffset < 0) { printf("Could not find configuration node: %s\n", fdt_strerror(cfg_noffset)); return CMD_RET_FAILURE; @@ -20,7 +20,7 @@ U_BOOT_CMD( "determine a file's size", "<interface> <dev[:part]> <filename>\n" " - Find file 'filename' from 'dev' on 'interface'\n" - " and determine its size." + " determine its size, and store in the 'filesize' variable." ); static int do_load_wrapper(struct cmd_tbl *cmdtp, int flag, int argc, diff --git a/cmd/fwu_mdata.c b/cmd/fwu_mdata.c index f04af27..5ecda45 100644 --- a/cmd/fwu_mdata.c +++ b/cmd/fwu_mdata.c @@ -43,23 +43,10 @@ static void print_mdata(struct fwu_mdata *mdata) int do_fwu_mdata_read(struct cmd_tbl *cmdtp, int flag, int argc, char * const argv[]) { - struct udevice *dev; int ret = CMD_RET_SUCCESS, res; - struct fwu_mdata mdata = { 0 }; + struct fwu_mdata mdata; - if (uclass_get_device(UCLASS_FWU_MDATA, 0, &dev) || !dev) { - log_err("Unable to get FWU metadata device\n"); - return CMD_RET_FAILURE; - } - - res = fwu_check_mdata_validity(); - if (res < 0) { - log_err("FWU Metadata check failed\n"); - ret = CMD_RET_FAILURE; - goto out; - } - - res = fwu_get_mdata(dev, &mdata); + res = fwu_get_mdata(&mdata); if (res < 0) { log_err("Unable to get valid FWU metadata\n"); ret = CMD_RET_FAILURE; diff --git a/cmd/legacy-mtd-utils.c b/cmd/legacy-mtd-utils.c index ac7139f..5903a90 100644 --- a/cmd/legacy-mtd-utils.c +++ b/cmd/legacy-mtd-utils.c @@ -88,6 +88,11 @@ int mtd_arg_off_size(int argc, char *const argv[], int *idx, loff_t *off, return -1; } + if (*size == 0) { + debug("ERROR: Invalid size 0\n"); + return -1; + } + print: printf("device %d ", *idx); if (*size == chipsize) @@ -13,6 +13,7 @@ #include <bootstage.h> #include <command.h> #include <dm.h> +#include <dm/devres.h> #include <env.h> #include <image.h> #include <log.h> @@ -691,8 +692,58 @@ static int do_net_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const ar return CMD_RET_SUCCESS; } +static int do_net_stats(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + int nstats, err, i, off; + struct udevice *dev; + u64 *values; + u8 *strings; + + if (argc < 2) + return CMD_RET_USAGE; + + err = uclass_get_device_by_name(UCLASS_ETH, argv[1], &dev); + if (err) { + printf("Could not find device %s\n", argv[1]); + return CMD_RET_FAILURE; + } + + if (!eth_get_ops(dev)->get_sset_count || + !eth_get_ops(dev)->get_strings || + !eth_get_ops(dev)->get_stats) { + printf("Driver does not implement stats dump!\n"); + return CMD_RET_FAILURE; + } + + nstats = eth_get_ops(dev)->get_sset_count(dev); + strings = kcalloc(nstats, ETH_GSTRING_LEN, GFP_KERNEL); + if (!strings) + return CMD_RET_FAILURE; + + values = kcalloc(nstats, sizeof(u64), GFP_KERNEL); + if (!values) + goto err_free_strings; + + eth_get_ops(dev)->get_strings(dev, strings); + eth_get_ops(dev)->get_stats(dev, values); + + off = 0; + for (i = 0; i < nstats; i++) { + printf(" %s: %llu\n", &strings[off], values[i]); + off += ETH_GSTRING_LEN; + }; + + return CMD_RET_SUCCESS; + +err_free_strings: + kfree(strings); + + return CMD_RET_FAILURE; +} + static struct cmd_tbl cmd_net[] = { U_BOOT_CMD_MKENT(list, 1, 0, do_net_list, "", ""), + U_BOOT_CMD_MKENT(stats, 2, 0, do_net_stats, "", ""), }; static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) @@ -714,9 +765,10 @@ static int do_net(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) } U_BOOT_CMD( - net, 2, 1, do_net, + net, 3, 1, do_net, "NET sub-system", "list - list available devices\n" + "stats <device> - dump statistics for specified device\n" ); #if defined(CONFIG_CMD_NCSI) diff --git a/cmd/nvedit.c b/cmd/nvedit.c index 12eae06..9e4ee4b 100644 --- a/cmd/nvedit.c +++ b/cmd/nvedit.c @@ -43,28 +43,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_ENV_IS_IN_EEPROM) || \ - defined(CONFIG_ENV_IS_IN_FLASH) || \ - defined(CONFIG_ENV_IS_IN_MMC) || \ - defined(CONFIG_ENV_IS_IN_FAT) || \ - defined(CONFIG_ENV_IS_IN_EXT4) || \ - defined(CONFIG_ENV_IS_IN_NAND) || \ - defined(CONFIG_ENV_IS_IN_NVRAM) || \ - defined(CONFIG_ENV_IS_IN_ONENAND) || \ - defined(CONFIG_ENV_IS_IN_SPI_FLASH) || \ - defined(CONFIG_ENV_IS_IN_REMOTE) || \ - defined(CONFIG_ENV_IS_IN_UBI) - -#define ENV_IS_IN_DEVICE - -#endif - -#if !defined(ENV_IS_IN_DEVICE) && \ - !defined(CONFIG_ENV_IS_NOWHERE) -# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|\ -NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE -#endif - /* * Maximum expected input data size for import command */ @@ -596,7 +574,7 @@ static int do_env_edit(struct cmd_tbl *cmdtp, int flag, int argc, } #endif /* CONFIG_CMD_EDITENV */ -#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE) +#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT) static int do_env_save(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -1105,7 +1083,7 @@ static int do_env_info(struct cmd_tbl *cmdtp, int flag, int eval_flags = 0; int eval_results = 0; bool quiet = false; -#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE) +#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT) enum env_location loc; #endif @@ -1148,7 +1126,7 @@ static int do_env_info(struct cmd_tbl *cmdtp, int flag, /* evaluate whether environment can be persisted */ if (eval_flags & ENV_INFO_IS_PERSISTED) { -#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE) +#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT) loc = env_get_location(ENVOP_SAVE, gd->env_load_prio); if (ENVL_NOWHERE != loc && ENVL_UNKNOWN != loc) { if (!quiet) @@ -1229,7 +1207,7 @@ static struct cmd_tbl cmd_env_sub[] = { #if defined(CONFIG_CMD_RUN) U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""), #endif -#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE) +#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT) U_BOOT_CMD_MKENT(save, 1, 0, do_env_save, "", ""), #if defined(CONFIG_CMD_ERASEENV) U_BOOT_CMD_MKENT(erase, 1, 0, do_env_erase, "", ""), @@ -1320,7 +1298,7 @@ static char env_help_text[] = #if defined(CONFIG_CMD_RUN) "env run var [...] - run commands in an environment variable\n" #endif -#if defined(CONFIG_CMD_SAVEENV) && defined(ENV_IS_IN_DEVICE) +#if defined(CONFIG_CMD_SAVEENV) && !IS_ENABLED(CONFIG_ENV_IS_DEFAULT) "env save - save environment\n" #if defined(CONFIG_CMD_ERASEENV) "env erase - erase environment\n" diff --git a/cmd/riscv/sbi.c b/cmd/riscv/sbi.c index 6f2cad4..c4707fe 100644 --- a/cmd/riscv/sbi.c +++ b/cmd/riscv/sbi.c @@ -46,6 +46,9 @@ static struct sbi_ext extensions[] = { { SBI_EXT_HSM, "Hart State Management Extension" }, { SBI_EXT_SRST, "System Reset Extension" }, { SBI_EXT_PMU, "Performance Monitoring Unit Extension" }, + { SBI_EXT_DBCN, "Debug Console Extension" }, + { SBI_EXT_SUSP, "System Suspend Extension" }, + { SBI_EXT_CPPC, "Collaborative Processor Performance Control Extension" }, }; static int do_sbi(struct cmd_tbl *cmdtp, int flag, int argc, @@ -353,6 +353,11 @@ static int do_spi_flash_erase(int argc, char *const argv[]) if (ret != 1) return CMD_RET_USAGE; + if (size == 0) { + debug("ERROR: Invalid size 0\n"); + return CMD_RET_FAILURE; + } + /* Consistency checking */ if (offset + size > flash->size) { printf("ERROR: attempting %s past flash size (%#x)\n", diff --git a/cmd/tpm-common.c b/cmd/tpm-common.c index d0c63ca..a7dc23d 100644 --- a/cmd/tpm-common.c +++ b/cmd/tpm-common.c @@ -11,6 +11,7 @@ #include <asm/unaligned.h> #include <linux/string.h> #include <tpm-common.h> +#include <tpm_api.h> #include "tpm-user-utils.h" static struct udevice *tpm_dev; @@ -367,6 +368,21 @@ int do_tpm_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) return report_return_code(tpm_init(dev)); } +int do_tpm_autostart(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + struct udevice *dev; + int rc; + + if (argc != 1) + return CMD_RET_USAGE; + rc = get_tpm(&dev); + if (rc) + return rc; + + return report_return_code(tpm_auto_start(dev)); +} + int do_tpm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { struct cmd_tbl *tpm_commands, *cmd; diff --git a/cmd/tpm-user-utils.h b/cmd/tpm-user-utils.h index de4a934..dfa1135 100644 --- a/cmd/tpm-user-utils.h +++ b/cmd/tpm-user-utils.h @@ -20,6 +20,7 @@ int get_tpm(struct udevice **devp); int do_tpm_device(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_tpm_init(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_tpm_autostart(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_tpm_info(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_tpm_report_state(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/cmd/tpm-v1.c b/cmd/tpm-v1.c index 0efb079..3b95c95 100644 --- a/cmd/tpm-v1.c +++ b/cmd/tpm-v1.c @@ -655,6 +655,7 @@ TPM_COMMAND_NO_ARG(tpm_physical_disable) static struct cmd_tbl tpm1_commands[] = { U_BOOT_CMD_MKENT(device, 0, 1, do_tpm_device, "", ""), U_BOOT_CMD_MKENT(info, 0, 1, do_tpm_info, "", ""), + U_BOOT_CMD_MKENT(init, 0, 1, do_tpm_autostart, "", ""), U_BOOT_CMD_MKENT(init, 0, 1, do_tpm_init, "", ""), U_BOOT_CMD_MKENT(startup, 0, 1, do_tpm_startup, "", ""), @@ -733,9 +734,12 @@ U_BOOT_CMD(tpm, CONFIG_SYS_MAXARGS, 1, do_tpm, " device [num device]\n" " - Show all devices or set the specified device\n" " info - Show information about the TPM\n" +" autostart\n" +" - Initalize the tpm, perform a Startup(clear) and run a full selftest\n" +" sequence\n" " init\n" " - Put TPM into a state where it waits for 'startup' command.\n" -" startup mode\n" +" startup mode\n" " - Issue TPM_Starup command. <mode> is one of TPM_ST_CLEAR,\n" " TPM_ST_STATE, and TPM_ST_DEACTIVATED.\n" "Admin Testing Commands:\n" diff --git a/cmd/tpm-v2.c b/cmd/tpm-v2.c index d93b83a..7e479b9 100644 --- a/cmd/tpm-v2.c +++ b/cmd/tpm-v2.c @@ -370,6 +370,7 @@ static struct cmd_tbl tpm2_commands[] = { U_BOOT_CMD_MKENT(dam_reset, 0, 1, do_tpm_dam_reset, "", ""), U_BOOT_CMD_MKENT(dam_parameters, 0, 1, do_tpm_dam_parameters, "", ""), U_BOOT_CMD_MKENT(change_auth, 0, 1, do_tpm_change_auth, "", ""), + U_BOOT_CMD_MKENT(autostart, 0, 1, do_tpm_autostart, "", ""), U_BOOT_CMD_MKENT(pcr_setauthpolicy, 0, 1, do_tpm_pcr_setauthpolicy, "", ""), U_BOOT_CMD_MKENT(pcr_setauthvalue, 0, 1, @@ -392,8 +393,13 @@ U_BOOT_CMD(tpm2, CONFIG_SYS_MAXARGS, 1, do_tpm, "Issue a TPMv2.x command", " Show information about the TPM.\n" "state\n" " Show internal state from the TPM (if available)\n" +"autostart\n" +" Initalize the tpm, perform a Startup(clear) and run a full selftest\n" +" sequence\n" "init\n" " Initialize the software stack. Always the first command to issue.\n" +" 'tpm startup' is the only acceptable command after a 'tpm init' has been\n" +" issued\n" "startup <mode>\n" " Issue a TPM2_Startup command.\n" " <mode> is one of:\n" @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /** - * ufs.c - UFS specific U-boot commands + * ufs.c - UFS specific U-Boot commands * * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com * diff --git a/cmd/version.c b/cmd/version.c index 190ef6a..87e1fa4 100644 --- a/cmd/version.c +++ b/cmd/version.c @@ -19,6 +19,8 @@ U_BOOT_TIME " " U_BOOT_TZ ")" CONFIG_IDENT_STRING const char version_string[] = U_BOOT_VERSION_STRING; +const unsigned short version_num = U_BOOT_VERSION_NUM; +const unsigned char version_num_patch = U_BOOT_VERSION_NUM_PATCH; static int do_version(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) diff --git a/common/Kconfig b/common/Kconfig index bbabadb..42baca2 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -256,6 +256,7 @@ config SYS_CONSOLE_OVERWRITE_ROUTINE config SYS_CONSOLE_ENV_OVERWRITE bool "Update environment variables during console init" + depends on SYS_CONSOLE_IS_IN_ENV help The console environment variables (stdout, stdin, stderr) can be used to determine the correct console devices on start-up. This diff --git a/common/cli_hush.c b/common/cli_hush.c index 171069f..cee8724 100644 --- a/common/cli_hush.c +++ b/common/cli_hush.c @@ -324,7 +324,7 @@ typedef struct { /* I can almost use ordinary FILE *. Is open_memstream() universally * available? Where is it documented? */ struct in_str { - const char *p; + const unsigned char *p; #ifndef __U_BOOT__ char peek_buf[2]; #endif diff --git a/common/fdt_support.c b/common/fdt_support.c index 2053fe3..5e49078 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -13,6 +13,7 @@ #include <mapmem.h> #include <net.h> #include <stdio_dev.h> +#include <dm/ofnode.h> #include <linux/ctype.h> #include <linux/types.h> #include <asm/global_data.h> @@ -1050,6 +1051,79 @@ void fdt_fixup_mtdparts(void *blob, const struct node_info *node_info, } #endif +int fdt_copy_fixed_partitions(void *blob) +{ + ofnode node, subnode; + int off, suboff, res; + char path[256]; + int address_cells, size_cells; + u8 i, j, child_count; + + node = ofnode_by_compatible(ofnode_null(), "fixed-partitions"); + while (ofnode_valid(node)) { + /* copy the U-Boot fixed partition */ + address_cells = ofnode_read_simple_addr_cells(node); + size_cells = ofnode_read_simple_size_cells(node); + + res = ofnode_get_path(ofnode_get_parent(node), path, sizeof(path)); + if (res) + return res; + + off = fdt_path_offset(blob, path); + if (off < 0) + return -ENODEV; + + off = fdt_find_or_add_subnode(blob, off, "partitions"); + res = fdt_setprop_string(blob, off, "compatible", "fixed-partitions"); + if (res) + return res; + + res = fdt_setprop_u32(blob, off, "#address-cells", address_cells); + if (res) + return res; + + res = fdt_setprop_u32(blob, off, "#size-cells", size_cells); + if (res) + return res; + + /* + * parse partition in reverse order as fdt_find_or_add_subnode() only + * insert the new node after the parent's properties + */ + child_count = ofnode_get_child_count(node); + for (i = child_count; i > 0 ; i--) { + subnode = ofnode_first_subnode(node); + if (!ofnode_valid(subnode)) + break; + + for (j = 0; (j < i - 1); j++) + subnode = ofnode_next_subnode(subnode); + + if (!ofnode_valid(subnode)) + break; + + const u32 *reg; + int len; + + suboff = fdt_find_or_add_subnode(blob, off, ofnode_get_name(subnode)); + res = fdt_setprop_string(blob, suboff, "label", + ofnode_read_string(subnode, "label")); + if (res) + return res; + + reg = ofnode_get_property(subnode, "reg", &len); + res = fdt_setprop(blob, suboff, "reg", reg, len); + if (res) + return res; + } + + /* go to next fixed-partitions node */ + node = ofnode_by_compatible(node, "fixed-partitions"); + } + + return 0; +} + void fdt_del_node_and_alias(void *blob, const char *alias) { int off = fdt_path_offset(blob, alias); @@ -1065,7 +1139,6 @@ void fdt_del_node_and_alias(void *blob, const char *alias) /* Max address size we deal with */ #define OF_MAX_ADDR_CELLS 4 -#define OF_BAD_ADDR FDT_ADDR_T_NONE #define OF_CHECK_COUNTS(na, ns) ((na) > 0 && (na) <= OF_MAX_ADDR_CELLS && \ (ns) > 0) diff --git a/common/memsize.c b/common/memsize.c index 66d5be6..d646df8 100644 --- a/common/memsize.c +++ b/common/memsize.c @@ -7,9 +7,18 @@ #include <common.h> #include <init.h> #include <asm/global_data.h> +#include <cpu_func.h> +#include <stdint.h> DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SYS_CACHELINE_SIZE +# define MEMSIZE_CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE +#else +/* Just use the greatest cache flush alignment requirement I'm aware of */ +# define MEMSIZE_CACHELINE_SIZE 128 +#endif + #ifdef __PPC__ /* * At least on G2 PowerPC cores, sequential accesses to non-existent @@ -20,6 +29,15 @@ DECLARE_GLOBAL_DATA_PTR; # define sync() /* nothing */ #endif +static void dcache_flush_invalidate(volatile long *p) +{ + uintptr_t start, stop; + start = ALIGN_DOWN((uintptr_t)p, MEMSIZE_CACHELINE_SIZE); + stop = start + MEMSIZE_CACHELINE_SIZE; + flush_dcache_range(start, stop); + invalidate_dcache_range(start, stop); +} + /* * Check memory range for valid RAM. A simple memory test determines * the actually available RAM size between addresses `base' and @@ -34,6 +52,7 @@ long get_ram_size(long *base, long maxsize) long val; long size; int i = 0; + int dcache_en = dcache_status(); for (cnt = (maxsize / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) { addr = base + cnt; /* pointer arith! */ @@ -41,6 +60,8 @@ long get_ram_size(long *base, long maxsize) save[i++] = *addr; sync(); *addr = ~cnt; + if (dcache_en) + dcache_flush_invalidate(addr); } addr = base; @@ -50,6 +71,9 @@ long get_ram_size(long *base, long maxsize) *addr = 0; sync(); + if (dcache_en) + dcache_flush_invalidate(addr); + if ((val = *addr) != 0) { /* Restore the original data before leaving the function. */ sync(); diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 2c042ad..bee231b 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -1263,6 +1263,33 @@ config SPL_SATA_RAW_U_BOOT_SECTOR Sector on the SATA disk to load U-Boot from, when the SATA disk is being used in raw mode. Units: SATA disk sectors (1 sector = 512 bytes). +config SPL_NVME + bool "NVM Express device support" + depends on BLK + select HAVE_BLOCK_DEVICE + select FS_LOADER + select SPL_BLK_FS + help + This option enables support for NVM Express devices. + It supports basic functions of NVMe (read/write). + +config SPL_NVME_PCI + bool "NVM Express PCI device support for SPL" + depends on SPL_PCI && SPL_NVME + help + This option enables support for NVM Express PCI devices. + This allows use of NVMe devices for loading u-boot. + +config SPL_NVME_BOOT_DEVICE + hex "NVMe boot device number" + depends on SPL_NVME + default 0x0 + +config SYS_NVME_BOOT_PARTITION + hex "NVMe boot partition number" + depends on SPL_NVME + default 0x1 + config SPL_SERIAL bool "Support serial" select SPL_PRINTF @@ -1345,96 +1372,6 @@ config SPL_THERMAL automatic power-off when the temperature gets too high or low. Other devices may be discrete but connected on a suitable bus. -config SPL_USB_HOST - bool "Support USB host drivers" - help - Enable access to USB (Universal Serial Bus) host devices so that - SPL can load U-Boot from a connected USB peripheral, such as a USB - flash stick. While USB takes a little longer to start up than most - buses, it is very flexible since many different types of storage - device can be attached. This option enables the drivers in - drivers/usb/host as part of an SPL build. - -config SPL_USB_STORAGE - bool "Support loading from USB" - depends on SPL_USB_HOST - help - Enable support for USB devices in SPL. This allows use of USB - devices such as hard drives and flash drivers for loading U-Boot. - The actual drivers are enabled separately using the normal U-Boot - config options. This enables loading from USB using a configured - device. - -config SYS_USB_FAT_BOOT_PARTITION - int "Partition on USB to use to load U-Boot from" - depends on SPL_USB_STORAGE - default 1 - help - Partition on the USB storage device to load U-Boot from - -config SPL_USB_GADGET - bool "Suppport USB Gadget drivers" - help - Enable USB Gadget API which allows to enable USB device functions - in SPL. - -if SPL_USB_GADGET - -config SPL_USB_ETHER - bool "Support USB Ethernet drivers" - depends on SPL_NET - help - Enable access to the USB network subsystem and associated - drivers in SPL. This permits SPL to load U-Boot over a - USB-connected Ethernet link (such as a USB Ethernet dongle) rather - than from an onboard peripheral. Environment support is required - since the network stack uses a number of environment variables. - See also SPL_NET and SPL_ETH. - -config SPL_DFU - bool "Support DFU (Device Firmware Upgrade)" - select SPL_HASH - select SPL_DFU_NO_RESET - depends on SPL_RAM_SUPPORT - help - This feature enables the DFU (Device Firmware Upgrade) in SPL with - RAM memory device support. The ROM code will load and execute - the SPL built with dfu. The user can load binaries (u-boot/kernel) to - selected device partition from host-pc using dfu-utils. - This feature is useful to flash the binaries to factory or bare-metal - boards using USB interface. - -choice - bool "DFU device selection" - depends on SPL_DFU - -config SPL_DFU_RAM - bool "RAM device" - depends on SPL_DFU && SPL_RAM_SUPPORT - help - select RAM/DDR memory device for loading binary images - (u-boot/kernel) to the selected device partition using - DFU and execute the u-boot/kernel from RAM. - -endchoice - -config SPL_USB_SDP_SUPPORT - bool "Support SDP (Serial Download Protocol)" - depends on SPL_SERIAL - help - Enable Serial Download Protocol (SDP) device support in SPL. This - allows to download images into memory and execute (jump to) them - using the same protocol as implemented by the i.MX family's boot ROM. - -config SPL_SDP_USB_DEV - int "SDP USB controller index" - default 0 - depends on SPL_USB_SDP_SUPPORT - help - Some boards have USB controller other than 0. Define this option - so it can be used in compiled environment. -endif - config SPL_WATCHDOG bool "Support watchdog drivers" imply SPL_WDT if !HW_WATCHDOG @@ -1524,8 +1461,10 @@ config SPL_OPENSBI_SCRATCH_OPTIONS default 0x1 depends on SPL_OPENSBI help - Options passed to fw_dynamic, for example SBI_SCRATCH_NO_BOOT_PRINTS or - SBI_SCRATCH_DEBUG_PRINTS. + This bitmap of options is passed from U-Boot SPL to OpenSBI. + As of OpenSBI 1.3 the following bits are defined: + - SBI_SCRATCH_NO_BOOT_PRINTS = 0x1 (Disable prints during boot) + - SBI_SCRATCH_DEBUG_PRINTS = 0x2 (Enable runtime debug prints) config SPL_TARGET string "Addtional build targets for 'make'" diff --git a/common/spl/Kconfig.tpl b/common/spl/Kconfig.tpl index 1874f9d..3d6cf1e 100644 --- a/common/spl/Kconfig.tpl +++ b/common/spl/Kconfig.tpl @@ -43,6 +43,7 @@ config TPL_FRAMEWORK config TPL_BANNER_PRINT bool "Enable output of the TPL banner 'U-Boot TPL ...'" + depends on DEBUG_UART && TPL_SERIAL default y help If this option is enabled, TPL will print the banner with version diff --git a/common/spl/Makefile b/common/spl/Makefile index 13db3df..bad2bbf 100644 --- a/common/spl/Makefile +++ b/common/spl/Makefile @@ -10,6 +10,7 @@ ifdef CONFIG_SPL_BUILD obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o obj-$(CONFIG_$(SPL_TPL_)BOOTROM_SUPPORT) += spl_bootrom.o obj-$(CONFIG_$(SPL_TPL_)LOAD_FIT) += spl_fit.o +obj-$(CONFIG_$(SPL_TPL_)BLK_FS) += spl_blk_fs.o obj-$(CONFIG_$(SPL_TPL_)LEGACY_IMAGE_FORMAT) += spl_legacy.o obj-$(CONFIG_$(SPL_TPL_)NOR_SUPPORT) += spl_nor.o obj-$(CONFIG_$(SPL_TPL_)XIP_SUPPORT) += spl_xip.o @@ -28,6 +29,7 @@ obj-$(CONFIG_$(SPL_TPL_)USB_STORAGE) += spl_usb.o obj-$(CONFIG_$(SPL_TPL_)FS_FAT) += spl_fat.o obj-$(CONFIG_$(SPL_TPL_)FS_EXT4) += spl_ext.o obj-$(CONFIG_$(SPL_TPL_)SATA) += spl_sata.o +obj-$(CONFIG_$(SPL_TPL_)NVME) += spl_nvme.o obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += spl_semihosting.o obj-$(CONFIG_$(SPL_TPL_)DFU) += spl_dfu.o obj-$(CONFIG_$(SPL_TPL_)SPI_LOAD) += spl_spi.o diff --git a/common/spl/spl.c b/common/spl/spl.c index 72078a8..d74acec 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -321,7 +321,7 @@ static int spl_load_fit_image(struct spl_image_info *spl_image, spl_image->fdt_addr = (void *)dt_data; if (spl_image->os == IH_OS_U_BOOT) { - /* HACK: U-boot expects FDT at a specific address */ + /* HACK: U-Boot expects FDT at a specific address */ fdt_hack = spl_image->load_addr + spl_image->size; fdt_hack = (fdt_hack + 3) & ~3; debug("Relocating FDT to %p\n", spl_image->fdt_addr); @@ -331,7 +331,7 @@ static int spl_load_fit_image(struct spl_image_info *spl_image, conf_noffset = fit_conf_get_node((const void *)header, fit_uname_config); - if (conf_noffset <= 0) + if (conf_noffset < 0) return 0; for (idx = 0; diff --git a/common/spl/spl_blk_fs.c b/common/spl/spl_blk_fs.c new file mode 100644 index 0000000..d97adc4 --- /dev/null +++ b/common/spl/spl_blk_fs.c @@ -0,0 +1,134 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 + * Ventana Micro Systems Inc. + * + */ + +#include <common.h> +#include <spl.h> +#include <image.h> +#include <fs.h> + +struct blk_dev { + const char *ifname; + char dev_part_str[8]; +}; + +static ulong spl_fit_read(struct spl_load_info *load, ulong file_offset, + ulong size, void *buf) +{ + loff_t actlen; + int ret; + struct blk_dev *dev = (struct blk_dev *)load->priv; + + ret = fs_set_blk_dev(dev->ifname, dev->dev_part_str, FS_TYPE_ANY); + if (ret) { + printf("spl: unable to set blk_dev %s %s. Err - %d\n", + dev->ifname, dev->dev_part_str, ret); + return ret; + } + + ret = fs_read(load->filename, (ulong)buf, file_offset, size, &actlen); + if (ret < 0) { + printf("spl: error reading image %s. Err - %d\n", + load->filename, ret); + return ret; + } + + return actlen; +} + +int spl_blk_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev, + enum uclass_id uclass_id, int devnum, int partnum) +{ + const char *filename = CONFIG_SPL_PAYLOAD; + struct disk_partition part_info = {}; + struct legacy_img_hdr *header; + struct blk_desc *blk_desc; + loff_t actlen, filesize; + struct blk_dev dev; + int ret; + + blk_desc = blk_get_devnum_by_uclass_id(uclass_id, devnum); + if (!blk_desc) { + printf("blk desc for %d %d not found\n", uclass_id, devnum); + goto out; + } + + blk_show_device(uclass_id, devnum); + header = spl_get_load_buffer(-sizeof(*header), sizeof(*header)); + ret = part_get_info(blk_desc, 1, &part_info); + if (ret) { + printf("spl: no partition table found. Err - %d\n", ret); + goto out; + } + + dev.ifname = blk_get_uclass_name(uclass_id); + snprintf(dev.dev_part_str, sizeof(dev.dev_part_str) - 1, "%d:%d", + devnum, partnum); + ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY); + if (ret) { + printf("spl: unable to set blk_dev %s %s. Err - %d\n", + dev.ifname, dev.dev_part_str, ret); + goto out; + } + + ret = fs_read(filename, (ulong)header, 0, + sizeof(struct legacy_img_hdr), &actlen); + if (ret) { + printf("spl: unable to read file %s. Err - %d\n", filename, + ret); + goto out; + } + + if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && + image_get_magic(header) == FDT_MAGIC) { + struct spl_load_info load; + + debug("Found FIT\n"); + load.read = spl_fit_read; + load.bl_len = 1; + load.filename = (void *)filename; + load.priv = &dev; + + return spl_load_simple_fit(spl_image, &load, 0, header); + } + + ret = spl_parse_image_header(spl_image, bootdev, header); + if (ret) { + printf("spl: unable to parse image header. Err - %d\n", + ret); + goto out; + } + + ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY); + if (ret) { + printf("spl: unable to set blk_dev %s %s. Err - %d\n", + dev.ifname, dev.dev_part_str, ret); + goto out; + } + + ret = fs_size(filename, &filesize); + if (ret) { + printf("spl: unable to get file size: %s. Err - %d\n", + filename, ret); + goto out; + } + + ret = fs_set_blk_dev(dev.ifname, dev.dev_part_str, FS_TYPE_ANY); + if (ret) { + printf("spl: unable to set blk_dev %s %s. Err - %d\n", + dev.ifname, dev.dev_part_str, ret); + goto out; + } + + ret = fs_read(filename, (ulong)spl_image->load_addr, 0, filesize, + &actlen); + if (ret) + printf("spl: unable to read file %s. Err - %d\n", + filename, ret); +out: + return ret; +} diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c index a072216..a665091 100644 --- a/common/spl/spl_mmc.c +++ b/common/spl/spl_mmc.c @@ -250,7 +250,7 @@ static int mmc_load_image_raw_os(struct spl_image_info *spl_image, return ret; if (spl_image->os != IH_OS_LINUX && spl_image->os != IH_OS_TEE) { - puts("Expected image is not found. Trying to start U-boot\n"); + puts("Expected image is not found. Trying to start U-Boot\n"); return -ENOENT; } diff --git a/common/spl/spl_nor.c b/common/spl/spl_nor.c index 1ef5e41..5b65b96 100644 --- a/common/spl/spl_nor.c +++ b/common/spl/spl_nor.c @@ -121,6 +121,6 @@ static int spl_nor_load_image(struct spl_image_info *spl_image, &hdr); } - return 0; + return -EINVAL; } SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image); diff --git a/common/spl/spl_nvme.c b/common/spl/spl_nvme.c new file mode 100644 index 0000000..2af63f1 --- /dev/null +++ b/common/spl/spl_nvme.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023 + * Ventana Micro Systems Inc. + * + */ + +#include <common.h> +#include <spl.h> +#include <init.h> +#include <nvme.h> + +static int spl_nvme_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + int ret; + + ret = pci_init(); + if (ret < 0) + return ret; + + ret = nvme_scan_namespace(); + if (ret < 0) + return ret; + + ret = spl_blk_load_image(spl_image, bootdev, UCLASS_NVME, + CONFIG_SPL_NVME_BOOT_DEVICE, + CONFIG_SYS_NVME_BOOT_PARTITION); + return ret; +} + +SPL_LOAD_IMAGE_METHOD("NVME", 0, BOOT_DEVICE_NVME, spl_nvme_load_image); diff --git a/common/stdio.c b/common/stdio.c index cbedfdd..894cbd3 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -386,11 +386,3 @@ int stdio_add_devices(void) return 0; } - -int stdio_init(void) -{ - stdio_init_tables(); - stdio_add_devices(); - - return 0; -} diff --git a/configs/ad401_defconfig b/configs/ad401_defconfig new file mode 100644 index 0000000..529e553 --- /dev/null +++ b/configs/ad401_defconfig @@ -0,0 +1,54 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_TEXT_BASE=0x00000000 +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00200000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="meson-a1-ad401" +CONFIG_SYS_PROMPT="ad401 # " +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_MESON_A1=y +CONFIG_DEBUG_UART_BASE=0xfe001c00 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_SYS_LOAD_ADDR=0x0 +CONFIG_DEBUG_UART=y +CONFIG_ANDROID_BOOT_IMAGE=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_BOOTCOMMAND="run storeboot" +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_ADC=y +CONFIG_SARADC_MESON=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_LED=y +CONFIG_MISC=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_A1=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_PWM=y +CONFIG_PWM_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_WDT=y diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index 090b902..6ef3c78 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -18,7 +18,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;" CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y @@ -57,10 +56,10 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +# CONFIG_TI_SYSC is not set CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SPEED=1000 CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MMC_OMAP_HS_ADMA=y @@ -79,6 +78,8 @@ CONFIG_PHY_SMSC=y CONFIG_DM_MDIO=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_DM_PMIC=y +# CONFIG_PMIC_CHILDREN is not set CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -94,5 +95,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_ETHER=y -CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" CONFIG_WDT=y diff --git a/configs/am335x_boneblack_vboot_defconfig b/configs/am335x_boneblack_vboot_defconfig index c42d2a0..e581acc 100644 --- a/configs/am335x_boneblack_vboot_defconfig +++ b/configs/am335x_boneblack_vboot_defconfig @@ -34,8 +34,6 @@ CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_ETHER=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_SPL=y @@ -89,8 +87,10 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 CONFIG_USB_ETHER=y +CONFIG_SPL_USB_ETHER=y CONFIG_LZO=y diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig index ffeeb85..a179f1e 100644 --- a/configs/am335x_evm_defconfig +++ b/configs/am335x_evm_defconfig @@ -39,8 +39,6 @@ CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_ETHER=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_EXTENSION=y @@ -115,10 +113,12 @@ CONFIG_USB_MUSB_HOST=y CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 CONFIG_USB_ETHER=y +CONFIG_SPL_USB_ETHER=y CONFIG_WDT=y # CONFIG_SPL_WDT is not set CONFIG_DYNAMIC_CRC_TABLE=y diff --git a/configs/am335x_guardian_defconfig b/configs/am335x_guardian_defconfig index ad0fa46..a485cc6 100644 --- a/configs/am335x_guardian_defconfig +++ b/configs/am335x_guardian_defconfig @@ -45,8 +45,6 @@ CONFIG_SPL_NAND_BASE=y CONFIG_SPL_NET=y CONFIG_SPL_NET_VCI_STRING="Guardian U-Boot SPL" CONFIG_SPL_POWER=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_ETHER=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_BOOTM_LEN=0x1000000 CONFIG_CMD_ASKENV=y @@ -127,10 +125,12 @@ CONFIG_USB_MUSB_GADGET=y CONFIG_USB_MUSB_TI=y # CONFIG_USB_STORAGE is not set CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 CONFIG_USB_ETHER=y +CONFIG_SPL_USB_ETHER=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_BMP_16BPP=y CONFIG_SPL_WDT=y diff --git a/configs/am43xx_evm_defconfig b/configs/am43xx_evm_defconfig index 34525d6..3238620 100644 --- a/configs/am43xx_evm_defconfig +++ b/configs/am43xx_evm_defconfig @@ -34,9 +34,6 @@ CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_ETHER=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00100000 @@ -97,6 +94,7 @@ CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_OMAP=y @@ -106,8 +104,10 @@ CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_ETHER=y +CONFIG_SPL_USB_ETHER=y diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig index 64ecd92..406c0fc 100644 --- a/configs/am43xx_evm_usbhost_boot_defconfig +++ b/configs/am43xx_evm_usbhost_boot_defconfig @@ -30,9 +30,6 @@ CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1700 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x1500 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_STORAGE=y -CONFIG_SPL_USB_GADGET=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_SPL=y CONFIG_CMD_SPL_NAND_OFS=0x00100000 @@ -98,6 +95,7 @@ CONFIG_TI_QSPI=y CONFIG_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_OMAP=y @@ -106,7 +104,9 @@ CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y +CONFIG_SPL_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00 diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig index 6715a25..466b12e 100644 --- a/configs/am43xx_hs_evm_defconfig +++ b/configs/am43xx_hs_evm_defconfig @@ -34,10 +34,6 @@ CONFIG_SPL_NAND_ECC=y CONFIG_SPL_NAND_BASE=y CONFIG_SPL_NET=y CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL" -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_STORAGE=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_ETHER=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set @@ -95,6 +91,7 @@ CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_XHCI_OMAP=y @@ -103,9 +100,12 @@ CONFIG_USB_DWC3_OMAP=y CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y +CONFIG_SPL_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0403 CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_ETHER=y +CONFIG_SPL_USB_ETHER=y diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig index fe71738..39fdc05 100644 --- a/configs/am57xx_hs_evm_usb_defconfig +++ b/configs/am57xx_hs_evm_usb_defconfig @@ -44,8 +44,6 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_BOOTM_LEN=0x4000000 @@ -120,7 +118,9 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 +CONFIG_SPL_DFU=y CONFIG_LIBAVB=y diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index 41fa6f3..76ec5ed 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -35,6 +35,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_MMC=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/am64x_evm_a53_defconfig b/configs/am64x_evm_a53_defconfig index 4589624..6485ed1 100644 --- a/configs/am64x_evm_a53_defconfig +++ b/configs/am64x_evm_a53_defconfig @@ -1,6 +1,7 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x8000 CONFIG_SPL_GPIO=y @@ -59,10 +60,6 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_STORAGE=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_BOOTM_LEN=0x800000 @@ -153,16 +150,20 @@ CONFIG_SYSRESET_TI_SCI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y CONFIG_SPL_USB_CDNS3_GADGET=y CONFIG_SPL_USB_CDNS3_HOST=y +CONFIG_SPL_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_MASS_STORAGE=y +CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig index 023ee63..45d3265 100644 --- a/configs/am64x_evm_r5_defconfig +++ b/configs/am64x_evm_r5_defconfig @@ -1,5 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_K3=y +CONFIG_TI_SECURE_DEVICE=y CONFIG_SYS_MALLOC_LEN=0x2000000 CONFIG_SYS_MALLOC_F_LEN=0x80000 CONFIG_SPL_GPIO=y @@ -65,10 +66,6 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_STORAGE=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 @@ -159,6 +156,7 @@ CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y @@ -166,9 +164,12 @@ CONFIG_USB_CDNS3_HOST=y CONFIG_SPL_USB_CDNS3_GADGET=y CONFIG_SPL_USB_CDNS3_HOST=y CONFIG_USB_STORAGE=y +CONFIG_SPL_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6165 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig index f294a45..c3a2f09 100644 --- a/configs/am65x_evm_a53_defconfig +++ b/configs/am65x_evm_a53_defconfig @@ -61,10 +61,6 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_STORAGE=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y @@ -167,15 +163,19 @@ CONFIG_SYSRESET_TI_SCI=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_KEYBOARD=y +CONFIG_SPL_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y CONFIG_PHANDLE_CHECK_SEQ=y diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig index 8b01925..88f68aa 100644 --- a/configs/am65x_evm_r5_usbdfu_defconfig +++ b/configs/am65x_evm_r5_usbdfu_defconfig @@ -51,8 +51,6 @@ CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 @@ -130,8 +128,10 @@ CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig index 01e46e6..8da49c7 100644 --- a/configs/am65x_evm_r5_usbmsc_defconfig +++ b/configs/am65x_evm_r5_usbmsc_defconfig @@ -50,9 +50,6 @@ CONFIG_SPL_POWER_DOMAIN=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_REMOTEPROC=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_STORAGE=y -CONFIG_SPL_USB_GADGET=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 @@ -120,12 +117,15 @@ CONFIG_OMAP_TIMER=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y CONFIG_SPL_DM_USB_GADGET=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_STORAGE=y +CONFIG_SPL_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6162 diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index d7342c4..dcee517 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -43,9 +43,6 @@ CONFIG_MISC_INIT_R=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=48 CONFIG_SYS_CBSIZE=1024 CONFIG_SYS_PBSIZE=1055 @@ -113,12 +110,15 @@ CONFIG_DM_SCSI=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig index db68b21..d1eb2ab 100644 --- a/configs/aristainetos2c_defconfig +++ b/configs/aristainetos2c_defconfig @@ -59,7 +59,6 @@ CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/aristainetos2ccslb_defconfig b/configs/aristainetos2ccslb_defconfig index d369505..638976d 100644 --- a/configs/aristainetos2ccslb_defconfig +++ b/configs/aristainetos2ccslb_defconfig @@ -59,7 +59,6 @@ CONFIG_OF_CONTROL=y CONFIG_DTB_RESELECT=y CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index e25cde9..9d2a201 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -42,9 +42,6 @@ CONFIG_MISC_INIT_R=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_I2C=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=48 CONFIG_SYS_CBSIZE=1024 CONFIG_SYS_PBSIZE=1056 @@ -110,12 +107,15 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_KEYBOARD=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Toradex" CONFIG_USB_GADGET_VENDOR_NUM=0x1b67 CONFIG_USB_GADGET_PRODUCT_NUM=0x4000 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/corstone1000_defconfig b/configs/corstone1000_defconfig index 2d39104..a8a79fd 100644 --- a/configs/corstone1000_defconfig +++ b/configs/corstone1000_defconfig @@ -15,19 +15,25 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyAMA0 loglevel=9 ip=dhcp earlyprintk" -CONFIG_BOOTCOMMAND="run retrieve_kernel_load_addr; echo Loading kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" +CONFIG_BOOTCOMMAND="echo Loading kernel from $kernel_addr to memory ... ; loadm $kernel_addr $kernel_addr_r 0xc00000; usb start; usb reset; run distro_bootcmd; bootefi $kernel_addr_r $fdtcontroladdr;" CONFIG_CONSOLE_RECORD=y CONFIG_LOGLEVEL=7 # CONFIG_DISPLAY_CPUINFO is not set # CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_BOARD_LATE_INIT=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=512 # CONFIG_CMD_CONSOLE is not set +CONFIG_CMD_FWU_METADATA=y CONFIG_CMD_BOOTZ=y CONFIG_SYS_BOOTM_LEN=0x800000 # CONFIG_CMD_XIMG is not set +CONFIG_CMD_NVMXIP=y +CONFIG_CMD_GPT=y +# CONFIG_RANDOM_UUID is not set CONFIG_CMD_LOADM=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set # CONFIG_CMD_NFS is not set @@ -39,6 +45,8 @@ CONFIG_OF_CONTROL=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y +CONFIG_FWU_MDATA=y +CONFIG_FWU_MDATA_GPT_BLK=y CONFIG_MISC=y # CONFIG_MMC is not set CONFIG_NVMXIP_QSPI=y @@ -50,6 +58,10 @@ CONFIG_RAM=y CONFIG_DM_RTC=y CONFIG_RTC_EMULATION=y CONFIG_DM_SERIAL=y +CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_USB_ISP1760=y +CONFIG_EFI_CAPSULE_ON_DISK=y +CONFIG_EFI_IGNORE_OSINDICATIONS=y +CONFIG_FWU_MULTI_BANK_UPDATE=y CONFIG_ERRNO_STR=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index a45d3cb..c1094b4 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -42,9 +42,6 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400 -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 @@ -112,15 +109,18 @@ CONFIG_MXC_SPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="dh" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x17ffffc0 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_WATCHDOG_TIMEOUT_MSECS=60000 CONFIG_IMX_WATCHDOG=y CONFIG_BZIP2=y diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 4b3a4bf..a5396f7 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -48,9 +48,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x3F00 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x10 CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000 -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_CBSIZE=2048 @@ -129,12 +126,15 @@ CONFIG_MXC_SPI=y CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Liebherr" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_WATCHDOG_TIMEOUT_MSECS=15000 CONFIG_IMX_WATCHDOG=y CONFIG_PANIC_HANG=y diff --git a/configs/dra7xx_evm_defconfig b/configs/dra7xx_evm_defconfig index 371c888..14dff63 100644 --- a/configs/dra7xx_evm_defconfig +++ b/configs/dra7xx_evm_defconfig @@ -47,8 +47,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x200 CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_SPL=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -148,6 +146,8 @@ CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 +CONFIG_SPL_DFU=y diff --git a/configs/dra7xx_hs_evm_defconfig b/configs/dra7xx_hs_evm_defconfig index 3165b9b..0d6d9ef 100644 --- a/configs/dra7xx_hs_evm_defconfig +++ b/configs/dra7xx_hs_evm_defconfig @@ -44,8 +44,6 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 # CONFIG_CMD_FLASH is not set @@ -141,6 +139,8 @@ CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_DWC3_PHY_OMAP=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 +CONFIG_SPL_DFU=y diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig index 6ed98cf..506a65a 100644 --- a/configs/dra7xx_hs_evm_usb_defconfig +++ b/configs/dra7xx_hs_evm_usb_defconfig @@ -43,8 +43,6 @@ CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 @@ -128,6 +126,8 @@ CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_SPL_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0xd022 +CONFIG_SPL_DFU=y diff --git a/configs/ge_b1x5v2_defconfig b/configs/ge_b1x5v2_defconfig index 07e357e..b3b69a6 100644 --- a/configs/ge_b1x5v2_defconfig +++ b/configs/ge_b1x5v2_defconfig @@ -14,6 +14,7 @@ CONFIG_ENV_SECT_SIZE=0x10000 # CONFIG_GE_RTC is not set CONFIG_MX6QDL=y CONFIG_TARGET_GE_B1X5V2=y +CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="imx6dl-b1x5v2" CONFIG_SPL_TEXT_BASE=0x00908000 CONFIG_SPL_SERIAL=y @@ -41,9 +42,6 @@ CONFIG_MISC_INIT_R=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400 -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 @@ -121,15 +119,18 @@ CONFIG_POWEROFF_GPIO=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_KEYBOARD=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Congatec" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_IPUV3=y CONFIG_IMX_VIDEO_SKIP=y diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index 15dc16b..8626918 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -52,6 +52,9 @@ CONFIG_SPI_FLASH_MACRONIX=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_BITBANGMII=y CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_SMSC=y +CONFIG_PHY_ETHERNET_ID=y +CONFIG_DM_ETH_PHY=y CONFIG_SH_ETHER=y CONFIG_PINCTRL=y CONFIG_DM_REGULATOR=y diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig index ccccb95..a811653 100644 --- a/configs/imx6q_bosch_acc_defconfig +++ b/configs/imx6q_bosch_acc_defconfig @@ -77,7 +77,6 @@ CONFIG_SPL_OF_CONTROL=y CONFIG_MULTI_DTB_FIT=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clocks clock-names interrupt-parent" CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_SYS_MMC_ENV_PART=1 diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 2bc4679..2814e2c 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -42,9 +42,6 @@ CONFIG_SPL_FALCON_BOOT_MMCSD=y CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR=0x1000 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR=0x800 CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS=0x800 -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=543 @@ -116,9 +113,12 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y # CONFIG_SPL_DM_USB is not set +CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/imx6ulz_smm_m2_defconfig b/configs/imx6ulz_smm_m2_defconfig index b322083..f3da19d 100644 --- a/configs/imx6ulz_smm_m2_defconfig +++ b/configs/imx6ulz_smm_m2_defconfig @@ -27,9 +27,6 @@ CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_MTD_SUPPORT=y CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y @@ -71,9 +68,12 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="BSH" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x877fffc0 +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig index e18fcf9..c43aed4 100644 --- a/configs/imx7_cm_defconfig +++ b/configs/imx7_cm_defconfig @@ -30,9 +30,6 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_I2C=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set @@ -102,13 +99,16 @@ CONFIG_FSL_QSPI=y # CONFIG_FSL_QSPI_AHB_FULL_MAP is not set CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_SYS_WHITE_ON_BLACK=y CONFIG_SPLASH_SCREEN=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index 00f7c54..13bd195 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -51,9 +51,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 @@ -133,14 +130,17 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y # CONFIG_USB_STORAGE is not set CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Menlo" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index 4a96bd2..bb02b9b 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -40,9 +40,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 @@ -134,13 +131,16 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index dacd473..ac9810f 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -39,9 +39,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 @@ -108,14 +105,17 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y # CONFIG_USB_STORAGE is not set CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/imx8mm_phg_defconfig b/configs/imx8mm_phg_defconfig index 4f988f5..9fdce5c 100644 --- a/configs/imx8mm_phg_defconfig +++ b/configs/imx8mm_phg_defconfig @@ -39,9 +39,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_CBSIZE=2048 @@ -106,14 +103,17 @@ CONFIG_SYSRESET_PSCI=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_DM_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y # CONFIG_USB_STORAGE is not set CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_IMX_WATCHDOG=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index e40900f..cc68a21 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -47,7 +47,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" @@ -64,8 +64,6 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y @@ -197,9 +195,11 @@ CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y CONFIG_SPL_USB_CDNS3_GADGET=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6164 +CONFIG_SPL_DFU=y CONFIG_UFS=y CONFIG_CADENCE_UFS=y CONFIG_TI_J721E_UFS=y diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index 94a6523..c4dd336 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -43,7 +43,7 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y @@ -61,8 +61,6 @@ CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 @@ -160,10 +158,12 @@ CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y CONFIG_SPL_USB_CDNS3_GADGET=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6164 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y CONFIG_FS_EXT4=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_LIB_RATIONAL=y diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig index eaf83e0..32ac47c 100644 --- a/configs/j721e_evm_a72_defconfig +++ b/configs/j721e_evm_a72_defconfig @@ -62,8 +62,6 @@ CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y @@ -201,9 +199,11 @@ CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y CONFIG_SPL_USB_CDNS3_GADGET=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6163 +CONFIG_SPL_DFU=y CONFIG_UFS=y CONFIG_CADENCE_UFS=y CONFIG_TI_J721E_UFS=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index ed14582..cf7bc87 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -66,8 +66,6 @@ CONFIG_SPL_REMOTEPROC=y CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 @@ -170,10 +168,12 @@ CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y CONFIG_SPL_USB_CDNS3_GADGET=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6163 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y CONFIG_FS_EXT4=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_LIB_RATIONAL=y diff --git a/configs/j721s2_evm_a72_defconfig b/configs/j721s2_evm_a72_defconfig index 594c8da..37c1fde 100644 --- a/configs/j721s2_evm_a72_defconfig +++ b/configs/j721s2_evm_a72_defconfig @@ -62,8 +62,6 @@ CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000 CONFIG_SPL_THERMAL=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_SYS_MAXARGS=64 CONFIG_CMD_ASKENV=y @@ -205,9 +203,11 @@ CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y CONFIG_SPL_USB_CDNS3_GADGET=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6168 +CONFIG_SPL_DFU=y CONFIG_UFS=y CONFIG_CADENCE_UFS=y CONFIG_TI_J721E_UFS=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 4ddbe8f..1e66ac2 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -68,8 +68,6 @@ CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 CONFIG_SPL_THERMAL=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=64 @@ -169,10 +167,12 @@ CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y CONFIG_SPL_USB_CDNS3_GADGET=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments" CONFIG_USB_GADGET_VENDOR_NUM=0x0451 CONFIG_USB_GADGET_PRODUCT_NUM=0x6168 CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y CONFIG_FS_EXT4=y CONFIG_FS_FAT_MAX_CLUSTSIZE=16384 CONFIG_PANIC_HANG=y diff --git a/configs/kontron-sl-mx6ul_defconfig b/configs/kontron-sl-mx6ul_defconfig index 0dbf7ea..d54e603 100644 --- a/configs/kontron-sl-mx6ul_defconfig +++ b/configs/kontron-sl-mx6ul_defconfig @@ -36,9 +36,6 @@ CONFIG_SPL_LEGACY_IMAGE_CRC_CHECK=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x11400 -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 @@ -100,11 +97,14 @@ CONFIG_FSL_QSPI=y CONFIG_MXC_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_FDT_FIXUP_PARTITIONS=y diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig index b846a83..973b2ea 100644 --- a/configs/librem5_defconfig +++ b/configs/librem5_defconfig @@ -50,8 +50,6 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 CONFIG_SPL_I2C=y CONFIG_SPL_POWER=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=1050 @@ -144,8 +142,10 @@ CONFIG_USB_XHCI_DWC3=y CONFIG_USB_DWC3=y CONFIG_USB_DWC3_GENERIC=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Purism" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_SDP_LOADADDR=0x40400000 CONFIG_USB_FUNCTION_ACM=y +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/ls1043ardb_SECURE_BOOT_defconfig b/configs/ls1043ardb_SECURE_BOOT_defconfig index 069a8dc..ea195d7 100644 --- a/configs/ls1043ardb_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_SECURE_BOOT_defconfig @@ -86,7 +86,9 @@ CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_defconfig b/configs/ls1043ardb_defconfig index e796c0a..ae8600f 100644 --- a/configs/ls1043ardb_defconfig +++ b/configs/ls1043ardb_defconfig @@ -89,7 +89,9 @@ CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x60940000 CONFIG_SYS_QE_FMAN_FW_IN_NOR=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index f5faa02..d9ff0fd 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -110,7 +110,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index b75550b..ad11818 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -117,7 +117,8 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 3e0d164..fe0dd04 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -110,7 +110,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index 04e66f1..aa5404c 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -115,7 +115,8 @@ CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 CONFIG_SYS_QE_FMAN_FW_IN_MMC=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig index cf4623e..480e928 100644 --- a/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_tfa_SECURE_BOOT_defconfig @@ -84,7 +84,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1043ardb_tfa_defconfig b/configs/ls1043ardb_tfa_defconfig index 15e2916..e259041 100644 --- a/configs/ls1043ardb_tfa_defconfig +++ b/configs/ls1043ardb_tfa_defconfig @@ -90,7 +90,9 @@ CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_NVME_PCI=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_SYS_QE_FW_ADDR=0x940000 -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_USB=y diff --git a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig index 8d6a137..d280cf8 100644 --- a/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046afrwy_tfa_SECURE_BOOT_defconfig @@ -30,6 +30,7 @@ CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=532 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -61,13 +62,16 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_VITESSE=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y CONFIG_SYS_FMAN_FW_ADDR=0x900000 CONFIG_DM_PCI_COMPAT=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046afrwy_tfa_defconfig b/configs/ls1046afrwy_tfa_defconfig index e5d2b55..207f411 100644 --- a/configs/ls1046afrwy_tfa_defconfig +++ b/configs/ls1046afrwy_tfa_defconfig @@ -34,6 +34,7 @@ CONFIG_MISC_INIT_R=y CONFIG_SYS_MAXARGS=64 CONFIG_SYS_PBSIZE=532 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 +CONFIG_CMD_DM=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y @@ -67,6 +68,7 @@ CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set CONFIG_PHYLIB=y CONFIG_PHY_VITESSE=y +CONFIG_DM_MDIO=y CONFIG_PHY_GIGE=y CONFIG_E1000=y CONFIG_FMAN_ENET=y @@ -76,7 +78,9 @@ CONFIG_DM_PCI_COMPAT=y CONFIG_PCIE_LAYERSCAPE_RC=y CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 7be98df..924ff78 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -111,7 +111,8 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig index 3cefae0..bb27884 100644 --- a/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_qspi_SECURE_BOOT_defconfig @@ -86,7 +86,9 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_defconfig b/configs/ls1046ardb_qspi_defconfig index 02979dd..0fb1a6c 100644 --- a/configs/ls1046ardb_qspi_defconfig +++ b/configs/ls1046ardb_qspi_defconfig @@ -90,7 +90,9 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index 8f7d05f..eb0184c 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -118,7 +118,8 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index 900e26b..2813c79 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -109,7 +109,9 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_SCSI_AHCI_PLAT=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index ded6be5..a621859 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -111,7 +111,8 @@ CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_DM_SERIAL=y +CONFIG_SPL_SYS_NS16550_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig index 3eaa985..fbcf294 100644 --- a/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_tfa_SECURE_BOOT_defconfig @@ -79,7 +79,9 @@ CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/ls1046ardb_tfa_defconfig b/configs/ls1046ardb_tfa_defconfig index 7e8d86d..24a5423 100644 --- a/configs/ls1046ardb_tfa_defconfig +++ b/configs/ls1046ardb_tfa_defconfig @@ -85,7 +85,9 @@ CONFIG_PCIE_LAYERSCAPE_EP=y CONFIG_POWER_LEGACY=y CONFIG_POWER_I2C=y CONFIG_DM_SCSI=y -CONFIG_SYS_NS16550_SERIAL=y +CONFIG_SPECIFY_CONSOLE_INDEX=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_FSL_QSPI=y diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig index 6aa1d03..589da32 100644 --- a/configs/microblaze-generic_defconfig +++ b/configs/microblaze-generic_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_LEN=0xc0000 CONFIG_SYS_MALLOC_F_LEN=0x400 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SIZE=0x20000 +CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="microblaze-generic" CONFIG_SYS_PROMPT="U-Boot-mONStR> " CONFIG_SPL_SERIAL=y diff --git a/configs/microchip_mpfs_icicle_defconfig b/configs/microchip_mpfs_icicle_defconfig index c03c8ec..fa49d38 100644 --- a/configs/microchip_mpfs_icicle_defconfig +++ b/configs/microchip_mpfs_icicle_defconfig @@ -4,7 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 CONFIG_ENV_SIZE=0x2000 -CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit" +CONFIG_DEFAULT_DEVICE_TREE="mpfs-icicle-kit" CONFIG_SYS_PROMPT="RISC-V # " CONFIG_SYS_MEM_TOP_HIDE=0x400000 CONFIG_SYS_LOAD_ADDR=0x80200000 diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 503a733..ee518ca 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -35,9 +35,6 @@ CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 @@ -101,16 +98,19 @@ CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP8 is not set diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index a0befcc..0a8b047 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -33,9 +33,6 @@ CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SPL_LEGACY_IMAGE_FORMAT=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 @@ -109,13 +106,16 @@ CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y # CONFIG_VIDEO_BPP8 is not set diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index 1572afb..0e03660 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -33,9 +33,6 @@ CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 @@ -94,13 +91,16 @@ CONFIG_FSL_QSPI=y CONFIG_SOFT_SPI=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig index 637860c..8e3938d 100644 --- a/configs/myir_mys_6ulx_defconfig +++ b/configs/myir_mys_6ulx_defconfig @@ -23,8 +23,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 @@ -70,4 +68,6 @@ CONFIG_SYSINFO=y CONFIG_SYSINFO_SMBIOS=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index 9386d6f..2d06621 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -20,7 +20,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 @@ -63,6 +62,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Phytec" CONFIG_USB_GADGET_VENDOR_NUM=0x01b67 diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index 64ebc9f..327ea56 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -20,7 +20,6 @@ CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run mmc_mmc_fit" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 @@ -54,6 +53,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Phytec" CONFIG_USB_GADGET_VENDOR_NUM=0x01b67 diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig index ff50909..4fd5880 100644 --- a/configs/pico-dwarf-imx6ul_defconfig +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -27,9 +27,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTMENU=y @@ -72,9 +69,12 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 8a5ed1e..2cd906a 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -26,9 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set @@ -80,14 +77,17 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index 58d6d14..c430b4d 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -28,9 +28,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTMENU=y @@ -75,9 +72,12 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 3cdb4d3..b63281e 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -26,9 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set @@ -79,14 +76,17 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index 821cb97..be7b119 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -31,9 +31,6 @@ CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FIT_IMAGE_TINY=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 @@ -85,11 +82,14 @@ CONFIG_PINCTRL_IMX6=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y # CONFIG_BACKLIGHT is not set diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index 78cd63c..a6cbc51 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -28,9 +28,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="ask" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTMENU=y @@ -79,12 +76,15 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_VIDEO_MXS=y diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 74aab86..546e1e6 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -28,9 +28,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 @@ -77,15 +74,18 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 447342f..f11e1f4 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -26,9 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set @@ -80,14 +77,17 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 8a5ed1e..2cd906a 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -26,9 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set @@ -80,14 +77,17 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index b7d1ccd..3c822d1 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -28,9 +28,6 @@ CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 CONFIG_CMD_BOOTMENU=y @@ -75,9 +72,12 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 2f028c2..3e26aae 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -26,9 +26,6 @@ CONFIG_SPL_MAX_SIZE=0xe000 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_MAX_SIZE=0x100000 CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 # CONFIG_CMD_BOOTD is not set @@ -80,14 +77,17 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_EHCI_HCD=y CONFIG_MXC_USB_OTG_HACTIVE=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="FSL" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y +CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_VIDEO=y CONFIG_VIDEO_LOGO=y CONFIG_SYS_WHITE_ON_BLACK=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index 105b937..5f0746e 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -1,6 +1,7 @@ CONFIG_PPC=y CONFIG_TEXT_BASE=0xf00000 CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="qemu-ppce500" CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SYS_CLK_FREQ=33000000 diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig new file mode 100644 index 0000000..74a140a --- /dev/null +++ b/configs/r8a77970_v3msk_defconfig @@ -0,0 +1,87 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=16666666 +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_RMOBILE=y +CONFIG_TEXT_BASE=0x50000000 +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="r8a77970-v3msk-u-boot" +CONFIG_SPL_TEXT_BASE=0xe6318000 +CONFIG_RCAR_GEN3=y +CONFIG_R8A77970=y +CONFIG_TARGET_V3MSK=y +CONFIG_SPL_STACK=0xe6304000 +CONFIG_SYS_LOAD_ADDR=0x58000000 +CONFIG_LTO=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 +CONFIG_FIT=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_BOOTARGS=y +CONFIG_DEFAULT_FDT_FILE="r8a77970-v3msk.dtb" +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_DFU=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_DFU_TFTP=y +CONFIG_DFU_RAM=y +CONFIG_DFU_SF=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_I2C=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_RENESAS_RAVB=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_SYSRESET=y diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig new file mode 100644 index 0000000..564ff2d --- /dev/null +++ b/configs/r8a77980_v3hsk_defconfig @@ -0,0 +1,83 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=16666666 +CONFIG_ARCH_CPU_INIT=y +CONFIG_ARCH_RMOBILE=y +CONFIG_SYS_MALLOC_LEN=0x4000000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x40000 +CONFIG_ENV_OFFSET=0x700000 +CONFIG_ENV_SECT_SIZE=0x40000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="r8a77980-v3hsk-u-boot" +CONFIG_SPL_TEXT_BASE=0xe6318000 +CONFIG_RCAR_GEN3=y +CONFIG_R8A77980=y +CONFIG_TARGET_V3HSK=y +CONFIG_SPL_STACK=0xe6304000 +CONFIG_SYS_LOAD_ADDR=0x58000000 +CONFIG_LTO=y +CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 +CONFIG_FIT=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_USE_BOOTARGS=y +CONFIG_DEFAULT_FDT_FILE="r8a77980-v3hsk.dtb" +# CONFIG_BOARD_EARLY_INIT_F is not set +CONFIG_SYS_MALLOC_BOOTPARAMS=y +CONFIG_SPL_HAS_BSS_LINKER_SECTION=y +CONFIG_SPL_BSS_START_ADDR=0xe631f000 +CONFIG_SPL_BSS_MAX_SIZE=0x1000 +# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_MAXARGS=64 +CONFIG_SYS_PBSIZE=2068 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_ASKENV=y +CONFIG_CMD_DFU=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_OF_DTB_PROPS_REMOVE=y +CONFIG_OF_REMOVE_PROPS="dmas dma-names interrupt-parent interrupts interrupts-extended interrupt-names interrupt-map interrupt-map-mask iommus" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_VERSION_VARIABLE=y +CONFIG_REGMAP=y +CONFIG_SYSCON=y +CONFIG_CLK=y +CONFIG_CLK_RENESAS=y +CONFIG_RCAR_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_RCAR_I2C=y +CONFIG_MMC_IO_VOLTAGE=y +CONFIG_MMC_UHS_SUPPORT=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_RENESAS_SDHI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set +CONFIG_BITBANGMII=y +CONFIG_BITBANGMII_MULTI=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_SH_ETHER=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_SCIF_CONSOLE=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_RENESAS_RPC_SPI=y +CONFIG_SYSRESET=y diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig index 93031c7..9dec10e 100644 --- a/configs/seeed_npi_imx6ull_defconfig +++ b/configs/seeed_npi_imx6ull_defconfig @@ -24,8 +24,6 @@ CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_DMA=y CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 @@ -75,4 +73,6 @@ CONFIG_DM_REGULATOR_GPIO=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 6b67021..ba5990b 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -68,7 +68,6 @@ CONFIG_MTDIDS_DEFAULT="nor0=fe000000.nor_flash,nand0=socrates_nand" CONFIG_MTDPARTS_DEFAULT="mtdparts=fe000000.nor_flash:13312k(system1),13312k(system2),5120k(data),128k(env),128k(env-red),768k(u-boot);socrates_nand:256M(ubi-data1),-(ubi-data2)" # CONFIG_CMD_IRQ is not set CONFIG_OF_CONTROL=y -CONFIG_ENV_IS_NOWHERE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_ADDR_REDUND=0xFFF00000 diff --git a/configs/stm32mp13_defconfig b/configs/stm32mp13_defconfig index b076573..82b6274 100644 --- a/configs/stm32mp13_defconfig +++ b/configs/stm32mp13_defconfig @@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0x900000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp135f-dk" CONFIG_SYS_PROMPT="STM32MP> " CONFIG_STM32MP13x=y -CONFIG_DDR_CACHEABLE_SIZE=0x10000000 +CONFIG_DDR_CACHEABLE_SIZE=0x8000000 CONFIG_CMD_STM32KEY=y CONFIG_TARGET_ST_STM32MP13x=y CONFIG_ENV_OFFSET_REDUND=0x940000 @@ -39,7 +39,6 @@ CONFIG_CMD_RNG=y CONFIG_CMD_TIMER=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y CONFIG_CMD_LOG=y CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y @@ -59,7 +58,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_PINCONF=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y @@ -75,7 +73,6 @@ CONFIG_TEE=y CONFIG_OPTEE=y # CONFIG_OPTEE_TA_AVB is not set CONFIG_ERRNO_STR=y -CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig index 13355eb..424ae5d 100644 --- a/configs/stm32mp15_basic_defconfig +++ b/configs/stm32mp15_basic_defconfig @@ -75,7 +75,6 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y CONFIG_CMD_LOG=y CONFIG_CMD_UBI=y # CONFIG_SPL_DOS_PARTITION is not set @@ -102,7 +101,6 @@ CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 -CONFIG_FASTBOOT_USB_DEV=1 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y @@ -110,7 +108,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y CONFIG_GPIO_HOG=y @@ -125,7 +122,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_SYS_NAND_ONFI_DETECTION=y @@ -189,7 +185,6 @@ CONFIG_WDT=y CONFIG_WDT_STM32MP=y # CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y -CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/stm32mp15_defconfig b/configs/stm32mp15_defconfig index 2669aae..2700b5c 100644 --- a/configs/stm32mp15_defconfig +++ b/configs/stm32mp15_defconfig @@ -3,15 +3,15 @@ CONFIG_ARCH_STM32MP=y CONFIG_TFABOOT=y CONFIG_SYS_MALLOC_F_LEN=0x80000 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc0100000 -CONFIG_ENV_OFFSET=0x480000 +CONFIG_ENV_OFFSET=0x900000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DEFAULT_DEVICE_TREE="stm32mp157c-ev1" CONFIG_SYS_PROMPT="STM32MP> " -CONFIG_DDR_CACHEABLE_SIZE=0x10000000 +CONFIG_DDR_CACHEABLE_SIZE=0x8000000 CONFIG_CMD_STM32KEY=y CONFIG_TYPEC_STUSB160X=y CONFIG_TARGET_ST_STM32MP15x=y -CONFIG_ENV_OFFSET_REDUND=0x4C0000 +CONFIG_ENV_OFFSET_REDUND=0x940000 CONFIG_CMD_STM32PROG=y # CONFIG_ARMV7_NONSEC is not set CONFIG_SYS_LOAD_ADDR=0xc2000000 @@ -51,7 +51,6 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y CONFIG_CMD_LOG=y CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y @@ -75,7 +74,6 @@ CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 -CONFIG_FASTBOOT_USB_DEV=1 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y @@ -83,7 +81,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y CONFIG_GPIO_HOG=y @@ -98,7 +95,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_SYS_NAND_ONFI_DETECTION=y @@ -165,7 +161,6 @@ CONFIG_WDT=y CONFIG_WDT_STM32MP=y # CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y -CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/stm32mp15_dhcom_basic_defconfig b/configs/stm32mp15_dhcom_basic_defconfig index 93494f8..77f0faf 100644 --- a/configs/stm32mp15_dhcom_basic_defconfig +++ b/configs/stm32mp15_dhcom_basic_defconfig @@ -55,8 +55,6 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_TARGET="u-boot.itb" CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x2000000 @@ -87,9 +85,6 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=nor0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(env1),64k(env2)" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set @@ -166,11 +161,13 @@ CONFIG_USB_DWC2=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="dh" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y CONFIG_WDT=y CONFIG_WDT_STM32MP=y CONFIG_FAT_WRITE=y diff --git a/configs/stm32mp15_dhcor_basic_defconfig b/configs/stm32mp15_dhcor_basic_defconfig index b54ff93..6438ad8 100644 --- a/configs/stm32mp15_dhcor_basic_defconfig +++ b/configs/stm32mp15_dhcor_basic_defconfig @@ -53,8 +53,6 @@ CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y CONFIG_SPL_SPI_FLASH_MTD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000 -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_DFU=y CONFIG_SPL_TARGET="u-boot.itb" CONFIG_SYS_PBSIZE=1050 CONFIG_SYS_BOOTM_LEN=0x2000000 @@ -85,13 +83,11 @@ CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_BTRFS=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nor0=nor0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:256k(fsbl1),256k(fsbl2),1408k(uboot),64k(env1),64k(env2)" # CONFIG_SPL_DOS_PARTITION is not set # CONFIG_ISO_PARTITION is not set # CONFIG_SPL_PARTITION_UUIDS is not set CONFIG_OF_LIVE=y +CONFIG_OF_LIST="stm32mp15xx-dhcor-avenger96 stm32mp15xx-dhcor-testbench stm32mp15xx-dhcor-drc-compact" CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-names interrupts-extended interrupt-controller \\\#interrupt-cells interrupt-parent dmas dma-names assigned-clocks assigned-clock-rates assigned-clock-parents hwlocks" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y @@ -165,11 +161,13 @@ CONFIG_USB_DWC2=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="dh" CONFIG_USB_GADGET_VENDOR_NUM=0x0483 CONFIG_USB_GADGET_PRODUCT_NUM=0x5720 CONFIG_USB_GADGET_DWC2_OTG=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_DFU=y CONFIG_WDT=y CONFIG_WDT_STM32MP=y CONFIG_FAT_WRITE=y diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 5f0fb45..5b94e0c 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -52,7 +52,6 @@ CONFIG_CMD_TIMER=y CONFIG_CMD_PMIC=y CONFIG_CMD_REGULATOR=y CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y CONFIG_CMD_LOG=y CONFIG_CMD_UBI=y CONFIG_OF_LIVE=y @@ -76,7 +75,6 @@ CONFIG_SET_DFU_ALT_INFO=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0xC0000000 CONFIG_FASTBOOT_BUF_SIZE=0x02000000 -CONFIG_FASTBOOT_USB_DEV=1 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y @@ -84,7 +82,6 @@ CONFIG_FASTBOOT_MMC_BOOT1_NAME="mmc1boot0" CONFIG_FASTBOOT_MMC_BOOT2_NAME="mmc1boot1" CONFIG_FASTBOOT_MMC_USER_SUPPORT=y CONFIG_FASTBOOT_MMC_USER_NAME="mmc1" -CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_FASTBOOT_CMD_OEM_PARTCONF=y CONFIG_FASTBOOT_CMD_OEM_BOOTBUS=y CONFIG_GPIO_HOG=y @@ -99,7 +96,6 @@ CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_STM32_SDMMC2=y CONFIG_MTD=y CONFIG_DM_MTD=y -CONFIG_SYS_MTDPARTS_RUNTIME=y CONFIG_MTD_RAW_NAND=y CONFIG_NAND_STM32_FMC2=y CONFIG_SYS_NAND_ONFI_DETECTION=y @@ -165,7 +161,6 @@ CONFIG_WDT=y CONFIG_WDT_STM32MP=y # CONFIG_BINMAN_FDT is not set CONFIG_ERRNO_STR=y -CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 diff --git a/configs/synquacer_developerbox_defconfig b/configs/synquacer_developerbox_defconfig index 68f7bac..17d70ef 100644 --- a/configs/synquacer_developerbox_defconfig +++ b/configs/synquacer_developerbox_defconfig @@ -1,13 +1,13 @@ CONFIG_ARM=y CONFIG_ARCH_SYNQUACER=y -CONFIG_TEXT_BASE=0x08200000 +CONFIG_POSITION_INDEPENDENT=y CONFIG_SYS_MALLOC_LEN=0x1000000 -CONFIG_SYS_MALLOC_F_LEN=0x400 +CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xe0000000 CONFIG_SF_DEFAULT_SPEED=31250000 CONFIG_ENV_SIZE=0x30000 -CONFIG_ENV_OFFSET=0x300000 +CONFIG_ENV_OFFSET=0x580000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="synquacer-sc2a11-developerbox" @@ -97,3 +97,11 @@ CONFIG_EFI_RUNTIME_UPDATE_CAPSULE=y CONFIG_EFI_CAPSULE_ON_DISK=y CONFIG_EFI_IGNORE_OSINDICATIONS=y CONFIG_EFI_CAPSULE_FIRMWARE_RAW=y +CONFIG_EFI_SECURE_BOOT=y +CONFIG_FWU_MULTI_BANK_UPDATE=y +CONFIG_FWU_MDATA=y +CONFIG_FWU_MDATA_MTD=y +CONFIG_FWU_NUM_BANKS=2 +CONFIG_FWU_NUM_IMAGES_PER_BANK=1 +CONFIG_CMD_FWU_METADATA=y +CONFIG_TOOLS_MKFWUMDATA=y diff --git a/configs/ti816x_evm_defconfig b/configs/ti816x_evm_defconfig deleted file mode 100644 index a4bc993..0000000 --- a/configs/ti816x_evm_defconfig +++ /dev/null @@ -1,82 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_ARCH_OMAP2PLUS=y -CONFIG_SYS_MALLOC_F_LEN=0x400 -CONFIG_SPL_GPIO=y -CONFIG_SPL_LIBCOMMON_SUPPORT=y -CONFIG_SPL_LIBGENERIC_SUPPORT=y -CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y -CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4031ff00 -CONFIG_ENV_SIZE=0x2000 -CONFIG_ENV_OFFSET=0x1C0000 -CONFIG_DM_GPIO=y -CONFIG_DEFAULT_DEVICE_TREE="dm8168-evm" -CONFIG_SPL_TEXT_BASE=0x40400000 -CONFIG_TI816X=y -CONFIG_TARGET_TI816X_EVM=y -CONFIG_SPL_MMC=y -CONFIG_SPL_SERIAL=y -CONFIG_SPL=y -CONFIG_ENV_OFFSET_REDUND=0x1E0000 -CONFIG_SYS_CLK_FREQ=27000000 -CONFIG_SPL_FS_FAT=y -CONFIG_SPL_LIBDISK_SUPPORT=y -CONFIG_DISTRO_DEFAULTS=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttyO2,115200n8 noinitrd earlyprintk" -CONFIG_BOOTCOMMAND="mmc rescan;fatload mmc 0 ${loadaddr} uImage;bootm ${loadaddr}" -CONFIG_SYS_CONSOLE_INFO_QUIET=y -# CONFIG_DISPLAY_BOARDINFO is not set -# CONFIG_MISC_INIT_R is not set -CONFIG_SPL_MAX_SIZE=0xfff1b400 -CONFIG_SYS_SPL_MALLOC=y -CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 -CONFIG_SPL_NAND_SUPPORT=y -CONFIG_SPL_NAND_DRIVERS=y -CONFIG_SPL_NAND_ECC=y -CONFIG_SPL_NAND_BASE=y -CONFIG_SYS_MAXARGS=64 -CONFIG_CMD_ASKENV=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND=y -# CONFIG_CMD_SETEXPR is not set -CONFIG_BOOTP_DNS2=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_MTDPARTS=y -CONFIG_MTDIDS_DEFAULT="nand0=nand.0" -CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)" -# CONFIG_ISO_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -CONFIG_OF_CONTROL=y -CONFIG_ENV_OVERWRITE=y -CONFIG_ENV_IS_IN_NAND=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_VERSION_VARIABLE=y -CONFIG_NET_RETRY_COUNT=10 -CONFIG_BOOTP_SEND_HOSTNAME=y -CONFIG_DM_I2C=y -CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_OMAP24XX=y -CONFIG_MMC_OMAP_HS=y -CONFIG_MTD=y -CONFIG_MTD_RAW_NAND=y -CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 -CONFIG_SYS_NAND_ONFI_DETECTION=y -CONFIG_SYS_NAND_PAGE_COUNT=0x40 -CONFIG_SYS_NAND_PAGE_SIZE=0x800 -CONFIG_SYS_NAND_OOBSIZE=0x40 -CONFIG_SYS_NAND_BUSWIDTH_16BIT=y -CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y -CONFIG_SYS_NAND_U_BOOT_OFFS=0xc0000 -CONFIG_MII=y -CONFIG_DRIVER_TI_EMAC=y -CONFIG_SYS_NS16550_SERIAL=y -CONFIG_SPI=y -# CONFIG_USE_PRIVATE_LIBGCC is not set diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 698a41d..1cfa342 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -20,7 +20,6 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run mmc_mmc_fit" CONFIG_SYS_SPL_MALLOC=y -CONFIG_SPL_USB_HOST=y CONFIG_SPL_WATCHDOG=y CONFIG_SYS_MAXARGS=32 CONFIG_SYS_PBSIZE=532 @@ -59,6 +58,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Variscite" diff --git a/configs/videostrong-kii-pro_defconfig b/configs/videostrong-kii-pro_defconfig new file mode 100644 index 0000000..71a8029 --- /dev/null +++ b/configs/videostrong-kii-pro_defconfig @@ -0,0 +1,70 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_TEXT_BASE=0x01000000 +CONFIG_SYS_LOAD_ADDR=0x1000000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x2000 +CONFIG_DM_GPIO=y +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_IDENT_STRING=" kii-pro" +CONFIG_DEFAULT_DEVICE_TREE="meson-gxbb-kii-pro" +CONFIG_DEBUG_UART=y +CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20000000 +CONFIG_OF_BOARD_SETUP=y +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_MISC_INIT_R=y +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SARADC_MESON=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MESON=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE_MESON8B=y +CONFIG_PHY=y +CONFIG_MESON_GXBB_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_GXBB=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_EE_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_KEYBOARD=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_SPLASH_SCREEN=y +CONFIG_SPLASH_SCREEN_ALIGN=y +CONFIG_VIDEO_BMP_RLE8=y +CONFIG_BMP_16BPP=y +CONFIG_BMP_24BPP=y +CONFIG_BMP_32BPP=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 2aa272f..cbb8259 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -37,9 +37,6 @@ CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_FS_EXT4=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot-dtb.img" CONFIG_SPL_I2C=y -CONFIG_SPL_USB_HOST=y -CONFIG_SPL_USB_GADGET=y -CONFIG_SPL_USB_SDP_SUPPORT=y CONFIG_SPL_WATCHDOG=y CONFIG_HUSH_PARSER=y CONFIG_SYS_MAXARGS=32 @@ -96,13 +93,16 @@ CONFIG_DM_SERIAL=y CONFIG_MXC_UART=y CONFIG_IMX_THERMAL=y CONFIG_USB=y +CONFIG_SPL_USB_HOST=y CONFIG_USB_MAX_CONTROLLER_COUNT=2 CONFIG_USB_STORAGE=y CONFIG_USB_HOST_ETHER=y CONFIG_USB_ETHER_ASIX=y CONFIG_USB_GADGET=y +CONFIG_SPL_USB_GADGET=y CONFIG_USB_GADGET_MANUFACTURER="Softing" CONFIG_USB_GADGET_VENDOR_NUM=0x0525 CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 CONFIG_CI_UDC=y CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_SPL_USB_SDP_SUPPORT=y diff --git a/doc/README.pcap b/doc/README.pcap index 8e30b93..10318ef 100644 --- a/doc/README.pcap +++ b/doc/README.pcap @@ -1,6 +1,6 @@ PCAP: -U-boot supports live Ethernet packet capture in PCAP(2.4) format. +U-Boot supports live Ethernet packet capture in PCAP(2.4) format. This is enabled by CONFIG_CMD_PCAP. The capture is stored on physical memory, and should be copied to diff --git a/doc/README.rmobile b/doc/README.rmobile index ea170a2..524d839 100644 --- a/doc/README.rmobile +++ b/doc/README.rmobile @@ -35,6 +35,7 @@ Currently the following boards are supported: | R8A77965 M3-N | Renesas Electronics ULCB | r8a77965_ulcb |---------------+----------------------------------------+------------------- | R8A77970 V3M | Renesas Electronics Eagle | r8a77970_eagle_defconfig +| R8A77970 V3M | Renesas Electronics V3MSK | r8a77970_v3msk_defconfig |---------------+----------------------------------------+------------------- | R8A77995 D3 | Renesas Electronics Draak | r8a77995_draak_defconfig '===============+========================================+=================== diff --git a/doc/README.s5p4418 b/doc/README.s5p4418 index ac724d0..8ec7b05 100644 --- a/doc/README.s5p4418 +++ b/doc/README.s5p4418 @@ -38,7 +38,7 @@ The source code for (the used?) LUbuntu 16.04 can be found at [5]. Links ===== -[1] FriendlyArm U-boot v2016.01: +[1] FriendlyArm U-Boot v2016.01: https://github.com/friendlyarm/u-boot/tree/nanopi2-v2016.01 diff --git a/doc/SPL/README.spl-secure-boot b/doc/SPL/README.spl-secure-boot index f2f8d78..982fbec 100644 --- a/doc/SPL/README.spl-secure-boot +++ b/doc/SPL/README.spl-secure-boot @@ -12,7 +12,7 @@ Methodology The SPL image is responsible for loading the next stage boot loader, which is the main u-boot image. For secure boot process on these platforms ROM verifies -SPL image, so to continue chain of trust SPL image verifies U-boot image using +SPL image, so to continue chain of trust SPL image verifies U-Boot image using spl_validate_uboot(). This function uses QorIQ Trust Architecture header -(appended to U-boot image) to validate the U-boot binary just before passing +(appended to U-Boot image) to validate the U-Boot binary just before passing control to it. diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index 66b581c..46f44bf 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -118,6 +118,7 @@ Board Documentation sei610 s400 u200 + videostrong-kii-pro wetek-core2 wetek-hub wetek-play2 diff --git a/doc/board/amlogic/p201.rst b/doc/board/amlogic/p201.rst index 28aae98d..13b732f 100644 --- a/doc/board/amlogic/p201.rst +++ b/doc/board/amlogic/p201.rst @@ -56,7 +56,7 @@ image but sources have been shared by Linux development contractor, Baylibre: $ make $ export FIPDIR=$PWD/fip -Go back to mainline U-boot source tree then : +Go back to mainline U-Boot source tree then : .. code-block:: bash diff --git a/doc/board/amlogic/p212.rst b/doc/board/amlogic/p212.rst index c1b73e8..a872f32 100644 --- a/doc/board/amlogic/p212.rst +++ b/doc/board/amlogic/p212.rst @@ -50,7 +50,7 @@ the git tree published by the board vendor: $ make $ export FIPDIR=$PWD/fip -Go back to mainline U-boot source tree then : +Go back to mainline U-Boot source tree then : .. code-block:: bash diff --git a/doc/board/amlogic/s400.rst b/doc/board/amlogic/s400.rst index 59dda82..205e7c3 100644 --- a/doc/board/amlogic/s400.rst +++ b/doc/board/amlogic/s400.rst @@ -56,7 +56,7 @@ image but sources have been shared by Linux development contractor, Baylibre: $ make $ export FIPDIR=$PWD/fip -Go back to mainline U-boot source tree then : +Go back to mainline U-Boot source tree then : .. code-block:: bash diff --git a/doc/board/amlogic/videostrong-kii-pro.rst b/doc/board/amlogic/videostrong-kii-pro.rst new file mode 100644 index 0000000..1c6adac --- /dev/null +++ b/doc/board/amlogic/videostrong-kii-pro.rst @@ -0,0 +1,112 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +U-Boot for Videostrong KII Pro (S905) +===================================== + +Videostrong KII Pro is an Android STB manufactured by Videostrong and +based on the Amlogic p201 reference board, with the following specification: + + - Amlogic S905 ARM Cortex-A53 quad-core SoC @ 1.5GHz + - ARM Mali 450 GPU + - 2GB DDR3 SDRAM + - 16GB eMMC + - Gigabit Ethernet + - Boardcom BCM4335 WiFi and BT 4.0 + - HDMI 2.0 4K/60Hz display + - 3x USB 2.0 host + - 1x USB 2.0 otg + - microSD + - Infrared receiver + - Blue LED + - Red LED + - Power button (case, front) + - Reset button (underside) + - DVB Card: DVB-S and DVB-T/C + +Schematics are not publicly available. + +U-Boot Compilation +------------------ + +.. code-block:: bash + + $ export CROSS_COMPILE=aarch64-none-elf- + $ make videostrong-kii-pro_defconfig + $ make + +U-Boot Signing with Pre-Built FIP repo +-------------------------------------- + +.. code-block:: bash + + $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1 + $ cd amlogic-boot-fip + $ mkdir my-output-dir + $ ./build-fip.sh wetek-play2 /path/to/u-boot/u-boot.bin my-output-dir + +U-Boot Manual Signing +--------------------- + +Amlogic does not provide sources for the firmware and tools needed to create +a bootloader image and Videostrong has not publicly shared the U-Boot sources +needed to build FIP binaries for signing. However you can use the WeTek +Play2 binaries from the amlogic-boot-fip repo as the WeTek Play2 and the +Videostrong KII Pro share the same RAM chips. + +.. code-block:: bash + + $ git clone https://github.com/LibreELEC/amlogic-boot-fip --depth=1 + $ cd amlogic-boot-fip/wetek-play2 + $ export FIPDIR=$PWD + +Go back to the mainline U-Boot source tree then: + +.. code-block:: bash + + $ mkdir fip + $ cp $FIPDIR/bl2.bin fip/ + $ cp $FIPDIR/acs.bin fip/ + $ cp $FIPDIR/bl21.bin fip/ + $ cp $FIPDIR/bl30.bin fip/ + $ cp $FIPDIR/bl301.bin fip/ + $ cp $FIPDIR/bl31.img fip/ + $ cp u-boot.bin fip/bl33.bin + $ $FIPDIR/blx_fix.sh \ + fip/bl30.bin \ + fip/zero_tmp \ + fip/bl30_zero.bin \ + fip/bl301.bin \ + fip/bl301_zero.bin \ + fip/bl30_new.bin \ + bl30 + $ $FIPDIR/fip_create --bl30 fip/bl30_new.bin \ + --bl31 fip/bl31.img \ + --bl33 fip/bl33.bin \ + fip/fip.bin + $ sed -i 's/\x73\x02\x08\x91/\x1F\x20\x03\xD5/' fip/bl2.bin + $ python3 $FIPDIR/acs_tool.py fip/bl2.bin fip/bl2_acs.bin fip/acs.bin 0 + $ $FIPDIR/blx_fix.sh \ + fip/bl2_acs.bin \ + fip/zero_tmp \ + fip/bl2_zero.bin \ + fip/bl21.bin \ + fip/bl21_zero.bin \ + fip/bl2_new.bin \ + bl2 + $ cat fip/bl2_new.bin fip/fip.bin > fip/boot_new.bin + $ $FIPDIR/aml_encrypt_gxb --bootsig \ + --input fip/boot_new.bin + --output fip/u-boot.bin + +Then write U-Boot to SD or eMMC with: + +.. code-block:: bash + + $ DEV=/dev/boot_device + $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 conv=fsync + $ dd if=fip/u-boot.bin of=fip/u-boot.bin.gxbb bs=512 seek=9 skip=8 count=87 conv=fsync,notrunc + $ dd if=/dev/zero of=fip/u-boot.bin.gxbb bs=512 seek=8 count=1 conv=fsync,notrunc + $ dd if=bl1.bin.hardkernel of=fip/u-boot.bin.gxbb bs=512 seek=2 skip=2 count=1 conv=fsync,notrunc + $ ./aml_chksum fip/u-boot.bin.gxbb + $ dd if=fip/u-boot.bin.gxbb of=$DEV conv=fsync,notrunc bs=512 skip=1 seek=1 + $ dd if=fip/u-boot.bin.gxbb of=$DEV conv=fsync,notrunc bs=1 count=440 diff --git a/doc/board/emulation/qemu-arm.rst b/doc/board/emulation/qemu-arm.rst index 16f6638..b42d924 100644 --- a/doc/board/emulation/qemu-arm.rst +++ b/doc/board/emulation/qemu-arm.rst @@ -54,7 +54,7 @@ Note that for some odd reason qemu-system-aarch64 needs to be explicitly told to use a 64-bit CPU or it will boot in 32-bit mode. The -nographic argument ensures that output appears on the terminal. Use Ctrl-A X to quit. -Additional persistent U-boot environment support can be added as follows: +Additional persistent U-Boot environment support can be added as follows: - Create envstore.img using qemu-img:: diff --git a/doc/board/microchip/mpfs_icicle.rst b/doc/board/microchip/mpfs_icicle.rst index 09c2c6a..1464e53 100644 --- a/doc/board/microchip/mpfs_icicle.rst +++ b/doc/board/microchip/mpfs_icicle.rst @@ -134,7 +134,7 @@ Build OpenSBI .. code-block:: none make PLATFORM=generic FW_PAYLOAD_PATH=<u-boot-directory>/u-boot.bin - FW_FDT_PATH=<u-boot-directory>/arch/riscv/dts/microchip-mpfs-icicle-kit-.dtb + FW_FDT_PATH=<u-boot-directory>/arch/riscv/dts/mpfs-icicle-kit-.dtb 3. Output "fw_payload.bin" file available at "<opensbi-directory>/build/platform/generic/firmware/fw_payload.bin" @@ -277,14 +277,14 @@ load uImage (with initramfs). done Bytes transferred = 14482480 (dcfc30 hex) - RISC-V # tftpboot ${fdt_addr_r} microchip-mpfs-icicle-kit.dtb + RISC-V # tftpboot ${fdt_addr_r} mpfs-icicle-kit.dtb ethernet@20112000: PHY present at 9 ethernet@20112000: Starting autonegotiation... ethernet@20112000: Autonegotiation complete ethernet@20112000: link up, 1000Mbps full-duplex (lpa: 0x7800) Using ethernet@20112000 device TFTP from server 192.168.1.3; our IP address is 192.168.1.5 - Filename 'microchip-mpfs-icicle-kit.dtb'. + Filename 'mpfs-icicle-kit.dtb'. Load address: 0x82200000 Loading: # 2.5 MiB/s diff --git a/doc/board/nxp/ls1046ardb.rst b/doc/board/nxp/ls1046ardb.rst index 35465d0..49b4842 100644 --- a/doc/board/nxp/ls1046ardb.rst +++ b/doc/board/nxp/ls1046ardb.rst @@ -150,7 +150,7 @@ Then, launch openocd like:: openocd -f u-boot.tcl -You should see the U-boot SPL banner followed by the banner for U-Boot proper +You should see the U-Boot SPL banner followed by the banner for U-Boot proper in the output of openocd. The CMSIS-DAP adapter is slow, so this can take a long time. If you don't see it, something has gone wrong. After a while, you should see the prompt. You can load an image using semihosting by running:: diff --git a/doc/board/nxp/mx6sabresd.rst b/doc/board/nxp/mx6sabresd.rst index fe15ba7..c9869f4 100644 --- a/doc/board/nxp/mx6sabresd.rst +++ b/doc/board/nxp/mx6sabresd.rst @@ -53,7 +53,7 @@ This will generate the SPL and u-boot-dtb.img binaries. - Boot first from SD card as shown in the previous section -In U-boot change the eMMC partition config:: +In U-Boot change the eMMC partition config:: => mmc partconf 2 1 0 0 diff --git a/doc/board/rockchip/rockchip.rst b/doc/board/rockchip/rockchip.rst index 99376fb..4c555e1 100644 --- a/doc/board/rockchip/rockchip.rst +++ b/doc/board/rockchip/rockchip.rst @@ -333,12 +333,12 @@ Note: Unlike later SoC models the rk3066 BootROM doesn't have SDMMC support. If all other boot options fail then it enters into a BootROM mode on the USB OTG port. -This method loads TPL/SPL on NAND with U-boot and kernel on SD card. +This method loads TPL/SPL on NAND with U-Boot and kernel on SD card. SD Card ^^^^^^^ -U-boot expects a GPT partition map and a boot directory structure with files on the SD card. +U-Boot expects a GPT partition map and a boot directory structure with files on the SD card. .. code-block:: none @@ -363,7 +363,7 @@ Boot partition: zImage rk3066a-mk808.dtb -To write a U-boot image to the SD card (assumed to be /dev/sda): +To write a U-Boot image to the SD card (assumed to be /dev/sda): .. code-block:: bash diff --git a/doc/board/sifive/unmatched.rst b/doc/board/sifive/unmatched.rst index de2aab5..c515949 100644 --- a/doc/board/sifive/unmatched.rst +++ b/doc/board/sifive/unmatched.rst @@ -558,7 +558,7 @@ for partitions one through three respectively. --new=3:10280:10535 --change-name=3:env --typecode=3:3DE21764-95BD-54BD-A5C3-4ABE786F38A8 \ /dev/mtdblock0 -Write U-boot SPL and U-boot to their partitions. +Write U-Boot SPL and U-Boot to their partitions. .. code-block:: none diff --git a/doc/board/socionext/developerbox.rst b/doc/board/socionext/developerbox.rst index 2d943c2..aa7080e 100644 --- a/doc/board/socionext/developerbox.rst +++ b/doc/board/socionext/developerbox.rst @@ -57,14 +57,20 @@ Installation You can install the SNI_NOR_UBOOT.fd via NOR flash writer. -Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine or other mezzanine which can connect to LS-UART0 port. -Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the board on again. The flash writer program will be started automatically; don’t forget to turn the DSW2-7 off again after flashing. +Flashing the U-Boot image on DeveloperBox requires a 96boards UART mezzanine +or other mezzanine which can connect to the LS-UART0 port. +Connect USB cable from host to the LS-UART0 and set DSW2-7 to ON, and turn the +board on again. The flash writer program will be started automatically; +don't forget to turn the DSW2-7 off again after flashing. -*!!CAUTION!! If you failed to write the U-Boot image on wrong address, the board can be bricked. See below page if you need to recover the bricked board. See the following page for more detail* +*!!CAUTION!! If you write the U-Boot image on wrong address, the board can +be bricked. See below page if you need to recover the bricked board. See +the following page for more details* https://www.96boards.org/documentation/enterprise/developerbox/installation/board-recovery.md.html -When the serial flasher is running correctly is will show the following boot messages shown via LS-UART0:: +When the serial flasher is running correctly it will show the following boot +messages printed to the LS-UART0 console:: /*------------------------------------------*/ @@ -81,7 +87,143 @@ Once the flasher tool is running we are ready flash the UEFI image:: flash rawwrite 200000 100000 >> Send SPI_NOR_UBOOT.fd via XMODEM (Control-A S in minicom) << -*!!NOTE!! The flasher command parameter is different from the command for board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the size 100000 (1-five-0, 1M in hex).* +*!!NOTE!! The flasher command parameter is different from the command for +board recovery. U-Boot uses the offset 200000 (2-five-0, 2M in hex) and the +size 100000 (1-five-0, 1M in hex).* -After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and reset the board. +After transferring the SPI_NOR_UBOOT.fd, turn off the DSW2-7 and +reset the board. + +Enable FWU Multi Bank Update +============================ + +DeveloperBox supports the FWU Multi Bank Update. You *MUST* update both +*SCP firmware* and *TF-A* for this feature. This will change the layout and +the boot process but you can switch back to the normal one by changing +the DSW 1-4 off. + +Configure U-Boot +---------------- + +To enable the FWU Multi Bank Update on the DeveloperBox board the +configs/synquacer_developerbox_defconfig enables default FWU configuration :: + + CONFIG_FWU_MULTI_BANK_UPDATE=y + CONFIG_FWU_MDATA=y + CONFIG_FWU_MDATA_MTD=y + CONFIG_FWU_NUM_BANKS=2 + CONFIG_FWU_NUM_IMAGES_PER_BANK=1 + CONFIG_CMD_FWU_METADATA=y + +And build it:: + + cd u-boot/ + export ARCH=arm64 + export CROSS_COMPILE=aarch64-linux-gnu- + make synquacer_developerbox_defconfig + make -j `noproc` + cd ../ + +By default, the CONFIG_FWU_NUM_BANKS and CONFIG_FWU_NUM_IMAGES_PER_BANKS are +set to 2 and 1 respectively. This uses FIP (Firmware Image Package) type image +which contains TF-A, U-Boot and OP-TEE (the OP-TEE is optional). +You can use fiptool to compose the FIP image from those firmware images. + +Rebuild SCP firmware +-------------------- + +Rebuild SCP firmware which supports FWU Multi Bank Update as below:: + + cd SCP-firmware/ + OUT=./build/product/synquacer + ROMFW_FILE=$OUT/scp_romfw/$SCP_BUILD_MODE/bin/scp_romfw.bin + RAMFW_FILE=$OUT/scp_ramfw/$SCP_BUILD_MODE/bin/scp_ramfw.bin + ROMRAMFW_FILE=scp_romramfw_release.bin + + make CC=arm-none-eabi-gcc PRODUCT=synquacer MODE=release + tr "\000" "\377" < /dev/zero | dd of=${ROMRAMFW_FILE} bs=1 count=196608 + dd if=${ROMFW_FILE} of=${ROMRAMFW_FILE} bs=1 conv=notrunc seek=0 + dd if=${RAMFW_FILE} of=${ROMRAMFW_FILE} bs=1 seek=65536 + cd ../ + +And you can get the `scp_romramfw_release.bin` file. + +Rebuild OPTEE firmware +---------------------- + +Rebuild OPTEE to use in new-layout FIP as below:: + + cd optee_os/ + make -j`nproc` PLATFORM=synquacer ARCH=arm \ + CROSS_COMPILE64=aarch64-linux-gnu- CFG_ARM64_core=y \ + CFG_CRYPTO_WITH_CE=y CFG_CORE_HEAP_SIZE=524288 CFG_CORE_DYN_SHM=y \ + CFG_CORE_ARM64_PA_BITS=48 CFG_TEE_CORE_LOG_LEVEL=1 CFG_TEE_TA_LOG_LEVEL=1 + cp out/arm-plat-synquacer/core/tee-pager_v2.bin ../arm-trusted-firmware/ + +The produced `tee-pager_v2.bin` is to be used while building TF-A next. + + +Rebuild TF-A and FIP +-------------------- + +Rebuild TF-A which supports FWU Multi Bank Update as below:: + + cd arm-trusted-firmware/ + make CROSS_COMPILE=aarch64-linux-gnu- -j`nproc` PLAT=synquacer \ + TRUSTED_BOARD_BOOT=1 SPD=opteed SQ_RESET_TO_BL2=1 GENERATE_COT=1 \ + MBEDTLS_DIR=../mbedtls BL32=tee-pager_v2.bin \ + BL33=../u-boot/u-boot.bin all fip fiptool + +And make a FIP image.:: + + cp build/synquacer/release/fip.bin SPI_NOR_NEWFIP.fd + tools/fiptool/fiptool update --tb-fw build/synquacer/release/bl2.bin SPI_NOR_NEWFIP.fd + +UUIDs for the FWU Multi Bank Update +----------------------------------- + +FWU multi-bank update requires some UUIDs. The DeveloperBox platform uses +following UUIDs. + + - Location UUID for the FIP image: 17e86d77-41f9-4fd7-87ec-a55df9842de5 + - Image type UUID for the FIP image: 10c36d7d-ca52-b843-b7b9-f9d6c501d108 + - Image UUID for Bank0 : 5a66a702-99fd-4fef-a392-c26e261a2828 + - Image UUID for Bank1 : a8f868a1-6e5c-4757-878d-ce63375ef2c0 + +These UUIDs are used for making a FWU metadata image. + +u-boot$ ./tools/mkfwumdata -i 1 -b 2 \ + 17e86d77-41f9-4fd7-87ec-a55df9842de5,10c36d7d-ca52-b843-b7b9-f9d6c501d108,5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \ + ../devbox-fwu-mdata.img + +Create Accept & Revert capsules + +u-boot$ ./tools/mkeficapsule -A -g 7d6dc310-52ca-43b8-b7b9-f9d6c501d108 NEWFIP_accept.Cap +u-boot$ ./tools/mkeficapsule -R NEWFIP_revert.Cap + +Install via flash writer +------------------------ + +As explained in above section, the new FIP image and the FWU metadata image +can be installed via NOR flash writer. + +Once the flasher tool is running we are ready to flash the images.:: +Write the FIP image to the Bank-0 & 1 at 6MB and 10MB offset.:: + + flash rawwrite 600000 180000 + flash rawwrite a00000 180000 + >> Send SPI_NOR_NEWFIP.fd via XMODEM (Control-A S in minicom) << + + flash rawwrite 500000 1000 + flash rawwrite 530000 1000 + >> Send devbox-fwu-mdata.img via XMODEM (Control-A S in minicom) << + +And write the new SCP firmware.:: + + flash write cm3 + >> Send scp_romramfw_release.bin via XMODEM (Control-A S in minicom) << + +At last, turn on the DSW 3-4 on the board, and reboot. +Note that if DSW 3-4 is turned off, the DeveloperBox will boot from +the original EDK2 firmware (or non-FWU U-Boot if you already installed). diff --git a/doc/board/st/stm32mp1.rst b/doc/board/st/stm32mp1.rst index c0b1daa..63b4477 100644 --- a/doc/board/st/stm32mp1.rst +++ b/doc/board/st/stm32mp1.rst @@ -345,7 +345,7 @@ Build Procedure - BL33=u-boot-nodtb.bin - BL33_CFG=u-boot.dtb - You can also update a existing FIP after U-boot compilation with fiptool, + You can also update a existing FIP after U-Boot compilation with fiptool, a tool provided by TF-A_:: # fiptool update --nt-fw u-boot-nodtb.bin --hw-config u-boot.dtb fip-stm32mp157c-ev1.bin diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst new file mode 100644 index 0000000..0d3a526 --- /dev/null +++ b/doc/board/ti/j7200_evm.rst @@ -0,0 +1,332 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Udit Kumar <u-kumar1@ti.com> + +J7200 Platforms +=============== + +Introduction: +------------- +The J7200 family of SoCs are part of K3 Multicore SoC architecture platform +targeting automotive applications. They are designed as a low power, high +performance and highly integrated device architecture, adding significant +enhancement on processing power, graphics capability, video and imaging +processing, virtualization and coherent memory support. + +The device is partitioned into three functional domains, each containing +specific processing cores and peripherals: + +1. Wake-up (WKUP) domain: + * Device Management and Security Controller (DMSC) + +2. Microcontroller (MCU) domain: + * Dual Core ARM Cortex-R5F processor + +3. MAIN domain: + * Dual core 64-bit ARM Cortex-A72 + +More info can be found in TRM: https://www.ti.com/lit/pdf/spruiu1 + +Boot Flow: +---------- +Below is the pictorial representation of boot flow: + +.. code-block:: text + + +------------------------------------------------------------------------+-----------------------+ + | DMSC | MCU R5 | A72 | MAIN R5/C7x | + +------------------------------------------------------------------------+-----------------------+ + | +--------+ | | | | + | | Reset | | | | | + | +--------+ | | | | + | : | | | | + | +--------+ | +-----------+ | | | + | | *ROM* |----------|-->| Reset rls | | | | + | +--------+ | +-----------+ | | | + | | | | : | | | + | | ROM | | : | | | + | |services| | : | | | + | | | | +-------------+ | | | + | | | | | *R5 ROM* | | | | + | | | | +-------------+ | | | + | | |<---------|---|Load and auth| | | | + | | | | | tiboot3.bin | | | | + | | Start | | +-------------+ | | | + | | TIFS |<---------|---| Start | | | | + | | | | | TIFS | | | | + | +--------+ | +-------------+ | | | + | : | | | | | | + | +---------+ | | Load | | | | + | | *TIFS* | | | system | | | | + | +---------+ | | Config data | | | | + | | |<--------|---| | | | | + | | | | +-------------+ | | | + | | | | : | | | + | | | | : | | | + | | | | : | | | + | | | | +-------------+ | | | + | | | | | *R5 SPL* | | | | + | | | | +-------------+ | | | + | | | | | DDR | | | | + | | | | | config | | | | + | | | | +-------------+ | | | + | | | | | Load | | | | + | | | | | tispl.bin | | | | + | | | | +-------------+ | | | + | | | | | Load R5 | | | | + | | | | | firmware | | | | + | | | | +-------------+ | | | + | | |<--------|---| Start A72 | | | | + | | | | | and jump to | | | | + | | | | | DM fw image | | | | + | | | | +-------------+ | | | + | | | | | +-----------+ | | + | | |---------|-----------------------|---->| Reset rls | | | + | | | | | +-----------+ | | + | | TIFS | | | : | | + | |Services | | | +-----------+ | | + | | |<--------|-----------------------|---->|*ATF/OPTEE*| | | + | | | | | +-----------+ | | + | | | | | : | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|---->| *A72 SPL* | | | + | | | | | +-----------+ | | + | | | | | | Load | | | + | | | | | | u-boot.img| | | + | | | | | +-----------+ | | + | | | | | : | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|---->| *U-Boot* | | | + | | | | | +-----------+ | | + | | | | | | prompt | | | + | | | | | +-----------+ | | + | | | | | | Load R5 | | | + | | | | | | Firmware | | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|-----| Start R5 | | +-----------+ | + | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | + | | | | | | Load C7 | | +-----------+ | + | | | | | | Firmware | | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|-----| Start C7 | | +-----------+ | + | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | + | | | | | | +-----------+ | + | | | | | | | + | +---------+ | | | | + | | | | | + +------------------------------------------------------------------------+-----------------------+ + +- Here DMSC acts as master and provides all the critical services. R5/A72 + requests DMSC to get these services done as shown in the above diagram. + +Sources: +-------- +1. SYSFW: + Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git + Branch: master + +2. ATF: + Tree: https://github.com/ARM-software/arm-trusted-firmware.git + Branch: master + +3. OPTEE: + Tree: https://github.com/OP-TEE/optee_os.git + Branch: master + +4. DM Firmware: + Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git + Branch: ti-linux-firmware + +5. U-Boot: + Tree: https://source.denx.de/u-boot/u-boot + Branch: master + +Build procedure: +---------------- +1. SYSFW: + +.. code-block:: bash + + make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=j7200 SBL=u-boot-spl.bin SYSFW_PATH=<path to sysfw>/ti-fs-firmware-j7200-gp.bin + u-boot-spl.bin is generated at step 4. + +2. ATF: + +.. code-block:: bash + + make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed + +3. OPTEE: + +.. code-block:: bash + + make PLATFORM=k3-j7200 CFG_ARM64_core=y + +4. U-Boot: + +* 4.1 R5: + +.. code-block:: bash + + make CROSS_COMPILE=arm-linux-gnueabihf- j7200_evm_r5_defconfig O=build/r5 + make CROSS_COMPILE=arm-linux-gnueabihf- O=build/r5 + +* 4.2 A72: + +.. code-block:: bash + + make CROSS_COMPILE=aarch64-linux-gnu- j7200_evm_a72_defconfig O=build/a72 + make CROSS_COMPILE=aarch64-linux-gnu- ATF=<ATF dir>/build/k3/generic/release/bl31.bin TEE=<OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<DM firmware>/ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f O=build/a72 + +Target Images +-------------- +Copy the below images to an SD card and boot: + - tiboot3.bin from step 1 + - tispl.bin, u-boot.img from 4.2 + +Image formats: +-------------- + +- tiboot3.bin: + +.. code-block:: console + + +-----------------------+ + | X.509 | + | Certificate | + | +-------------------+ | + | | | | + | | R5 | | + | | u-boot-spl.bin | | + | | | | + | +-------------------+ | + | | | | + | | FIT header | | + | | +---------------+ | | + | | | | | | + | | | DTB 1...N | | | + | | +---------------+ | | + | +-------------------+ | + | | | | + | | FIT HEADER | | + | | +---------------+ | | + | | | | | | + | | | sysfw.bin | | | + | | +---------------+ | | + | | | | | | + | | | board config | | | + | | +---------------+ | | + | | | | | | + | | | PM config | | | + | | +---------------+ | | + | | | | | | + | | | RM config | | | + | | +---------------+ | | + | | | | | | + | | | Secure config | | | + | | +---------------+ | | + | +-------------------+ | + +-----------------------+ + +- tispl.bin + +.. code-block:: console + + +-----------------------+ + | | + | FIT HEADER | + | +-------------------+ | + | | | | + | | A72 ATF | | + | +-------------------+ | + | | | | + | | A72 OPTEE | | + | +-------------------+ | + | | | | + | | R5 DM FW | | + | +-------------------+ | + | | | | + | | A72 SPL | | + | +-------------------+ | + | | | | + | | SPL DTB 1...N | | + | +-------------------+ | + +-----------------------+ + + +Switch Setting for Boot Mode +---------------------------- + +Boot Mode pins provide means to select the boot mode and options before the +device is powered up. After every POR, they are the main source to populate +the Boot Parameter Tables. + +The following table shows some common boot modes used on J7200 platform. More +details can be found in the Technical Reference Manual: +https://www.ti.com/lit/pdf/spruiu1 under the `Boot Mode Pins` section. + + +*Boot Modes* + +============ ============= ============= +Switch Label SW9: 12345678 SW8: 12345678 +============ ============= ============= +SD 00000000 10000010 +EMMC 01000000 10000000 +OSPI 01000000 00000110 +UART 01110000 00000000 +USB DFU 00100000 10000000 +============ ============= ============= + +For SW8 and SW9, the switch state in the "ON" position = 1. + +eMMC: +----- +ROM supports booting from eMMC raw read or UDA FS mode. + +Below is memory layout in case of booting from +boot 0/1 partition in raw mode. + +Current allocated size for tiboot3 size is 1MB, tispl is 2MB. + +Size of u-boot.img is taken 4MB for refernece, +But this is subject to change depending upon atf, optee size + +.. code-block:: console + + boot0/1 partition (8 MB) user partition + 0x0+----------------------------------+ 0x0+------------------------+ + | tiboot3.bin (1 MB) | | | + 0x800+----------------------------------+ | | + | tispl.bin (2 MB) | | | + 0x1800+----------------------------------+ | | + | u-boot.img (4MB) | | | + 0x3800+----------------------------------+ | | + | | | | + 0x3900+ environment | | | + | | | | + 0x3A00+----------------------------------+ +-------------------------+ + +In case of UDA FS mode booting, following is layout. + +All boot images tiboot3.bin, tispl and u-boot should be written to +fat formatted UDA FS as file. + +.. code-block:: console + + boot0/1 partition (8 MB) user partition + 0x0+---------------------------------+ 0x0+-------------------------+ + | | | tiboot3.bin* | + 0x800+----------------------------------+ | | + | | | tispl.bin | + 0x1800+----------------------------------+ | | + | | | u-boot.img | + 0x3800+----------------------------------+ | | + | | | | + 0x3900+ | | environment | + | | | | + 0x3A00+----------------------------------+ +-------------------------+ + + + +In case of booting from eMMC, write above images into raw or UDA FS. +and set mmc partconf accordingly. diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index b49a60c..2b2f4bb 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -31,6 +31,7 @@ K3 Based SoCs :maxdepth: 1 j721e_evm + j7200_evm am62x_sk Boot Flow Overview diff --git a/doc/board/xen/xenguest_arm64.rst b/doc/board/xen/xenguest_arm64.rst index 1327f88..e9bdaf7 100644 --- a/doc/board/xen/xenguest_arm64.rst +++ b/doc/board/xen/xenguest_arm64.rst @@ -6,7 +6,7 @@ Xen guest ARM64 board This board specification ------------------------ -This board is to be run as a virtual Xen [1] guest with U-boot as its primary +This board is to be run as a virtual Xen [1] guest with U-Boot as its primary bootloader. Xen is a type 1 hypervisor that allows multiple operating systems to run simultaneously on a single physical server. Xen is capable of running virtual machines in both full virtualization and para-virtualization (PV) @@ -16,7 +16,7 @@ Paravirtualized drivers are a special type of device drivers that are used in a guest system in the Xen domain and perform I/O operations using a special interface provided by the virtualization system and the host system. -Xen support for U-boot is implemented by introducing a new Xen guest ARM64 +Xen support for U-Boot is implemented by introducing a new Xen guest ARM64 board and porting essential drivers from MiniOS [3] as well as some of the work previously done by NXP [4]: @@ -39,7 +39,7 @@ previously done by NXP [4]: Board limitations ----------------- -1. U-boot runs without MMU enabled at the early stages. +1. U-Boot runs without MMU enabled at the early stages. According to Xen on ARM ABI (xen/include/public/arch-arm.h): all memory which is shared with other entities in the system (including the hypervisor and other guests) must reside in memory which is mapped as Normal Inner @@ -54,14 +54,14 @@ Board limitations 2. No serial console until MMU is up. Because data cache maintenance is required until the MMU setup the early/debug serial console is not implemented. Therefore, we do not have - usual prints like U-boot’s banner etc. until the serial driver is + usual prints like U-Boot’s banner etc. until the serial driver is initialized. 3. Single RAM bank supported. If a Xen guest is given much memory it is possible that Xen allocates two memory banks for it. The first one is allocated under 4GB address space and in some cases may represent the whole guest’s memory. It is assumed that - U-boot most likely won’t require high memory bank for its work andlaunching + U-Boot most likely won’t require high memory bank for its work andlaunching OS, so it is enough to take the first one. diff --git a/doc/build/clang.rst b/doc/build/clang.rst index 1d35616..cc26550 100644 --- a/doc/build/clang.rst +++ b/doc/build/clang.rst @@ -74,3 +74,39 @@ simplified with a simple wrapper script - saved as #!/bin/sh exec clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd "$@" + + +Known Issues +------------ + +When build U-boot for `xenguest_arm64_defconfig` target, it reports linkage +error: + +.. code-block:: bash + + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `do_hypervisor_callback': + /home/leoy/Dev2/u-boot/drivers/xen/hypervisor.c:188: undefined reference to `__aarch64_swp8_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_clear_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_set_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/gnttab.o: in function `gnttab_end_access': + /home/leoy/Dev2/u-boot/drivers/xen/gnttab.c:109: undefined reference to `__aarch64_cas2_acq_rel' + Segmentation fault + +To fix the failure, we need to append option `-mno-outline-atomics` in Clang +command to not generate local calls to out-of-line atomic operations: + +.. code-block:: bash + + make HOSTCC=clang xenguest_arm64_defconfig + make HOSTCC=clang CROSS_COMPILE=aarch64-linux-gnu- \ + CC="clang -target aarch64-linux-gnueabi -mno-outline-atomics" -j8 diff --git a/doc/develop/driver-model/bind.rst b/doc/develop/driver-model/bind.rst index b19661b..0d0d407 100644 --- a/doc/develop/driver-model/bind.rst +++ b/doc/develop/driver-model/bind.rst @@ -7,7 +7,7 @@ Binding/unbinding a driver This document aims to describe the bind and unbind commands. For debugging purpose, it should be useful to bind or unbind a driver from -the U-boot command line. +the U-Boot command line. The unbind command calls the remove device driver callback and unbind the device from its driver. diff --git a/doc/develop/driver-model/fs_firmware_loader.rst b/doc/develop/driver-model/fs_firmware_loader.rst index b082370..149b8b4 100644 --- a/doc/develop/driver-model/fs_firmware_loader.rst +++ b/doc/develop/driver-model/fs_firmware_loader.rst @@ -92,9 +92,9 @@ For example of getting DT phandle from /chosen and creating instance: if (ret) return ret; -Firmware loader driver is also designed to support U-boot environment +Firmware loader driver is also designed to support U-Boot environment variables, so all these data from FDT can be overwritten -through the U-boot environment variable during run time. +through the U-Boot environment variable during run time. For examples: @@ -110,7 +110,7 @@ fw_ubi_volume: When above environment variables are set, environment values would be used instead of data from FDT. The benefit of this design allows user to change storage attribute data -at run time through U-boot console and saving the setting as default +at run time through U-Boot console and saving the setting as default environment values in the storage for the next power cycle, so no compilation is required for both driver and FDT. diff --git a/doc/develop/uefi/uefi.rst b/doc/develop/uefi/uefi.rst index ffe25ca..6626cee 100644 --- a/doc/develop/uefi/uefi.rst +++ b/doc/develop/uefi/uefi.rst @@ -318,6 +318,33 @@ Run the following command --guid <image GUID> \ <capsule_file_name> +The UEFI specification does not define the firmware versioning mechanism. +EDK II reference implementation inserts the FMP Payload Header right before +the payload. It coutains the fw_version and lowest supported version, +EDK II reference implementation uses these information to implement the +firmware versioning and anti-rollback protection, the firmware version and +lowest supported version is stored into EFI non-volatile variable. + +In U-Boot, the firmware versioning is implemented utilizing +the FMP Payload Header same as EDK II reference implementation, +reads the FMP Payload Header and stores the firmware version into +"FmpStateXXXX" EFI non-volatile variable. XXXX indicates the image index, +since FMP protocol handles multiple image indexes. + +To add the fw_version into the FMP Payload Header, +add --fw-version option in mkeficapsule tool. + +.. code-block:: console + + $ mkeficapsule \ + --index <index> --instance 0 \ + --guid <image GUID> \ + --fw-version 5 \ + <capsule_file_name> + +If the --fw-version option is not set, FMP Payload Header is not inserted +and fw_version is set as 0. + Performing the update ********************* @@ -330,7 +357,7 @@ bit in OsIndications variable with => setenv -e -nv -bs -rt -v OsIndications =0x0000000000000004 -Since U-boot doesn't currently support SetVariable at runtime, its value +Since U-Boot doesn't currently support SetVariable at runtime, its value won't be taken over across the reboot. If this is the case, you can skip this feature check with the Kconfig option (CONFIG_EFI_IGNORE_OSINDICATIONS) set. @@ -510,6 +537,45 @@ where signature.dts looks like:: }; }; +Anti-rollback Protection +************************ + +Anti-rollback prevents unintentional installation of outdated firmware. +To enable anti-rollback, you must add the lowest-supported-version property +to dtb and specify --fw-version when creating a capsule file with the +mkeficapsule tool. +When executing capsule update, U-Boot checks if fw_version is greater than +or equal to lowest-supported-version. If fw_version is less than +lowest-supported-version, the update will fail. +For example, if lowest-supported-version is set to 7 and you run capsule +update using a capsule file with --fw-version of 5, the update will fail. +When the --fw-version in the capsule file is updated, lowest-supported-version +in the dtb might be updated accordingly. + +To insert the lowest supported version into a dtb + +.. code-block:: console + + $ dtc -@ -I dts -O dtb -o version.dtbo version.dts + $ fdtoverlay -i orig.dtb -o new.dtb -v version.dtbo + +where version.dts looks like:: + + /dts-v1/; + /plugin/; + &{/} { + firmware-version { + image1 { + image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8"; + image-index = <1>; + lowest-supported-version = <3>; + }; + }; + }; + +The properties of image-type-id and image-index must match the value +defined in the efi_fw_image array as image_type_id and image_index. + Executing the boot manager ~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/doc/device-tree-bindings/firmware/firmware-version.txt b/doc/device-tree-bindings/firmware/firmware-version.txt new file mode 100644 index 0000000..ee90ce3 --- /dev/null +++ b/doc/device-tree-bindings/firmware/firmware-version.txt @@ -0,0 +1,22 @@ +firmware-version bindings +------------------------------- + +Required properties: +- image-type-id : guid for image blob type +- image-index : image index +- lowest-supported-version : lowest supported version + +Example: + + firmware-version { + image1 { + image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8"; + image-index = <1>; + lowest-supported-version = <3>; + }; + image2 { + image-type-id = "5A7021F5-FEF2-48B4-AABA-832E777418C0"; + image-index = <2>; + lowest-supported-version = <7>; + }; + }; diff --git a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml index 4f5404f..6a22aee 100644 --- a/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml +++ b/doc/device-tree-bindings/firmware/fwu-mdata-mtd.yaml @@ -1,13 +1,13 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-sf.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# +$id: http://devicetree.org/schemas/firmware/u-boot,fwu-mdata-mtd.yaml# +$schema: http://devicetree.org/meta-schemas/base.yaml# title: FWU metadata on MTD device without GPT maintainers: - - Masami Hiramatsu <masami.hiramatsu@linaro.org> + - Jassi Brar <jaswinder.singh@linaro.org> properties: compatible: @@ -15,24 +15,101 @@ properties: - const: u-boot,fwu-mdata-mtd fwu-mdata-store: - maxItems: 1 - description: Phandle of the MTD device which contains the FWU medatata. + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle of the MTD device which contains the FWU MetaData and Banks. - mdata-offsets: + mdata-parts: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array minItems: 2 - description: Offsets of the primary and secondary FWU metadata in the NOR flash. + maxItems: 2 + description: labels of the primary and secondary FWU metadata partitions in the 'fixed-partitions' subnode of the 'jedec,spi-nor' flash device node. + + patternProperties: + "fwu-bank[0-9]": + type: object + description: List of FWU mtd-backed banks. Typically two banks. + + properties: + id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Index of the bank. + + label: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + minItems: 1 + maxItems: 1 + description: label of the partition, in the 'fixed-partitions' subnode of the 'jedec,spi-nor' flash device node, that holds this bank. + + patternProperties: + "fwu-image[0-9]": + type: object + description: List of images in the FWU mtd-backed bank. + + properties: + id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Index of the bank. + + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset, from start of the bank, where the image is located. + + size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Size reserved for the image. + + uuid: + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + minItems: 1 + maxItems: 1 + description: UUID of the image. + + required: + - id + - offset + - size + - uuid + additionalProperties: false + + required: + - id + - label + - fwu-images + additionalProperties: false required: - compatible - fwu-mdata-store - - mdata-offsets - + - mdata-parts + - fwu-banks additionalProperties: false examples: - | - fwu-mdata { - compatible = "u-boot,fwu-mdata-mtd"; - fwu-mdata-store = <&spi-flash>; - mdata-offsets = <0x500000 0x530000>; - }; + fwu-mdata { + compatible = "u-boot,fwu-mdata-mtd"; + fwu-mdata-store = <&flash0>; + mdata-parts = "MDATA-Pri", "MDATA-Sec"; + + fwu-bank0 { + id = <0>; + label = "FIP-Bank0"; + fwu-image0 { + id = <0>; + offset = <0x0>; + size = <0x400000>; + uuid = "5a66a702-99fd-4fef-a392-c26e261a2828"; + }; + }; + fwu-bank1 { + id = <1>; + label = "FIP-Bank1"; + fwu-image0 { + id = <0>; + offset = <0x0>; + size = <0x400000>; + uuid = "a8f868a1-6e5c-4757-878d-ce63375ef2c0"; + }; + }; + }; +... diff --git a/doc/mkeficapsule.1 b/doc/mkeficapsule.1 index 1ca245a..c4c2057 100644 --- a/doc/mkeficapsule.1 +++ b/doc/mkeficapsule.1 @@ -62,6 +62,16 @@ Specify an image index Specify a hardware instance .PP +FMP Payload Header is inserted right before the payload if +.BR --fw-version +is specified + + +.TP +.BI "-v\fR,\fB --fw-version " firmware-version +Specify a firmware version, 0 if omitted + +.PP For generation of firmware accept empty capsule .BR --guid is mandatory diff --git a/doc/mkfwumdata.1 b/doc/mkfwumdata.1 new file mode 100644 index 0000000..7dd718b --- /dev/null +++ b/doc/mkfwumdata.1 @@ -0,0 +1,89 @@ +.\" SPDX-License-Identifier: GPL-2.0-or-later +.\" Copyright (C) 2023 Jassi Brar <jaswinder.singh@linaro.org> +.TH MKFWUMDATA 1 2023-04-10 U-Boot +.SH NAME +mkfwumdata \- create FWU metadata image +. +.SH SYNOPSIS +.SY mkfwumdata +.OP \-a activeidx +.OP \-p previousidx +.OP \-g +.BI \-i\~ imagecount +.BI \-b\~ bankcount +.I UUIDs +.I outputimage +.YS +.SY mkfwumdata +.B \-h +.YS +. +.SH DESCRIPTION +.B mkfwumdata +creates metadata info to be used with FWU. +. +.SH OPTIONS +.TP +.B \-h +Print usage information and exit. +. +.TP +.B \-a +Set +.IR activeidx +as the currently active Bank. Default is 0. +. +.TP +.B \-p +Set +.IR previousidx +as the previous active Bank. Default is +.IR activeidx "-1" +or +.IR bankcount "-1," +whichever is non-negative. +. +.TP +.B \-g +Convert the +.IR UUIDs +as GUIDs before use. +. +.TP +.B \-i +Specify there are +.IR imagecount +images in each bank. +. +.TP +.B \-b +Specify there are a total of +.IR bankcount +banks. +. +.TP +.IR UUIDs +Comma-separated list of UUIDs required to create the metadata :- +location_uuid,image_type_uuid,<images per bank uuid list of all banks> +. +.TP +.IR outputimage +Specify the name of the metadata image file to be created. +. +.SH BUGS +Please report bugs to the +.UR https://\:source\:.denx\:.de/\:u-boot/\:u-boot/\:issues +U-Boot bug tracker +.UE . +.SH EXAMPLES +Create a metadata image with 2 banks and 1 image/bank, BankAct=0, BankPrev=1: +.PP +.EX +.in +4 +$ \c +.B mkfwumdata \-a 0 \-p 1 \-b 2 \-i 1 \\\\\& +.in +6 +.B 17e86d77-41f9-4fd7-87ec-a55df9842de5,\\\\\& +.B 10c36d7d-ca52-b843-b7b9-f9d6c501d108,\\\\\& +.B 5a66a702-99fd-4fef-a392-c26e261a2828,a8f868a1-6e5c-4757-878d-ce63375ef2c0 \\\\\& +.B fwu-mdata.img diff --git a/doc/sphinx/requirements.txt b/doc/sphinx/requirements.txt index f9f6cc6..aed4492 100644 --- a/doc/sphinx/requirements.txt +++ b/doc/sphinx/requirements.txt @@ -11,7 +11,7 @@ packaging==21.3 Pygments==2.11.2 pyparsing==3.0.7 pytz==2022.1 -requests==2.27.1 +requests==2.31.0 six==1.16.0 snowballstemmer==2.2.0 Sphinx==3.4.3 diff --git a/doc/usage/cmd/source.rst b/doc/usage/cmd/source.rst index 6f5fa28..697f644 100644 --- a/doc/usage/cmd/source.rst +++ b/doc/usage/cmd/source.rst @@ -161,7 +161,7 @@ The boot scripts (boot.scr) is created with: mkimage -T script -n 'Test script' -d boot.txt boot.scr -The script can be execute in U-boot like this: +The script can be execute in U-Boot like this: .. code-block:: diff --git a/doc/usage/dfu.rst b/doc/usage/dfu.rst index ed47ff5..68cacbb 100644 --- a/doc/usage/dfu.rst +++ b/doc/usage/dfu.rst @@ -9,7 +9,7 @@ Overview The Device Firmware Upgrade (DFU) allows to download and upload firmware to/from U-Boot connected over USB. -U-boot follows the Universal Serial Bus Device Class Specification for +U-Boot follows the Universal Serial Bus Device Class Specification for Device Firmware Upgrade Version 1.1 the USB forum (DFU v1.1 in www.usb.org). U-Boot implements this DFU capability (CONFIG_DFU) with the command dfu diff --git a/drivers/Makefile b/drivers/Makefile index 29be78a..78dcf62 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox/ obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/ obj-$(CONFIG_$(SPL_)SYSINFO) += sysinfo/ obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/ +obj-$(CONFIG_$(SPL_)NVME) += nvme/ obj-$(CONFIG_XEN) += xen/ obj-$(CONFIG_$(SPL_)FPGA) += fpga/ obj-y += bus/ diff --git a/drivers/axi/axi-emul-uclass.c b/drivers/axi/axi-emul-uclass.c index 793336d..e6f3ef0 100644 --- a/drivers/axi/axi-emul-uclass.c +++ b/drivers/axi/axi-emul-uclass.c @@ -14,7 +14,7 @@ #include <asm/axi.h> int axi_sandbox_get_emul(struct udevice *bus, ulong address, - enum axi_size_t size, struct udevice **emulp) + const enum axi_size_t size, struct udevice **emulp) { struct udevice *dev; u32 reg[2]; diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig index 5a1aeb3d..6baaa6f 100644 --- a/drivers/block/Kconfig +++ b/drivers/block/Kconfig @@ -107,6 +107,13 @@ config EFI_MEDIA For sandbox there is a test driver. +config SPL_BLK_FS + bool "Load images from filesystems on block devices" + depends on SPL_BLK + help + Use generic support to load images from fat/ext filesystems on + different types of block devices such as NVMe. + if EFI_MEDIA config EFI_MEDIA_SANDBOX diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c index 184d426..017f25f 100644 --- a/drivers/clk/clk-mux.c +++ b/drivers/clk/clk-mux.c @@ -184,7 +184,7 @@ struct clk *clk_hw_register_mux_table(struct device *dev, const char *name, if (!mux) return ERR_PTR(-ENOMEM); - /* U-boot specific assignments */ + /* U-Boot specific assignments */ mux->parent_names = parent_names; mux->num_parents = num_parents; diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 45c679a..be0ee50 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -691,6 +691,7 @@ static ulong zynqmp_clk_get_rate(struct clk *clk) case topsw_lsbus: case sata_ref ... gpu_pp1_ref: two_divs = true; + fallthrough; case cpu_r5: case dbg_fpd: case ams_ref: diff --git a/drivers/clk/sifive/Makefile b/drivers/clk/sifive/Makefile index 51348b1..84859d9 100644 --- a/drivers/clk/sifive/Makefile +++ b/drivers/clk/sifive/Makefile @@ -1,5 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ -obj-y += sifive-prci.o - -obj-$(CONFIG_CLK_SIFIVE_PRCI) += fu540-prci.o fu740-prci.o +obj-$(CONFIG_CLK_SIFIVE_PRCI) += sifive-prci.o fu540-prci.o fu740-prci.o diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 02e6d90..7492b1f 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -185,7 +185,7 @@ static void jh7110_pll_set_rate(struct clk_jh7110_pllx *pll, PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1); PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv); PLLX_SET(pll->offset->fbdiv, pll->offset->fbdiv_mask, rate->fbdiv); - PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1, 0); + PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1_mask, 0); PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON); if (set) { diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig index 8d7f13d..c3a0b93 100644 --- a/drivers/dfu/Kconfig +++ b/drivers/dfu/Kconfig @@ -41,7 +41,6 @@ config DFU_MMC config DFU_MTD bool "MTD back end for DFU" depends on DM_MTD - depends on CMD_MTDPARTS help This option enables using DFU to read and write to on any MTD device. diff --git a/drivers/dfu/dfu.c b/drivers/dfu/dfu.c index 516dda6..b2ee5f1 100644 --- a/drivers/dfu/dfu.c +++ b/drivers/dfu/dfu.c @@ -135,6 +135,7 @@ int dfu_config_interfaces(char *env) a = s; do { part = strsep(&a, ";"); + part = skip_spaces(part); ret = dfu_alt_add(dfu, i, d, part); if (ret) return ret; @@ -629,6 +630,7 @@ int dfu_config_entities(char *env, char *interface, char *devstr) for (i = 0; i < dfu_alt_num; i++) { s = strsep(&env, ";"); + s = skip_spaces(s); ret = dfu_alt_add(dfu, interface, devstr, s); if (ret) { /* We will free "dfu" in dfu_free_entities() */ diff --git a/drivers/dfu/dfu_mtd.c b/drivers/dfu/dfu_mtd.c index c7075f1..75e2f6a 100644 --- a/drivers/dfu/dfu_mtd.c +++ b/drivers/dfu/dfu_mtd.c @@ -10,7 +10,6 @@ #include <common.h> #include <dfu.h> #include <mtd.h> -#include <jffs2/load_kernel.h> #include <linux/err.h> #include <linux/ctype.h> @@ -275,7 +274,7 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char **argv, int a { char *s; struct mtd_info *mtd; - int ret, part; + int part; mtd = get_mtd_device_nm(devstr); if (IS_ERR_OR_NULL(mtd)) @@ -299,10 +298,9 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char **argv, int a if (*s) return -EINVAL; } else if ((!strcmp(argv[0], "part")) || (!strcmp(argv[0], "partubi"))) { - char mtd_id[32]; - struct mtd_device *mtd_dev; - u8 part_num; - struct part_info *pi; + struct mtd_info *partition; + int partnum = 0; + bool part_found = false; if (argc != 2) return -EINVAL; @@ -313,19 +311,25 @@ int dfu_fill_entity_mtd(struct dfu_entity *dfu, char *devstr, char **argv, int a if (*s) return -EINVAL; - sprintf(mtd_id, "%s,%d", devstr, part - 1); - printf("using id '%s'\n", mtd_id); + /* register partitions with MTDIDS/MTDPARTS or OF fallback */ + mtd_probe_devices(); - mtdparts_init(); - - ret = find_dev_and_part(mtd_id, &mtd_dev, &part_num, &pi); - if (ret != 0) { - printf("Could not locate '%s'\n", mtd_id); + partnum = 0; + list_for_each_entry(partition, &mtd->partitions, node) { + partnum++; + if (partnum == part) { + part_found = true; + break; + } + } + if (!part_found) { + printf("No partition %d in %s\n", part, mtd->name); return -1; } + log_debug("partition %d:%s in %s\n", partnum, partition->name, mtd->name); - dfu->data.mtd.start = pi->offset; - dfu->data.mtd.size = pi->size; + dfu->data.mtd.start = partition->offset; + dfu->data.mtd.size = partition->size; if (!strcmp(argv[0], "partubi")) dfu->data.mtd.ubi = 1; } else { diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c index 621146b..4e9d9b7 100644 --- a/drivers/fastboot/fb_common.c +++ b/drivers/fastboot/fb_common.c @@ -135,7 +135,7 @@ void fastboot_boot(void) s = env_get("fastboot_bootcmd"); if (s) { run_command(s, CMD_FLAG_ENV); - } else { + } else if (IS_ENABLED(CONFIG_CMD_BOOTM)) { static char boot_addr_start[20]; static char *const bootm_args[] = { "bootm", boot_addr_start, NULL diff --git a/drivers/firmware/firmware-zynqmp.c b/drivers/firmware/firmware-zynqmp.c index dc8e3ad..ab4c4f1 100644 --- a/drivers/firmware/firmware-zynqmp.c +++ b/drivers/firmware/firmware-zynqmp.c @@ -23,10 +23,10 @@ #define XST_PM_NO_ACCESS 2002L #define XST_PM_ALREADY_CONFIGURED 2009L -struct zynqmp_power { +static struct zynqmp_power { struct mbox_chan tx_chan; struct mbox_chan rx_chan; -} zynqmp_power = {}; +} zynqmp_power __section(".data"); #define NODE_ID_LOCATION 5 @@ -63,29 +63,32 @@ static unsigned int xpm_configobject_close[] = { int zynqmp_pmufw_config_close(void) { - zynqmp_pmufw_load_config_object(xpm_configobject_close, - sizeof(xpm_configobject_close)); - return 0; + return zynqmp_pmufw_load_config_object(xpm_configobject_close, + sizeof(xpm_configobject_close)); } int zynqmp_pmufw_node(u32 id) { - static bool skip_config; - int ret; + static bool check = true; + static bool permission = true; + + if (check) { + check = false; + + if (zynqmp_pmufw_node(NODE_OCM_BANK_0) == -EACCES) { + printf("PMUFW: No permission to change config object\n"); + permission = false; + } + } - if (skip_config) + if (!permission) return 0; /* Record power domain id */ xpm_configobject[NODE_ID_LOCATION] = id; - ret = zynqmp_pmufw_load_config_object(xpm_configobject, - sizeof(xpm_configobject)); - - if (ret == XST_PM_NO_ACCESS && id == NODE_OCM_BANK_0) - skip_config = true; - - return 0; + return zynqmp_pmufw_load_config_object(xpm_configobject, + sizeof(xpm_configobject)); } static int do_pm_probe(void) @@ -235,8 +238,7 @@ int zynqmp_pm_is_function_supported(const u32 api_id, const u32 id) * * @cfg_obj: Pointer to the configuration object * @size: Size of @cfg_obj in bytes - * Return: 0 on success otherwise negative errno. If the config object - * is not loadable returns positive errno XST_PM_NO_ACCESS(2002) + * Return: 0 on success otherwise negative errno. */ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) { @@ -251,10 +253,6 @@ int zynqmp_pmufw_load_config_object(const void *cfg_obj, size_t size) err = xilinx_pm_request(PM_SET_CONFIGURATION, (u32)(u64)cfg_obj, 0, 0, 0, ret_payload); if (err == XST_PM_NO_ACCESS) { - if (((u32 *)cfg_obj)[NODE_ID_LOCATION] == NODE_OCM_BANK_0) { - printf("PMUFW: No permission to change config object\n"); - return err; - } return -EACCES; } @@ -298,9 +296,6 @@ static int zynqmp_power_probe(struct udevice *dev) ret >> ZYNQMP_PM_VERSION_MAJOR_SHIFT, ret & ZYNQMP_PM_VERSION_MINOR_MASK); - if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) - zynqmp_pmufw_node(NODE_OCM_BANK_0); - return 0; }; @@ -320,7 +315,8 @@ U_BOOT_DRIVER(zynqmp_power) = { int __maybe_unused xilinx_pm_request(u32 api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3, u32 *ret_payload) { - debug("%s at EL%d, API ID: 0x%0x\n", __func__, current_el(), api_id); + debug("%s at EL%d, API ID: 0x%0x, 0x%0x, 0x%0x, 0x%0x, 0x%0x\n", + __func__, current_el(), api_id, arg0, arg1, arg2, arg3); if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { #if defined(CONFIG_ZYNQMP_IPI) @@ -398,7 +394,7 @@ static int zynqmp_firmware_bind(struct udevice *dev) } } - return dm_scan_fdt_dev(dev); + return 0; } U_BOOT_DRIVER(zynqmp_firmware) = { diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index bd7379a..72f572d 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -265,7 +265,7 @@ static int ti_sci_do_xfer(struct ti_sci_info *info, if (xfer->rx_len) { ret = ti_sci_get_response(info, xfer, &info->chan_rx); if (!ti_sci_is_response_ack(xfer->tx_message.buf)) { - dev_err(info->dev, "Message not acknowledged"); + dev_err(info->dev, "Message not acknowledged\n"); ret = -ENODEV; } } diff --git a/drivers/fwu-mdata/Kconfig b/drivers/fwu-mdata/Kconfig index 36c4479..42736a5 100644 --- a/drivers/fwu-mdata/Kconfig +++ b/drivers/fwu-mdata/Kconfig @@ -6,6 +6,11 @@ config FWU_MDATA FWU Metadata partitions reside on the same storage device which contains the other FWU updatable firmware images. +choice + prompt "Storage Layout Scheme" + depends on FWU_MDATA + default FWU_MDATA_GPT_BLK + config FWU_MDATA_GPT_BLK bool "FWU Metadata access for GPT partitioned Block devices" select PARTITION_TYPE_GUID @@ -14,3 +19,13 @@ config FWU_MDATA_GPT_BLK help Enable support for accessing FWU Metadata on GPT partitioned block devices. + +config FWU_MDATA_MTD + bool "Raw MTD devices" + depends on MTD + help + Enable support for accessing FWU Metadata on non-partitioned + (or non-GPT partitioned, e.g. partition nodes in devicetree) + MTD devices. + +endchoice diff --git a/drivers/fwu-mdata/Makefile b/drivers/fwu-mdata/Makefile index 3fee64c..06c4974 100644 --- a/drivers/fwu-mdata/Makefile +++ b/drivers/fwu-mdata/Makefile @@ -6,3 +6,4 @@ obj-$(CONFIG_FWU_MDATA) += fwu-mdata-uclass.o obj-$(CONFIG_FWU_MDATA_GPT_BLK) += gpt_blk.o +obj-$(CONFIG_FWU_MDATA_MTD) += raw_mtd.o diff --git a/drivers/fwu-mdata/fwu-mdata-uclass.c b/drivers/fwu-mdata/fwu-mdata-uclass.c index b477e96..0a8edaa 100644 --- a/drivers/fwu-mdata/fwu-mdata-uclass.c +++ b/drivers/fwu-mdata/fwu-mdata-uclass.c @@ -14,170 +14,39 @@ #include <linux/errno.h> #include <linux/types.h> -#include <u-boot/crc.h> /** - * fwu_get_mdata_part_num() - Get the FWU metadata partition numbers - * @dev: FWU metadata device - * @mdata_parts: array for storing the metadata partition numbers - * - * Get the partition numbers on the storage device on which the - * FWU metadata is stored. Two partition numbers will be returned. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_get_mdata_part_num(struct udevice *dev, uint *mdata_parts) -{ - const struct fwu_mdata_ops *ops = device_get_ops(dev); - - if (!ops->get_mdata_part_num) { - log_debug("get_mdata_part_num() method not defined\n"); - return -ENOSYS; - } - - return ops->get_mdata_part_num(dev, mdata_parts); -} - -/** - * fwu_read_mdata_partition() - Read the FWU metadata from a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number from which FWU metadata is to be read - * - * Read the FWU metadata from the specified partition number - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_read_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata, - uint part_num) -{ - const struct fwu_mdata_ops *ops = device_get_ops(dev); - - if (!ops->read_mdata_partition) { - log_debug("read_mdata_partition() method not defined\n"); - return -ENOSYS; - } - - return ops->read_mdata_partition(dev, mdata, part_num); -} - -/** - * fwu_write_mdata_partition() - Write the FWU metadata to a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number to which FWU metadata is to be written - * - * Write the FWU metadata to the specified partition number - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_write_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata, - uint part_num) -{ - const struct fwu_mdata_ops *ops = device_get_ops(dev); - - if (!ops->write_mdata_partition) { - log_debug("write_mdata_partition() method not defined\n"); - return -ENOSYS; - } - - return ops->write_mdata_partition(dev, mdata, part_num); -} - -/** - * fwu_mdata_check() - Check if the FWU metadata is valid - * @dev: FWU metadata device - * - * Validate both copies of the FWU metadata. If one of the copies - * has gone bad, restore it from the other copy. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_mdata_check(struct udevice *dev) -{ - const struct fwu_mdata_ops *ops = device_get_ops(dev); - - if (!ops->check_mdata) { - log_debug("check_mdata() method not defined\n"); - return -ENOSYS; - } - - return ops->check_mdata(dev); -} - -/** - * fwu_get_mdata() - Get a FWU metadata copy - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * - * Get a valid copy of the FWU metadata. - * - * Note: This function is to be called first when modifying any fields - * in the metadata. The sequence of calls to modify any field in the - * metadata would be 1) fwu_get_mdata 2) Modify metadata, followed by - * 3) fwu_update_mdata + * fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata() * * Return: 0 if OK, -ve on error - * */ -int fwu_get_mdata(struct udevice *dev, struct fwu_mdata *mdata) +int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) { const struct fwu_mdata_ops *ops = device_get_ops(dev); - if (!ops->get_mdata) { - log_debug("get_mdata() method not defined\n"); + if (!ops->read_mdata) { + log_debug("read_mdata() method not defined\n"); return -ENOSYS; } - return ops->get_mdata(dev, mdata); + return ops->read_mdata(dev, mdata, primary); } /** - * fwu_update_mdata() - Update the FWU metadata - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * - * Update the FWU metadata structure by writing to the - * FWU metadata partitions. - * - * Note: This function is not to be called directly to update the - * metadata fields. The sequence of function calls should be - * 1) fwu_get_mdata() 2) Modify the medata fields 3) fwu_update_mdata() - * - * The sequence of updating the partitions should be, update the - * primary metadata partition (first partition encountered), followed - * by updating the secondary partition. With this update sequence, in - * the rare scenario that the two metadata partitions are valid but do - * not match, maybe due to power outage at the time of updating the - * metadata copies, the secondary partition can be updated from the - * primary. + * fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata() * * Return: 0 if OK, -ve on error - * */ -int fwu_update_mdata(struct udevice *dev, struct fwu_mdata *mdata) +int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) { - void *buf; const struct fwu_mdata_ops *ops = device_get_ops(dev); - if (!ops->update_mdata) { - log_debug("get_mdata() method not defined\n"); + if (!ops->write_mdata) { + log_debug("write_mdata() method not defined\n"); return -ENOSYS; } - /* - * Calculate the crc32 for the updated FWU metadata - * and put the updated value in the FWU metadata crc32 - * field - */ - buf = &mdata->version; - mdata->crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32)); - - return ops->update_mdata(dev, mdata); + return ops->write_mdata(dev, mdata, primary); } UCLASS_DRIVER(fwu_mdata) = { diff --git a/drivers/fwu-mdata/gpt_blk.c b/drivers/fwu-mdata/gpt_blk.c index d35ce49..c728491 100644 --- a/drivers/fwu-mdata/gpt_blk.c +++ b/drivers/fwu-mdata/gpt_blk.c @@ -24,38 +24,40 @@ enum { MDATA_WRITE, }; -static int gpt_get_mdata_partitions(struct blk_desc *desc, - uint mdata_parts[2]) +static uint g_mdata_part[2]; /* = {0, 0} to check against uninit parts */ + +static int gpt_get_mdata_partitions(struct blk_desc *desc) { - int i, ret; + int i; u32 nparts; efi_guid_t part_type_guid; struct disk_partition info; const efi_guid_t fwu_mdata_guid = FWU_MDATA_GUID; + /* if primary and secondary partitions already found */ + if (g_mdata_part[0] && g_mdata_part[1]) + return 0; + nparts = 0; - for (i = 1; i < MAX_SEARCH_PARTITIONS; i++) { + for (i = 1; i < MAX_SEARCH_PARTITIONS && nparts < 2; i++) { if (part_get_info(desc, i, &info)) continue; uuid_str_to_bin(info.type_guid, part_type_guid.b, UUID_STR_FORMAT_GUID); - if (!guidcmp(&fwu_mdata_guid, &part_type_guid)) { - if (nparts < 2) - mdata_parts[nparts] = i; - ++nparts; - } + if (!guidcmp(&fwu_mdata_guid, &part_type_guid)) + g_mdata_part[nparts++] = i; } if (nparts != 2) { log_debug("Expect two copies of the FWU metadata instead of %d\n", nparts); - ret = -EINVAL; - } else { - ret = 0; + g_mdata_part[0] = 0; + g_mdata_part[1] = 0; + return -EINVAL; } - return ret; + return 0; } static int gpt_get_mdata_disk_part(struct blk_desc *desc, @@ -123,112 +125,6 @@ static int gpt_read_write_mdata(struct blk_desc *desc, return 0; } -static int fwu_gpt_update_mdata(struct udevice *dev, struct fwu_mdata *mdata) -{ - int ret; - struct blk_desc *desc; - uint mdata_parts[2]; - struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); - - desc = dev_get_uclass_plat(priv->blk_dev); - - ret = gpt_get_mdata_partitions(desc, mdata_parts); - if (ret < 0) { - log_debug("Error getting the FWU metadata partitions\n"); - return -ENOENT; - } - - /* First write the primary partition */ - ret = gpt_read_write_mdata(desc, mdata, MDATA_WRITE, mdata_parts[0]); - if (ret < 0) { - log_debug("Updating primary FWU metadata partition failed\n"); - return ret; - } - - /* And now the replica */ - ret = gpt_read_write_mdata(desc, mdata, MDATA_WRITE, mdata_parts[1]); - if (ret < 0) { - log_debug("Updating secondary FWU metadata partition failed\n"); - return ret; - } - - return 0; -} - -static int gpt_get_mdata(struct blk_desc *desc, struct fwu_mdata *mdata) -{ - int ret; - uint mdata_parts[2]; - - ret = gpt_get_mdata_partitions(desc, mdata_parts); - - if (ret < 0) { - log_debug("Error getting the FWU metadata partitions\n"); - return -ENOENT; - } - - ret = gpt_read_write_mdata(desc, mdata, MDATA_READ, mdata_parts[0]); - if (ret < 0) { - log_debug("Failed to read the FWU metadata from the device\n"); - return -EIO; - } - - ret = fwu_verify_mdata(mdata, 1); - if (!ret) - return 0; - - /* - * Verification of the primary FWU metadata copy failed. - * Try to read the replica. - */ - memset(mdata, '\0', sizeof(struct fwu_mdata)); - ret = gpt_read_write_mdata(desc, mdata, MDATA_READ, mdata_parts[1]); - if (ret < 0) { - log_debug("Failed to read the FWU metadata from the device\n"); - return -EIO; - } - - ret = fwu_verify_mdata(mdata, 0); - if (!ret) - return 0; - - /* Both the FWU metadata copies are corrupted. */ - return -EIO; -} - -static int fwu_gpt_get_mdata(struct udevice *dev, struct fwu_mdata *mdata) -{ - struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); - - return gpt_get_mdata(dev_get_uclass_plat(priv->blk_dev), mdata); -} - -static int fwu_gpt_get_mdata_partitions(struct udevice *dev, uint *mdata_parts) -{ - struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); - - return gpt_get_mdata_partitions(dev_get_uclass_plat(priv->blk_dev), - mdata_parts); -} - -static int fwu_gpt_read_mdata_partition(struct udevice *dev, - struct fwu_mdata *mdata, uint part_num) -{ - struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); - - return gpt_read_write_mdata(dev_get_uclass_plat(priv->blk_dev), - mdata, MDATA_READ, part_num); -} - -static int fwu_gpt_write_mdata_partition(struct udevice *dev, - struct fwu_mdata *mdata, uint part_num) -{ - struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); - - return gpt_read_write_mdata(dev_get_uclass_plat(priv->blk_dev), - mdata, MDATA_WRITE, part_num); -} - static int fwu_get_mdata_device(struct udevice *dev, struct udevice **mdata_dev) { u32 phandle; @@ -267,12 +163,43 @@ static int fwu_mdata_gpt_blk_probe(struct udevice *dev) return 0; } +static int fwu_gpt_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, + bool primary) +{ + struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); + struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev); + int ret; + + ret = gpt_get_mdata_partitions(desc); + if (ret < 0) { + log_debug("Error getting the FWU metadata partitions\n"); + return -ENOENT; + } + + return gpt_read_write_mdata(desc, mdata, MDATA_READ, + primary ? g_mdata_part[0] : g_mdata_part[1]); +} + +static int fwu_gpt_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, + bool primary) +{ + struct fwu_mdata_gpt_blk_priv *priv = dev_get_priv(dev); + struct blk_desc *desc = dev_get_uclass_plat(priv->blk_dev); + int ret; + + ret = gpt_get_mdata_partitions(desc); + if (ret < 0) { + log_debug("Error getting the FWU metadata partitions\n"); + return -ENOENT; + } + + return gpt_read_write_mdata(desc, mdata, MDATA_WRITE, + primary ? g_mdata_part[0] : g_mdata_part[1]); +} + static const struct fwu_mdata_ops fwu_gpt_blk_ops = { - .get_mdata = fwu_gpt_get_mdata, - .update_mdata = fwu_gpt_update_mdata, - .get_mdata_part_num = fwu_gpt_get_mdata_partitions, - .read_mdata_partition = fwu_gpt_read_mdata_partition, - .write_mdata_partition = fwu_gpt_write_mdata_partition, + .read_mdata = fwu_gpt_read_mdata, + .write_mdata = fwu_gpt_write_mdata, }; static const struct udevice_id fwu_mdata_ids[] = { diff --git a/drivers/fwu-mdata/raw_mtd.c b/drivers/fwu-mdata/raw_mtd.c new file mode 100644 index 0000000..17e4517 --- /dev/null +++ b/drivers/fwu-mdata/raw_mtd.c @@ -0,0 +1,269 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023, Linaro Limited + */ + +#define LOG_CATEGORY UCLASS_FWU_MDATA + +#include <fwu.h> +#include <fwu_mdata.h> +#include <memalign.h> + +#include <linux/errno.h> +#include <linux/types.h> + +/* Internal helper structure to move data around */ +struct fwu_mdata_mtd_priv { + struct mtd_info *mtd; + char pri_label[50]; + char sec_label[50]; + u32 pri_offset; + u32 sec_offset; +}; + +enum fwu_mtd_op { + FWU_MTD_READ, + FWU_MTD_WRITE, +}; + +extern struct fwu_mtd_image_info fwu_mtd_images[]; + +static bool mtd_is_aligned_with_block_size(struct mtd_info *mtd, u64 size) +{ + return !do_div(size, mtd->erasesize); +} + +static int mtd_io_data(struct mtd_info *mtd, u32 offs, u32 size, void *data, + enum fwu_mtd_op op) +{ + struct mtd_oob_ops io_op = {}; + u64 lock_len; + size_t len; + void *buf; + int ret; + + if (!mtd_is_aligned_with_block_size(mtd, offs)) { + log_err("Offset unaligned with a block (0x%x)\n", mtd->erasesize); + return -EINVAL; + } + + /* This will expand erase size to align with the block size */ + lock_len = round_up(size, mtd->erasesize); + + ret = mtd_unlock(mtd, offs, lock_len); + if (ret && ret != -EOPNOTSUPP) + return ret; + + if (op == FWU_MTD_WRITE) { + struct erase_info erase_op = {}; + + erase_op.mtd = mtd; + erase_op.addr = offs; + erase_op.len = lock_len; + erase_op.scrub = 0; + + ret = mtd_erase(mtd, &erase_op); + if (ret) + goto lock; + } + + /* Also, expand the write size to align with the write size */ + len = round_up(size, mtd->writesize); + + buf = memalign(ARCH_DMA_MINALIGN, len); + if (!buf) { + ret = -ENOMEM; + goto lock; + } + memset(buf, 0xff, len); + + io_op.mode = MTD_OPS_AUTO_OOB; + io_op.len = len; + io_op.datbuf = buf; + + if (op == FWU_MTD_WRITE) { + memcpy(buf, data, size); + ret = mtd_write_oob(mtd, offs, &io_op); + } else { + ret = mtd_read_oob(mtd, offs, &io_op); + if (!ret) + memcpy(data, buf, size); + } + free(buf); + +lock: + mtd_lock(mtd, offs, lock_len); + + return ret; +} + +static int fwu_mtd_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) +{ + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); + struct mtd_info *mtd = mtd_priv->mtd; + u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset; + + return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_READ); +} + +static int fwu_mtd_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary) +{ + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); + struct mtd_info *mtd = mtd_priv->mtd; + u32 offs = primary ? mtd_priv->pri_offset : mtd_priv->sec_offset; + + return mtd_io_data(mtd, offs, sizeof(struct fwu_mdata), mdata, FWU_MTD_WRITE); +} + +static int flash_partition_offset(struct udevice *dev, const char *part_name, fdt_addr_t *offset) +{ + ofnode node, parts_node; + fdt_addr_t size = 0; + + parts_node = ofnode_by_compatible(dev_ofnode(dev), "fixed-partitions"); + node = ofnode_by_prop_value(parts_node, "label", part_name, strlen(part_name) + 1); + if (!ofnode_valid(node)) { + log_err("Warning: Failed to find partition by label <%s>\n", part_name); + return -ENOENT; + } + + *offset = ofnode_get_addr_size_index_notrans(node, 0, &size); + + return (int)size; +} + +static int fwu_mdata_mtd_of_to_plat(struct udevice *dev) +{ + struct fwu_mdata_mtd_priv *mtd_priv = dev_get_priv(dev); + const fdt32_t *phandle_p = NULL; + struct udevice *mtd_dev; + struct mtd_info *mtd; + const char *label; + fdt_addr_t offset; + int ret, size; + u32 phandle; + ofnode bank; + int off_img; + + /* Find the FWU mdata storage device */ + phandle_p = ofnode_get_property(dev_ofnode(dev), + "fwu-mdata-store", &size); + if (!phandle_p) { + log_err("FWU meta data store not defined in device-tree\n"); + return -ENOENT; + } + + phandle = fdt32_to_cpu(*phandle_p); + + ret = device_get_global_by_ofnode(ofnode_get_by_phandle(phandle), + &mtd_dev); + if (ret) { + log_err("FWU: failed to get mtd device\n"); + return ret; + } + + mtd_probe_devices(); + + mtd_for_each_device(mtd) { + if (mtd->dev == mtd_dev) { + mtd_priv->mtd = mtd; + log_debug("Found the FWU mdata mtd device %s\n", mtd->name); + break; + } + } + if (!mtd_priv->mtd) { + log_err("Failed to find mtd device by fwu-mdata-store\n"); + return -ENODEV; + } + + /* Get the offset of primary and secondary mdata */ + ret = ofnode_read_string_index(dev_ofnode(dev), "mdata-parts", 0, &label); + if (ret) + return ret; + strncpy(mtd_priv->pri_label, label, 50); + + ret = flash_partition_offset(mtd_dev, mtd_priv->pri_label, &offset); + if (ret <= 0) + return ret; + mtd_priv->pri_offset = offset; + + ret = ofnode_read_string_index(dev_ofnode(dev), "mdata-parts", 1, &label); + if (ret) + return ret; + strncpy(mtd_priv->sec_label, label, 50); + + ret = flash_partition_offset(mtd_dev, mtd_priv->sec_label, &offset); + if (ret <= 0) + return ret; + mtd_priv->sec_offset = offset; + + off_img = 0; + + ofnode_for_each_subnode(bank, dev_ofnode(dev)) { + int bank_num, bank_offset, bank_size; + const char *bank_name; + ofnode image; + + ofnode_read_u32(bank, "id", &bank_num); + bank_name = ofnode_read_string(bank, "label"); + bank_size = flash_partition_offset(mtd_dev, bank_name, &offset); + if (bank_size <= 0) + return bank_size; + bank_offset = offset; + log_debug("Bank%d: %s [0x%x - 0x%x]\n", + bank_num, bank_name, bank_offset, bank_offset + bank_size); + + ofnode_for_each_subnode(image, bank) { + int image_num, image_offset, image_size; + const char *uuid; + + if (off_img == CONFIG_FWU_NUM_BANKS * + CONFIG_FWU_NUM_IMAGES_PER_BANK) { + log_err("DT provides more images than configured!\n"); + break; + } + + uuid = ofnode_read_string(image, "uuid"); + ofnode_read_u32(image, "id", &image_num); + ofnode_read_u32(image, "offset", &image_offset); + ofnode_read_u32(image, "size", &image_size); + + fwu_mtd_images[off_img].start = bank_offset + image_offset; + fwu_mtd_images[off_img].size = image_size; + fwu_mtd_images[off_img].bank_num = bank_num; + fwu_mtd_images[off_img].image_num = image_num; + strcpy(fwu_mtd_images[off_img].uuidbuf, uuid); + log_debug("\tImage%d: %s @0x%x\n\n", + image_num, uuid, bank_offset + image_offset); + off_img++; + } + } + + return 0; +} + +static int fwu_mdata_mtd_probe(struct udevice *dev) +{ + /* Ensure the metadata can be read. */ + return fwu_get_mdata(NULL); +} + +static struct fwu_mdata_ops fwu_mtd_ops = { + .read_mdata = fwu_mtd_read_mdata, + .write_mdata = fwu_mtd_write_mdata, +}; + +static const struct udevice_id fwu_mdata_ids[] = { + { .compatible = "u-boot,fwu-mdata-mtd" }, + { } +}; + +U_BOOT_DRIVER(fwu_mdata_mtd) = { + .name = "fwu-mdata-mtd", + .id = UCLASS_FWU_MDATA, + .of_match = fwu_mdata_ids, + .ops = &fwu_mtd_ops, + .probe = fwu_mdata_mtd_probe, + .of_to_plat = fwu_mdata_mtd_of_to_plat, + .priv_auto = sizeof(struct fwu_mdata_mtd_priv), +}; diff --git a/drivers/gpio/gpio-fxl6408.c b/drivers/gpio/gpio-fxl6408.c index 902da05..ca7aa14 100644 --- a/drivers/gpio/gpio-fxl6408.c +++ b/drivers/gpio/gpio-fxl6408.c @@ -27,7 +27,7 @@ * https://patchwork.kernel.org/patch/9148419/ * - the Toradex version by Max Krummenacher <max.krummenacher@toradex.com>: * http://git.toradex.com/cgit/linux-toradex.git/tree/drivers/gpio/gpio-fxl6408.c?h=toradex_5.4-2.3.x-imx - * - the U-boot PCA953x driver by Peng Fan <van.freenix@gmail.com>: + * - the U-Boot PCA953x driver by Peng Fan <van.freenix@gmail.com>: * drivers/gpio/pca953x_gpio.c * * TODO: diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c index 9ffb4a5..d6cfbd2 100644 --- a/drivers/gpio/gpio-rcar.c +++ b/drivers/gpio/gpio-rcar.c @@ -130,20 +130,9 @@ static int rcar_gpio_get_function(struct udevice *dev, unsigned offset) return GPIOF_INPUT; } -static int rcar_gpio_request(struct udevice *dev, unsigned offset, - const char *label) -{ - return pinctrl_gpio_request(dev, offset, label); -} - -static int rcar_gpio_free(struct udevice *dev, unsigned offset) -{ - return pinctrl_gpio_free(dev, offset); -} - static const struct dm_gpio_ops rcar_gpio_ops = { - .request = rcar_gpio_request, - .rfree = rcar_gpio_free, + .request = pinctrl_gpio_request, + .rfree = pinctrl_gpio_free, .direction_input = rcar_gpio_direction_input, .direction_output = rcar_gpio_direction_output, .get_value = rcar_gpio_get_value, diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c index 8afd57f..98e5dc7 100644 --- a/drivers/gpio/npcm_gpio.c +++ b/drivers/gpio/npcm_gpio.c @@ -37,14 +37,14 @@ static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset, { struct npcm_gpio_priv *priv = dev_get_priv(dev); - clrbits_le32(priv->base + GPIO_IEM, BIT(offset)); - writel(BIT(offset), priv->base + GPIO_OES); - if (value) setbits_le32(priv->base + GPIO_DOUT, BIT(offset)); else clrbits_le32(priv->base + GPIO_DOUT, BIT(offset)); + clrbits_le32(priv->base + GPIO_IEM, BIT(offset)); + writel(BIT(offset), priv->base + GPIO_OES); + return 0; } diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index 05b14d2..5e81698 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -744,7 +744,6 @@ config SYS_I2C_SPEED config SYS_I2C_BUS_MAX int "Max I2C busses" depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA - default 2 if TI816X default 3 if OMAP34XX || AM33XX || AM43XX default 4 if ARCH_SOCFPGA || OMAP44XX default 5 if OMAP54XX diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c index 1af6af8..72c1076 100644 --- a/drivers/mmc/mmc.c +++ b/drivers/mmc/mmc.c @@ -2262,7 +2262,7 @@ static int mmc_startup_v4(struct mmc *mmc) return 0; if (!mmc->ext_csd) - memset(ext_csd_bkup, 0, sizeof(ext_csd_bkup)); + memset(ext_csd_bkup, 0, MMC_MAX_BLOCK_LEN); err = mmc_send_ext_csd(mmc, ext_csd); if (err) diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index e44868a..e779251 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -873,7 +873,7 @@ static int arasan_sdhci_set_tapdelay(struct sdhci_host *host) if (ret) return ret; } else if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) && - device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) { + device_is_compatible(dev, "xlnx,versal-net-emmc")) { if (mmc->clock >= MIN_PHY_CLK_HZ) if (iclk_phase == VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLY_CHAIN) iclk_phase = VERSAL_NET_EMMC_ICLK_PHASE_DDR52_DLL; @@ -948,7 +948,7 @@ static void arasan_dt_parse_clk_phases(struct udevice *dev) } if (IS_ENABLED(CONFIG_ARCH_VERSAL_NET) && - device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) { + device_is_compatible(dev, "xlnx,versal-net-emmc")) { for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { clk_data->clk_phase_in[i] = versal_net_emmc_iclk_phases[i]; clk_data->clk_phase_out[i] = versal_net_emmc_oclk_phases[i]; @@ -1102,7 +1102,7 @@ static int arasan_sdhci_probe(struct udevice *dev) } } #endif - if (device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) + if (device_is_compatible(dev, "xlnx,versal-net-emmc")) priv->internal_phy_reg = true; ret = clk_get_by_index(dev, 0, &clk); @@ -1136,7 +1136,7 @@ static int arasan_sdhci_probe(struct udevice *dev) host->quirks |= SDHCI_QUIRK_NO_1_8_V; if (CONFIG_IS_ENABLED(ARCH_VERSAL_NET) && - device_is_compatible(dev, "xlnx,versal-net-5.1-emmc")) + device_is_compatible(dev, "xlnx,versal-net-emmc")) host->quirks |= SDHCI_QUIRK_CAPS_BIT63_FOR_HS400; plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ; @@ -1219,7 +1219,7 @@ static int arasan_sdhci_bind(struct udevice *dev) static const struct udevice_id arasan_sdhci_ids[] = { { .compatible = "arasan,sdhci-8.9a" }, - { .compatible = "xlnx,versal-net-5.1-emmc" }, + { .compatible = "xlnx,versal-net-emmc" }, { } }; diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index d115fcf..d624589 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -553,7 +553,7 @@ config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS bool "Enable use of 1st stage bootloader timing for NAND" depends on NAND_ZYNQ help - This flag prevent U-boot reconfigure NAND flash controller and reuse + This flag prevent U-Boot reconfigure NAND flash controller and reuse the NAND timing from 1st stage bootloader. config NAND_OCTEONTX @@ -732,10 +732,10 @@ config SYS_NAND_BAD_BLOCK_POS default 5 if HAS_NAND_SMALL_BADBLOCK_POS config SYS_NAND_U_BOOT_LOCATIONS - bool "Define U-boot binaries locations in NAND" + bool "Define U-Boot binaries locations in NAND" help Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig. - This option should not be enabled when compiling U-boot for boards + This option should not be enabled when compiling U-Boot for boards defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h file. diff --git a/drivers/mtd/nand/raw/fsl_ifc_spl.c b/drivers/mtd/nand/raw/fsl_ifc_spl.c index 60a865b..c67065e 100644 --- a/drivers/mtd/nand/raw/fsl_ifc_spl.c +++ b/drivers/mtd/nand/raw/fsl_ifc_spl.c @@ -275,8 +275,8 @@ void nand_boot(void) #ifdef CONFIG_CHAIN_OF_TRUST /* - * U-Boot header is appended at end of U-boot image, so - * calculate U-boot header address using U-boot header size. + * U-Boot header is appended at end of U-Boot image, so + * calculate U-Boot header address using U-Boot header size. */ #define FSL_U_BOOT_HDR_ADDR \ ((CFG_SYS_NAND_U_BOOT_START + \ diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 39eee98..d662dd3 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -696,6 +696,7 @@ config SUN8I_EMAC config SH_ETHER bool "Renesas SH Ethernet MAC" select PHYLIB + select PHY_ETHERNET_ID help This driver supports the Ethernet for Renesas SH and ARM SoCs. @@ -765,6 +766,7 @@ config RENESAS_RAVB bool "Renesas Ethernet AVB MAC" depends on RCAR_64 select PHYLIB + select PHY_ETHERNET_ID help This driver implements support for the Ethernet AVB block in Renesas M3 and H3 SoCs. diff --git a/drivers/net/altera_tse.c b/drivers/net/altera_tse.c index 912d28f..e234093 100644 --- a/drivers/net/altera_tse.c +++ b/drivers/net/altera_tse.c @@ -430,17 +430,11 @@ static int tse_mdio_init(const char *name, struct altera_tse_priv *priv) static int tse_phy_init(struct altera_tse_priv *priv, void *dev) { struct phy_device *phydev; - unsigned int mask = 0xffffffff; - if (priv->phyaddr) - mask = 1 << priv->phyaddr; - - phydev = phy_find_by_mask(priv->bus, mask); + phydev = phy_connect(priv->bus, -1, dev, priv->interface); if (!phydev) return -ENODEV; - phy_connect_dev(phydev, dev, priv->interface); - phydev->supported &= PHY_GBIT_FEATURES; phydev->advertising = phydev->supported; diff --git a/drivers/net/eth-phy-uclass.c b/drivers/net/eth-phy-uclass.c index 27b7744..9d1e8d3 100644 --- a/drivers/net/eth-phy-uclass.c +++ b/drivers/net/eth-phy-uclass.c @@ -144,10 +144,18 @@ static int eth_phy_of_to_plat(struct udevice *dev) uc_priv->reset_assert_delay = dev_read_u32_default(dev, "reset-assert-us", 0); uc_priv->reset_deassert_delay = dev_read_u32_default(dev, "reset-deassert-us", 0); + /* These are used by some DTs, try these as a fallback. */ + if (!uc_priv->reset_assert_delay && !uc_priv->reset_deassert_delay) { + uc_priv->reset_assert_delay = + dev_read_u32_default(dev, "reset-delay-us", 0); + uc_priv->reset_deassert_delay = + dev_read_u32_default(dev, "reset-post-delay-us", 0); + } + return 0; } -void eth_phy_reset(struct udevice *dev, int value) +static void eth_phy_reset(struct udevice *dev, int value) { struct eth_phy_device_priv *uc_priv = dev_get_uclass_priv(dev); u32 delay; diff --git a/drivers/net/ethoc.c b/drivers/net/ethoc.c index 29067e9..13fad81 100644 --- a/drivers/net/ethoc.c +++ b/drivers/net/ethoc.c @@ -608,18 +608,16 @@ static int ethoc_mdio_init(const char *name, struct ethoc *priv) static int ethoc_phy_init(struct ethoc *priv, void *dev) { struct phy_device *phydev; - int mask = 0xffffffff; + int mask = -1; #ifdef CONFIG_PHY_ADDR - mask = 1 << CONFIG_PHY_ADDR; + mask = CONFIG_PHY_ADDR; #endif - phydev = phy_find_by_mask(priv->bus, mask); + phydev = phy_connect(priv->bus, mask, dev, PHY_INTERFACE_MODE_MII); if (!phydev) return -ENODEV; - phy_connect_dev(phydev, dev, PHY_INTERFACE_MODE_MII); - phydev->supported &= PHY_BASIC_FEATURES; phydev->advertising = phydev->supported; diff --git a/drivers/net/fsl-mc/dpbp.c b/drivers/net/fsl-mc/dpbp.c index c609efb..5e17ccf 100644 --- a/drivers/net/fsl-mc/dpbp.c +++ b/drivers/net/fsl-mc/dpbp.c @@ -3,25 +3,40 @@ * Freescale Layerscape MC I/O wrapper * * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017-2023 NXP */ #include <fsl-mc/fsl_mc_sys.h> #include <fsl-mc/fsl_mc_cmd.h> #include <fsl-mc/fsl_dpbp.h> -int dpbp_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpbp_id, - uint16_t *token) +/** + * dpbp_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpbp_id: DPBP unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpbp_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpbp_id, u16 *token) { + struct dpbp_cmd_open *cmd_params; struct mc_command cmd = { 0 }; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_OPEN, - cmd_flags, - 0); - DPBP_CMD_OPEN(cmd, dpbp_id); + cmd_flags, 0); + cmd_params = (struct dpbp_cmd_open *)cmd.params; + cmd_params->dpbp_id = cpu_to_le32(dpbp_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -29,14 +44,23 @@ int dpbp_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return err; } -int dpbp_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpbp_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -48,11 +72,26 @@ int dpbp_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpbp_create(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - const struct dpbp_cfg *cfg, - uint32_t *obj_id) +/** + * dpbp_create() - Create the DPBP object. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: Returned object id; use in subsequent API calls + * + * Create the DPBP object, allocate required resources and + * perform required initialization. + * + * This function accepts an authentication token of a parent + * container that this object should be assigned to and returns + * an object id. This object_id will be used in all subsequent calls to + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpbp_cfg *cfg, u32 *obj_id) { struct mc_command cmd = { 0 }; int err; @@ -61,8 +100,7 @@ int dpbp_create(struct fsl_mc_io *mc_io, /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_CREATE, - cmd_flags, - dprc_token); + cmd_flags, dprc_token); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -70,33 +108,46 @@ int dpbp_create(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - MC_CMD_READ_OBJ_ID(cmd, *obj_id); + *obj_id = mc_cmd_read_object_id(&cmd); return 0; } -int dpbp_destroy(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - uint32_t obj_id) +/** + * dpbp_destroy() - Destroy the DPBP object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @obj_id: ID of DPBP object + * + * Return: '0' on Success; error code otherwise. + */ +int dpbp_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 obj_id) { + struct dpbp_cmd_destroy *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_DESTROY, - cmd_flags, - dprc_token); + cmd_flags, dprc_token); - /* set object id to destroy */ - CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id); + cmd_params = (struct dpbp_cmd_destroy *)cmd.params; + cmd_params->object_id = cpu_to_le32(obj_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpbp_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpbp_enable() - Enable the DPBP. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -108,48 +159,66 @@ int dpbp_enable(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpbp_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpbp_disable() - Disable the DPBP. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_DISABLE, - cmd_flags, - token); + cmd_flags, token); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpbp_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpbp_reset() - Reset the DPBP, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_RESET, - cmd_flags, - token); + cmd_flags, token); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpbp_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpbp_get_attributes - Retrieve DPBP attributes. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPBP object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpbp_attr *attr) { + struct dpbp_rsp_get_attributes *rsp_params; struct mc_command cmd = { 0 }; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPBP_CMDID_GET_ATTR, - cmd_flags, - token); + cmd_flags, token); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -157,15 +226,24 @@ int dpbp_get_attributes(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPBP_RSP_GET_ATTRIBUTES(cmd, attr); + rsp_params = (struct dpbp_rsp_get_attributes *)cmd.params; + attr->bpid = le16_to_cpu(rsp_params->bpid); + attr->id = le32_to_cpu(rsp_params->id); return 0; } -int dpbp_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dpbp_get_api_version - Get Data Path Buffer Pool API version + * @mc_io: Pointer to Mc portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: Major version of Buffer Pool API + * @minor_ver: Minor version of Buffer Pool API + * + * Return: '0' on Success; Error code otherwise. + */ +int dpbp_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; diff --git a/drivers/net/fsl-mc/dpio/dpio.c b/drivers/net/fsl-mc/dpio/dpio.c index 8884455..d17210b 100644 --- a/drivers/net/fsl-mc/dpio/dpio.c +++ b/drivers/net/fsl-mc/dpio/dpio.c @@ -1,18 +1,34 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #include <fsl-mc/fsl_mc_sys.h> #include <fsl-mc/fsl_mc_cmd.h> #include <fsl-mc/fsl_dpio.h> -int dpio_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint32_t dpio_id, - uint16_t *token) +/** + * dpio_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpio_id: DPIO unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpio_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and any MC portals + * assigned to the parent container; this token must be used in + * all subsequent commands for this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpio_id, + u16 *token) { + struct dpio_cmd_open *cmd_params; struct mc_command cmd = { 0 }; int err; @@ -20,7 +36,8 @@ int dpio_open(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPIO_CMDID_OPEN, cmd_flags, 0); - DPIO_CMD_OPEN(cmd, dpio_id); + cmd_params = (struct dpio_cmd_open *)cmd.params; + cmd_params->dpio_id = cpu_to_le32(dpio_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -28,14 +45,20 @@ int dpio_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return 0; } -int dpio_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpio_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -48,12 +71,32 @@ int dpio_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpio_create(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - const struct dpio_cfg *cfg, - uint32_t *obj_id) +/** + * dpio_create() - Create the DPIO object. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: Returned object id + * + * Create the DPIO object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * The function accepts an authentication token of a parent + * container that this object should be assigned to. The token + * can be '0' so the object will be assigned to the default container. + * The newly created object can be opened with the returned + * object id and using the container's associated tokens and MC portals. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpio_cfg *cfg, u32 *obj_id) { + struct dpio_cmd_create *cmd_params; struct mc_command cmd = { 0 }; int err; @@ -61,7 +104,11 @@ int dpio_create(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPIO_CMDID_CREATE, cmd_flags, dprc_token); - DPIO_CMD_CREATE(cmd, cfg); + cmd_params = (struct dpio_cmd_create *)cmd.params; + cmd_params->num_priorities = cfg->num_priorities; + dpio_set_field(cmd_params->channel_mode, + CHANNEL_MODE, + cfg->channel_mode); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -69,33 +116,54 @@ int dpio_create(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - MC_CMD_READ_OBJ_ID(cmd, *obj_id); + *obj_id = mc_cmd_read_object_id(&cmd); return 0; } -int dpio_destroy(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - uint32_t obj_id) +/** + * dpio_destroy() - Destroy the DPIO object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @object_id: The object id; it must be a valid id within the container that + * created this object; + * + * The function accepts the authentication token of the parent container that + * created the object (not the one that currently owns the object). The object + * is searched within parent using the provided 'object_id'. + * All tokens to the object must be closed before calling destroy. + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id) { + struct dpio_cmd_destroy *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPIO_CMDID_DESTROY, - cmd_flags, - dprc_token); + cmd_flags, + dprc_token); /* set object id to destroy */ - CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id); + cmd_params = (struct dpio_cmd_destroy *)cmd.params; + cmd_params->dpio_id = cpu_to_le32(object_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpio_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpio_enable() - Enable the DPIO, allow I/O portal operations. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -108,9 +176,15 @@ int dpio_enable(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpio_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpio_disable() - Disable the DPIO, stop any I/O portal operation. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -123,26 +197,19 @@ int dpio_disable(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpio_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPIO_CMDID_RESET, - cmd_flags, - token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -int dpio_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpio_get_attributes() - Retrieve DPIO attributes + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPIO object + * @attr: Returned object's attributes + * + * Return: '0' on Success; Error code otherwise + */ +int dpio_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpio_attr *attr) { + struct dpio_rsp_get_attr *rsp_params; struct mc_command cmd = { 0 }; int err; @@ -157,29 +224,42 @@ int dpio_get_attributes(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPIO_RSP_GET_ATTR(cmd, attr); + rsp_params = (struct dpio_rsp_get_attr *)cmd.params; + attr->id = le32_to_cpu(rsp_params->id); + attr->qbman_portal_id = le16_to_cpu(rsp_params->qbman_portal_id); + attr->num_priorities = rsp_params->num_priorities; + attr->qbman_portal_ce_offset = le64_to_cpu(rsp_params->qbman_portal_ce_offset); + attr->qbman_portal_ci_offset = le64_to_cpu(rsp_params->qbman_portal_ci_offset); + attr->qbman_version = le32_to_cpu(rsp_params->qbman_version); + attr->clk = le32_to_cpu(rsp_params->clk); + attr->channel_mode = dpio_get_field(rsp_params->channel_mode, ATTR_CHANNEL_MODE); return 0; } -int dpio_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dpio_get_api_version() - Get Data Path I/O API version + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: Major version of data path i/o API + * @minor_ver: Minor version of data path i/o API + * + * Return: '0' on Success; Error code otherwise. + */ +int dpio_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; - /* prepare command */ cmd.header = mc_encode_cmd_header(DPIO_CMDID_GET_API_VERSION, - cmd_flags, 0); + cmd_flags, + 0); - /* send command to mc */ err = mc_send_command(mc_io, &cmd); if (err) return err; - /* retrieve response parameters */ mc_cmd_read_api_version(&cmd, major_ver, minor_ver); return 0; diff --git a/drivers/net/fsl-mc/dpmac.c b/drivers/net/fsl-mc/dpmac.c index 43a2ff4..5d4f6c6 100644 --- a/drivers/net/fsl-mc/dpmac.c +++ b/drivers/net/fsl-mc/dpmac.c @@ -11,19 +11,33 @@ #include <fsl-mc/fsl_mc_cmd.h> #include <fsl-mc/fsl_dpmac.h> -int dpmac_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpmac_id, - uint16_t *token) +/** + * dpmac_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpmac_id: DPMAC unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpmac_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpmac_id, u16 *token) { + struct dpmac_cmd_open *cmd_params; struct mc_command cmd = { 0 }; int err; /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN, - cmd_flags, - 0); - DPMAC_CMD_OPEN(cmd, dpmac_id); + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_OPEN, cmd_flags, 0); + cmd_params = (struct dpmac_cmd_open *)cmd.params; + cmd_params->dpmac_id = cpu_to_le32(dpmac_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -31,39 +45,63 @@ int dpmac_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return err; } -int dpmac_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpmac_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags, - token); + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CLOSE, cmd_flags, token); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpmac_create(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - const struct dpmac_cfg *cfg, - uint32_t *obj_id) +/** + * dpmac_create() - Create the DPMAC object. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: Returned object id + * + * Create the DPMAC object, allocate required resources and + * perform required initialization. + * + * The function accepts an authentication token of a parent + * container that this object should be assigned to. The token + * can be '0' so the object will be assigned to the default container. + * The newly created object can be opened with the returned + * object id and using the container's associated tokens and MC portals. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpmac_cfg *cfg, u32 *obj_id) { + struct dpmac_cmd_create *cmd_params; struct mc_command cmd = { 0 }; int err; /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE, - cmd_flags, - dprc_token); - DPMAC_CMD_CREATE(cmd, cfg); + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_CREATE, cmd_flags, dprc_token); + cmd_params = (struct dpmac_cmd_create *)cmd.params; + cmd_params->mac_id = cpu_to_le32(cfg->mac_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -71,142 +109,87 @@ int dpmac_create(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - MC_CMD_READ_OBJ_ID(cmd, *obj_id); + *obj_id = mc_cmd_read_object_id(&cmd); return 0; } -int dpmac_destroy(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - uint32_t obj_id) +/** + * dpmac_destroy() - Destroy the DPMAC object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @object_id: The object id; it must be a valid id within the container that + * created this object; + * + * The function accepts the authentication token of the parent container that + * created the object (not the one that currently owns the object). The object + * is searched within parent using the provided 'object_id'. + * All tokens to the object must be closed before calling destroy. + * + * Return: '0' on Success; error code otherwise. + */ +int dpmac_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id) { + struct dpmac_cmd_destroy *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_DESTROY, cmd_flags, dprc_token); - - /* set object id to destroy */ - CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -int dpmac_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_attr *attr) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_ATTR, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPMAC_RSP_GET_ATTRIBUTES(cmd, attr); - - return 0; -} - -int dpmac_mdio_read(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_mdio_cfg *cfg) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_READ, - cmd_flags, - token); - DPMAC_CMD_MDIO_READ(cmd, cfg); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPMAC_RSP_MDIO_READ(cmd, cfg->data); - - return 0; -} - -int dpmac_mdio_write(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_mdio_cfg *cfg) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_MDIO_WRITE, - cmd_flags, - token); - DPMAC_CMD_MDIO_WRITE(cmd, cfg); + cmd_params = (struct dpmac_cmd_destroy *)cmd.params; + cmd_params->dpmac_id = cpu_to_le32(object_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_link_cfg *cfg) -{ - struct mc_command cmd = { 0 }; - int err = 0; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_LINK_CFG, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - DPMAC_RSP_GET_LINK_CFG(cmd, cfg); - - return 0; -} - -int dpmac_set_link_state(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpmac_set_link_state() - Set the Ethernet link status + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @link_state: Link state configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_set_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpmac_link_state *link_state) { + struct dpmac_cmd_set_link_state *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ - cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE, - cmd_flags, - token); - DPMAC_CMD_SET_LINK_STATE(cmd, link_state); + cmd.header = mc_encode_cmd_header(DPMAC_CMDID_SET_LINK_STATE, cmd_flags, token); + cmd_params = (struct dpmac_cmd_set_link_state *)cmd.params; + cmd_params->options = cpu_to_le64(link_state->options); + cmd_params->rate = cpu_to_le32(link_state->rate); + cmd_params->up = dpmac_get_field(link_state->up, STATE); + dpmac_set_field(cmd_params->up, STATE_VALID, link_state->state_valid); + cmd_params->supported = cpu_to_le64(link_state->supported); + cmd_params->advertising = cpu_to_le64(link_state->advertising); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpmac_get_counter(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpmac_counter type, - uint64_t *counter) +/** + * dpmac_get_counter() - Read a specific DPMAC counter + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPMAC object + * @type: The requested counter + * @counter: Returned counter value + * + * Return: The requested counter; '0' otherwise. + */ +int dpmac_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpmac_counter type, uint64_t *counter) { + struct dpmac_cmd_get_counter *dpmac_cmd; + struct dpmac_rsp_get_counter *dpmac_rsp; struct mc_command cmd = { 0 }; int err = 0; @@ -214,36 +197,43 @@ int dpmac_get_counter(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_COUNTER, cmd_flags, token); - DPMAC_CMD_GET_COUNTER(cmd, type); + dpmac_cmd = (struct dpmac_cmd_get_counter *)cmd.params; + dpmac_cmd->type = type; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); if (err) return err; - DPMAC_RSP_GET_COUNTER(cmd, *counter); + dpmac_rsp = (struct dpmac_rsp_get_counter *)cmd.params; + *counter = le64_to_cpu(dpmac_rsp->counter); return 0; } -int dpmac_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dpmac_get_api_version() - Get Data Path MAC version + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: Major version of data path mac API + * @minor_ver: Minor version of data path mac API + * + * Return: '0' on Success; Error code otherwise. + */ +int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; - /* prepare command */ cmd.header = mc_encode_cmd_header(DPMAC_CMDID_GET_API_VERSION, - cmd_flags, 0); + cmd_flags, + 0); - /* send command to mc */ err = mc_send_command(mc_io, &cmd); if (err) return err; - /* retrieve response parameters */ mc_cmd_read_api_version(&cmd, major_ver, minor_ver); return 0; diff --git a/drivers/net/fsl-mc/dpmng.c b/drivers/net/fsl-mc/dpmng.c index 8314243..147ca6d 100644 --- a/drivers/net/fsl-mc/dpmng.c +++ b/drivers/net/fsl-mc/dpmng.c @@ -1,15 +1,24 @@ // SPDX-License-Identifier: GPL-2.0+ /* Copyright 2013-2015 Freescale Semiconductor Inc. + * Copyright 2023 NXP */ #include <fsl-mc/fsl_mc_sys.h> #include <fsl-mc/fsl_mc_cmd.h> #include <fsl-mc/fsl_dpmng.h> #include "fsl_dpmng_cmd.h" -int mc_get_version(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - struct mc_version *mc_ver_info) +/** + * mc_get_version() - Retrieves the Management Complex firmware + * version information + * @mc_io: Pointer to opaque I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @mc_ver_info: Returned version information structure + * + * Return: '0' on Success; Error code otherwise. + */ +int mc_get_version(struct fsl_mc_io *mc_io, uint32_t cmd_flags, struct mc_version *mc_ver_info) { + struct dpmng_rsp_get_version *rsp_params; struct mc_command cmd = { 0 }; int err; @@ -24,7 +33,10 @@ int mc_get_version(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPMNG_RSP_GET_VERSION(cmd, mc_ver_info); + rsp_params = (struct dpmng_rsp_get_version *)cmd.params; + mc_ver_info->revision = le32_to_cpu(rsp_params->revision); + mc_ver_info->major = le32_to_cpu(rsp_params->version_major); + mc_ver_info->minor = le32_to_cpu(rsp_params->version_minor); return 0; } diff --git a/drivers/net/fsl-mc/dpni.c b/drivers/net/fsl-mc/dpni.c index 5290be2..5b815a4 100644 --- a/drivers/net/fsl-mc/dpni.c +++ b/drivers/net/fsl-mc/dpni.c @@ -1,46 +1,43 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #include <fsl-mc/fsl_mc_sys.h> #include <fsl-mc/fsl_mc_cmd.h> #include <fsl-mc/fsl_dpni.h> -int dpni_prepare_cfg(const struct dpni_cfg *cfg, - uint8_t *cfg_buf) -{ - uint64_t *params = (uint64_t *)cfg_buf; - - DPNI_PREP_CFG(params, cfg); - - return 0; -} - -int dpni_extract_cfg(struct dpni_cfg *cfg, - const uint8_t *cfg_buf) -{ - uint64_t *params = (uint64_t *)cfg_buf; - - DPNI_EXT_CFG(params, cfg); - - return 0; -} - -int dpni_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpni_id, - uint16_t *token) +/** + * dpni_open() - Open a control session for the specified object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @dpni_id: DPNI unique ID + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpni_create() function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpni_id, u16 *token) { + struct dpni_cmd_open *cmd_params; struct mc_command cmd = { 0 }; + int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_OPEN, cmd_flags, 0); - DPNI_CMD_OPEN(cmd, dpni_id); + cmd_params = (struct dpni_cmd_open *)cmd.params; + cmd_params->dpni_id = cpu_to_le32(dpni_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -48,14 +45,23 @@ int dpni_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return 0; } -int dpni_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpni_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -68,12 +74,32 @@ int dpni_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpni_create(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - const struct dpni_cfg *cfg, - uint32_t *obj_id) +/** + * dpni_create() - Create the DPNI object + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @cfg: Configuration structure + * @obj_id: Returned object id + * + * Create the DPNI object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * + * The function accepts an authentication token of a parent + * container that this object should be assigned to. The token + * can be '0' so the object will be assigned to the default container. + * The newly created object can be opened with the returned + * object id and using the container's associated tokens and MC portals. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpni_cfg *cfg, u32 *obj_id) { + struct dpni_cmd_create *cmd_params; struct mc_command cmd = { 0 }; int err; @@ -81,7 +107,19 @@ int dpni_create(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPNI_CMDID_CREATE, cmd_flags, dprc_token); - DPNI_CMD_CREATE(cmd, cfg); + cmd_params = (struct dpni_cmd_create *)cmd.params; + cmd_params->options = cpu_to_le32(cfg->options); + cmd_params->num_queues = cfg->num_queues; + cmd_params->num_tcs = cfg->num_tcs; + cmd_params->mac_filter_entries = cfg->mac_filter_entries; + cmd_params->num_rx_tcs = cfg->num_rx_tcs; + cmd_params->vlan_filter_entries = cfg->vlan_filter_entries; + cmd_params->qos_entries = cfg->qos_entries; + cmd_params->fs_entries = cpu_to_le16(cfg->fs_entries); + cmd_params->num_cgs = cfg->num_cgs; + cmd_params->num_opr = cfg->num_opr; + cmd_params->dist_key_size = cfg->dist_key_size; + cmd_params->num_channels = cfg->num_channels; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -89,50 +127,94 @@ int dpni_create(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - MC_CMD_READ_OBJ_ID(cmd, *obj_id); + *obj_id = mc_cmd_read_object_id(&cmd); return 0; } -int dpni_destroy(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - uint32_t obj_id) +/** + * dpni_destroy() - Destroy the DPNI object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @dprc_token: Parent container token; '0' for default container + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @object_id: The object id; it must be a valid id within the container that + * created this object; + * + * The function accepts the authentication token of the parent container that + * created the object (not the one that currently owns the object). The object + * is searched within parent using the provided 'object_id'. + * All tokens to the object must be closed before calling destroy. + * + * Return: '0' on Success; error code otherwise. + */ +int dpni_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id) { + struct dpni_cmd_destroy *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_DESTROY, cmd_flags, dprc_token); - /* set object id to destroy */ - CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id); + cmd_params = (struct dpni_cmd_destroy *)cmd.params; + cmd_params->dpni_id = cpu_to_le32(object_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_set_pools(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpni_set_pools() - Set buffer pools configuration + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Buffer pools configuration + * + * mandatory for DPNI operation + * warning:Allowed only when DPNI is disabled + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_pools(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, const struct dpni_pools_cfg *cfg) { struct mc_command cmd = { 0 }; + struct dpni_cmd_set_pools *cmd_params; + int i; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_POOLS, cmd_flags, token); - DPNI_CMD_SET_POOLS(cmd, cfg); + cmd_params = (struct dpni_cmd_set_pools *)cmd.params; + cmd_params->num_dpbp = cfg->num_dpbp; + cmd_params->pool_options = cfg->pool_options; + for (i = 0; i < DPNI_MAX_DPBP; i++) { + cmd_params->pool[i].dpbp_id = + cpu_to_le16(cfg->pools[i].dpbp_id); + cmd_params->pool[i].priority_mask = + cfg->pools[i].priority_mask; + cmd_params->buffer_size[i] = + cpu_to_le16(cfg->pools[i].buffer_size); + cmd_params->backup_pool_mask |= + DPNI_BACKUP_POOL(cfg->pools[i].backup_pool, i); + } /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpni_enable() - Enable the DPNI, allow sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -145,9 +227,15 @@ int dpni_enable(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpni_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpni_disable() - Disable the DPNI, stop sending and receiving frames. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -160,9 +248,15 @@ int dpni_disable(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpni_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dpni_reset() - Reset the DPNI, returns the object to initial state. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -175,76 +269,121 @@ int dpni_reset(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpni_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpni_get_attributes() - Retrieve DPNI attributes. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @attr: Object's attributes + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpni_attr *attr) { struct mc_command cmd = { 0 }; + struct dpni_rsp_get_attr *rsp_params; + int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_ATTR, cmd_flags, token); + /* send command to mc*/ err = mc_send_command(mc_io, &cmd); if (err) return err; /* retrieve response parameters */ - DPNI_RSP_GET_ATTR(cmd, attr); + rsp_params = (struct dpni_rsp_get_attr *)cmd.params; + attr->options = le32_to_cpu(rsp_params->options); + attr->num_queues = rsp_params->num_queues; + attr->num_rx_tcs = rsp_params->num_rx_tcs; + attr->num_tx_tcs = rsp_params->num_tx_tcs; + attr->mac_filter_entries = rsp_params->mac_filter_entries; + attr->vlan_filter_entries = rsp_params->vlan_filter_entries; + attr->num_channels = rsp_params->num_channels; + attr->qos_entries = rsp_params->qos_entries; + attr->fs_entries = le16_to_cpu(rsp_params->fs_entries); + attr->num_opr = le16_to_cpu(rsp_params->num_opr); + attr->qos_key_size = rsp_params->qos_key_size; + attr->fs_key_size = rsp_params->fs_key_size; + attr->wriop_version = le16_to_cpu(rsp_params->wriop_version); + attr->num_cgs = rsp_params->num_cgs; return 0; } -int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_error_cfg *cfg) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_ERRORS_BEHAVIOR, - cmd_flags, - token); - DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_buffer_layout *layout, - enum dpni_queue_type type) +/** + * dpni_set_buffer_layout() - Set buffer layout configuration. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @qtype: Type of queue this configuration applies to + * @layout: Buffer layout configuration + * + * Return: '0' on Success; Error code otherwise. + * + * @warning Allowed only when DPNI is disabled + */ +int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, + const struct dpni_buffer_layout *layout) { + struct dpni_cmd_set_buffer_layout *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_BUFFER_LAYOUT, cmd_flags, token); - DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, type); + cmd_params = (struct dpni_cmd_set_buffer_layout *)cmd.params; + cmd_params->qtype = qtype; + cmd_params->options = cpu_to_le16((u16)layout->options); + dpni_set_field(cmd_params->flags, PASS_TS, layout->pass_timestamp); + dpni_set_field(cmd_params->flags, PASS_PR, layout->pass_parser_result); + dpni_set_field(cmd_params->flags, PASS_FS, layout->pass_frame_status); + dpni_set_field(cmd_params->flags, PASS_SWO, layout->pass_sw_opaque); + cmd_params->private_data_size = cpu_to_le16(layout->private_data_size); + cmd_params->data_align = cpu_to_le16(layout->data_align); + cmd_params->head_room = cpu_to_le16(layout->data_head_room); + cmd_params->tail_room = cpu_to_le16(layout->data_tail_room); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_get_qdid(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t *qdid) +/** + * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used + * for enqueue operations + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @qtype: Type of queue to receive QDID for + * @qdid: Returned virtual QDID value that should be used as an argument + * in all enqueue operations + * + * Return: '0' on Success; Error code otherwise. + * + * If dpni object is created using multiple Tc channels this function will return + * qdid value for the first channel + */ +int dpni_get_qdid(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 *qdid) { struct mc_command cmd = { 0 }; + struct dpni_cmd_get_qdid *cmd_params; + struct dpni_rsp_get_qdid *rsp_params; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QDID, cmd_flags, token); + cmd_params = (struct dpni_cmd_get_qdid *)cmd.params; + cmd_params->qtype = qtype; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -252,17 +391,26 @@ int dpni_get_qdid(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPNI_RSP_GET_QDID(cmd, *qdid); + rsp_params = (struct dpni_rsp_get_qdid *)cmd.params; + *qdid = le16_to_cpu(rsp_params->qdid); return 0; } -int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t *data_offset) +/** + * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer) + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @data_offset: Tx data offset (from start of buffer) + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u16 *data_offset) { struct mc_command cmd = { 0 }; + struct dpni_rsp_get_tx_data_offset *rsp_params; int err; /* prepare command */ @@ -276,34 +424,54 @@ int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPNI_RSP_GET_TX_DATA_OFFSET(cmd, *data_offset); + rsp_params = (struct dpni_rsp_get_tx_data_offset *)cmd.params; + *data_offset = le16_to_cpu(rsp_params->data_offset); return 0; } -int dpni_set_link_cfg(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpni_set_link_cfg() - set the link configuration. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @cfg: Link configuration + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_link_cfg(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, const struct dpni_link_cfg *cfg) { struct mc_command cmd = { 0 }; + struct dpni_cmd_set_link_cfg *cmd_params; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_LINK_CFG, cmd_flags, token); - DPNI_CMD_SET_LINK_CFG(cmd, cfg); + cmd_params = (struct dpni_cmd_set_link_cfg *)cmd.params; + cmd_params->rate = cpu_to_le32(cfg->rate); + cmd_params->options = cpu_to_le64(cfg->options); + cmd_params->advertising = cpu_to_le64(cfg->advertising); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_get_link_state(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dpni_get_link_state() - Return the link state (either up or down) + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @state: Returned link state; + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, struct dpni_link_state *state) { struct mc_command cmd = { 0 }; + struct dpni_rsp_get_link_state *rsp_params; int err; /* prepare command */ @@ -317,211 +485,279 @@ int dpni_get_link_state(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPNI_RSP_GET_LINK_STATE(cmd, state); - - return 0; -} - - -int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_PRIM_MAC, - cmd_flags, - token); - DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t mac_addr[6]) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_PRIM_MAC, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr); + rsp_params = (struct dpni_rsp_get_link_state *)cmd.params; + state->up = dpni_get_field(rsp_params->flags, LINK_STATE); + state->state_valid = dpni_get_field(rsp_params->flags, STATE_VALID); + state->rate = le32_to_cpu(rsp_params->rate); + state->options = le64_to_cpu(rsp_params->options); + state->supported = le64_to_cpu(rsp_params->supported); + state->advertising = le64_to_cpu(rsp_params->advertising); return 0; } -int dpni_add_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]) +/** + * dpni_add_mac_addr() - Add MAC address filter + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @mac_addr: MAC address to add + * @flags :0 - tc_id and flow_id will be ignored. + * Pkt with this mac_id will be passed to the next + * classification stages + * DPNI_MAC_SET_QUEUE_ACTION + * Pkt with this mac will be forward directly to + * queue defined by the tc_id and flow_id + * @tc_id : Traffic class selection (0-7) + * @flow_id : Selects the specific queue out of the set allocated for the + * same as tc_id. Value must be in range 0 to NUM_QUEUES - 1 + * Return: '0' on Success; Error code otherwise. + */ +int dpni_add_mac_addr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const u8 mac_addr[6], u8 flags, + u8 tc_id, u8 flow_id) { + struct dpni_cmd_add_mac_addr *cmd_params; struct mc_command cmd = { 0 }; + int i; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_ADD_MAC_ADDR, cmd_flags, token); - DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr); + cmd_params = (struct dpni_cmd_add_mac_addr *)cmd.params; + cmd_params->flags = flags; + cmd_params->tc_id = tc_id; + cmd_params->fq_id = flow_id; - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -int dpni_remove_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPNI_CMDID_REMOVE_MAC_ADDR, - cmd_flags, - token); - DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr); + for (i = 0; i < 6; i++) + cmd_params->mac_addr[i] = mac_addr[5 - i]; /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dpni_get_api_version() - Get Data Path Network Interface API version + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: Major version of data path network interface API + * @minor_ver: Minor version of data path network interface API + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; - /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_API_VERSION, - cmd_flags, 0); + cmd_flags, + 0); - /* send command to mc */ err = mc_send_command(mc_io, &cmd); if (err) return err; - /* retrieve response parameters */ mc_cmd_read_api_version(&cmd, major_ver, minor_ver); return 0; } -int dpni_set_queue(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_queue_type type, - uint8_t tc, - uint8_t index, - const struct dpni_queue *queue) +/** + * dpni_set_queue() - Set queue parameters + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @qtype: Type of queue - all queue types are supported, although + * the command is ignored for Tx + * @tc: Traffic class, in range 0 to NUM_TCS - 1 + * @index: Selects the specific queue out of the set allocated for the + * same TC. Value must be in range 0 to NUM_QUEUES - 1 + * @options: A combination of DPNI_QUEUE_OPT_ values that control what + * configuration options are set on the queue + * @queue: Queue structure + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 param, u8 index, + u8 options, const struct dpni_queue *queue) { struct mc_command cmd = { 0 }; + struct dpni_cmd_set_queue *cmd_params; + /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_QUEUE, cmd_flags, token); - DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue); + cmd_params = (struct dpni_cmd_set_queue *)cmd.params; + cmd_params->qtype = qtype; + cmd_params->tc = (u8)(param & 0xff); + cmd_params->channel_id = (u8)((param >> 8) & 0xff); + cmd_params->index = index; + cmd_params->options = options; + cmd_params->dest_id = cpu_to_le32(queue->destination.id); + cmd_params->dest_prio = queue->destination.priority; + dpni_set_field(cmd_params->flags, DEST_TYPE, queue->destination.type); + dpni_set_field(cmd_params->flags, STASH_CTRL, queue->flc.stash_control); + dpni_set_field(cmd_params->flags, HOLD_ACTIVE, + queue->destination.hold_active); + cmd_params->flc = cpu_to_le64(queue->flc.value); + cmd_params->user_context = cpu_to_le64(queue->user_context); + cmd_params->cgid = queue->cgid; - /* send command to mc*/ + /* send command to mc */ return mc_send_command(mc_io, &cmd); } -int dpni_get_queue(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_queue_type type, - uint8_t tc, - uint8_t index, - struct dpni_queue *queue) +/** + * dpni_get_queue() - Get queue parameters + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @qtype: Type of queue - all queue types are supported + * @param: Traffic class and channel ID. + * MSB - channel id; used only for DPNI_QUEUE_TX and + * DPNI_QUEUE_TX_CONFIRM, ignored for the rest + * LSB - traffic class + * Use macro DPNI_BUILD_PARAM() to build correct value. + * If dpni uses a single channel (uses only channel zero) + * the parameter can receive traffic class directly. + * @index: Selects the specific queue out of the set allocated for the + * same TC. Value must be in range 0 to NUM_QUEUES - 1 + * @queue: Queue configuration structure + * @qid: Queue identification + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 param, u8 index, + struct dpni_queue *queue, struct dpni_queue_id *qid) { struct mc_command cmd = { 0 }; + struct dpni_cmd_get_queue *cmd_params; + struct dpni_rsp_get_queue *rsp_params; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_QUEUE, cmd_flags, token); - DPNI_CMD_GET_QUEUE(cmd, type, tc, index); + cmd_params = (struct dpni_cmd_get_queue *)cmd.params; + cmd_params->qtype = qtype; + cmd_params->tc = (u8)(param & 0xff); + cmd_params->index = index; + cmd_params->channel_id = (u8)((param >> 8) & 0xff); - /* send command to mc*/ + /* send command to mc */ err = mc_send_command(mc_io, &cmd); if (err) return err; /* retrieve response parameters */ - DPNI_RSP_GET_QUEUE(cmd, queue); + rsp_params = (struct dpni_rsp_get_queue *)cmd.params; + queue->destination.id = le32_to_cpu(rsp_params->dest_id); + queue->destination.priority = rsp_params->dest_prio; + queue->destination.type = dpni_get_field(rsp_params->flags, DEST_TYPE); + queue->flc.stash_control = dpni_get_field(rsp_params->flags, STASH_CTRL); + queue->destination.hold_active = dpni_get_field(rsp_params->flags, HOLD_ACTIVE); + queue->flc.value = le64_to_cpu(rsp_params->flc); + queue->user_context = le64_to_cpu(rsp_params->user_context); + qid->fqid = le32_to_cpu(rsp_params->fqid); + qid->qdbin = le16_to_cpu(rsp_params->qdbin); + if (dpni_get_field(rsp_params->flags, CGID_VALID)) + queue->cgid = rsp_params->cgid; + else + queue->cgid = -1; + return 0; } -int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_confirmation_mode mode) +/** + * dpni_set_tx_confirmation_mode() - Tx confirmation mode + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @ceetm_ch_idx: ceetm channel index + * @mode: Tx confirmation mode + * + * This function is useful only when 'DPNI_OPT_TX_CONF_DISABLED' is not + * selected at DPNI creation. + * Calling this function with 'mode' set to DPNI_CONF_DISABLE disables all + * transmit confirmation (including the private confirmation queues), regardless + * of previous settings; Note that in this case, Tx error frames are still + * enqueued to the general transmit errors queue. + * Calling this function with 'mode' set to DPNI_CONF_SINGLE switches all + * Tx confirmations to a shared Tx conf queue. 'index' field in dpni_get_queue + * command will be ignored. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 ceetm_ch_idx, enum dpni_confirmation_mode mode) { struct dpni_tx_confirmation_mode *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_SET_TX_CONFIRMATION_MODE, - cmd_flags, - token); - + cmd_flags, token); cmd_params = (struct dpni_tx_confirmation_mode *)cmd.params; + cmd_params->ceetm_ch_idx = ceetm_ch_idx; cmd_params->confirmation_mode = mode; /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpni_get_statistics(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t page, - struct dpni_statistics *stat) +/** + * dpni_get_statistics() - Get DPNI statistics + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPNI object + * @page: Selects the statistics page to retrieve, see + * DPNI_GET_STATISTICS output. Pages are numbered 0 to 6. + * @param: Custom parameter for some pages used to select + * a certain statistic source, for example the TC. + * - page_0: not used + * - page_1: not used + * - page_2: not used + * - page_3: high_byte - channel_id, low_byte - traffic class + * - page_4: high_byte - queue_index have meaning only if dpni is + * created using option DPNI_OPT_CUSTOM_CG, low_byte - traffic class + * - page_5: not used + * - page_6: not used + * @stat: Structure containing the statistics + * + * Return: '0' on Success; Error code otherwise. + */ +int dpni_get_statistics(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 page, u16 param, union dpni_statistics *stat) { + struct dpni_cmd_get_statistics *cmd_params; + struct dpni_rsp_get_statistics *rsp_params; struct mc_command cmd = { 0 }; - int err; + int i, err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPNI_CMDID_GET_STATISTICS, - cmd_flags, token); - DPNI_CMD_GET_STATISTICS(cmd, page); + cmd_flags, + token); + cmd_params = (struct dpni_cmd_get_statistics *)cmd.params; + cmd_params->page_number = page; + cmd_params->param = param; - /* send command to mc*/ + /* send command to mc */ err = mc_send_command(mc_io, &cmd); if (err) return err; /* retrieve response parameters */ - DPNI_RSP_GET_STATISTICS(cmd, stat); + rsp_params = (struct dpni_rsp_get_statistics *)cmd.params; + for (i = 0; i < DPNI_STATISTICS_CNT; i++) + stat->raw.counter[i] = le64_to_cpu(rsp_params->counter[i]); return 0; } - -int dpni_reset_statistics(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPNI_CMDID_RESET_STATISTICS, - cmd_flags, token); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} diff --git a/drivers/net/fsl-mc/dprc.c b/drivers/net/fsl-mc/dprc.c index e0a2865..d1a74ab 100644 --- a/drivers/net/fsl-mc/dprc.c +++ b/drivers/net/fsl-mc/dprc.c @@ -3,16 +3,22 @@ * Freescale Layerscape MC I/O wrapper * * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #include <fsl-mc/fsl_mc_sys.h> #include <fsl-mc/fsl_mc_cmd.h> #include <fsl-mc/fsl_dprc.h> -int dprc_get_container_id(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int *container_id) +/** + * dprc_get_container_id - Get container ID associated with a given portal. + * @mc_io: Pointer to Mc portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @container_id: Requested container id + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_container_id(struct fsl_mc_io *mc_io, u32 cmd_flags, int *container_id) { struct mc_command cmd = { 0 }; int err; @@ -28,23 +34,33 @@ int dprc_get_container_id(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPRC_RSP_GET_CONTAINER_ID(cmd, *container_id); + *container_id = (int)mc_cmd_read_object_id(&cmd); return 0; } -int dprc_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int container_id, - uint16_t *token) +/** + * dprc_open() - Open DPRC object for use + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @container_id: Container ID to open + * @token: Returned token of DPRC object + * + * Return: '0' on Success; Error code otherwise. + * + * @warning Required before any operation on the object. + */ +int dprc_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int container_id, u16 *token) { + struct dprc_cmd_open *cmd_params; struct mc_command cmd = { 0 }; int err; /* prepare command */ cmd.header = mc_encode_cmd_header(DPRC_CMDID_OPEN, cmd_flags, 0); - DPRC_CMD_OPEN(cmd, container_id); + cmd_params = (struct dprc_cmd_open *)cmd.params; + cmd_params->container_id = cpu_to_le32(container_id); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -52,14 +68,23 @@ int dprc_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return 0; } -int dprc_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token) +/** + * dprc_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -71,22 +96,35 @@ int dprc_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dprc_create_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dprc_cfg *cfg, - int *child_container_id, - uint64_t *child_portal_paddr) +/** + * dprc_create_container() - Create child container + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @cfg: Child container configuration + * @child_container_id: Returned child container ID + * @child_portal_offset:Returned child portal offset from MC portal base + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_create_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dprc_cfg *cfg, int *child_container_id, + uint64_t *child_portal_offset) { + struct dprc_cmd_create_container *cmd_params; + struct dprc_rsp_create_container *rsp_params; struct mc_command cmd = { 0 }; - int err; + int err, i; /* prepare command */ - DPRC_CMD_CREATE_CONTAINER(cmd, cfg); - cmd.header = mc_encode_cmd_header(DPRC_CMDID_CREATE_CONT, - cmd_flags, - token); + cmd_flags, token); + cmd_params = (struct dprc_cmd_create_container *)cmd.params; + cmd_params->options = cpu_to_le32(cfg->options); + cmd_params->icid = cpu_to_le32(cfg->icid); + cmd_params->portal_id = cpu_to_le32(cfg->portal_id); + for (i = 0; i < 16; i++) + cmd_params->label[i] = cfg->label[i]; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -94,253 +132,156 @@ int dprc_create_container(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPRC_RSP_CREATE_CONTAINER(cmd, *child_container_id, - *child_portal_paddr); + rsp_params = (struct dprc_rsp_create_container *)cmd.params; + *child_container_id = le32_to_cpu(rsp_params->child_container_id); + *child_portal_offset = le64_to_cpu(rsp_params->child_portal_addr); return 0; } -int dprc_destroy_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dprc_destroy_container() - Destroy child container. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @child_container_id: ID of the container to destroy + * + * This function terminates the child container, so following this call the + * child container ID becomes invalid. + * + * Notes: + * - All resources and objects of the destroyed container are returned to the + * parent container or destroyed if were created be the destroyed container. + * - This function destroy all the child containers of the specified + * container prior to destroying the container itself. + * + * warning: Only the parent container is allowed to destroy a child policy + * Container 0 can't be destroyed + * + * Return: '0' on Success; Error code otherwise. + * + */ +int dprc_destroy_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, int child_container_id) { + struct dprc_cmd_destroy_container *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPRC_CMDID_DESTROY_CONT, - cmd_flags, - token); - DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id); + cmd_flags, token); + cmd_params = (struct dprc_cmd_destroy_container *)cmd.params; + cmd_params->child_container_id = cpu_to_le32(child_container_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dprc_reset_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int child_container_id) -{ - struct mc_command cmd = { 0 }; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_RESET_CONT, - cmd_flags, - token); - DPRC_CMD_RESET_CONTAINER(cmd, child_container_id); - - /* send command to mc*/ - return mc_send_command(mc_io, &cmd); -} - -int dprc_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dprc_attributes *attr) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_ATTR, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_ATTRIBUTES(cmd, attr); - - return 0; -} - -int dprc_get_obj_count(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int *obj_count) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_COUNT, - cmd_flags, - token); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_OBJ_COUNT(cmd, *obj_count); - - return 0; -} - -int dprc_get_obj(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int obj_index, - struct dprc_obj_desc *obj_desc) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ, - cmd_flags, - token); - DPRC_CMD_GET_OBJ(cmd, obj_index); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_OBJ(cmd, obj_desc); - - return 0; -} - -int dprc_get_res_count(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *type, - int *res_count) -{ - struct mc_command cmd = { 0 }; - int err; - - *res_count = 0; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_COUNT, - cmd_flags, - token); - DPRC_CMD_GET_RES_COUNT(cmd, type); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_RES_COUNT(cmd, *res_count); - - return 0; -} - -int dprc_get_res_ids(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *type, - struct dprc_res_ids_range_desc *range_desc) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_RES_IDS, - cmd_flags, - token); - DPRC_CMD_GET_RES_IDS(cmd, range_desc, type); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_RES_IDS(cmd, range_desc); - - return 0; -} - -int dprc_get_obj_region(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *obj_type, - int obj_id, - uint8_t region_index, - struct dprc_region_desc *region_desc) -{ - struct mc_command cmd = { 0 }; - int err; - - /* prepare command */ - cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_OBJ_REG, - cmd_flags, - token); - DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index); - - /* send command to mc*/ - err = mc_send_command(mc_io, &cmd); - if (err) - return err; - - /* retrieve response parameters */ - DPRC_RSP_GET_OBJ_REGION(cmd, region_desc); - - return 0; -} - -int dprc_connect(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dprc_connect() - Connect two endpoints to create a network link between them + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @endpoint1: Endpoint 1 configuration parameters + * @endpoint2: Endpoint 2 configuration parameters + * @cfg: Connection configuration. The connection configuration + * is ignored for connections made to DPMAC objects, where + * rate is retrieved from the MAC configuration. + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_connect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, const struct dprc_endpoint *endpoint1, const struct dprc_endpoint *endpoint2, const struct dprc_connection_cfg *cfg) { + struct dprc_cmd_connect *cmd_params; struct mc_command cmd = { 0 }; + int i; /* prepare command */ cmd.header = mc_encode_cmd_header(DPRC_CMDID_CONNECT, cmd_flags, token); - DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg); + cmd_params = (struct dprc_cmd_connect *)cmd.params; + cmd_params->ep1_id = cpu_to_le32(endpoint1->id); + cmd_params->ep1_interface_id = cpu_to_le16(endpoint1->if_id); + cmd_params->ep2_id = cpu_to_le32(endpoint2->id); + cmd_params->ep2_interface_id = cpu_to_le16(endpoint2->if_id); + cmd_params->max_rate = cpu_to_le32(cfg->max_rate); + cmd_params->committed_rate = cpu_to_le32(cfg->committed_rate); + for (i = 0; i < 16; i++) { + cmd_params->ep1_type[i] = endpoint1->type[i]; + cmd_params->ep2_type[i] = endpoint2->type[i]; + } /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dprc_disconnect(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dprc_disconnect() - Disconnect one endpoint to remove its network connection + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @endpoint: Endpoint configuration parameters + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_disconnect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, const struct dprc_endpoint *endpoint) { + struct dprc_cmd_disconnect *cmd_params; struct mc_command cmd = { 0 }; + int i; /* prepare command */ cmd.header = mc_encode_cmd_header(DPRC_CMDID_DISCONNECT, cmd_flags, token); - DPRC_CMD_DISCONNECT(cmd, endpoint); + cmd_params = (struct dprc_cmd_disconnect *)cmd.params; + cmd_params->id = cpu_to_le32(endpoint->id); + cmd_params->interface_id = cpu_to_le32(endpoint->if_id); + for (i = 0; i < 16; i++) + cmd_params->type[i] = endpoint->type[i]; /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dprc_get_connection(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, +/** + * dprc_get_connection() - Get connected endpoint and link status if connection + * exists. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPRC object + * @endpoint1: Endpoint 1 configuration parameters + * @endpoint2: Returned endpoint 2 configuration parameters + * @state: Returned link state: + * 1 - link is up; + * 0 - link is down; + * -1 - no connection (endpoint2 information is irrelevant) + * + * Return: '0' on Success; -ENAVAIL if connection does not exist. + */ +int dprc_get_connection(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, const struct dprc_endpoint *endpoint1, - struct dprc_endpoint *endpoint2, - int *state) + struct dprc_endpoint *endpoint2, int *state) { + struct dprc_cmd_get_connection *cmd_params; + struct dprc_rsp_get_connection *rsp_params; struct mc_command cmd = { 0 }; - int err; + int err, i; /* prepare command */ cmd.header = mc_encode_cmd_header(DPRC_CMDID_GET_CONNECTION, cmd_flags, token); - DPRC_CMD_GET_CONNECTION(cmd, endpoint1); + cmd_params = (struct dprc_cmd_get_connection *)cmd.params; + cmd_params->ep1_id = cpu_to_le32(endpoint1->id); + cmd_params->ep1_interface_id = cpu_to_le16(endpoint1->if_id); + for (i = 0; i < 16; i++) + cmd_params->ep1_type[i] = endpoint1->type[i]; /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -348,15 +289,27 @@ int dprc_get_connection(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - DPRC_RSP_GET_CONNECTION(cmd, endpoint2, *state); + rsp_params = (struct dprc_rsp_get_connection *)cmd.params; + endpoint2->id = le32_to_cpu(rsp_params->ep2_id); + endpoint2->if_id = le16_to_cpu(rsp_params->ep2_interface_id); + *state = le32_to_cpu(rsp_params->state); + for (i = 0; i < 16; i++) + endpoint2->type[i] = rsp_params->ep2_type[i]; return 0; } -int dprc_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dprc_get_api_version - Get Data Path Resource Container API version + * @mc_io: Pointer to Mc portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: Major version of Data Path Resource Container API + * @minor_ver: Minor version of Data Path Resource Container API + * + * Return: '0' on Success; Error code otherwise. + */ +int dprc_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; diff --git a/drivers/net/fsl-mc/dpsparser.c b/drivers/net/fsl-mc/dpsparser.c index cfd1ba6..09dfb8f 100644 --- a/drivers/net/fsl-mc/dpsparser.c +++ b/drivers/net/fsl-mc/dpsparser.c @@ -2,15 +2,29 @@ /* * Data Path Soft Parser * - * Copyright 2018 NXP + * Copyright 2018, 2023 NXP */ #include <fsl-mc/fsl_mc_sys.h> #include <fsl-mc/fsl_mc_cmd.h> #include <fsl-mc/fsl_dpsparser.h> -int dpsparser_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *token) +/** + * dpsparser_open() - Open a control session for the specified object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Returned token; use in subsequent API calls + * + * This function can be used to open a control session for an + * already created object; an object may have been declared in + * the DPL or by calling the dpsparser_create function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent commands for + * this specific object + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_open(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 *token) { struct mc_command cmd = { 0 }; int err; @@ -26,14 +40,23 @@ int dpsparser_open(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - *token = MC_CMD_HDR_READ_TOKEN(cmd.header); + *token = mc_cmd_hdr_read_token(&cmd); return err; } -int dpsparser_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token) +/** + * dpsparser_close() - Close the control session of the object + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSPARSER object + * + * After this function is called, no further operations are + * allowed on the object without opening a new control session. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token) { struct mc_command cmd = { 0 }; @@ -45,9 +68,27 @@ int dpsparser_close(struct fsl_mc_io *mc_io, return mc_send_command(mc_io, &cmd); } -int dpsparser_create(struct fsl_mc_io *mc_io, - u16 token, - u32 cmd_flags, +/** + * dpsparser_create() - Create the DPSPARSER object. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Returned token; use in subsequent API calls + * + * Create the DPSPARSER object, allocate required resources and + * perform required initialization. + * + * The object can be created either by declaring it in the + * DPL file, or by calling this function. + * This function returns a unique authentication token, + * associated with the specific object ID and the specific MC + * portal; this token must be used in all subsequent calls to + * this specific object. For objects that are created using the + * DPL file, call dpsparser_open function to get an authentication + * token first. + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_create(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags, u32 *obj_id) { struct mc_command cmd = { 0 }; @@ -64,36 +105,51 @@ int dpsparser_create(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters */ - MC_CMD_READ_OBJ_ID(cmd, *obj_id); + *obj_id = mc_cmd_read_object_id(&cmd); return 0; } -int dpsparser_destroy(struct fsl_mc_io *mc_io, - u16 token, - u32 cmd_flags, +/** + * dpsparser_destroy() - Destroy the DPSPARSER object and release all its resources. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSPARSER object + * + * Return: '0' on Success; error code otherwise. + */ +int dpsparser_destroy(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags, u32 obj_id) { + struct dpsparser_cmd_destroy *cmd_params; struct mc_command cmd = { 0 }; /* prepare command */ cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_DESTROY, cmd_flags, token); - - /* set object id to destroy */ - CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, obj_id); + cmd_params = (struct dpsparser_cmd_destroy *)cmd.params; + cmd_params->dpsparser_id = cpu_to_le32(obj_id); /* send command to mc*/ return mc_send_command(mc_io, &cmd); } -int dpsparser_apply_spb(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u64 blob_addr, - u16 *error) +/** + * dpsparser_apply_spb() - Applies the Soft Parser Blob loaded at specified address. + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @token: Token of DPSPARSER object + * @blob_addr: Blob loading address + * @error: Error reported by MC related to SP Blob parsing and apply + * + * Return: '0' on Success; error code otherwise. + */ +int dpsparser_apply_spb(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u64 blob_addr, u16 *error) { + struct dpsparser_rsp_blob_report_error *rsp_params; + struct dpsparser_cmd_blob_set_address *cmd_params; struct mc_command cmd = { 0 }; int err; @@ -101,7 +157,8 @@ int dpsparser_apply_spb(struct fsl_mc_io *mc_io, cmd.header = mc_encode_cmd_header(DPSPARSER_CMDID_APPLY_SPB, cmd_flags, token); - DPSPARSER_CMD_BLOB_SET_ADDR(cmd, blob_addr); + cmd_params = (struct dpsparser_cmd_blob_set_address *)cmd.params; + cmd_params->blob_addr = cpu_to_le64(blob_addr); /* send command to mc*/ err = mc_send_command(mc_io, &cmd); @@ -109,15 +166,24 @@ int dpsparser_apply_spb(struct fsl_mc_io *mc_io, return err; /* retrieve response parameters: MC error code */ - DPSPARSER_CMD_BLOB_REPORT_ERROR(cmd, *error); + rsp_params = (struct dpsparser_rsp_blob_report_error *)cmd.params; + *error = le16_to_cpu(rsp_params->error); return 0; } -int dpsparser_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver) +/** + * dpsparser_get_api_version - Retrieve DPSPARSER Major and Minor version info. + * + * @mc_io: Pointer to MC portal's I/O object + * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' + * @major_ver: DPSPARSER major version + * @minor_ver: DPSPARSER minor version + * + * Return: '0' on Success; Error code otherwise. + */ +int dpsparser_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver) { struct mc_command cmd = { 0 }; int err; diff --git a/drivers/net/fsl-mc/fsl_dpmng_cmd.h b/drivers/net/fsl-mc/fsl_dpmng_cmd.h index e18c88d..e6efcea 100644 --- a/drivers/net/fsl-mc/fsl_dpmng_cmd.h +++ b/drivers/net/fsl-mc/fsl_dpmng_cmd.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #ifndef __FSL_DPMNG_CMD_H #define __FSL_DPMNG_CMD_H @@ -8,12 +8,13 @@ /* Command IDs */ #define DPMNG_CMDID_GET_VERSION 0x8311 -/* cmd, param, offset, width, type, arg_name */ -#define DPMNG_RSP_GET_VERSION(cmd, mc_ver_info) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, uint32_t, mc_ver_info->revision); \ - MC_RSP_OP(cmd, 0, 32, 32, uint32_t, mc_ver_info->major); \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, mc_ver_info->minor); \ -} while (0) +#pragma pack(push, 1) +struct dpmng_rsp_get_version { + __le32 revision; + __le32 version_major; + __le32 version_minor; +}; + +#pragma pack(pop) #endif /* __FSL_DPMNG_CMD_H */ diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index 78a40f2..984616f 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -1353,10 +1353,9 @@ err: static int dpni_init(void) { - int err; - uint8_t cfg_buf[256] = {0}; - struct dpni_cfg dpni_cfg; + struct dpni_cfg dpni_cfg = {0}; uint16_t major_ver, minor_ver; + int err; dflt_dpni = calloc(sizeof(struct fsl_dpni_obj), 1); if (!dflt_dpni) { @@ -1365,14 +1364,6 @@ static int dpni_init(void) goto err_calloc; } - memset(&dpni_cfg, 0, sizeof(dpni_cfg)); - err = dpni_prepare_cfg(&dpni_cfg, &cfg_buf[0]); - if (err < 0) { - err = -ENODEV; - printf("dpni_prepare_cfg() failed: %d\n", err); - goto err_prepare_cfg; - } - err = dpni_create(dflt_mc_io, dflt_dprc_handle, MC_CMD_NO_FLAGS, @@ -1429,7 +1420,6 @@ err_get_version: MC_CMD_NO_FLAGS, dflt_dpni->dpni_id); err_create: -err_prepare_cfg: free(dflt_dpni); err_calloc: return err; diff --git a/drivers/net/fsl-mc/mc_sys.c b/drivers/net/fsl-mc/mc_sys.c index b5ae2ea..4d32516 100644 --- a/drivers/net/fsl-mc/mc_sys.c +++ b/drivers/net/fsl-mc/mc_sys.c @@ -13,8 +13,13 @@ #include <asm/io.h> #include <linux/delay.h> -#define MC_CMD_HDR_READ_CMDID(_hdr) \ - ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_CMDID_O, MC_CMD_HDR_CMDID_S)) +static u16 mc_cmd_hdr_read_cmdid(struct mc_command *cmd) +{ + struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; + u16 cmd_id = le16_to_cpu(hdr->cmd_id); + + return cmd_id; +} /** * mc_send_command - Send MC command and wait for response @@ -52,8 +57,8 @@ int mc_send_command(struct fsl_mc_io *mc_io, if (status != MC_CMD_STATUS_OK) { printf("Error: MC command failed (portal: %p, obj handle: %#x, command: %#x, status: %#x)\n", mc_io->mmio_regs, - (unsigned int)MC_CMD_HDR_READ_TOKEN(cmd->header), - (unsigned int)MC_CMD_HDR_READ_CMDID(cmd->header), + (unsigned int)mc_cmd_hdr_read_token(cmd), + (unsigned int)mc_cmd_hdr_read_cmdid(cmd), (unsigned int)status); return -EIO; diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.c b/drivers/net/ldpaa_eth/ldpaa_eth.c index 2cb6e9b..87fbada 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.c +++ b/drivers/net/ldpaa_eth/ldpaa_eth.c @@ -38,146 +38,90 @@ static void init_phy(struct udevice *dev) } #endif -#ifdef DEBUG - -#define DPNI_STATS_PER_PAGE 6 - -static const char *dpni_statistics[][DPNI_STATS_PER_PAGE] = { - { - "DPNI_CNT_ING_ALL_FRAMES", - "DPNI_CNT_ING_ALL_BYTES", - "DPNI_CNT_ING_MCAST_FRAMES", - "DPNI_CNT_ING_MCAST_BYTES", - "DPNI_CNT_ING_BCAST_FRAMES", - "DPNI_CNT_ING_BCAST_BYTES", - }, { - "DPNI_CNT_EGR_ALL_FRAMES", - "DPNI_CNT_EGR_ALL_BYTES", - "DPNI_CNT_EGR_MCAST_FRAMES", - "DPNI_CNT_EGR_MCAST_BYTES", - "DPNI_CNT_EGR_BCAST_FRAMES", - "DPNI_CNT_EGR_BCAST_BYTES", - }, { - "DPNI_CNT_ING_FILTERED_FRAMES", - "DPNI_CNT_ING_DISCARDED_FRAMES", - "DPNI_CNT_ING_NOBUFFER_DISCARDS", - "DPNI_CNT_EGR_DISCARDED_FRAMES", - "DPNI_CNT_EGR_CNF_FRAMES", - "" - }, -}; - -static void print_dpni_stats(const char *strings[], - struct dpni_statistics dpni_stats) +static void ldpaa_eth_collect_dpni_stats(struct udevice *dev, u64 *data) { - uint64_t *stat; - int i; + union dpni_statistics dpni_stats; + int dpni_stats_page_size[DPNI_STATISTICS_CNT] = { + sizeof(dpni_stats.page_0), + sizeof(dpni_stats.page_1), + sizeof(dpni_stats.page_2), + sizeof(dpni_stats.page_3), + sizeof(dpni_stats.page_4), + sizeof(dpni_stats.page_5), + sizeof(dpni_stats.page_6), + }; + int j, k, num_cnt, err, i = 0; - stat = (uint64_t *)&dpni_stats; - for (i = 0; i < DPNI_STATS_PER_PAGE; i++) { - if (strcmp(strings[i], "\0") == 0) - break; - printf("%s= %llu\n", strings[i], *stat); - stat++; + for (j = 0; j <= 6; j++) { + /* We're not interested in pages 4 & 5 for now */ + if (j == 4 || j == 5) + continue; + err = dpni_get_statistics(dflt_mc_io, MC_CMD_NO_FLAGS, + dflt_dpni->dpni_handle, + j, 0, &dpni_stats); + if (err) { + memset(&dpni_stats, 0, sizeof(dpni_stats)); + printf("dpni_get_stats(%d) failed\n", j); + } + + num_cnt = dpni_stats_page_size[j] / sizeof(u64); + for (k = 0; k < num_cnt; k++) + *(data + i++) = dpni_stats.raw.counter[k]; } } -static void ldpaa_eth_get_dpni_counter(void) +static void ldpaa_eth_add_dpni_stats(struct udevice *dev, u64 *data) { - int err = 0; - unsigned int page = 0; - struct dpni_statistics dpni_stats; + struct ldpaa_eth_priv *priv = dev_get_priv(dev); + int i; - printf("DPNI counters ..\n"); - for (page = 0; page < 3; page++) { - err = dpni_get_statistics(dflt_mc_io, MC_CMD_NO_FLAGS, - dflt_dpni->dpni_handle, page, - &dpni_stats); - if (err < 0) { - printf("dpni_get_statistics: failed:"); - printf("%d for page[%d]\n", err, page); - return; - } - print_dpni_stats(dpni_statistics[page], dpni_stats); - } + for (i = 0; i < LDPAA_ETH_DPNI_NUM_STATS; i++) + priv->dpni_stats[i] += data[i]; } -static void ldpaa_eth_get_dpmac_counter(struct udevice *dev) +static void ldpaa_eth_collect_dpmac_stats(struct udevice *dev, u64 *data) { struct ldpaa_eth_priv *priv = dev_get_priv(dev); - int err = 0; + int err, i; u64 value; - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_ING_BYTE, - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n"); - return; - } - printf("\nDPMAC counters ..\n"); - printf("DPMAC_CNT_ING_BYTE=%lld\n", value); + for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++) { + err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, + priv->dpmac_handle, i, + &value); + if (err) + printf("dpmac_get_counter(%d) failed\n", i); - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_ING_FRAME_DISCARD, - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_ING_FRAME_DISCARD failed\n"); - return; + *(data + i) = value; } - printf("DPMAC_CNT_ING_FRAME_DISCARD=%lld\n", value); +} - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_ING_ALIGN_ERR, - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_ING_ALIGN_ERR failed\n"); - return; - } - printf("DPMAC_CNT_ING_ALIGN_ERR =%lld\n", value); +static void ldpaa_eth_add_dpmac_stats(struct udevice *dev, u64 *data) +{ + struct ldpaa_eth_priv *priv = dev_get_priv(dev); + int i; - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_ING_BYTE, - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_ING_BYTE failed\n"); - return; - } - printf("DPMAC_CNT_ING_BYTE=%lld\n", value); + for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++) + priv->dpmac_stats[i] += data[i]; +} - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_ING_ERR_FRAME, - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_ING_ERR_FRAME failed\n"); - return; - } - printf("DPMAC_CNT_ING_ERR_FRAME=%lld\n", value); +#ifdef DEBUG +static void ldpaa_eth_dump_dpni_stats(struct udevice *dev, u64 *data) +{ + int i; - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_EGR_BYTE , - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_EGR_BYTE failed\n"); - return; - } - printf("DPMAC_CNT_EGR_BYTE =%lld\n", value); + printf("DPNI counters:\n"); + for (i = 0; i < LDPAA_ETH_DPNI_NUM_STATS; i++) + printf(" %s: %llu\n", ldpaa_eth_dpni_stat_strings[i], data[i]); +} - err = dpmac_get_counter(dflt_mc_io, MC_CMD_NO_FLAGS, - priv->dpmac_handle, - DPMAC_CNT_EGR_ERR_FRAME , - &value); - if (err < 0) { - printf("dpmac_get_counter: DPMAC_CNT_EGR_ERR_FRAME failed\n"); - return; - } - printf("DPMAC_CNT_EGR_ERR_FRAME =%lld\n", value); +static void ldpaa_eth_dump_dpmac_stats(struct udevice *dev, u64 *data) +{ + int i; + + printf("DPMAC counters:\n"); + for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++) + printf(" %s: %llu\n", ldpaa_eth_dpmac_stat_strings[i], data[i]); } #endif @@ -434,7 +378,8 @@ static int ldpaa_eth_open(struct udevice *dev) struct dpni_link_state link_state; #endif int err = 0; - struct dpni_queue d_queue; + struct dpni_queue d_queue_cfg = { 0 }; + struct dpni_queue_id d_queue; if (eth_is_active(dev)) return 0; @@ -478,7 +423,7 @@ static int ldpaa_eth_open(struct udevice *dev) goto err_dpni_bind; err = dpni_add_mac_addr(dflt_mc_io, MC_CMD_NO_FLAGS, - dflt_dpni->dpni_handle, plat->enetaddr); + dflt_dpni->dpni_handle, plat->enetaddr, 0, 0, 0); if (err) { printf("dpni_add_mac_addr() failed\n"); return err; @@ -517,7 +462,7 @@ static int ldpaa_eth_open(struct udevice *dev) memset(&d_queue, 0, sizeof(struct dpni_queue)); err = dpni_get_queue(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, DPNI_QUEUE_RX, - 0, 0, &d_queue); + 0, 0, &d_queue_cfg, &d_queue); if (err) { printf("dpni_get_queue failed\n"); goto err_get_queue; @@ -526,7 +471,7 @@ static int ldpaa_eth_open(struct udevice *dev) priv->rx_dflt_fqid = d_queue.fqid; err = dpni_get_qdid(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - &priv->tx_qdid); + DPNI_QUEUE_TX, &priv->tx_qdid); if (err) { printf("dpni_get_qdid() failed\n"); goto err_qdid; @@ -556,14 +501,30 @@ static void ldpaa_eth_stop(struct udevice *dev) struct ldpaa_eth_priv *priv = dev_get_priv(dev); struct phy_device *phydev = NULL; int err = 0; + u64 *data; if (!eth_is_active(dev)) return; + data = kzalloc(sizeof(u64) * LDPAA_ETH_DPNI_NUM_STATS, GFP_KERNEL); + if (data) { + ldpaa_eth_collect_dpni_stats(dev, data); + ldpaa_eth_add_dpni_stats(dev, data); #ifdef DEBUG - ldpaa_eth_get_dpni_counter(); - ldpaa_eth_get_dpmac_counter(dev); + ldpaa_eth_dump_dpni_stats(dev, data); #endif + } + kfree(data); + + data = kzalloc(sizeof(u64) * LDPAA_ETH_DPMAC_NUM_STATS, GFP_KERNEL); + if (data) { + ldpaa_eth_collect_dpmac_stats(dev, data); + ldpaa_eth_add_dpmac_stats(dev, data); +#ifdef DEBUG + ldpaa_eth_dump_dpmac_stats(dev, data); +#endif + } + kfree(data); err = dprc_disconnect(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dprc_handle, &dpmac_endpoint); @@ -885,7 +846,7 @@ static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv) /* ...rx, ... */ err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - &dflt_dpni->buf_layout, DPNI_QUEUE_RX); + DPNI_QUEUE_RX, &dflt_dpni->buf_layout); if (err) { printf("dpni_set_buffer_layout() failed"); goto err_buf_layout; @@ -897,7 +858,7 @@ static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv) DPNI_BUF_LAYOUT_OPT_PARSER_RESULT); err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - &dflt_dpni->buf_layout, DPNI_QUEUE_TX); + DPNI_QUEUE_TX, &dflt_dpni->buf_layout); if (err) { printf("dpni_set_buffer_layout() failed"); goto err_buf_layout; @@ -907,8 +868,7 @@ static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv) dflt_dpni->buf_layout.options &= ~DPNI_BUF_LAYOUT_OPT_PRIVATE_DATA_SIZE; err = dpni_set_buffer_layout(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - &dflt_dpni->buf_layout, - DPNI_QUEUE_TX_CONFIRM); + DPNI_QUEUE_TX_CONFIRM, &dflt_dpni->buf_layout); if (err) { printf("dpni_set_buffer_layout() failed"); goto err_buf_layout; @@ -963,7 +923,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) err = dpni_set_queue(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - DPNI_QUEUE_TX, 0, 0, &tx_queue); + DPNI_QUEUE_TX, 0, 0, 0, &tx_queue); if (err) { printf("dpni_set_queue() failed\n"); @@ -972,7 +932,7 @@ static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv) err = dpni_set_tx_confirmation_mode(dflt_mc_io, MC_CMD_NO_FLAGS, dflt_dpni->dpni_handle, - DPNI_CONF_DISABLE); + 0, DPNI_CONF_DISABLE); if (err) { printf("dpni_set_tx_confirmation_mode() failed\n"); return err; @@ -1038,11 +998,47 @@ static int ldpaa_eth_of_to_plat(struct udevice *dev) return 0; } +static int ldpaa_eth_get_sset_count(struct udevice *dev) +{ + return LDPAA_ETH_DPNI_NUM_STATS + LDPAA_ETH_DPMAC_NUM_STATS; +} + +static void ldpaa_eth_get_strings(struct udevice *dev, u8 *data) +{ + u8 *p = data; + int i; + + for (i = 0; i < LDPAA_ETH_DPNI_NUM_STATS; i++) { + strlcpy(p, ldpaa_eth_dpni_stat_strings[i], ETH_GSTRING_LEN); + p += ETH_GSTRING_LEN; + } + + for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++) { + strlcpy(p, ldpaa_eth_dpmac_stat_strings[i], ETH_GSTRING_LEN); + p += ETH_GSTRING_LEN; + } +} + +static void ldpaa_eth_get_stats(struct udevice *dev, u64 *data) +{ + struct ldpaa_eth_priv *priv = dev_get_priv(dev); + int i, j = 0; + + for (i = 0; i < LDPAA_ETH_DPNI_NUM_STATS; i++) + *(data + j++) = priv->dpni_stats[i]; + + for (i = 0; i < LDPAA_ETH_DPMAC_NUM_STATS; i++) + *(data + j++) = priv->dpmac_stats[i]; +} + static const struct eth_ops ldpaa_eth_ops = { - .start = ldpaa_eth_open, - .send = ldpaa_eth_tx, - .recv = ldpaa_eth_pull_dequeue_rx, - .stop = ldpaa_eth_stop, + .start = ldpaa_eth_open, + .send = ldpaa_eth_tx, + .recv = ldpaa_eth_pull_dequeue_rx, + .stop = ldpaa_eth_stop, + .get_sset_count = ldpaa_eth_get_sset_count, + .get_strings = ldpaa_eth_get_strings, + .get_stats = ldpaa_eth_get_stats, }; static const struct udevice_id ldpaa_eth_of_ids[] = { diff --git a/drivers/net/ldpaa_eth/ldpaa_eth.h b/drivers/net/ldpaa_eth/ldpaa_eth.h index 16d0106..af082e3 100644 --- a/drivers/net/ldpaa_eth/ldpaa_eth.h +++ b/drivers/net/ldpaa_eth/ldpaa_eth.h @@ -115,6 +115,66 @@ struct ldpaa_fas { LDPAA_ETH_FAS_MNLE | \ LDPAA_ETH_FAS_TIDE) +static const char ldpaa_eth_dpni_stat_strings[][ETH_GSTRING_LEN] = { + "[dpni ] rx frames", + "[dpni ] rx bytes", + "[dpni ] rx mcast frames", + "[dpni ] rx mcast bytes", + "[dpni ] rx bcast frames", + "[dpni ] rx bcast bytes", + "[dpni ] tx frames", + "[dpni ] tx bytes", + "[dpni ] tx mcast frames", + "[dpni ] tx mcast bytes", + "[dpni ] tx bcast frames", + "[dpni ] tx bcast bytes", + "[dpni ] rx filtered frames", + "[dpni ] rx discarded frames", + "[dpni ] rx nobuffer discards", + "[dpni ] tx discarded frames", + "[dpni ] tx confirmed frames", + "[dpni ] tx dequeued bytes", + "[dpni ] tx dequeued frames", + "[dpni ] tx rejected bytes", + "[dpni ] tx rejected frames", + "[dpni ] tx pending frames", +}; + +#define LDPAA_ETH_DPNI_NUM_STATS ARRAY_SIZE(ldpaa_eth_dpni_stat_strings) + +static const char ldpaa_eth_dpmac_stat_strings[][ETH_GSTRING_LEN] = { + [DPMAC_CNT_ING_ALL_FRAME] = "[mac] rx all frames", + [DPMAC_CNT_ING_GOOD_FRAME] = "[mac] rx frames ok", + [DPMAC_CNT_ING_ERR_FRAME] = "[mac] rx frame errors", + [DPMAC_CNT_ING_FRAME_DISCARD] = "[mac] rx frame discards", + [DPMAC_CNT_ING_UCAST_FRAME] = "[mac] rx u-cast", + [DPMAC_CNT_ING_BCAST_FRAME] = "[mac] rx b-cast", + [DPMAC_CNT_ING_MCAST_FRAME] = "[mac] rx m-cast", + [DPMAC_CNT_ING_FRAME_64] = "[mac] rx 64 bytes", + [DPMAC_CNT_ING_FRAME_127] = "[mac] rx 65-127 bytes", + [DPMAC_CNT_ING_FRAME_255] = "[mac] rx 128-255 bytes", + [DPMAC_CNT_ING_FRAME_511] = "[mac] rx 256-511 bytes", + [DPMAC_CNT_ING_FRAME_1023] = "[mac] rx 512-1023 bytes", + [DPMAC_CNT_ING_FRAME_1518] = "[mac] rx 1024-1518 bytes", + [DPMAC_CNT_ING_FRAME_1519_MAX] = "[mac] rx 1519-max bytes", + [DPMAC_CNT_ING_FRAG] = "[mac] rx frags", + [DPMAC_CNT_ING_JABBER] = "[mac] rx jabber", + [DPMAC_CNT_ING_ALIGN_ERR] = "[mac] rx align errors", + [DPMAC_CNT_ING_OVERSIZED] = "[mac] rx oversized", + [DPMAC_CNT_ING_VALID_PAUSE_FRAME] = "[mac] rx pause", + [DPMAC_CNT_ING_BYTE] = "[mac] rx bytes", + [DPMAC_CNT_EGR_GOOD_FRAME] = "[mac] tx frames ok", + [DPMAC_CNT_EGR_UCAST_FRAME] = "[mac] tx u-cast", + [DPMAC_CNT_EGR_MCAST_FRAME] = "[mac] tx m-cast", + [DPMAC_CNT_EGR_BCAST_FRAME] = "[mac] tx b-cast", + [DPMAC_CNT_EGR_ERR_FRAME] = "[mac] tx frame errors", + [DPMAC_CNT_EGR_UNDERSIZED] = "[mac] tx undersized", + [DPMAC_CNT_EGR_VALID_PAUSE_FRAME] = "[mac] tx b-pause", + [DPMAC_CNT_EGR_BYTE] = "[mac] tx bytes", +}; + +#define LDPAA_ETH_DPMAC_NUM_STATS ARRAY_SIZE(ldpaa_eth_dpmac_stat_strings) + struct ldpaa_eth_priv { struct phy_device *phy; int phy_mode; @@ -129,6 +189,10 @@ struct ldpaa_eth_priv { uint16_t tx_flow_id; enum ldpaa_eth_type type; /* 1G or 10G ethernet */ + + /* SW kept statistics */ + u64 dpni_stats[LDPAA_ETH_DPNI_NUM_STATS]; + u64 dpmac_stats[LDPAA_ETH_DPMAC_NUM_STATS]; }; struct dprc_endpoint dpmac_endpoint; diff --git a/drivers/net/pch_gbe.c b/drivers/net/pch_gbe.c index ad7b5b8..ecf8c28 100644 --- a/drivers/net/pch_gbe.c +++ b/drivers/net/pch_gbe.c @@ -414,16 +414,13 @@ static int pch_gbe_phy_init(struct udevice *dev) struct pch_gbe_priv *priv = dev_get_priv(dev); struct eth_pdata *plat = dev_get_plat(dev); struct phy_device *phydev; - int mask = 0xffffffff; - phydev = phy_find_by_mask(priv->bus, mask); + phydev = phy_connect(priv->bus, -1, dev, plat->phy_interface); if (!phydev) { printf("pch_gbe: cannot find the phy\n"); return -1; } - phy_connect_dev(phydev, dev, plat->phy_interface); - phydev->supported &= PHY_GBIT_FEATURES; phydev->advertising = phydev->supported; diff --git a/drivers/net/pfe_eth/pfe_hw.c b/drivers/net/pfe_eth/pfe_hw.c index 4db6f31..9f2f92d 100644 --- a/drivers/net/pfe_eth/pfe_hw.c +++ b/drivers/net/pfe_eth/pfe_hw.c @@ -814,7 +814,7 @@ static inline void class_set_config(struct class_cfg *cfg) writel(0x1, CLASS_AXI_CTRL); /*Make Util AXI transactions non-bufferable */ - /*Util is disabled in U-boot, do it from here */ + /*Util is disabled in U-Boot, do it from here */ writel(0x1, UTIL_AXI_CTRL); } diff --git a/drivers/net/phy/ethernet_id.c b/drivers/net/phy/ethernet_id.c index a715e83..877a51c 100644 --- a/drivers/net/phy/ethernet_id.c +++ b/drivers/net/phy/ethernet_id.c @@ -7,6 +7,8 @@ #include <common.h> #include <dm/device_compat.h> +#include <dm/device-internal.h> +#include <dm/lists.h> #include <phy.h> #include <linux/delay.h> #include <asm/gpio.h> @@ -17,6 +19,8 @@ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev, struct phy_device *phydev; struct ofnode_phandle_args phandle_args; struct gpio_desc gpio; + const char *node_name; + struct udevice *pdev; ofnode node; u32 id, assert, deassert; u16 vendor, device; @@ -72,5 +76,18 @@ struct phy_device *phy_connect_phy_id(struct mii_dev *bus, struct udevice *dev, if (phydev) phydev->node = node; + if (IS_ENABLED(CONFIG_DM_ETH_PHY) && ofnode_valid(node)) { + node_name = ofnode_get_name(node); + ret = device_bind_driver_to_node(dev, "eth_phy_generic_drv", + node_name, node, + &pdev); + if (ret) + return NULL; + + ret = device_probe(pdev); + if (ret) + return NULL; + } + return phydev; } diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 0eeb0cb..ae21acb 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -812,8 +812,8 @@ struct phy_device *phy_find_by_mask(struct mii_dev *bus, uint phy_mask) return get_phy_device_by_mask(bus, phy_mask); } -void phy_connect_dev(struct phy_device *phydev, struct udevice *dev, - phy_interface_t interface) +static void phy_connect_dev(struct phy_device *phydev, struct udevice *dev, + phy_interface_t interface) { /* Soft Reset the PHY */ phy_reset(phydev); diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index c74c8a8..0bcd6cf 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -131,7 +131,6 @@ struct ravb_priv { struct mii_dev *bus; void __iomem *iobase; struct clk_bulk clks; - struct gpio_desc reset_gpio; }; static inline void ravb_flush_dcache(u32 addr, u32 len) @@ -312,13 +311,6 @@ static int ravb_phy_config(struct udevice *dev) struct phy_device *phydev; int reg; - if (dm_gpio_is_valid(ð->reset_gpio)) { - dm_gpio_set_value(ð->reset_gpio, 1); - mdelay(20); - dm_gpio_set_value(ð->reset_gpio, 0); - mdelay(1); - } - phydev = phy_connect(eth->bus, -1, dev, pdata->phy_interface); if (!phydev) return -ENODEV; @@ -503,7 +495,6 @@ static int ravb_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_plat(dev); struct ravb_priv *eth = dev_get_priv(dev); - struct ofnode_phandle_args phandle_args; struct mii_dev *mdiodev; void __iomem *iobase; int ret; @@ -515,17 +506,6 @@ static int ravb_probe(struct udevice *dev) if (ret < 0) goto err_mdio_alloc; - ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args); - if (!ret) { - gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0, - ð->reset_gpio, GPIOD_IS_OUT); - } - - if (!dm_gpio_is_valid(ð->reset_gpio)) { - gpio_request_by_name(dev, "reset-gpios", 0, ð->reset_gpio, - GPIOD_IS_OUT); - } - mdiodev = mdio_alloc(); if (!mdiodev) { ret = -ENOMEM; @@ -576,8 +556,6 @@ static int ravb_remove(struct udevice *dev) free(eth->phydev); mdio_unregister(eth->bus); mdio_free(eth->bus); - if (dm_gpio_is_valid(ð->reset_gpio)) - dm_gpio_free(dev, ð->reset_gpio); unmap_physmem(eth->iobase, MAP_NOCACHE); return 0; diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 8f162ca..7b1f59d 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -129,11 +129,11 @@ static int sh_eth_recv_start(struct sh_eth_dev *eth) /* Check if the rx descriptor is ready */ invalidate_cache(port_info->rx_desc_cur, sizeof(struct rx_desc_s)); if (port_info->rx_desc_cur->rd0 & RD_RACT) - return -EINVAL; + return -EAGAIN; /* Check for errors */ if (port_info->rx_desc_cur->rd0 & RD_RFE) - return -EINVAL; + return 0; return port_info->rx_desc_cur->rd1 & 0xffff; } @@ -142,6 +142,8 @@ static void sh_eth_recv_finish(struct sh_eth_dev *eth) { struct sh_eth_info *port_info = ð->port_info[eth->port]; + invalidate_cache(ADDR_TO_P2(port_info->rx_desc_cur->rd2), MAX_BUF_SIZE); + /* Make current descriptor available again */ if (port_info->rx_desc_cur->rd0 & RD_RDLE) port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE; @@ -210,8 +212,6 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) goto err; } - flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size); - /* Make sure we use a P2 address (non-cacheable) */ port_info->tx_desc_base = (struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc); @@ -229,6 +229,7 @@ static int sh_eth_tx_desc_init(struct sh_eth_dev *eth) cur_tx_desc--; cur_tx_desc->td0 |= TD_TDLE; + flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size); /* * Point the controller to the tx descriptor list. Must use physical * addresses @@ -264,8 +265,6 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) goto err; } - flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size); - /* Make sure we use a P2 address (non-cacheable) */ port_info->rx_desc_base = (struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc); @@ -299,6 +298,9 @@ static int sh_eth_rx_desc_init(struct sh_eth_dev *eth) cur_rx_desc--; cur_rx_desc->rd0 |= RD_RDLE; + invalidate_cache(port_info->rx_buf_alloc, NUM_RX_DESC * MAX_BUF_SIZE); + flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size); + /* Point the controller to the rx descriptor list */ sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR); #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) @@ -530,7 +532,6 @@ struct sh_ether_priv { struct mii_dev *bus; phys_addr_t iobase; struct clk clk; - struct gpio_desc reset_gpio; }; static int sh_ether_send(struct udevice *dev, void *packet, int len) @@ -555,15 +556,13 @@ static int sh_ether_recv(struct udevice *dev, int flags, uchar **packetp) *packetp = packet; return len; - } else { - len = 0; + } - /* Restart the receiver if disabled */ - if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) - sh_eth_write(port_info, EDRRR_R, EDRRR); + /* Restart the receiver if disabled */ + if (!(sh_eth_read(port_info, EDRRR) & EDRRR_R)) + sh_eth_write(port_info, EDRRR_R, EDRRR); - return -EAGAIN; - } + return len; } static int sh_ether_free_pkt(struct udevice *dev, uchar *packet, int length) @@ -601,14 +600,11 @@ static int sh_eth_phy_config(struct udevice *dev) int ret = 0; struct sh_eth_info *port_info = ð->port_info[eth->port]; struct phy_device *phydev; - int mask = 0xffffffff; - phydev = phy_find_by_mask(priv->bus, mask); + phydev = phy_connect(priv->bus, -1, dev, pdata->phy_interface); if (!phydev) return -ENODEV; - phy_connect_dev(phydev, dev, pdata->phy_interface); - port_info->phydev = phydev; phy_config(phydev); @@ -653,7 +649,6 @@ static int sh_ether_probe(struct udevice *udev) struct eth_pdata *pdata = dev_get_plat(udev); struct sh_ether_priv *priv = dev_get_priv(udev); struct sh_eth_dev *eth = &priv->shdev; - struct ofnode_phandle_args phandle_args; struct mii_dev *mdiodev; int ret; @@ -664,18 +659,6 @@ static int sh_ether_probe(struct udevice *udev) if (ret < 0) return ret; #endif - - ret = dev_read_phandle_with_args(udev, "phy-handle", NULL, 0, 0, &phandle_args); - if (!ret) { - gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0, - &priv->reset_gpio, GPIOD_IS_OUT); - } - - if (!dm_gpio_is_valid(&priv->reset_gpio)) { - gpio_request_by_name(udev, "reset-gpios", 0, &priv->reset_gpio, - GPIOD_IS_OUT); - } - mdiodev = mdio_alloc(); if (!mdiodev) { ret = -ENOMEM; @@ -738,9 +721,6 @@ static int sh_ether_remove(struct udevice *udev) mdio_unregister(priv->bus); mdio_free(priv->bus); - if (dm_gpio_is_valid(&priv->reset_gpio)) - dm_gpio_free(udev, &priv->reset_gpio); - return 0; } diff --git a/drivers/net/sni_ave.c b/drivers/net/sni_ave.c index 014b070..f5a0d80 100644 --- a/drivers/net/sni_ave.c +++ b/drivers/net/sni_ave.c @@ -391,14 +391,12 @@ static int ave_mdiobus_init(struct ave_private *priv, const char *name) static int ave_phy_init(struct ave_private *priv, void *dev) { struct phy_device *phydev; - int mask = GENMASK(31, 0), ret; + int ret; - phydev = phy_find_by_mask(priv->bus, mask); + phydev = phy_connect(priv->bus, -1, dev, priv->phy_mode); if (!phydev) return -ENODEV; - phy_connect_dev(phydev, dev, priv->phy_mode); - phydev->supported &= PHY_GBIT_FEATURES; if (priv->max_speed) { ret = phy_set_supported(phydev, priv->max_speed); diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index ad9e1ab..4c90d4b 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -248,10 +248,10 @@ static int emac_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev) { - int ret, mask = 0xffffffff; + int ret, mask = -1; #ifdef CONFIG_PHY_ADDR - mask = 1 << CONFIG_PHY_ADDR; + mask = CONFIG_PHY_ADDR; #endif priv->bus = mdio_alloc(); @@ -269,11 +269,10 @@ static int sunxi_emac_init_phy(struct emac_eth_dev *priv, void *dev) if (ret) return ret; - priv->phydev = phy_find_by_mask(priv->bus, mask); + priv->phydev = phy_connect(priv->bus, mask, dev, PHY_INTERFACE_MODE_MII); if (!priv->phydev) return -ENODEV; - phy_connect_dev(priv->phydev, dev, PHY_INTERFACE_MODE_MII); phy_config(priv->phydev); return 0; diff --git a/drivers/net/ti/davinci_emac.c b/drivers/net/ti/davinci_emac.c index 29d2fc9..034877a 100644 --- a/drivers/net/ti/davinci_emac.c +++ b/drivers/net/ti/davinci_emac.c @@ -833,9 +833,9 @@ static int davinci_emac_probe(struct udevice *dev) #endif } -#if defined(CONFIG_TI816X) || (defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ +#if defined(CONFIG_DRIVER_TI_EMAC_USE_RMII) && \ defined(CONFIG_MACH_DAVINCI_DA850_EVM) && \ - !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE)) + !defined(CONFIG_DRIVER_TI_EMAC_RMII_NO_NEGOTIATE) for (i = 0; i < num_phy; i++) { if (phy[i].is_phy_connected(i)) phy[i].auto_negotiate(i); diff --git a/drivers/nvme/Makefile b/drivers/nvme/Makefile index fa7b619..fd3e68a 100644 --- a/drivers/nvme/Makefile +++ b/drivers/nvme/Makefile @@ -4,4 +4,4 @@ obj-y += nvme-uclass.o nvme.o nvme_show.o obj-$(CONFIG_NVME_APPLE) += nvme_apple.o -obj-$(CONFIG_NVME_PCI) += nvme_pci.o +obj-$(CONFIG_$(SPL_)NVME_PCI) += nvme_pci.o diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index ef328d2..84a2ae9 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -40,6 +40,12 @@ config PCI_PNP help Enable PCI memory and I/O space resource allocation and assignment. +config SPL_PCI_PNP + bool "Enable Plug & Play support for PCI" + help + Enable PCI memory and I/O space resource allocation and assignment. + This is required to auto configure the enumerated devices. + config PCI_REGION_MULTI_ENTRY bool "Enable Multiple entries of region type MEMORY in ranges for PCI" help @@ -374,4 +380,11 @@ config PCIE_UNIPHIER Say Y here if you want to enable PCIe controller support on UniPhier SoCs. +config PCIE_XILINX_NWL + bool "Xilinx NWL PCIe controller" + depends on ARCH_ZYNQMP + help + Say 'Y' here if you want support for Xilinx / AMD NWL PCIe + controller as Root Port. + endif diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile index 49506e7..11f60c6 100644 --- a/drivers/pci/Makefile +++ b/drivers/pci/Makefile @@ -49,3 +49,4 @@ obj-$(CONFIG_PCI_OCTEONTX) += pci_octeontx.o obj-$(CONFIG_PCIE_OCTEON) += pcie_octeon.o obj-$(CONFIG_PCIE_DW_SIFIVE) += pcie_dw_sifive.o obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o +obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o diff --git a/drivers/pci/pcie-xilinx-nwl.c b/drivers/pci/pcie-xilinx-nwl.c new file mode 100644 index 0000000..7ef2bdf --- /dev/null +++ b/drivers/pci/pcie-xilinx-nwl.c @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe host bridge driver for Xilinx / AMD ZynqMP NWL PCIe Bridge + * + * Based on the Linux driver which is: + * (C) Copyright 2014 - 2015, Xilinx, Inc. + * + * Author: Stefan Roese <sr@denx.de> + */ + +#include <clk.h> +#include <dm.h> +#include <dm/device_compat.h> +#include <dm/devres.h> +#include <mapmem.h> +#include <pci.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/ioport.h> + +/* Bridge core config registers */ +#define BRCFG_PCIE_RX0 0x00000000 +#define BRCFG_PCIE_RX1 0x00000004 +#define BRCFG_INTERRUPT 0x00000010 +#define BRCFG_PCIE_RX_MSG_FILTER 0x00000020 + +/* Egress - Bridge translation registers */ +#define E_BREG_CAPABILITIES 0x00000200 +#define E_BREG_CONTROL 0x00000208 +#define E_BREG_BASE_LO 0x00000210 +#define E_BREG_BASE_HI 0x00000214 +#define E_ECAM_CAPABILITIES 0x00000220 +#define E_ECAM_CONTROL 0x00000228 +#define E_ECAM_BASE_LO 0x00000230 +#define E_ECAM_BASE_HI 0x00000234 + +#define I_ISUB_CONTROL 0x000003E8 +#define SET_ISUB_CONTROL BIT(0) +/* Rxed msg fifo - Interrupt status registers */ +#define MSGF_MISC_STATUS 0x00000400 +#define MSGF_MISC_MASK 0x00000404 +#define MSGF_LEG_STATUS 0x00000420 +#define MSGF_LEG_MASK 0x00000424 +#define MSGF_MSI_STATUS_LO 0x00000440 +#define MSGF_MSI_STATUS_HI 0x00000444 +#define MSGF_MSI_MASK_LO 0x00000448 +#define MSGF_MSI_MASK_HI 0x0000044C + +/* Msg filter mask bits */ +#define CFG_ENABLE_PM_MSG_FWD BIT(1) +#define CFG_ENABLE_INT_MSG_FWD BIT(2) +#define CFG_ENABLE_ERR_MSG_FWD BIT(3) +#define CFG_ENABLE_MSG_FILTER_MASK (CFG_ENABLE_PM_MSG_FWD | \ + CFG_ENABLE_INT_MSG_FWD | \ + CFG_ENABLE_ERR_MSG_FWD) + +/* Misc interrupt status mask bits */ +#define MSGF_MISC_SR_RXMSG_AVAIL BIT(0) +#define MSGF_MISC_SR_RXMSG_OVER BIT(1) +#define MSGF_MISC_SR_SLAVE_ERR BIT(4) +#define MSGF_MISC_SR_MASTER_ERR BIT(5) +#define MSGF_MISC_SR_I_ADDR_ERR BIT(6) +#define MSGF_MISC_SR_E_ADDR_ERR BIT(7) +#define MSGF_MISC_SR_FATAL_AER BIT(16) +#define MSGF_MISC_SR_NON_FATAL_AER BIT(17) +#define MSGF_MISC_SR_CORR_AER BIT(18) +#define MSGF_MISC_SR_UR_DETECT BIT(20) +#define MSGF_MISC_SR_NON_FATAL_DEV BIT(22) +#define MSGF_MISC_SR_FATAL_DEV BIT(23) +#define MSGF_MISC_SR_LINK_DOWN BIT(24) +#define MSGF_MSIC_SR_LINK_AUTO_BWIDTH BIT(25) +#define MSGF_MSIC_SR_LINK_BWIDTH BIT(26) + +#define MSGF_MISC_SR_MASKALL (MSGF_MISC_SR_RXMSG_AVAIL | \ + MSGF_MISC_SR_RXMSG_OVER | \ + MSGF_MISC_SR_SLAVE_ERR | \ + MSGF_MISC_SR_MASTER_ERR | \ + MSGF_MISC_SR_I_ADDR_ERR | \ + MSGF_MISC_SR_E_ADDR_ERR | \ + MSGF_MISC_SR_FATAL_AER | \ + MSGF_MISC_SR_NON_FATAL_AER | \ + MSGF_MISC_SR_CORR_AER | \ + MSGF_MISC_SR_UR_DETECT | \ + MSGF_MISC_SR_NON_FATAL_DEV | \ + MSGF_MISC_SR_FATAL_DEV | \ + MSGF_MISC_SR_LINK_DOWN | \ + MSGF_MSIC_SR_LINK_AUTO_BWIDTH | \ + MSGF_MSIC_SR_LINK_BWIDTH) + +/* Legacy interrupt status mask bits */ +#define MSGF_LEG_SR_INTA BIT(0) +#define MSGF_LEG_SR_INTB BIT(1) +#define MSGF_LEG_SR_INTC BIT(2) +#define MSGF_LEG_SR_INTD BIT(3) +#define MSGF_LEG_SR_MASKALL (MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \ + MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD) + +/* MSI interrupt status mask bits */ +#define MSGF_MSI_SR_LO_MASK GENMASK(31, 0) +#define MSGF_MSI_SR_HI_MASK GENMASK(31, 0) + +/* Bridge config interrupt mask */ +#define BRCFG_INTERRUPT_MASK BIT(0) +#define BREG_PRESENT BIT(0) +#define BREG_ENABLE BIT(0) +#define BREG_ENABLE_FORCE BIT(1) + +/* E_ECAM status mask bits */ +#define E_ECAM_PRESENT BIT(0) +#define E_ECAM_CR_ENABLE BIT(0) +#define E_ECAM_SIZE_LOC GENMASK(20, 16) +#define E_ECAM_SIZE_SHIFT 16 +#define NWL_ECAM_VALUE_DEFAULT 12 + +#define CFG_DMA_REG_BAR GENMASK(2, 0) +#define CFG_PCIE_CACHE GENMASK(7, 0) + +/* Readin the PS_LINKUP */ +#define PS_LINKUP_OFFSET 0x00000238 +#define PCIE_PHY_LINKUP_BIT BIT(0) +#define PHY_RDY_LINKUP_BIT BIT(1) + +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + +struct nwl_pcie { + struct udevice *dev; + void __iomem *breg_base; + void __iomem *pcireg_base; + void __iomem *ecam_base; + phys_addr_t phys_breg_base; /* Physical Bridge Register Base */ + phys_addr_t phys_ecam_base; /* Physical Configuration Base */ + u32 ecam_value; +}; + +static int nwl_pcie_config_address(const struct udevice *bus, + pci_dev_t bdf, uint offset, + void **paddress) +{ + struct nwl_pcie *pcie = dev_get_priv(bus); + void *addr; + + addr = pcie->ecam_base; + addr += PCIE_ECAM_OFFSET(PCI_BUS(bdf) - dev_seq(bus), + PCI_DEV(bdf), PCI_FUNC(bdf), offset); + *paddress = addr; + + return 0; +} + +static int nwl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf, + uint offset, ulong *valuep, + enum pci_size_t size) +{ + return pci_generic_mmap_read_config(bus, nwl_pcie_config_address, + bdf, offset, valuep, size); +} + +static int nwl_pcie_write_config(struct udevice *bus, pci_dev_t bdf, + uint offset, ulong value, + enum pci_size_t size) +{ + return pci_generic_mmap_write_config(bus, nwl_pcie_config_address, + bdf, offset, value, size); +} + +static const struct dm_pci_ops nwl_pcie_ops = { + .read_config = nwl_pcie_read_config, + .write_config = nwl_pcie_write_config, +}; + +static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off) +{ + return readl(pcie->breg_base + off); +} + +static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off) +{ + writel(val, pcie->breg_base + off); +} + +static bool nwl_pcie_link_up(struct nwl_pcie *pcie) +{ + if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT) + return true; + return false; +} + +static bool nwl_phy_link_up(struct nwl_pcie *pcie) +{ + if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT) + return true; + return false; +} + +static int nwl_wait_for_link(struct nwl_pcie *pcie) +{ + struct udevice *dev = pcie->dev; + int retries; + + /* check if the link is up or not */ + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (nwl_phy_link_up(pcie)) + return 0; + udelay(LINK_WAIT_USLEEP_MIN); + } + + dev_warn(dev, "PHY link never came up\n"); + return -ETIMEDOUT; +} + +static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) +{ + struct udevice *dev = pcie->dev; + u32 breg_val, ecam_val; + int err; + + breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; + if (!breg_val) { + dev_err(dev, "BREG is not present\n"); + return breg_val; + } + + /* Write bridge_off to breg base */ + nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base), + E_BREG_BASE_LO); + nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base), + E_BREG_BASE_HI); + + /* Enable BREG */ + nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE, + E_BREG_CONTROL); + + /* Disable DMA channel registers */ + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) | + CFG_DMA_REG_BAR, BRCFG_PCIE_RX0); + + /* Enable Ingress subtractive decode translation */ + nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL); + + /* Enable msg filtering details */ + nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK, + BRCFG_PCIE_RX_MSG_FILTER); + + err = nwl_wait_for_link(pcie); + if (err) + return err; + + ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT; + if (!ecam_val) { + dev_err(dev, "ECAM is not present\n"); + return ecam_val; + } + + /* Enable ECAM */ + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | + E_ECAM_CR_ENABLE, E_ECAM_CONTROL); + + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | + (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + E_ECAM_CONTROL); + + nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), + E_ECAM_BASE_LO); + nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), + E_ECAM_BASE_HI); + + if (nwl_pcie_link_up(pcie)) + dev_info(dev, "Link is UP\n"); + else + dev_info(dev, "Link is DOWN\n"); + + /* Disable all misc interrupts */ + nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK); + + /* Clear pending misc interrupts */ + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) & + MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS); + + /* Disable all legacy interrupts */ + nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK); + + /* Clear pending legacy interrupts */ + nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) & + MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS); + + return 0; +} + +static int nwl_pcie_parse_dt(struct nwl_pcie *pcie) +{ + struct udevice *dev = pcie->dev; + struct resource res; + int ret; + + ret = dev_read_resource_byname(dev, "breg", &res); + if (ret) + return ret; + pcie->breg_base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(pcie->breg_base)) + return PTR_ERR(pcie->breg_base); + pcie->phys_breg_base = res.start; + + ret = dev_read_resource_byname(dev, "cfg", &res); + if (ret) + return ret; + pcie->ecam_base = devm_ioremap(dev, res.start, resource_size(&res)); + if (IS_ERR(pcie->ecam_base)) + return PTR_ERR(pcie->ecam_base); + pcie->phys_ecam_base = res.start; + + return 0; +} + +static int nwl_pcie_probe(struct udevice *dev) +{ + struct nwl_pcie *pcie = dev_get_priv(dev); + int err; + + pcie->dev = dev; + pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; + + err = nwl_pcie_parse_dt(pcie); + if (err) { + dev_err(dev, "Parsing DT failed\n"); + return err; + } + + err = nwl_pcie_bridge_init(pcie); + if (err) { + dev_err(dev, "HW Initialization failed\n"); + return err; + } + + return 0; +} + +static const struct udevice_id nwl_pcie_of_match[] = { + { .compatible = "xlnx,nwl-pcie-2.11", }, + { /* sentinel */ } +}; + +U_BOOT_DRIVER(nwl_pcie) = { + .name = "nwl-pcie", + .id = UCLASS_PCI, + .of_match = nwl_pcie_of_match, + .probe = nwl_pcie_probe, + .priv_auto = sizeof(struct nwl_pcie), + .ops = &nwl_pcie_ops, +}; diff --git a/drivers/phy/marvell/comphy_cp110.c b/drivers/phy/marvell/comphy_cp110.c index e063b51..a7e0099 100644 --- a/drivers/phy/marvell/comphy_cp110.c +++ b/drivers/phy/marvell/comphy_cp110.c @@ -25,7 +25,7 @@ DECLARE_GLOBAL_DATA_PTR; #define MV_SIP_COMPHY_PLL_LOCK 0x82000003 #define MV_SIP_COMPHY_XFI_TRAIN 0x82000004 -/* Used to distinguish between different possible callers (U-boot/Linux) */ +/* Used to distinguish between different possible callers (U-Boot/Linux) */ #define COMPHY_CALLER_UBOOT (0x1 << 21) #define COMPHY_FW_MODE_FORMAT(mode) ((mode) << 12) diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 2339717..34314d0 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -256,6 +256,7 @@ enum wiz_type { J721E_WIZ_10G, AM64_WIZ_10G, J784S4_WIZ_10G, + J721S2_WIZ_10G, }; struct wiz_data { @@ -307,6 +308,15 @@ static struct wiz_data j784s4_wiz_10g = { .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, }; +static struct wiz_data j721s2_10g_data = { + .type = J721S2_WIZ_10G, + .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, + .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, + .refclk_dig_sel = &refclk_dig_sel_10g, + .clk_mux_sel = clk_mux_sel_10g, + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, +}; + #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 @@ -1037,8 +1047,14 @@ static int j721e_wiz_bind_of_clocks(struct wiz *wiz) ofnode node; int i, rc; - if (type == AM64_WIZ_10G || type == J784S4_WIZ_10G) + switch (type) { + case AM64_WIZ_10G: + case J784S4_WIZ_10G: + case J721S2_WIZ_10G: return j721e_wiz_bind_clocks(wiz); + default: + break; + }; div_clk_drv = lists_driver_lookup_name("wiz_div_clk"); if (!div_clk_drv) { @@ -1282,6 +1298,9 @@ static const struct udevice_id j721e_wiz_ids[] = { { .compatible = "ti,j784s4-wiz-10g", .data = (ulong)&j784s4_wiz_10g, }, + { + .compatible = "ti,j721s2-wiz-10g", .data = (ulong)&j721s2_10g_data, + }, {} }; diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.h b/drivers/pinctrl/exynos/pinctrl-exynos.h index a7788b7..cbc5174 100644 --- a/drivers/pinctrl/exynos/pinctrl-exynos.h +++ b/drivers/pinctrl/exynos/pinctrl-exynos.h @@ -6,7 +6,7 @@ */ #ifndef __PINCTRL_EXYNOS_H_ -#define __PINCTRL_EXYNOS__H_ +#define __PINCTRL_EXYNOS_H_ #define PIN_CON 0x00 /* Offset of pin function register */ #define PIN_DAT 0x04 /* Offset of pin data register */ diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig index ef02087..97e5743 100644 --- a/drivers/pinctrl/meson/Kconfig +++ b/drivers/pinctrl/meson/Kconfig @@ -29,4 +29,8 @@ config PINCTRL_MESON_G12A bool "Amlogic Meson G12a SoC pinctrl driver" select PINCTRL_MESON_AXG_PMX +config PINCTRL_MESON_A1 + bool "Amlogic Meson A1 SoC pinctrl driver" + select PINCTRL_MESON_AXG_PMX + endif diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile index 80dba65..8d10d02 100644 --- a/drivers/pinctrl/meson/Makefile +++ b/drivers/pinctrl/meson/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_PINCTRL_MESON_GXBB) += pinctrl-meson-gxbb.o obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o +obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c b/drivers/pinctrl/meson/pinctrl-meson-a1.c new file mode 100644 index 0000000..30cf3bc --- /dev/null +++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c @@ -0,0 +1,867 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song <qianggui.song@amlogic.com> + * Copyright (C) 2023 SberDevices, Inc. + * Author: Igor Prusov <ivprusov@sberdevices.ru> + */ + +#include <common.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <dt-bindings/gpio/meson-a1-gpio.h> + +#include "pinctrl-meson.h" +#include "pinctrl-meson-axg.h" + +/* psram */ +static const unsigned int psram_clkn_pins[] = { GPIOP_0 }; +static const unsigned int psram_clkp_pins[] = { GPIOP_1 }; +static const unsigned int psram_ce_n_pins[] = { GPIOP_2 }; +static const unsigned int psram_rst_n_pins[] = { GPIOP_3 }; +static const unsigned int psram_adq0_pins[] = { GPIOP_4 }; +static const unsigned int psram_adq1_pins[] = { GPIOP_5 }; +static const unsigned int psram_adq2_pins[] = { GPIOP_6 }; +static const unsigned int psram_adq3_pins[] = { GPIOP_7 }; +static const unsigned int psram_adq4_pins[] = { GPIOP_8 }; +static const unsigned int psram_adq5_pins[] = { GPIOP_9 }; +static const unsigned int psram_adq6_pins[] = { GPIOP_10 }; +static const unsigned int psram_adq7_pins[] = { GPIOP_11 }; +static const unsigned int psram_dqs_dm_pins[] = { GPIOP_12 }; + +/* sdcard */ +static const unsigned int sdcard_d0_b_pins[] = { GPIOB_0 }; +static const unsigned int sdcard_d1_b_pins[] = { GPIOB_1 }; +static const unsigned int sdcard_d2_b_pins[] = { GPIOB_2 }; +static const unsigned int sdcard_d3_b_pins[] = { GPIOB_3 }; +static const unsigned int sdcard_clk_b_pins[] = { GPIOB_4 }; +static const unsigned int sdcard_cmd_b_pins[] = { GPIOB_5 }; + +static const unsigned int sdcard_d0_x_pins[] = { GPIOX_0 }; +static const unsigned int sdcard_d1_x_pins[] = { GPIOX_1 }; +static const unsigned int sdcard_d2_x_pins[] = { GPIOX_2 }; +static const unsigned int sdcard_d3_x_pins[] = { GPIOX_3 }; +static const unsigned int sdcard_clk_x_pins[] = { GPIOX_4 }; +static const unsigned int sdcard_cmd_x_pins[] = { GPIOX_5 }; + +/* spif */ +static const unsigned int spif_mo_pins[] = { GPIOB_0 }; +static const unsigned int spif_mi_pins[] = { GPIOB_1 }; +static const unsigned int spif_wp_n_pins[] = { GPIOB_2 }; +static const unsigned int spif_hold_n_pins[] = { GPIOB_3 }; +static const unsigned int spif_clk_pins[] = { GPIOB_4 }; +static const unsigned int spif_cs_pins[] = { GPIOB_5 }; + +/* i2c0 */ +static const unsigned int i2c0_sck_f9_pins[] = { GPIOF_9 }; +static const unsigned int i2c0_sda_f10_pins[] = { GPIOF_10 }; +static const unsigned int i2c0_sck_f11_pins[] = { GPIOF_11 }; +static const unsigned int i2c0_sda_f12_pins[] = { GPIOF_12 }; + +/* i2c1 */ +static const unsigned int i2c1_sda_x_pins[] = { GPIOX_9 }; +static const unsigned int i2c1_sck_x_pins[] = { GPIOX_10 }; +static const unsigned int i2c1_sda_a_pins[] = { GPIOA_10 }; +static const unsigned int i2c1_sck_a_pins[] = { GPIOA_11 }; + +/* i2c2 */ +static const unsigned int i2c2_sck_x0_pins[] = { GPIOX_0 }; +static const unsigned int i2c2_sda_x1_pins[] = { GPIOX_1 }; +static const unsigned int i2c2_sck_x15_pins[] = { GPIOX_15 }; +static const unsigned int i2c2_sda_x16_pins[] = { GPIOX_16 }; +static const unsigned int i2c2_sck_a4_pins[] = { GPIOA_4 }; +static const unsigned int i2c2_sda_a5_pins[] = { GPIOA_5 }; +static const unsigned int i2c2_sck_a8_pins[] = { GPIOA_8 }; +static const unsigned int i2c2_sda_a9_pins[] = { GPIOA_9 }; + +/* i2c3 */ +static const unsigned int i2c3_sck_f_pins[] = { GPIOF_4 }; +static const unsigned int i2c3_sda_f_pins[] = { GPIOF_5 }; +static const unsigned int i2c3_sck_x_pins[] = { GPIOX_11 }; +static const unsigned int i2c3_sda_x_pins[] = { GPIOX_12 }; + +/* i2c slave */ +static const unsigned int i2c_slave_sck_a_pins[] = { GPIOA_10 }; +static const unsigned int i2c_slave_sda_a_pins[] = { GPIOA_11 }; +static const unsigned int i2c_slave_sck_f_pins[] = { GPIOF_11 }; +static const unsigned int i2c_slave_sda_f_pins[] = { GPIOF_12 }; + +/* uart_a */ +static const unsigned int uart_a_tx_pins[] = { GPIOX_11 }; +static const unsigned int uart_a_rx_pins[] = { GPIOX_12 }; +static const unsigned int uart_a_cts_pins[] = { GPIOX_13 }; +static const unsigned int uart_a_rts_pins[] = { GPIOX_14 }; + +/* uart_b */ +static const unsigned int uart_b_tx_x_pins[] = { GPIOX_7 }; +static const unsigned int uart_b_rx_x_pins[] = { GPIOX_8 }; +static const unsigned int uart_b_tx_f_pins[] = { GPIOF_0 }; +static const unsigned int uart_b_rx_f_pins[] = { GPIOF_1 }; + +/* uart_c */ +static const unsigned int uart_c_tx_x0_pins[] = { GPIOX_0 }; +static const unsigned int uart_c_rx_x1_pins[] = { GPIOX_1 }; +static const unsigned int uart_c_cts_pins[] = { GPIOX_2 }; +static const unsigned int uart_c_rts_pins[] = { GPIOX_3 }; +static const unsigned int uart_c_tx_x15_pins[] = { GPIOX_15 }; +static const unsigned int uart_c_rx_x16_pins[] = { GPIOX_16 }; + +/* pmw_a */ +static const unsigned int pwm_a_x6_pins[] = { GPIOX_6 }; +static const unsigned int pwm_a_x7_pins[] = { GPIOX_7 }; +static const unsigned int pwm_a_f6_pins[] = { GPIOF_6 }; +static const unsigned int pwm_a_f10_pins[] = { GPIOF_10 }; +static const unsigned int pwm_a_a_pins[] = { GPIOA_5 }; + +/* pmw_b */ +static const unsigned int pwm_b_x_pins[] = { GPIOX_8 }; +static const unsigned int pwm_b_f_pins[] = { GPIOF_7 }; +static const unsigned int pwm_b_a_pins[] = { GPIOA_11 }; + +/* pmw_c */ +static const unsigned int pwm_c_x_pins[] = { GPIOX_9 }; +static const unsigned int pwm_c_f3_pins[] = { GPIOF_3 }; +static const unsigned int pwm_c_f8_pins[] = { GPIOF_8 }; +static const unsigned int pwm_c_a_pins[] = { GPIOA_10 }; + +/* pwm_d */ +static const unsigned int pwm_d_x10_pins[] = { GPIOX_10 }; +static const unsigned int pwm_d_x13_pins[] = { GPIOX_13 }; +static const unsigned int pwm_d_x15_pins[] = { GPIOX_15 }; +static const unsigned int pwm_d_f_pins[] = { GPIOF_11 }; + +/* pwm_e */ +static const unsigned int pwm_e_p_pins[] = { GPIOP_3 }; +static const unsigned int pwm_e_x2_pins[] = { GPIOX_2 }; +static const unsigned int pwm_e_x14_pins[] = { GPIOX_14 }; +static const unsigned int pwm_e_x16_pins[] = { GPIOX_16 }; +static const unsigned int pwm_e_f_pins[] = { GPIOF_3 }; +static const unsigned int pwm_e_a_pins[] = { GPIOA_0 }; + +/* pwm_f */ +static const unsigned int pwm_f_b_pins[] = { GPIOB_6 }; +static const unsigned int pwm_f_x_pins[] = { GPIOX_3 }; +static const unsigned int pwm_f_f4_pins[] = { GPIOF_4 }; +static const unsigned int pwm_f_f12_pins[] = { GPIOF_12 }; + +/* pwm_a_hiz */ +static const unsigned int pwm_a_hiz_f8_pins[] = { GPIOF_8 }; +static const unsigned int pwm_a_hiz_f10_pins[] = { GPIOF_10 }; +static const unsigned int pmw_a_hiz_f6_pins[] = { GPIOF_6 }; + +/* pwm_b_hiz */ +static const unsigned int pwm_b_hiz_pins[] = { GPIOF_7 }; + +/* pmw_c_hiz */ +static const unsigned int pwm_c_hiz_pins[] = { GPIOF_8 }; + +/* tdm_a */ +static const unsigned int tdm_a_dout1_pins[] = { GPIOX_7 }; +static const unsigned int tdm_a_dout0_pins[] = { GPIOX_8 }; +static const unsigned int tdm_a_fs_pins[] = { GPIOX_9 }; +static const unsigned int tdm_a_sclk_pins[] = { GPIOX_10 }; +static const unsigned int tdm_a_din1_pins[] = { GPIOX_7 }; +static const unsigned int tdm_a_din0_pins[] = { GPIOX_8 }; +static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_9 }; +static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_10 }; + +/* spi_a */ +static const unsigned int spi_a_mosi_x2_pins[] = { GPIOX_2 }; +static const unsigned int spi_a_ss0_x3_pins[] = { GPIOX_3 }; +static const unsigned int spi_a_sclk_x4_pins[] = { GPIOX_4 }; +static const unsigned int spi_a_miso_x5_pins[] = { GPIOX_5 }; +static const unsigned int spi_a_mosi_x7_pins[] = { GPIOX_7 }; +static const unsigned int spi_a_miso_x8_pins[] = { GPIOX_8 }; +static const unsigned int spi_a_ss0_x9_pins[] = { GPIOX_9 }; +static const unsigned int spi_a_sclk_x10_pins[] = { GPIOX_10 }; + +static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_6 }; +static const unsigned int spi_a_miso_a_pins[] = { GPIOA_7 }; +static const unsigned int spi_a_ss0_a_pins[] = { GPIOA_8 }; +static const unsigned int spi_a_sclk_a_pins[] = { GPIOA_9 }; + +/* pdm */ +static const unsigned int pdm_din0_x_pins[] = { GPIOX_7 }; +static const unsigned int pdm_din1_x_pins[] = { GPIOX_8 }; +static const unsigned int pdm_din2_x_pins[] = { GPIOX_9 }; +static const unsigned int pdm_dclk_x_pins[] = { GPIOX_10 }; + +static const unsigned int pdm_din2_a_pins[] = { GPIOA_6 }; +static const unsigned int pdm_din1_a_pins[] = { GPIOA_7 }; +static const unsigned int pdm_din0_a_pins[] = { GPIOA_8 }; +static const unsigned int pdm_dclk_pins[] = { GPIOA_9 }; + +/* gen_clk */ +static const unsigned int gen_clk_x_pins[] = { GPIOX_7 }; +static const unsigned int gen_clk_f8_pins[] = { GPIOF_8 }; +static const unsigned int gen_clk_f10_pins[] = { GPIOF_10 }; +static const unsigned int gen_clk_a_pins[] = { GPIOA_11 }; + +/* jtag_a */ +static const unsigned int jtag_a_clk_pins[] = { GPIOF_4 }; +static const unsigned int jtag_a_tms_pins[] = { GPIOF_5 }; +static const unsigned int jtag_a_tdi_pins[] = { GPIOF_6 }; +static const unsigned int jtag_a_tdo_pins[] = { GPIOF_7 }; + +/* clk_32_in */ +static const unsigned int clk_32k_in_pins[] = { GPIOF_2 }; + +/* ir in */ +static const unsigned int remote_input_f_pins[] = { GPIOF_3 }; +static const unsigned int remote_input_a_pins[] = { GPIOA_11 }; + +/* ir out */ +static const unsigned int remote_out_pins[] = { GPIOF_5 }; + +/* spdif */ +static const unsigned int spdif_in_f6_pins[] = { GPIOF_6 }; +static const unsigned int spdif_in_f7_pins[] = { GPIOF_7 }; + +/* sw */ +static const unsigned int swclk_pins[] = { GPIOF_4 }; +static const unsigned int swdio_pins[] = { GPIOF_5 }; + +/* clk_25 */ +static const unsigned int clk25_pins[] = { GPIOF_10 }; + +/* cec_a */ +static const unsigned int cec_a_pins[] = { GPIOF_2 }; + +/* cec_b */ +static const unsigned int cec_b_pins[] = { GPIOF_2 }; + +/* clk12_24 */ +static const unsigned int clk12_24_pins[] = { GPIOF_10 }; + +/* mclk_0 */ +static const unsigned int mclk_0_pins[] = { GPIOA_0 }; + +/* tdm_b */ +static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 }; +static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 }; +static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 }; +static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 }; +static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 }; +static const unsigned int tdm_b_dout3_pins[] = { GPIOA_6 }; +static const unsigned int tdm_b_dout4_pins[] = { GPIOA_7 }; +static const unsigned int tdm_b_dout5_pins[] = { GPIOA_8 }; +static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_5 }; +static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_6 }; +static const unsigned int tdm_b_din0_pins[] = { GPIOA_7 }; +static const unsigned int tdm_b_din1_pins[] = { GPIOA_8 }; +static const unsigned int tdm_b_din2_pins[] = { GPIOA_9 }; + +/* mclk_vad */ +static const unsigned int mclk_vad_pins[] = { GPIOA_0 }; + +/* tdm_vad */ +static const unsigned int tdm_vad_sclk_a1_pins[] = { GPIOA_1 }; +static const unsigned int tdm_vad_fs_a2_pins[] = { GPIOA_2 }; +static const unsigned int tdm_vad_sclk_a5_pins[] = { GPIOA_5 }; +static const unsigned int tdm_vad_fs_a6_pins[] = { GPIOA_6 }; + +/* tst_out */ +static const unsigned int tst_out0_pins[] = { GPIOA_0 }; +static const unsigned int tst_out1_pins[] = { GPIOA_1 }; +static const unsigned int tst_out2_pins[] = { GPIOA_2 }; +static const unsigned int tst_out3_pins[] = { GPIOA_3 }; +static const unsigned int tst_out4_pins[] = { GPIOA_4 }; +static const unsigned int tst_out5_pins[] = { GPIOA_5 }; +static const unsigned int tst_out6_pins[] = { GPIOA_6 }; +static const unsigned int tst_out7_pins[] = { GPIOA_7 }; +static const unsigned int tst_out8_pins[] = { GPIOA_8 }; +static const unsigned int tst_out9_pins[] = { GPIOA_9 }; +static const unsigned int tst_out10_pins[] = { GPIOA_10 }; +static const unsigned int tst_out11_pins[] = { GPIOA_11 }; + +/* mute */ +static const unsigned int mute_key_pins[] = { GPIOA_4 }; +static const unsigned int mute_en_pins[] = { GPIOA_5 }; + +static struct meson_pmx_group meson_a1_periphs_groups[] = { + GPIO_GROUP(GPIOP_0, 0), + GPIO_GROUP(GPIOP_1, 0), + GPIO_GROUP(GPIOP_2, 0), + GPIO_GROUP(GPIOP_3, 0), + GPIO_GROUP(GPIOP_4, 0), + GPIO_GROUP(GPIOP_5, 0), + GPIO_GROUP(GPIOP_6, 0), + GPIO_GROUP(GPIOP_7, 0), + GPIO_GROUP(GPIOP_8, 0), + GPIO_GROUP(GPIOP_9, 0), + GPIO_GROUP(GPIOP_10, 0), + GPIO_GROUP(GPIOP_11, 0), + GPIO_GROUP(GPIOP_12, 0), + GPIO_GROUP(GPIOB_0, 0), + GPIO_GROUP(GPIOB_1, 0), + GPIO_GROUP(GPIOB_2, 0), + GPIO_GROUP(GPIOB_3, 0), + GPIO_GROUP(GPIOB_4, 0), + GPIO_GROUP(GPIOB_5, 0), + GPIO_GROUP(GPIOB_6, 0), + GPIO_GROUP(GPIOX_0, 0), + GPIO_GROUP(GPIOX_1, 0), + GPIO_GROUP(GPIOX_2, 0), + GPIO_GROUP(GPIOX_3, 0), + GPIO_GROUP(GPIOX_4, 0), + GPIO_GROUP(GPIOX_5, 0), + GPIO_GROUP(GPIOX_6, 0), + GPIO_GROUP(GPIOX_7, 0), + GPIO_GROUP(GPIOX_8, 0), + GPIO_GROUP(GPIOX_9, 0), + GPIO_GROUP(GPIOX_10, 0), + GPIO_GROUP(GPIOX_11, 0), + GPIO_GROUP(GPIOX_12, 0), + GPIO_GROUP(GPIOX_13, 0), + GPIO_GROUP(GPIOX_14, 0), + GPIO_GROUP(GPIOX_15, 0), + GPIO_GROUP(GPIOX_16, 0), + GPIO_GROUP(GPIOF_0, 0), + GPIO_GROUP(GPIOF_1, 0), + GPIO_GROUP(GPIOF_2, 0), + GPIO_GROUP(GPIOF_3, 0), + GPIO_GROUP(GPIOF_4, 0), + GPIO_GROUP(GPIOF_5, 0), + GPIO_GROUP(GPIOF_6, 0), + GPIO_GROUP(GPIOF_7, 0), + GPIO_GROUP(GPIOF_8, 0), + GPIO_GROUP(GPIOF_9, 0), + GPIO_GROUP(GPIOF_10, 0), + GPIO_GROUP(GPIOF_11, 0), + GPIO_GROUP(GPIOF_12, 0), + GPIO_GROUP(GPIOA_0, 0), + GPIO_GROUP(GPIOA_1, 0), + GPIO_GROUP(GPIOA_2, 0), + GPIO_GROUP(GPIOA_3, 0), + GPIO_GROUP(GPIOA_4, 0), + GPIO_GROUP(GPIOA_5, 0), + GPIO_GROUP(GPIOA_6, 0), + GPIO_GROUP(GPIOA_7, 0), + GPIO_GROUP(GPIOA_8, 0), + GPIO_GROUP(GPIOA_9, 0), + GPIO_GROUP(GPIOA_10, 0), + GPIO_GROUP(GPIOA_11, 0), + + /* bank P func1 */ + GROUP(psram_clkn, 1), + GROUP(psram_clkp, 1), + GROUP(psram_ce_n, 1), + GROUP(psram_rst_n, 1), + GROUP(psram_adq0, 1), + GROUP(psram_adq1, 1), + GROUP(psram_adq2, 1), + GROUP(psram_adq3, 1), + GROUP(psram_adq4, 1), + GROUP(psram_adq5, 1), + GROUP(psram_adq6, 1), + GROUP(psram_adq7, 1), + GROUP(psram_dqs_dm, 1), + + /* bank P func2 */ + GROUP(pwm_e_p, 2), + + /* bank B func1 */ + GROUP(spif_mo, 1), + GROUP(spif_mi, 1), + GROUP(spif_wp_n, 1), + GROUP(spif_hold_n, 1), + GROUP(spif_clk, 1), + GROUP(spif_cs, 1), + GROUP(pwm_f_b, 1), + + /* bank B func2 */ + GROUP(sdcard_d0_b, 2), + GROUP(sdcard_d1_b, 2), + GROUP(sdcard_d2_b, 2), + GROUP(sdcard_d3_b, 2), + GROUP(sdcard_clk_b, 2), + GROUP(sdcard_cmd_b, 2), + + /* bank X func1 */ + GROUP(sdcard_d0_x, 1), + GROUP(sdcard_d1_x, 1), + GROUP(sdcard_d2_x, 1), + GROUP(sdcard_d3_x, 1), + GROUP(sdcard_clk_x, 1), + GROUP(sdcard_cmd_x, 1), + GROUP(pwm_a_x6, 1), + GROUP(tdm_a_dout1, 1), + GROUP(tdm_a_dout0, 1), + GROUP(tdm_a_fs, 1), + GROUP(tdm_a_sclk, 1), + GROUP(uart_a_tx, 1), + GROUP(uart_a_rx, 1), + GROUP(uart_a_cts, 1), + GROUP(uart_a_rts, 1), + GROUP(pwm_d_x15, 1), + GROUP(pwm_e_x16, 1), + + /* bank X func2 */ + GROUP(i2c2_sck_x0, 2), + GROUP(i2c2_sda_x1, 2), + GROUP(spi_a_mosi_x2, 2), + GROUP(spi_a_ss0_x3, 2), + GROUP(spi_a_sclk_x4, 2), + GROUP(spi_a_miso_x5, 2), + GROUP(tdm_a_din1, 2), + GROUP(tdm_a_din0, 2), + GROUP(tdm_a_slv_fs, 2), + GROUP(tdm_a_slv_sclk, 2), + GROUP(i2c3_sck_x, 2), + GROUP(i2c3_sda_x, 2), + GROUP(pwm_d_x13, 2), + GROUP(pwm_e_x14, 2), + GROUP(i2c2_sck_x15, 2), + GROUP(i2c2_sda_x16, 2), + + /* bank X func3 */ + GROUP(uart_c_tx_x0, 3), + GROUP(uart_c_rx_x1, 3), + GROUP(uart_c_cts, 3), + GROUP(uart_c_rts, 3), + GROUP(pdm_din0_x, 3), + GROUP(pdm_din1_x, 3), + GROUP(pdm_din2_x, 3), + GROUP(pdm_dclk_x, 3), + GROUP(uart_c_tx_x15, 3), + GROUP(uart_c_rx_x16, 3), + + /* bank X func4 */ + GROUP(pwm_e_x2, 4), + GROUP(pwm_f_x, 4), + GROUP(spi_a_mosi_x7, 4), + GROUP(spi_a_miso_x8, 4), + GROUP(spi_a_ss0_x9, 4), + GROUP(spi_a_sclk_x10, 4), + + /* bank X func5 */ + GROUP(uart_b_tx_x, 5), + GROUP(uart_b_rx_x, 5), + GROUP(i2c1_sda_x, 5), + GROUP(i2c1_sck_x, 5), + + /* bank X func6 */ + GROUP(pwm_a_x7, 6), + GROUP(pwm_b_x, 6), + GROUP(pwm_c_x, 6), + GROUP(pwm_d_x10, 6), + + /* bank X func7 */ + GROUP(gen_clk_x, 7), + + /* bank F func1 */ + GROUP(uart_b_tx_f, 1), + GROUP(uart_b_rx_f, 1), + GROUP(remote_input_f, 1), + GROUP(jtag_a_clk, 1), + GROUP(jtag_a_tms, 1), + GROUP(jtag_a_tdi, 1), + GROUP(jtag_a_tdo, 1), + GROUP(gen_clk_f8, 1), + GROUP(pwm_a_f10, 1), + GROUP(i2c0_sck_f11, 1), + GROUP(i2c0_sda_f12, 1), + + /* bank F func2 */ + GROUP(clk_32k_in, 2), + GROUP(pwm_e_f, 2), + GROUP(pwm_f_f4, 2), + GROUP(remote_out, 2), + GROUP(spdif_in_f6, 2), + GROUP(spdif_in_f7, 2), + GROUP(pwm_a_hiz_f8, 2), + GROUP(pwm_a_hiz_f10, 2), + GROUP(pwm_d_f, 2), + GROUP(pwm_f_f12, 2), + + /* bank F func3 */ + GROUP(pwm_c_f3, 3), + GROUP(swclk, 3), + GROUP(swdio, 3), + GROUP(pwm_a_f6, 3), + GROUP(pwm_b_f, 3), + GROUP(pwm_c_f8, 3), + GROUP(clk25, 3), + GROUP(i2c_slave_sck_f, 3), + GROUP(i2c_slave_sda_f, 3), + + /* bank F func4 */ + GROUP(cec_a, 4), + GROUP(i2c3_sck_f, 4), + GROUP(i2c3_sda_f, 4), + GROUP(pmw_a_hiz_f6, 4), + GROUP(pwm_b_hiz, 4), + GROUP(pwm_c_hiz, 4), + GROUP(i2c0_sck_f9, 4), + GROUP(i2c0_sda_f10, 4), + + /* bank F func5 */ + GROUP(cec_b, 5), + GROUP(clk12_24, 5), + + /* bank F func7 */ + GROUP(gen_clk_f10, 7), + + /* bank A func1 */ + GROUP(mclk_0, 1), + GROUP(tdm_b_sclk, 1), + GROUP(tdm_b_fs, 1), + GROUP(tdm_b_dout0, 1), + GROUP(tdm_b_dout1, 1), + GROUP(tdm_b_dout2, 1), + GROUP(tdm_b_dout3, 1), + GROUP(tdm_b_dout4, 1), + GROUP(tdm_b_dout5, 1), + GROUP(remote_input_a, 1), + + /* bank A func2 */ + GROUP(pwm_e_a, 2), + GROUP(tdm_b_slv_sclk, 2), + GROUP(tdm_b_slv_fs, 2), + GROUP(tdm_b_din0, 2), + GROUP(tdm_b_din1, 2), + GROUP(tdm_b_din2, 2), + GROUP(i2c1_sda_a, 2), + GROUP(i2c1_sck_a, 2), + + /* bank A func3 */ + GROUP(i2c2_sck_a4, 3), + GROUP(i2c2_sda_a5, 3), + GROUP(pdm_din2_a, 3), + GROUP(pdm_din1_a, 3), + GROUP(pdm_din0_a, 3), + GROUP(pdm_dclk, 3), + GROUP(pwm_c_a, 3), + GROUP(pwm_b_a, 3), + + /* bank A func4 */ + GROUP(pwm_a_a, 4), + GROUP(spi_a_mosi_a, 4), + GROUP(spi_a_miso_a, 4), + GROUP(spi_a_ss0_a, 4), + GROUP(spi_a_sclk_a, 4), + GROUP(i2c_slave_sck_a, 4), + GROUP(i2c_slave_sda_a, 4), + + /* bank A func5 */ + GROUP(mclk_vad, 5), + GROUP(tdm_vad_sclk_a1, 5), + GROUP(tdm_vad_fs_a2, 5), + GROUP(tdm_vad_sclk_a5, 5), + GROUP(tdm_vad_fs_a6, 5), + GROUP(i2c2_sck_a8, 5), + GROUP(i2c2_sda_a9, 5), + + /* bank A func6 */ + GROUP(tst_out0, 6), + GROUP(tst_out1, 6), + GROUP(tst_out2, 6), + GROUP(tst_out3, 6), + GROUP(tst_out4, 6), + GROUP(tst_out5, 6), + GROUP(tst_out6, 6), + GROUP(tst_out7, 6), + GROUP(tst_out8, 6), + GROUP(tst_out9, 6), + GROUP(tst_out10, 6), + GROUP(tst_out11, 6), + + /* bank A func7 */ + GROUP(mute_key, 7), + GROUP(mute_en, 7), + GROUP(gen_clk_a, 7), +}; + +static const char * const gpio_periphs_groups[] = { + "GPIOP_0", "GPIOP_1", "GPIOP_2", "GPIOP_3", "GPIOP_4", + "GPIOP_5", "GPIOP_6", "GPIOP_7", "GPIOP_8", "GPIOP_9", + "GPIOP_10", "GPIOP_11", "GPIOP_12", + + "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", + "GPIOB_5", "GPIOB_6", + + "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", + "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", + "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", + "GPIOX_15", "GPIOX_16", + + "GPIOF_0", "GPIOF_1", "GPIOF_2", "GPIOF_3", "GPIOF_4", + "GPIOF_5", "GPIOF_6", "GPIOF_7", "GPIOF_8", "GPIOF_9", + "GPIOF_10", "GPIOF_11", "GPIOF_12", + + "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4", + "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9", + "GPIOA_10", "GPIOA_11", +}; + +static const char * const psram_groups[] = { + "psram_clkn", "psram_clkp", "psram_ce_n", "psram_rst_n", "psram_adq0", + "psram_adq1", "psram_adq2", "psram_adq3", "psram_adq4", "psram_adq5", + "psram_adq6", "psram_adq7", "psram_dqs_dm", +}; + +static const char * const pwm_a_groups[] = { + "pwm_a_x6", "pwm_a_x7", "pwm_a_f10", "pwm_a_f6", "pwm_a_a", +}; + +static const char * const pwm_b_groups[] = { + "pwm_b_x", "pwm_b_f", "pwm_b_a", +}; + +static const char * const pwm_c_groups[] = { + "pwm_c_x", "pwm_c_f3", "pwm_c_f8", "pwm_c_a", +}; + +static const char * const pwm_d_groups[] = { + "pwm_d_x15", "pwm_d_x13", "pwm_d_x10", "pwm_d_f", +}; + +static const char * const pwm_e_groups[] = { + "pwm_e_p", "pwm_e_x16", "pwm_e_x14", "pwm_e_x2", "pwm_e_f", + "pwm_e_a", +}; + +static const char * const pwm_f_groups[] = { + "pwm_f_b", "pwm_f_x", "pwm_f_f4", "pwm_f_f12", +}; + +static const char * const pwm_a_hiz_groups[] = { + "pwm_a_hiz_f8", "pwm_a_hiz_f10", "pwm_a_hiz_f6", +}; + +static const char * const pwm_b_hiz_groups[] = { + "pwm_b_hiz", +}; + +static const char * const pwm_c_hiz_groups[] = { + "pwm_c_hiz", +}; + +static const char * const spif_groups[] = { + "spif_mo", "spif_mi", "spif_wp_n", "spif_hold_n", "spif_clk", + "spif_cs", +}; + +static const char * const sdcard_groups[] = { + "sdcard_d0_b", "sdcard_d1_b", "sdcard_d2_b", "sdcard_d3_b", + "sdcard_clk_b", "sdcard_cmd_b", + + "sdcard_d0_x", "sdcard_d1_x", "sdcard_d2_x", "sdcard_d3_x", + "sdcard_clk_x", "sdcard_cmd_x", +}; + +static const char * const tdm_a_groups[] = { + "tdm_a_din0", "tdm_a_din1", "tdm_a_fs", "tdm_a_sclk", + "tdm_a_slv_fs", "tdm_a_slv_sclk", "tdm_a_dout0", "tdm_a_dout1", +}; + +static const char * const uart_a_groups[] = { + "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts", +}; + +static const char * const uart_b_groups[] = { + "uart_b_tx_x", "uart_b_rx_x", "uart_b_tx_f", "uart_b_rx_f", +}; + +static const char * const uart_c_groups[] = { + "uart_c_tx_x0", "uart_c_rx_x1", "uart_c_cts", "uart_c_rts", + "uart_c_tx_x15", "uart_c_rx_x16", +}; + +static const char * const i2c0_groups[] = { + "i2c0_sck_f11", "i2c0_sda_f12", "i2c0_sck_f9", "i2c0_sda_f10", +}; + +static const char * const i2c1_groups[] = { + "i2c1_sda_x", "i2c1_sck_x", "i2c1_sda_a", "i2c1_sck_a", +}; + +static const char * const i2c2_groups[] = { + "i2c2_sck_x0", "i2c2_sda_x1", "i2c2_sck_x15", "i2c2_sda_x16", + "i2c2_sck_a4", "i2c2_sda_a5", "i2c2_sck_a8", "i2c2_sda_a9", +}; + +static const char * const i2c3_groups[] = { + "i2c3_sck_x", "i2c3_sda_x", "i2c3_sck_f", "i2c3_sda_f", +}; + +static const char * const spi_a_groups[] = { + "spi_a_mosi_x2", "spi_a_ss0_x3", "spi_a_sclk_x4", "spi_a_miso_x5", + "spi_a_mosi_x7", "spi_a_miso_x8", "spi_a_ss0_x9", "spi_a_sclk_x10", + + "spi_a_mosi_a", "spi_a_miso_a", "spi_a_ss0_a", "spi_a_sclk_a", +}; + +static const char * const pdm_groups[] = { + "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_dclk_x", "pdm_din2_a", + "pdm_din1_a", "pdm_din0_a", "pdm_dclk", +}; + +static const char * const gen_clk_groups[] = { + "gen_clk_x", "gen_clk_f8", "gen_clk_f10", "gen_clk_a", +}; + +static const char * const remote_input_groups[] = { + "remote_input_f", + "remote_input_a", +}; + +static const char * const jtag_a_groups[] = { + "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo", +}; + +static const char * const clk_32k_in_groups[] = { + "clk_32k_in", +}; + +static const char * const remote_out_groups[] = { + "remote_out", +}; + +static const char * const spdif_in_groups[] = { + "spdif_in_f6", "spdif_in_f7", +}; + +static const char * const sw_groups[] = { + "swclk", "swdio", +}; + +static const char * const clk25_groups[] = { + "clk_25", +}; + +static const char * const cec_a_groups[] = { + "cec_a", +}; + +static const char * const cec_b_groups[] = { + "cec_b", +}; + +static const char * const clk12_24_groups[] = { + "clk12_24", +}; + +static const char * const mclk_0_groups[] = { + "mclk_0", +}; + +static const char * const tdm_b_groups[] = { + "tdm_b_din0", "tdm_b_din1", "tdm_b_din2", + "tdm_b_sclk", "tdm_b_fs", "tdm_b_dout0", "tdm_b_dout1", + "tdm_b_dout2", "tdm_b_dout3", "tdm_b_dout4", "tdm_b_dout5", + "tdm_b_slv_sclk", "tdm_b_slv_fs", +}; + +static const char * const mclk_vad_groups[] = { + "mclk_vad", +}; + +static const char * const tdm_vad_groups[] = { + "tdm_vad_sclk_a1", "tdm_vad_fs_a2", "tdm_vad_sclk_a5", "tdm_vad_fs_a6", +}; + +static const char * const tst_out_groups[] = { + "tst_out0", "tst_out1", "tst_out2", "tst_out3", + "tst_out4", "tst_out5", "tst_out6", "tst_out7", + "tst_out8", "tst_out9", "tst_out10", "tst_out11", +}; + +static const char * const mute_groups[] = { + "mute_key", "mute_en", +}; + +static struct meson_pmx_func meson_a1_periphs_functions[] = { + FUNCTION(gpio_periphs), + FUNCTION(psram), + FUNCTION(pwm_a), + FUNCTION(pwm_b), + FUNCTION(pwm_c), + FUNCTION(pwm_d), + FUNCTION(pwm_e), + FUNCTION(pwm_f), + FUNCTION(pwm_a_hiz), + FUNCTION(pwm_b_hiz), + FUNCTION(pwm_c_hiz), + FUNCTION(spif), + FUNCTION(sdcard), + FUNCTION(tdm_a), + FUNCTION(uart_a), + FUNCTION(uart_b), + FUNCTION(uart_c), + FUNCTION(i2c0), + FUNCTION(i2c1), + FUNCTION(i2c2), + FUNCTION(i2c3), + FUNCTION(spi_a), + FUNCTION(pdm), + FUNCTION(gen_clk), + FUNCTION(remote_input), + FUNCTION(jtag_a), + FUNCTION(clk_32k_in), + FUNCTION(remote_out), + FUNCTION(spdif_in), + FUNCTION(sw), + FUNCTION(clk25), + FUNCTION(cec_a), + FUNCTION(cec_b), + FUNCTION(clk12_24), + FUNCTION(mclk_0), + FUNCTION(tdm_b), + FUNCTION(mclk_vad), + FUNCTION(tdm_vad), + FUNCTION(tst_out), + FUNCTION(mute), +}; + +static struct meson_bank meson_a1_periphs_banks[] = { + /* name first last pullen pull dir out in ds */ + BANK_DS("P", GPIOP_0, GPIOP_12, 0x3, 0, 0x4, 0, 0x2, 0, 0x1, 0, 0x0, 0, 0x5, 0), + BANK_DS("B", GPIOB_0, GPIOB_6, 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0, 0x15, 0), + BANK_DS("X", GPIOX_0, GPIOX_16, 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0, 0x25, 0), + BANK_DS("F", GPIOF_0, GPIOF_12, 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0, 0x35, 0), + BANK_DS("A", GPIOA_0, GPIOA_11, 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0, 0x45, 0), +}; + +static struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = { + /* name first last reg offset */ + BANK_PMX("P", GPIOP_0, GPIOP_12, 0x0, 0), + BANK_PMX("B", GPIOB_0, GPIOB_6, 0x2, 0), + BANK_PMX("X", GPIOX_0, GPIOX_16, 0x3, 0), + BANK_PMX("F", GPIOF_0, GPIOF_12, 0x6, 0), + BANK_PMX("A", GPIOA_0, GPIOA_11, 0x8, 0), +}; + +static struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = { + .pmx_banks = meson_a1_periphs_pmx_banks, + .num_pmx_banks = ARRAY_SIZE(meson_a1_periphs_pmx_banks), +}; + +static struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = { + .name = "periphs-banks", + .groups = meson_a1_periphs_groups, + .funcs = meson_a1_periphs_functions, + .banks = meson_a1_periphs_banks, + .num_pins = 62, + .num_groups = ARRAY_SIZE(meson_a1_periphs_groups), + .num_funcs = ARRAY_SIZE(meson_a1_periphs_functions), + .num_banks = ARRAY_SIZE(meson_a1_periphs_banks), + .pmx_data = &meson_a1_periphs_pmx_banks_data, +}; + +static const struct udevice_id meson_a1_pinctrl_match[] = { + { + .compatible = "amlogic,meson-a1-periphs-pinctrl", + .data = (ulong)&meson_a1_periphs_pinctrl_data, + }, + { }, +}; + +U_BOOT_DRIVER(meson_a1_pinctrl) = { + .name = "meson-a1-pinctrl", + .id = UCLASS_PINCTRL, + .of_match = of_match_ptr(meson_a1_pinctrl_match), + .probe = meson_pinctrl_probe, + .priv_auto = sizeof(struct meson_pinctrl), + .ops = &meson_axg_pinctrl_ops, +}; diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 1ad8bfb..9251382 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -1552,12 +1552,12 @@ static int npcm7xx_pinconf_set(struct udevice *dev, unsigned int pin, setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio)); case PIN_CONFIG_OUTPUT: dev_dbg(dev, "set pin %d output %d\n", pin, arg); - clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio)); - setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio)); if (arg) setbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio)); else clrbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio)); + clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio)); + setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio)); break; case PIN_CONFIG_DRIVE_PUSH_PULL: dev_dbg(dev, "set pin %d push pull\n", pin); diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index 0ec47e9..f18be08 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -900,12 +900,12 @@ static int npcm8xx_pinconf_set(struct udevice *dev, unsigned int selector, setbits_le32(base + GPIO_OES, BIT(gpio)); case PIN_CONFIG_OUTPUT: dev_dbg(dev, "set pin %d output %d\n", pin, arg); - clrbits_le32(base + GPIO_IEM, BIT(gpio)); - setbits_le32(base + GPIO_OES, BIT(gpio)); if (arg) setbits_le32(base + GPIO_DOUT, BIT(gpio)); else clrbits_le32(base + GPIO_DOUT, BIT(gpio)); + clrbits_le32(base + GPIO_IEM, BIT(gpio)); + setbits_le32(base + GPIO_OES, BIT(gpio)); break; case PIN_CONFIG_DRIVE_PUSH_PULL: dev_dbg(dev, "set pin %d push pull\n", pin); diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig index 7e1b8c0..411c210 100644 --- a/drivers/power/domain/Kconfig +++ b/drivers/power/domain/Kconfig @@ -68,6 +68,13 @@ config MESON_EE_POWER_DOMAIN Enable support for manipulating Amlogic Meson Everything-Else power domains. +config MESON_SECURE_POWER_DOMAIN + bool "Enable Amlogic Secure power domain driver" + depends on POWER_DOMAIN && ARCH_MESON && MESON_A1 + help + Enable support for manipulating Amlogic Meson Secure power domains. + Support for Amlogic A1 series. + config SANDBOX_POWER_DOMAIN bool "Enable the sandbox power domain test driver" depends on POWER_DOMAIN && SANDBOX diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile index e624477..aa5a4ba 100644 --- a/drivers/power/domain/Makefile +++ b/drivers/power/domain/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_IMX8MP_HSIOMIX_BLKCTRL) += imx8mp-hsiomix.o obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o +obj-$(CONFIG_MESON_SECURE_POWER_DOMAIN) += meson-secure-pwrc.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o diff --git a/drivers/power/domain/meson-secure-pwrc.c b/drivers/power/domain/meson-secure-pwrc.c new file mode 100644 index 0000000..f70f8e0 --- /dev/null +++ b/drivers/power/domain/meson-secure-pwrc.c @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023 SberDevices, Inc. + * Author: Alexey Romanov <avromanov@sberdevices.ru> + */ + +#include <dm.h> +#include <asm/arch/sm.h> +#include <power-domain.h> +#include <power-domain-uclass.h> +#include <dt-bindings/power/meson-a1-power.h> + +struct meson_secure_pwrc_domain_desc { + char *name; + size_t index; +}; + +struct meson_secure_pwrc_domain_data { + unsigned int count; + struct meson_secure_pwrc_domain_desc *domains; +}; + +struct meson_secure_pwrc_priv { + const struct meson_secure_pwrc_domain_data *data; +}; + +static int meson_secure_pwrc_on(struct power_domain *power_domain) +{ + struct meson_secure_pwrc_priv *priv = dev_get_priv(power_domain->dev); + struct meson_secure_pwrc_domain_desc *pwrc_domain; + int err; + + pwrc_domain = &priv->data->domains[power_domain->id]; + + err = meson_sm_pwrdm_on(pwrc_domain->index); + if (err) { + pr_err("meson_sm_pwrdm_on() failed (%d)\n", err); + return err; + } + + pr_debug("enable %s power domain\n", pwrc_domain->name); + + return 0; +} + +static int meson_secure_pwrc_off(struct power_domain *power_domain) +{ + struct meson_secure_pwrc_priv *priv = dev_get_priv(power_domain->dev); + struct meson_secure_pwrc_domain_desc *pwrc_domain; + int err; + + pwrc_domain = &priv->data->domains[power_domain->id]; + + err = meson_sm_pwrdm_off(pwrc_domain->index); + if (err) { + pr_err("meson_sm_pwrdm_off() failed (%d)\n", err); + return err; + } + + pr_debug("disable %s power domain\n", pwrc_domain->name); + + return 0; +} + +static int meson_secure_pwrc_of_xlate(struct power_domain *power_domain, + struct ofnode_phandle_args *args) +{ + struct meson_secure_pwrc_priv *priv = dev_get_priv(power_domain->dev); + struct meson_secure_pwrc_domain_desc *pwrc_domain; + + if (args->args_count < 1) { + pr_err("invalid args count: %d\n", args->args_count); + return -EINVAL; + } + + power_domain->id = args->args[0]; + + if (power_domain->id >= priv->data->count) { + pr_err("domain with ID=%lu is invalid\n", power_domain->id); + return -EINVAL; + } + + pwrc_domain = &priv->data->domains[power_domain->id]; + + if (!pwrc_domain->name) { + pr_err("domain with ID=%lu is invalid\n", power_domain->id); + return -EINVAL; + } + + return 0; +} + +#define SEC_PD(__name) \ +[PWRC_##__name##_ID] = \ +{ \ + .name = #__name, \ + .index = PWRC_##__name##_ID, \ +} + +static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = { + SEC_PD(DSPA), + SEC_PD(DSPB), + SEC_PD(UART), + SEC_PD(DMC), + SEC_PD(I2C), + SEC_PD(PSRAM), + SEC_PD(ACODEC), + SEC_PD(AUDIO), + SEC_PD(OTP), + SEC_PD(DMA), + SEC_PD(SD_EMMC), + SEC_PD(RAMA), + SEC_PD(RAMB), + SEC_PD(IR), + SEC_PD(SPICC), + SEC_PD(SPIFC), + SEC_PD(USB), + SEC_PD(NIC), + SEC_PD(PDMIN), + SEC_PD(RSA), +}; + +struct power_domain_ops meson_secure_pwrc_ops = { + .on = meson_secure_pwrc_on, + .off = meson_secure_pwrc_off, + .of_xlate = meson_secure_pwrc_of_xlate, +}; + +static struct meson_secure_pwrc_domain_data meson_secure_a1_pwrc_data = { + .count = ARRAY_SIZE(a1_pwrc_domains), + .domains = a1_pwrc_domains, +}; + +static const struct udevice_id meson_secure_pwrc_ids[] = { + { + .compatible = "amlogic,meson-a1-pwrc", + .data = (unsigned long)&meson_secure_a1_pwrc_data, + }, + { } +}; + +static int meson_secure_pwrc_probe(struct udevice *dev) +{ + struct meson_secure_pwrc_priv *priv = dev_get_priv(dev); + + priv->data = (void *)dev_get_driver_data(dev); + if (!priv->data) + return -EINVAL; + + return 0; +} + +U_BOOT_DRIVER(meson_secure_pwrc) = { + .name = "meson_secure_pwrc", + .id = UCLASS_POWER_DOMAIN, + .of_match = meson_secure_pwrc_ids, + .probe = meson_secure_pwrc_probe, + .ops = &meson_secure_pwrc_ops, + .priv_auto = sizeof(struct meson_secure_pwrc_priv), +}; diff --git a/drivers/power/domain/zynqmp-power-domain.c b/drivers/power/domain/zynqmp-power-domain.c index adbbb5f..5ee9e02 100644 --- a/drivers/power/domain/zynqmp-power-domain.c +++ b/drivers/power/domain/zynqmp-power-domain.c @@ -23,12 +23,17 @@ static int zynqmp_pm_request_node(const u32 node, const u32 capabilities, static int zynqmp_power_domain_request(struct power_domain *power_domain) { + int ret = 0; + dev_dbg(power_domain->dev, "Request for id: %ld\n", power_domain->id); - if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) - return zynqmp_pmufw_node(power_domain->id); + if (IS_ENABLED(CONFIG_ARCH_ZYNQMP)) { + ret = zynqmp_pmufw_node(power_domain->id); + if (ret == -ENODEV) + ret = 0; + } - return 0; + return ret; } static int zynqmp_power_domain_free(struct power_domain *power_domain) diff --git a/drivers/power/pmic/stpmic1.c b/drivers/power/pmic/stpmic1.c index 2c85410..8701d4f 100644 --- a/drivers/power/pmic/stpmic1.c +++ b/drivers/power/pmic/stpmic1.c @@ -34,7 +34,9 @@ static const struct pmic_child_info stpmic1_children_info[] = { { .prefix = "ldo", .driver = "stpmic1_ldo" }, { .prefix = "buck", .driver = "stpmic1_buck" }, { .prefix = "vref_ddr", .driver = "stpmic1_vref_ddr" }, + { .prefix = "vref-ddr", .driver = "stpmic1_vref_ddr" }, { .prefix = "pwr_sw", .driver = "stpmic1_pwr_sw" }, + { .prefix = "pwr-sw", .driver = "stpmic1_pwr_sw" }, { .prefix = "boost", .driver = "stpmic1_boost" }, { }, }; diff --git a/drivers/power/regulator/fan53555.c b/drivers/power/regulator/fan53555.c index 5681206..815f96b 100644 --- a/drivers/power/regulator/fan53555.c +++ b/drivers/power/regulator/fan53555.c @@ -101,7 +101,7 @@ struct fan53555_priv { static int fan53555_regulator_of_to_plat(struct udevice *dev) { - struct fan53555_plat *dev_pdata = dev_get_plat(dev); + struct fan53555_plat *plat = dev_get_plat(dev); struct dm_regulator_uclass_plat *uc_pdata = dev_get_uclass_plat(dev); u32 sleep_vsel; @@ -118,12 +118,12 @@ static int fan53555_regulator_of_to_plat(struct udevice *dev) */ switch (sleep_vsel) { case FAN53555_VSEL0: - dev_pdata->sleep_reg = FAN53555_VSEL0; - dev_pdata->vol_reg = FAN53555_VSEL1; + plat->sleep_reg = FAN53555_VSEL0; + plat->vol_reg = FAN53555_VSEL1; break; case FAN53555_VSEL1: - dev_pdata->sleep_reg = FAN53555_VSEL1; - dev_pdata->vol_reg = FAN53555_VSEL0; + plat->sleep_reg = FAN53555_VSEL1; + plat->vol_reg = FAN53555_VSEL0; break; default: pr_err("%s: invalid vsel id %d\n", dev->name, sleep_vsel); diff --git a/drivers/power/regulator/fixed.c b/drivers/power/regulator/fixed.c index 90004d1..ad3b4b9 100644 --- a/drivers/power/regulator/fixed.c +++ b/drivers/power/regulator/fixed.c @@ -24,16 +24,16 @@ struct fixed_clock_regulator_plat { static int fixed_regulator_of_to_plat(struct udevice *dev) { struct dm_regulator_uclass_plat *uc_pdata; - struct regulator_common_plat *dev_pdata; + struct regulator_common_plat *plat; - dev_pdata = dev_get_plat(dev); + plat = dev_get_plat(dev); uc_pdata = dev_get_uclass_plat(dev); if (!uc_pdata) return -ENXIO; uc_pdata->type = REGULATOR_TYPE_FIXED; - return regulator_common_of_to_plat(dev, dev_pdata, "gpio"); + return regulator_common_of_to_plat(dev, plat, "gpio"); } static int fixed_regulator_get_value(struct udevice *dev) @@ -88,7 +88,7 @@ static int fixed_clock_regulator_get_enable(struct udevice *dev) static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable) { struct fixed_clock_regulator_plat *priv = dev_get_priv(dev); - struct regulator_common_plat *dev_pdata = dev_get_plat(dev); + struct regulator_common_plat *plat = dev_get_plat(dev); int ret = 0; if (enable) { @@ -101,11 +101,11 @@ static int fixed_clock_regulator_set_enable(struct udevice *dev, bool enable) if (ret) return ret; - if (enable && dev_pdata->startup_delay_us) - udelay(dev_pdata->startup_delay_us); + if (enable && plat->startup_delay_us) + udelay(plat->startup_delay_us); - if (!enable && dev_pdata->off_on_delay_us) - udelay(dev_pdata->off_on_delay_us); + if (!enable && plat->off_on_delay_us) + udelay(plat->off_on_delay_us); return ret; } diff --git a/drivers/power/regulator/gpio-regulator.c b/drivers/power/regulator/gpio-regulator.c index 9c0a68a..ded7be0 100644 --- a/drivers/power/regulator/gpio-regulator.c +++ b/drivers/power/regulator/gpio-regulator.c @@ -27,12 +27,12 @@ struct gpio_regulator_plat { static int gpio_regulator_of_to_plat(struct udevice *dev) { struct dm_regulator_uclass_plat *uc_pdata; - struct gpio_regulator_plat *dev_pdata; + struct gpio_regulator_plat *plat; struct gpio_desc *gpio; int ret, count, i, j; u32 states_array[GPIO_REGULATOR_MAX_STATES * 2]; - dev_pdata = dev_get_plat(dev); + plat = dev_get_plat(dev); uc_pdata = dev_get_uclass_plat(dev); if (!uc_pdata) return -ENXIO; @@ -47,7 +47,7 @@ static int gpio_regulator_of_to_plat(struct udevice *dev) * per gpio-regulator. As of now no instance with multiple * gpios is presnt */ - gpio = &dev_pdata->gpio; + gpio = &plat->gpio; ret = gpio_request_by_name(dev, "gpios", 0, gpio, GPIOD_IS_OUT); if (ret) debug("regulator gpio - not found! Error: %d", ret); @@ -68,21 +68,21 @@ static int gpio_regulator_of_to_plat(struct udevice *dev) return ret; for (i = 0, j = 0; i < count; i += 2) { - dev_pdata->voltages[j] = states_array[i]; - dev_pdata->states[j] = states_array[i + 1]; + plat->voltages[j] = states_array[i]; + plat->states[j] = states_array[i + 1]; j++; } - return regulator_common_of_to_plat(dev, &dev_pdata->common, "enable-gpios"); + return regulator_common_of_to_plat(dev, &plat->common, "enable-gpios"); } static int gpio_regulator_get_value(struct udevice *dev) { struct dm_regulator_uclass_plat *uc_pdata; - struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev); + struct gpio_regulator_plat *plat = dev_get_plat(dev); int enable; - if (!dev_pdata->gpio.dev) + if (!plat->gpio.dev) return -ENOSYS; uc_pdata = dev_get_uclass_plat(dev); @@ -91,30 +91,30 @@ static int gpio_regulator_get_value(struct udevice *dev) return -EINVAL; } - enable = dm_gpio_get_value(&dev_pdata->gpio); - if (enable == dev_pdata->states[0]) - return dev_pdata->voltages[0]; + enable = dm_gpio_get_value(&plat->gpio); + if (enable == plat->states[0]) + return plat->voltages[0]; else - return dev_pdata->voltages[1]; + return plat->voltages[1]; } static int gpio_regulator_set_value(struct udevice *dev, int uV) { - struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev); + struct gpio_regulator_plat *plat = dev_get_plat(dev); int ret; bool enable; - if (!dev_pdata->gpio.dev) + if (!plat->gpio.dev) return -ENOSYS; - if (uV == dev_pdata->voltages[0]) - enable = dev_pdata->states[0]; - else if (uV == dev_pdata->voltages[1]) - enable = dev_pdata->states[1]; + if (uV == plat->voltages[0]) + enable = plat->states[0]; + else if (uV == plat->voltages[1]) + enable = plat->states[1]; else return -EINVAL; - ret = dm_gpio_set_value(&dev_pdata->gpio, enable); + ret = dm_gpio_set_value(&plat->gpio, enable); if (ret) { pr_err("Can't set regulator : %s gpio to: %d\n", dev->name, enable); @@ -126,14 +126,14 @@ static int gpio_regulator_set_value(struct udevice *dev, int uV) static int gpio_regulator_get_enable(struct udevice *dev) { - struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev); - return regulator_common_get_enable(dev, &dev_pdata->common); + struct gpio_regulator_plat *plat = dev_get_plat(dev); + return regulator_common_get_enable(dev, &plat->common); } static int gpio_regulator_set_enable(struct udevice *dev, bool enable) { - struct gpio_regulator_plat *dev_pdata = dev_get_plat(dev); - return regulator_common_set_enable(dev, &dev_pdata->common, enable); + struct gpio_regulator_plat *plat = dev_get_plat(dev); + return regulator_common_set_enable(dev, &plat->common, enable); } static const struct dm_regulator_ops gpio_regulator_ops = { diff --git a/drivers/power/regulator/regulator-uclass.c b/drivers/power/regulator/regulator-uclass.c index d608f7c..3a6ba69 100644 --- a/drivers/power/regulator/regulator-uclass.c +++ b/drivers/power/regulator/regulator-uclass.c @@ -197,6 +197,12 @@ int regulator_set_enable_if_allowed(struct udevice *dev, bool enable) ret = regulator_set_enable(dev, enable); if (ret == -ENOSYS || ret == -EACCES) return 0; + /* if we want to disable but it's in use by someone else */ + if (!enable && ret == -EBUSY) + return 0; + /* if it's already enabled/disabled */ + if (ret == -EALREADY) + return 0; return ret; } diff --git a/drivers/power/regulator/regulator_common.c b/drivers/power/regulator/regulator_common.c index 93d8196..e26f5eb 100644 --- a/drivers/power/regulator/regulator_common.c +++ b/drivers/power/regulator/regulator_common.c @@ -13,7 +13,7 @@ #include "regulator_common.h" int regulator_common_of_to_plat(struct udevice *dev, - struct regulator_common_plat *dev_pdata, + struct regulator_common_plat *plat, const char *enable_gpio_name) { struct gpio_desc *gpio; @@ -26,7 +26,7 @@ int regulator_common_of_to_plat(struct udevice *dev, flags |= GPIOD_IS_OUT_ACTIVE; /* Get optional enable GPIO desc */ - gpio = &dev_pdata->gpio; + gpio = &plat->gpio; ret = gpio_request_by_name(dev, enable_gpio_name, 0, gpio, flags); if (ret) { debug("Regulator '%s' optional enable GPIO - not found! Error: %d\n", @@ -36,12 +36,11 @@ int regulator_common_of_to_plat(struct udevice *dev, } /* Get optional ramp up delay */ - dev_pdata->startup_delay_us = dev_read_u32_default(dev, - "startup-delay-us", 0); - dev_pdata->off_on_delay_us = - dev_read_u32_default(dev, "off-on-delay-us", 0); - if (!dev_pdata->off_on_delay_us) { - dev_pdata->off_on_delay_us = + plat->startup_delay_us = dev_read_u32_default(dev, + "startup-delay-us", 0); + plat->off_on_delay_us = dev_read_u32_default(dev, "off-on-delay-us", 0); + if (!plat->off_on_delay_us) { + plat->off_on_delay_us = dev_read_u32_default(dev, "u-boot,off-on-delay-us", 0); } @@ -49,43 +48,65 @@ int regulator_common_of_to_plat(struct udevice *dev, } int regulator_common_get_enable(const struct udevice *dev, - struct regulator_common_plat *dev_pdata) + struct regulator_common_plat *plat) { /* Enable GPIO is optional */ - if (!dev_pdata->gpio.dev) + if (!plat->gpio.dev) return true; - return dm_gpio_get_value(&dev_pdata->gpio); + return dm_gpio_get_value(&plat->gpio); } int regulator_common_set_enable(const struct udevice *dev, - struct regulator_common_plat *dev_pdata, bool enable) + struct regulator_common_plat *plat, bool enable) { int ret; debug("%s: dev='%s', enable=%d, delay=%d, has_gpio=%d\n", __func__, - dev->name, enable, dev_pdata->startup_delay_us, - dm_gpio_is_valid(&dev_pdata->gpio)); + dev->name, enable, plat->startup_delay_us, + dm_gpio_is_valid(&plat->gpio)); /* Enable GPIO is optional */ - if (!dm_gpio_is_valid(&dev_pdata->gpio)) { + if (!dm_gpio_is_valid(&plat->gpio)) { if (!enable) return -ENOSYS; return 0; } - ret = dm_gpio_set_value(&dev_pdata->gpio, enable); + /* If previously enabled, increase count */ + if (enable && plat->enable_count > 0) { + plat->enable_count++; + return -EALREADY; + } + + if (!enable) { + if (plat->enable_count > 1) { + /* If enabled multiple times, decrease count */ + plat->enable_count--; + return -EBUSY; + } else if (!plat->enable_count) { + /* If already disabled, do nothing */ + return -EALREADY; + } + } + + ret = dm_gpio_set_value(&plat->gpio, enable); if (ret) { pr_err("Can't set regulator : %s gpio to: %d\n", dev->name, enable); return ret; } - if (enable && dev_pdata->startup_delay_us) - udelay(dev_pdata->startup_delay_us); + if (enable && plat->startup_delay_us) + udelay(plat->startup_delay_us); debug("%s: done\n", __func__); - if (!enable && dev_pdata->off_on_delay_us) - udelay(dev_pdata->off_on_delay_us); + if (!enable && plat->off_on_delay_us) + udelay(plat->off_on_delay_us); + + if (enable) + plat->enable_count++; + else + plat->enable_count--; return 0; } diff --git a/drivers/power/regulator/regulator_common.h b/drivers/power/regulator/regulator_common.h index c10492f..d496289 100644 --- a/drivers/power/regulator/regulator_common.h +++ b/drivers/power/regulator/regulator_common.h @@ -13,14 +13,35 @@ struct regulator_common_plat { struct gpio_desc gpio; /* GPIO for regulator enable control */ unsigned int startup_delay_us; unsigned int off_on_delay_us; + unsigned int enable_count; }; int regulator_common_of_to_plat(struct udevice *dev, - struct regulator_common_plat *dev_pdata, const + struct regulator_common_plat *plat, const char *enable_gpio_name); int regulator_common_get_enable(const struct udevice *dev, - struct regulator_common_plat *dev_pdata); + struct regulator_common_plat *plat); +/* + * Enable or Disable a regulator + * + * This is a reentrant function and subsequent calls that enable will + * increase an internal counter, and disable calls will decrease the counter. + * The actual resource will be enabled when the counter gets to 1 coming from 0, + * and disabled when it reaches 0 coming from 1. + * + * @dev: regulator device + * @plat: Platform data + * @enable: bool indicating whether to enable or disable the regulator + * @return: + * 0 on Success + * -EBUSY if the regulator cannot be disabled because it's requested by + * another device + * -EALREADY if the regulator has already been enabled or has already been + * disabled + * -EACCES if there is no possibility to enable/disable the regulator + * -ve on different error situation + */ int regulator_common_set_enable(const struct udevice *dev, - struct regulator_common_plat *dev_pdata, bool enable); + struct regulator_common_plat *plat, bool enable); #endif /* _REGULATOR_COMMON_H */ diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 2ba92bf..0085113 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -18,6 +18,7 @@ #include <dm/device_compat.h> #include <linux/bitops.h> #include <linux/delay.h> +#include <linux/iopoll.h> #include "serial_stm32.h" #include <dm/device_compat.h> @@ -28,6 +29,10 @@ static void _stm32_serial_setbrg(fdt_addr_t base, { bool stm32f4 = uart_info->stm32f4; u32 int_div, mantissa, fraction, oversampling; + u8 uart_enable_bit = uart_info->uart_enable_bit; + + /* BRR register must be set when uart is disabled */ + clrbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit)); int_div = DIV_ROUND_CLOSEST(clock_rate, baudrate); @@ -43,6 +48,8 @@ static void _stm32_serial_setbrg(fdt_addr_t base, fraction = int_div % oversampling; writel(mantissa | fraction, base + BRR_OFFSET(stm32f4)); + + setbits_le32(base + CR1_OFFSET(stm32f4), BIT(uart_enable_bit)); } static int stm32_serial_setbrg(struct udevice *dev, int baudrate) @@ -181,9 +188,12 @@ static int stm32_serial_probe(struct udevice *dev) struct stm32x7_serial_plat *plat = dev_get_plat(dev); struct clk clk; struct reset_ctl reset; + u32 isr; int ret; + bool stm32f4; plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev); + stm32f4 = plat->uart_info->stm32f4; ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) @@ -195,6 +205,17 @@ static int stm32_serial_probe(struct udevice *dev) return ret; } + /* + * before uart initialization, wait for TC bit (Transmission Complete) + * in case there is still chars from previous bootstage to transmit + */ + ret = read_poll_timeout(readl, isr, isr & USART_ISR_TC, 10, 150, + plat->base + ISR_OFFSET(stm32f4)); + if (ret) { + clk_disable(&clk); + return ret; + } + ret = reset_get_by_index(dev, 0, &reset); if (!ret) { reset_assert(&reset); diff --git a/drivers/serial/serial_stm32.h b/drivers/serial/serial_stm32.h index 5bee68f..b7e7a90 100644 --- a/drivers/serial/serial_stm32.h +++ b/drivers/serial/serial_stm32.h @@ -66,6 +66,7 @@ struct stm32x7_serial_plat { #define USART_CR3_OVRDIS BIT(12) #define USART_ISR_TXE BIT(7) +#define USART_ISR_TC BIT(6) #define USART_ISR_RXNE BIT(5) #define USART_ISR_ORE BIT(3) #define USART_ISR_FE BIT(1) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 4f435fd..453a598 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -382,7 +382,7 @@ config SPI_QUP config RENESAS_RPC_SPI bool "Renesas RPC SPI driver" depends on RCAR_64 || RZA1 - imply SPI_FLASH_BAR + imply SPI_FLASH_SFDP_SUPPORT help Enable the Renesas RPC SPI driver, used to access SPI NOR flash on Renesas RCar Gen3 SoCs. This uses driver model and requires a diff --git a/drivers/spi/omap3_spi.c b/drivers/spi/omap3_spi.c index 1cbb5d4..ff7b55f 100644 --- a/drivers/spi/omap3_spi.c +++ b/drivers/spi/omap3_spi.c @@ -347,20 +347,28 @@ static void _omap3_spi_set_wordlen(struct omap3_spi_priv *priv) omap3_spi_write_chconf(priv, confr); } -static void spi_reset(struct mcspi *regs) +static void spi_reset(struct omap3_spi_priv *priv) { unsigned int tmp; - writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, ®s->sysconfig); + writel(OMAP3_MCSPI_SYSCONFIG_SOFTRESET, &priv->regs->sysconfig); do { - tmp = readl(®s->sysstatus); + tmp = readl(&priv->regs->sysstatus); } while (!(tmp & OMAP3_MCSPI_SYSSTATUS_RESETDONE)); writel(OMAP3_MCSPI_SYSCONFIG_AUTOIDLE | OMAP3_MCSPI_SYSCONFIG_ENAWAKEUP | - OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, ®s->sysconfig); + OMAP3_MCSPI_SYSCONFIG_SMARTIDLE, &priv->regs->sysconfig); - writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, ®s->wakeupenable); + writel(OMAP3_MCSPI_WAKEUPENABLE_WKEN, &priv->regs->wakeupenable); + + /* + * Set the same default mode for each channel, especially CS polarity + * which must be common for all SPI slaves before any transfer. + */ + for (priv->cs = 0 ; priv->cs < OMAP4_MCSPI_CHAN_NB ; priv->cs++) + _omap3_spi_set_mode(priv); + priv->cs = 0; } static void _omap3_spi_claim_bus(struct omap3_spi_priv *priv) @@ -430,7 +438,7 @@ static int omap3_spi_probe(struct udevice *dev) priv->pin_dir = plat->pin_dir; priv->wordlen = SPI_DEFAULT_WORDLEN; - spi_reset(priv->regs); + spi_reset(priv); return 0; } diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index cb2b8fb..51c37d7 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -17,6 +17,7 @@ #include <linux/bug.h> #include <linux/errno.h> #include <spi.h> +#include <spi-mem.h> #include <wait_bit.h> #define RPC_CMNCR 0x0000 /* R/W */ @@ -140,6 +141,7 @@ #define PRC_PHYCNT_EXDS BIT(21) #define RPC_PHYCNT_OCT BIT(20) #define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) +#define RPC_PHYCNT_STRTIM2(v) ((((v) & 0x7) << 15) | (((v) & 0x8) << 24)) #define RPC_PHYCNT_WBUF2 BIT(4) #define RPC_PHYCNT_WBUF BIT(2) #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0) @@ -167,10 +169,6 @@ struct rpc_spi_priv { fdt_addr_t regs; fdt_addr_t extr; struct clk clk; - - u8 cmdcopy[8]; - u32 cmdlen; - bool cmdstarted; }; static int rpc_spi_wait_sslf(struct udevice *dev) @@ -202,18 +200,35 @@ static void rpc_spi_flush_read_cache(struct udevice *dev) } +static u32 rpc_spi_get_strobe_delay(void) +{ +#ifndef CONFIG_RZA1 + u32 cpu_type = rmobile_get_cpu_type(); + + /* + * NOTE: RPC_PHYCNT_STRTIM value: + * 0: On H3 ES1.x (not supported in mainline U-Boot) + * 6: On M3 ES1.x + * 7: On other R-Car Gen3 + * 15: On R-Car Gen4 + */ + if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && rmobile_get_cpu_rev_integer() == 1) + return RPC_PHYCNT_STRTIM(6); + else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 || + cpu_type == RMOBILE_CPU_TYPE_R8A779G0) + return RPC_PHYCNT_STRTIM2(15); + else +#endif + return RPC_PHYCNT_STRTIM(7); +} + static int rpc_spi_claim_bus(struct udevice *dev, bool manual) { struct udevice *bus = dev->parent; struct rpc_spi_priv *priv = dev_get_priv(bus); - /* - * NOTE: The 0x260 are undocumented bits, but they must be set. - * NOTE: On H3 ES1.x (not supported in mainline U-Boot), the - * RPC_PHYCNT_STRTIM shall be 0, while on newer parts, the - * RPC_PHYCNT_STRTIM shall be 6. - */ - writel(RPC_PHYCNT_CAL | RPC_PHYCNT_STRTIM(6) | 0x260, + /* NOTE: The 0x260 are undocumented bits, but they must be set. */ + writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260, priv->regs + RPC_PHYCNT); writel((manual ? RPC_CMNCR_MD : 0) | RPC_CMNCR_SFDE | RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | RPC_CMNCR_BSZ(0), @@ -233,79 +248,91 @@ static int rpc_spi_release_bus(struct udevice *dev) struct rpc_spi_priv *priv = dev_get_priv(bus); /* NOTE: The 0x260 are undocumented bits, but they must be set. */ - writel(RPC_PHYCNT_STRTIM(6) | 0x260, priv->regs + RPC_PHYCNT); + writel(rpc_spi_get_strobe_delay() | 0x260, priv->regs + RPC_PHYCNT); rpc_spi_flush_read_cache(dev); return 0; } -static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen, - const void *dout, void *din, unsigned long flags) +static int rpc_spi_mem_exec_op(struct spi_slave *spi, + const struct spi_mem_op *op) { - struct udevice *bus = dev->parent; + struct udevice *bus = spi->dev->parent; struct rpc_spi_priv *priv = dev_get_priv(bus); - u32 wlen = dout ? (bitlen / 8) : 0; - u32 rlen = din ? (bitlen / 8) : 0; - u32 wloop = DIV_ROUND_UP(wlen, 4); - u32 smenr, smcr, offset; + const void *dout = op->data.buf.out ? op->data.buf.out : NULL; + void *din = op->data.buf.in ? op->data.buf.in : NULL; int ret = 0; - - if (!priv->cmdstarted) { - if (!wlen || rlen) - BUG(); - - memcpy(priv->cmdcopy, dout, wlen); - priv->cmdlen = wlen; - - /* Command transfer start */ - priv->cmdstarted = true; - if (!(flags & SPI_XFER_END)) - return 0; - } - - offset = (priv->cmdcopy[1] << 16) | (priv->cmdcopy[2] << 8) | - (priv->cmdcopy[3] << 0); + u32 offset = 0; + u32 smenr, smcr; smenr = 0; + offset = op->addr.val; + + switch (op->data.dir) { + case SPI_MEM_DATA_IN: + rpc_spi_claim_bus(spi->dev, false); + + writel(0, priv->regs + RPC_DRCMR); + writel(RPC_DRCMR_CMD(op->cmd.opcode), priv->regs + RPC_DRCMR); + smenr |= RPC_DRENR_CDE; + + writel(0, priv->regs + RPC_DREAR); + if (op->addr.nbytes == 4) { + writel(RPC_DREAR_EAV(offset >> 25) | RPC_DREAR_EAC(1), + priv->regs + RPC_DREAR); + smenr |= RPC_DRENR_ADE(0xF); + } else if (op->addr.nbytes == 3) { + smenr |= RPC_DRENR_ADE(0x7); + } else { + smenr |= RPC_DRENR_ADE(0); + } - if (wlen || (!rlen && !wlen) || flags == SPI_XFER_ONCE) { - if (wlen && flags == SPI_XFER_END) - smenr = RPC_SMENR_SPIDE(0xf); + writel(0, priv->regs + RPC_DRDMCR); + if (op->dummy.nbytes) { + writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_DRDMCR); + smenr |= RPC_DRENR_DME; + } - rpc_spi_claim_bus(dev, true); + writel(0, priv->regs + RPC_DROPR); + writel(smenr, priv->regs + RPC_DRENR); - writel(0, priv->regs + RPC_SMCR); + memcpy_fromio(din, (void *)(priv->extr + offset), op->data.nbytes); - if (priv->cmdlen >= 1) { /* Command(1) */ - writel(RPC_SMCMR_CMD(priv->cmdcopy[0]), - priv->regs + RPC_SMCMR); - smenr |= RPC_SMENR_CDE; - } else { - writel(0, priv->regs + RPC_SMCMR); - } + rpc_spi_release_bus(spi->dev); + break; + case SPI_MEM_DATA_OUT: + case SPI_MEM_NO_DATA: + rpc_spi_claim_bus(spi->dev, true); - if (priv->cmdlen >= 4) { /* Address(3) */ - writel(offset, priv->regs + RPC_SMADR); - smenr |= RPC_SMENR_ADE(7); - } else { - writel(0, priv->regs + RPC_SMADR); - } + writel(0, priv->regs + RPC_SMCR); + writel(0, priv->regs + RPC_SMCMR); + writel(RPC_SMCMR_CMD(op->cmd.opcode), priv->regs + RPC_SMCMR); + smenr |= RPC_SMENR_CDE; + + writel(0, priv->regs + RPC_SMADR); + if (op->addr.nbytes == 4) + smenr |= RPC_SMENR_ADE(0xF); + else if (op->addr.nbytes == 3) + smenr |= RPC_SMENR_ADE(0x7); + else + smenr |= RPC_SMENR_ADE(0); + writel(offset, priv->regs + RPC_SMADR); - if (priv->cmdlen >= 5) { /* Dummy(n) */ - writel(8 * (priv->cmdlen - 4) - 1, - priv->regs + RPC_SMDMCR); + writel(0, priv->regs + RPC_SMDMCR); + if (op->dummy.nbytes) { + writel(8 * op->dummy.nbytes - 1, priv->regs + RPC_SMDMCR); smenr |= RPC_SMENR_DME; - } else { - writel(0, priv->regs + RPC_SMDMCR); } writel(0, priv->regs + RPC_SMOPR); - writel(0, priv->regs + RPC_SMDRENR); - if (wlen && flags == SPI_XFER_END) { + if (dout && op->data.nbytes) { u32 *datout = (u32 *)dout; + u32 wloop = DIV_ROUND_UP(op->data.nbytes, 4); + + smenr |= RPC_SMENR_SPIDE(0xF); while (wloop--) { smcr = RPC_SMCR_SPIWE | RPC_SMCR_SPIE; @@ -314,57 +341,28 @@ static int rpc_spi_xfer(struct udevice *dev, unsigned int bitlen, writel(smenr, priv->regs + RPC_SMENR); writel(*datout, priv->regs + RPC_SMWDR0); writel(smcr, priv->regs + RPC_SMCR); - ret = rpc_spi_wait_tend(dev); - if (ret) - goto err; + ret = rpc_spi_wait_tend(spi->dev); + if (ret) { + rpc_spi_release_bus(spi->dev); + return ret; + } datout++; - smenr = RPC_SMENR_SPIDE(0xf); + smenr &= (~RPC_SMENR_CDE & ~RPC_SMENR_ADE(0xF)); } - ret = rpc_spi_wait_sslf(dev); - + ret = rpc_spi_wait_sslf(spi->dev); } else { writel(smenr, priv->regs + RPC_SMENR); writel(RPC_SMCR_SPIE, priv->regs + RPC_SMCR); - ret = rpc_spi_wait_tend(dev); - } - } else { /* Read data only, using DRx ext access */ - rpc_spi_claim_bus(dev, false); - - if (priv->cmdlen >= 1) { /* Command(1) */ - writel(RPC_DRCMR_CMD(priv->cmdcopy[0]), - priv->regs + RPC_DRCMR); - smenr |= RPC_DRENR_CDE; - } else { - writel(0, priv->regs + RPC_DRCMR); - } - - if (priv->cmdlen >= 4) /* Address(3) */ - smenr |= RPC_DRENR_ADE(7); - - if (priv->cmdlen >= 5) { /* Dummy(n) */ - writel(8 * (priv->cmdlen - 4) - 1, - priv->regs + RPC_DRDMCR); - smenr |= RPC_DRENR_DME; - } else { - writel(0, priv->regs + RPC_DRDMCR); + ret = rpc_spi_wait_tend(spi->dev); } - writel(0, priv->regs + RPC_DROPR); - - writel(smenr, priv->regs + RPC_DRENR); - - if (rlen) - memcpy_fromio(din, (void *)(priv->extr + offset), rlen); - else - readl(priv->extr); /* Dummy read */ + rpc_spi_release_bus(spi->dev); + break; + default: + break; } -err: - priv->cmdstarted = false; - - rpc_spi_release_bus(dev); - return ret; } @@ -380,6 +378,10 @@ static int rpc_spi_set_mode(struct udevice *bus, uint mode) return 0; } +static const struct spi_controller_mem_ops rpc_spi_mem_ops = { + .exec_op = rpc_spi_mem_exec_op +}; + static int rpc_spi_bind(struct udevice *parent) { const void *fdt = gd->fdt_blob; @@ -443,9 +445,9 @@ static int rpc_spi_of_to_plat(struct udevice *bus) } static const struct dm_spi_ops rpc_spi_ops = { - .xfer = rpc_spi_xfer, .set_speed = rpc_spi_set_speed, .set_mode = rpc_spi_set_mode, + .mem_ops = &rpc_spi_mem_ops }; static const struct udevice_id rpc_spi_ids[] = { diff --git a/drivers/spi/spi-qup.c b/drivers/spi/spi-qup.c index 7b64532..572cef1 100644 --- a/drivers/spi/spi-qup.c +++ b/drivers/spi/spi-qup.c @@ -9,7 +9,7 @@ * Author: Robert Marko <robert.marko@sartura.hr> * Author: Luka Kovacic <luka.kovacic@sartura.hr> * - * Based on stock U-boot and Linux drivers + * Based on stock U-Boot and Linux drivers */ #include <asm/gpio.h> diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig index 03f7fdd..bdbe2a9 100644 --- a/drivers/sysreset/Kconfig +++ b/drivers/sysreset/Kconfig @@ -61,14 +61,14 @@ endif config POWEROFF_GPIO bool "Enable support for GPIO poweroff driver" - select DM_GPIO + depends on DM_GPIO help Support for system poweroff using a GPIO pin. This can be used for systems having a single GPIO to trigger a system poweroff. config SYSRESET_GPIO bool "Enable support for GPIO reset driver" - select DM_GPIO + depends on DM_GPIO help Reset support via GPIO pin connected reset logic. This is used for example on Microblaze where reset logic can be controlled via GPIO diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 94fb32d..a972d87 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -126,6 +126,28 @@ config USB_HUB_DEBOUNCE_TIMEOUT value = 1s because some usb device needs around 1.5s to be initialized and a 2s value should solve detection issue on problematic USB keys. +if SPL_USB_HOST + +comment "USB peripherals in SPL" + +config SPL_USB_STORAGE + bool "Support loading from USB" + help + Enable support for USB devices in SPL. This allows use of USB + devices such as hard drives and flash drivers for loading U-Boot. + The actual drivers are enabled separately using the normal U-Boot + config options. This enables loading from USB using a configured + device. + +config SYS_USB_FAT_BOOT_PARTITION + int "Partition on USB to use to load U-Boot from" + depends on SPL_USB_STORAGE + default 1 + help + Partition on the USB storage device to load U-Boot from. + +endif + if USB_KEYBOARD config USB_KEYBOARD_FN_KEYS diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 66da5a8..35e4b36 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -105,7 +105,7 @@ static int dwc3_generic_probe(struct udevice *dev, if (CONFIG_IS_ENABLED(DM_GPIO) && device_is_compatible(dev->parent, "xlnx,zynqmp-dwc3")) { priv->ulpi_reset = devm_gpiod_get_optional(dev->parent, "reset", - GPIOD_ACTIVE_LOW); + GPIOD_IS_OUT | GPIOD_ACTIVE_LOW); /* property is optional, don't return error! */ if (priv->ulpi_reset) { /* Toggle ulpi to reset the phy. */ diff --git a/drivers/usb/eth/lan78xx.c b/drivers/usb/eth/lan78xx.c index 37912a1..1d8267c 100644 --- a/drivers/usb/eth/lan78xx.c +++ b/drivers/usb/eth/lan78xx.c @@ -146,11 +146,9 @@ static int lan78xx_read_otp(struct usb_device *udev, u32 offset, ret = lan78xx_read_raw_otp(udev, 0, 1, &sig); if (!ret) { - if (sig == LAN78XX_OTP_INDICATOR_1) - offset = offset; - else if (sig == LAN78XX_OTP_INDICATOR_2) + if (sig == LAN78XX_OTP_INDICATOR_2) offset += 0x100; - else + else if (sig != LAN78XX_OTP_INDICATOR_1) return -EINVAL; ret = lan78xx_read_raw_otp(udev, offset, length, data); if (ret) diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index 941f97c..1cfe602 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -36,6 +36,12 @@ menuconfig USB_GADGET peripheral/device side bus controller, and a "gadget driver" for your peripheral protocol. +config SPL_USB_GADGET + bool "USB Gadget Support in SPL" + help + Enable USB Gadget API which allows to enable USB device functions + in SPL. + if USB_GADGET config USB_GADGET_MANUFACTURER @@ -265,3 +271,85 @@ config USBNET_HOST_ADDR endif # USB_ETHER endif # USB_GADGET + +if SPL_USB_GADGET + +config SPL_USB_ETHER + bool "Support USB Ethernet drivers in SPL" + depends on SPL_NET + help + Enable access to the USB network subsystem and associated + drivers in SPL. This permits SPL to load U-Boot over a + USB-connected Ethernet link (such as a USB Ethernet dongle) rather + than from an onboard peripheral. Environment support is required + since the network stack uses a number of environment variables. + See also SPL_NET and SPL_ETH. + +if SPL_USB_ETHER + +choice + prompt "USB Ethernet Gadget Model in SPL" + default SPL_USB_ETH_RNDIS + help + There is several models (protocols) to implement Ethernet over USB + devices. The main ones are Microsoft's RNDIS and USB's CDC-Ethernet + (also called CDC-ECM). RNDIS is obviously compatible with Windows, + while CDC-ECM is not. Most other operating systems support both, so + if inter-operability is a concern, RNDIS is to be preferred. + +config SPL_USB_ETH_RNDIS + bool "RNDIS Protocol" + help + The RNDIS (Remote Network Driver Interface Specification) is a + Microsoft proprietary protocol to create an Ethernet device over USB. + Windows obviously supports it, as well as all the major operating + systems, so it's the best option for compatibility. + +endchoice + +endif # SPL_USB_ETHER + +config SPL_DFU + bool "Support DFU (Device Firmware Upgrade) in SPL" + select SPL_HASH + select SPL_DFU_NO_RESET + depends on SPL_RAM_SUPPORT + help + This feature enables the DFU (Device Firmware Upgrade) in SPL with + RAM memory device support. The ROM code will load and execute + the SPL built with dfu. The user can load binaries (u-boot/kernel) to + selected device partition from host-pc using dfu-utils. + This feature is useful to flash the binaries to factory or bare-metal + boards using USB interface. + +choice + bool "DFU device selection in SPL" + depends on SPL_DFU + +config SPL_DFU_RAM + bool "RAM device" + depends on SPL_DFU && SPL_RAM_SUPPORT + help + select RAM/DDR memory device for loading binary images + (u-boot/kernel) to the selected device partition using + DFU and execute the u-boot/kernel from RAM. + +endchoice + +config SPL_USB_SDP_SUPPORT + bool "Support SDP (Serial Download Protocol) in SPL" + depends on SPL_SERIAL + help + Enable Serial Download Protocol (SDP) device support in SPL. This + allows to download images into memory and execute (jump to) them + using the same protocol as implemented by the i.MX family's boot ROM. + +config SPL_SDP_USB_DEV + int "SDP USB controller index in SPL" + default 0 + depends on SPL_USB_SDP_SUPPORT + help + Some boards have USB controller other than 0. Define this option + so it can be used in compiled environment. + +endif # SPL_USB_GADGET diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 6cfe0f3..6abcce0 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -3,8 +3,9 @@ # (C) Copyright 2000-2007 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. -obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o -obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o +obj-$(CONFIG_$(SPL_TPL_)USB_GADGET) += epautoconf.o config.o usbstring.o +obj-$(CONFIG_$(SPL_TPL_)USB_ETHER) += epautoconf.o config.o usbstring.o ether.o +obj-$(CONFIG_$(SPL_TPL_)USB_ETH_RNDIS) += rndis.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_USB_GADGET) += g_dnl.o @@ -34,9 +35,6 @@ endif obj-$(CONFIG_CI_UDC) += ci_udc.o -obj-$(CONFIG_USB_ETHER) += ether.o -obj-$(CONFIG_USB_ETH_RNDIS) += rndis.o - # Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE # This is really only N900 and USBTTY now. obj-$(CONFIG_USB_DEVICE) += core.o ep0.o diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 6213b3c..1a883ba 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -6,6 +6,19 @@ comment "USB Host Controller Drivers" config USB_HOST bool select DM_USB + help + Enable access to USB (Universal Serial Bus) host devices so that + SPL can load U-Boot from a connected USB peripheral, such as a USB + flash stick. While USB takes a little longer to start up than most + buses, it is very flexible since many different types of storage + device can be attached. + +config SPL_USB_HOST + bool "Support USB host drivers" + depends on SPL + help + For detailed help see USB_HOST Kconfig symbol. This option enables + the drivers in drivers/usb/host as part of an SPL build. config USB_XHCI_HCD bool "xHCI HCD (USB 3.0) support" diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 1e2f4e6..4976295 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -740,14 +740,7 @@ config VIDEO_SEPS525 Enable support for the Syncoam PM-OLED display driver (RGB 160x128). Currently driver is supporting only SPI interface. -config VIDEO_ZYNQMP_DPSUB - bool "Enable video support for ZynqMP Display Port" - depends on ZYNQMP_POWER_DOMAIN - help - Enable support for Xilinx ZynqMP Display Port. Currently this file - is used as placeholder for driver. The main reason is to record - compatible string and calling power domain driver. - +source "drivers/video/zynqmp/Kconfig" source "drivers/video/nexell/Kconfig" config CONSOLE_SCROLL_LINES diff --git a/drivers/video/Makefile b/drivers/video/Makefile index 9a53cd1..f99d7e3 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -73,7 +73,7 @@ obj-$(CONFIG_VIDEO_SANDBOX_SDL) += sandbox_sdl.o obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o obj-$(CONFIG_VIDEO_VESA) += vesa.o obj-$(CONFIG_VIDEO_SEPS525) += seps525.o -obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp_dpsub.o +obj-$(CONFIG_VIDEO_ZYNQMP_DPSUB) += zynqmp/ obj-y += bridge/ obj-y += sunxi/ diff --git a/drivers/video/video-uclass.c b/drivers/video/video-uclass.c index 8396bdf..1b66a80 100644 --- a/drivers/video/video-uclass.c +++ b/drivers/video/video-uclass.c @@ -220,14 +220,20 @@ u32 video_index_to_colour(struct video_priv *priv, unsigned int idx) break; case VIDEO_BPP32: if (CONFIG_IS_ENABLED(VIDEO_BPP32)) { - if (priv->format == VIDEO_X2R10G10B10) + switch (priv->format) { + case VIDEO_X2R10G10B10: return (colours[idx].r << 22) | (colours[idx].g << 12) | (colours[idx].b << 2); - else + case VIDEO_RGBA8888: + return (colours[idx].r << 24) | + (colours[idx].g << 16) | + (colours[idx].b << 8) | 0xff; + default: return (colours[idx].r << 16) | (colours[idx].g << 8) | (colours[idx].b << 0); + } } break; default: diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c index 47e52c4..45f003c 100644 --- a/drivers/video/video_bmp.c +++ b/drivers/video/video_bmp.c @@ -43,6 +43,18 @@ static u32 get_bmp_col_x2r10g10b10(struct bmp_color_table_entry *cte) } /** + * get_bmp_col_rgba8888() - Convert a colour-table entry into a rgba8888 pixel value + * + * Return: value to write to the rgba8888 frame buffer for this palette entry + */ +static u32 get_bmp_col_rgba8888(struct bmp_color_table_entry *cte) +{ + return ((cte->red) | + (cte->green << 8U) | + (cte->blue << 16U) | 0xff << 24U); +} + +/** * write_pix8() - Write a pixel from a BMP image into the framebuffer * * This handles frame buffers with 8, 16, 24 or 32 bits per pixel @@ -71,6 +83,8 @@ static void write_pix8(u8 *fb, uint bpix, enum video_format eformat, *fb++ = cte->blue; } else if (eformat == VIDEO_X2R10G10B10) { *(u32 *)fb = get_bmp_col_x2r10g10b10(cte); + } else if (eformat == VIDEO_RGBA8888) { + *(u32 *)fb = get_bmp_col_rgba8888(cte); } else { *fb++ = cte->blue; *fb++ = cte->green; @@ -382,6 +396,17 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, *fb++ = (pix >> 8) & 0xff; *fb++ = (pix >> 16) & 0xff; *fb++ = pix >> 24; + } else if (eformat == VIDEO_RGBA8888) { + u32 pix; + + pix = *bmap++ << 8U; /* blue */ + pix |= *bmap++ << 16U; /* green */ + pix |= *bmap++ << 24U; /* red */ + + *fb++ = (pix >> 24) & 0xff; + *fb++ = (pix >> 16) & 0xff; + *fb++ = (pix >> 8) & 0xff; + *fb++ = 0xff; } else { *fb++ = *bmap++; *fb++ = *bmap++; @@ -409,6 +434,17 @@ int video_bmp_display(struct udevice *dev, ulong bmp_image, int x, int y, *fb++ = (pix >> 8) & 0xff; *fb++ = (pix >> 16) & 0xff; *fb++ = pix >> 24; + } else if (eformat == VIDEO_RGBA8888) { + u32 pix; + + pix = *bmap++ << 8U; /* blue */ + pix |= *bmap++ << 16U; /* green */ + pix |= *bmap++ << 24U; /* red */ + bmap++; + *fb++ = (pix >> 24) & 0xff; + *fb++ = (pix >> 16) & 0xff; + *fb++ = (pix >> 8) & 0xff; + *fb++ = 0xff; /* opacity */ } else { *fb++ = *bmap++; *fb++ = *bmap++; diff --git a/drivers/video/zynqmp/Kconfig b/drivers/video/zynqmp/Kconfig new file mode 100644 index 0000000..b35cd1f --- /dev/null +++ b/drivers/video/zynqmp/Kconfig @@ -0,0 +1,8 @@ + +config VIDEO_ZYNQMP_DPSUB + bool "Enable video support for ZynqMP Display Port" + depends on ZYNQMP_POWER_DOMAIN + help + Enable support for Xilinx ZynqMP Display Port. Currently this file + is used as placeholder for driver. The main reason is to record + compatible string and calling power domain driver. diff --git a/drivers/video/zynqmp/Makefile b/drivers/video/zynqmp/Makefile new file mode 100644 index 0000000..cc057f5 --- /dev/null +++ b/drivers/video/zynqmp/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0 +# +# Copyright (C) 2023, Advanced Micro Devices, Inc. + +obj-y += zynqmp_dpsub.o diff --git a/drivers/video/zynqmp/zynqmp_dpsub.c b/drivers/video/zynqmp/zynqmp_dpsub.c new file mode 100644 index 0000000..def4dcf --- /dev/null +++ b/drivers/video/zynqmp/zynqmp_dpsub.c @@ -0,0 +1,2225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2021 - 2022, Xilinx Inc. + * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. + * + * Xilinx displayport(DP) Tx Subsytem driver + */ + +#include <common.h> +#include <clk.h> +#include <cpu_func.h> +#include <dm.h> +#include <errno.h> +#include <generic-phy.h> +#include <stdlib.h> +#include <video.h> +#include <wait_bit.h> +#include <dm/device_compat.h> +#include <asm/io.h> +#include <linux/delay.h> +#include <linux/ioport.h> +#include <dm/device_compat.h> +#include <asm/global_data.h> + +#include "zynqmp_dpsub.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* Maximum supported resolution */ +#define WIDTH 1024 +#define HEIGHT 768 + +static struct dp_dma dp_dma; +static struct dp_dma_descriptor cur_desc __aligned(256); + +static void dma_init_video_descriptor(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + struct dp_dma_frame_buffer *frame_buffer = &dp_sub->frame_buffer; + + cur_desc.control = DPDMA_DESC_PREAMBLE | DPDMA_DESC_IGNR_DONE | + DPDMA_DESC_LAST_FRAME; + cur_desc.dscr_id = 0; + cur_desc.xfer_size = frame_buffer->size; + cur_desc.line_size_stride = ((frame_buffer->stride >> 4) << + DPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT) | + (frame_buffer->line_size); + cur_desc.addr_ext = (((u32)(frame_buffer->address >> + DPDMA_DESCRIPTOR_SRC_ADDR_WIDTH) << + DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT) | + (upper_32_bits((u64)&cur_desc))); + cur_desc.next_desr = lower_32_bits((u64)&cur_desc); + cur_desc.src_addr = lower_32_bits((u64)gd->fb_base); +} + +static void dma_set_descriptor_address(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + flush_dcache_range((u64)&cur_desc, + ALIGN(((u64)&cur_desc + sizeof(cur_desc)), + CONFIG_SYS_CACHELINE_SIZE)); + writel(upper_32_bits((u64)&cur_desc), dp_sub->dp_dma->base_addr + + DPDMA_CH3_DSCR_STRT_ADDRE); + writel(lower_32_bits((u64)&cur_desc), dp_sub->dp_dma->base_addr + + DPDMA_CH3_DSCR_STRT_ADDR); +} + +static void dma_setup_channel(struct udevice *dev) +{ + dma_init_video_descriptor(dev); + dma_set_descriptor_address(dev); +} + +static void dma_set_channel_state(struct udevice *dev) +{ + u32 mask = 0, regval = 0; + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + mask = DPDMA_CH_CNTL_EN_MASK | DPDMA_CH_CNTL_PAUSE_MASK; + regval = DPDMA_CH_CNTL_EN_MASK; + + clrsetbits_le32(dp_sub->dp_dma->base_addr + DPDMA_CH3_CNTL, + mask, regval); +} + +static void dma_trigger(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 trigger; + + trigger = DPDMA_GBL_TRG_CH3_MASK; + dp_sub->dp_dma->gfx.trigger_status = DPDMA_TRIGGER_DONE; + writel(trigger, dp_sub->dp_dma->base_addr + DPDMA_GBL); +} + +static void dma_vsync_intr_handler(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + dma_setup_channel(dev); + dma_set_channel_state(dev); + dma_trigger(dev); + + /* Clear VSync Interrupt */ + writel(DPDMA_ISR_VSYNC_INT_MASK, dp_sub->dp_dma->base_addr + DPDMA_ISR); +} + +/** + * wait_phy_ready() - Wait for the DisplayPort PHY to come out of reset + * @dev: The DP device + * + * Return: 0 if wait succeeded, -ve if error occurred + */ +static int wait_phy_ready(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 timeout = 100, phy_status; + u8 phy_ready_mask = DP_PHY_STATUS_RESET_LANE_0_DONE_MASK | + DP_PHY_STATUS_GT_PLL_LOCK_MASK; + + /* Wait until the PHY is ready. */ + do { + udelay(20); + phy_status = readl(dp_sub->base_addr + DP_PHY_STATUS); + phy_status &= phy_ready_mask; + /* Protect against an infinite loop. */ + if (!timeout--) + return -ETIMEDOUT; + } while (phy_status != phy_ready_mask); + + return 0; +} + +static int init_dp_tx(struct udevice *dev) +{ + u32 status, phyval, regval, rate; + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + phyval = readl(dp_sub->base_addr + DP_PHY_CONFIG); + writel(DP_SOFT_RESET_EN, dp_sub->base_addr + DP_SOFT_RESET); + status = readl(dp_sub->base_addr + DP_SOFT_RESET); + writel(DP_DISABLE, dp_sub->base_addr + DP_ENABLE); + + regval = (readl(dp_sub->base_addr + DP_AUX_CLK_DIVIDER) & + ~DP_AUX_CLK_DIVIDER_VAL_MASK) | + (60 << 8) | + (dp_sub->clock / 1000000); + writel(regval, dp_sub->base_addr + DP_AUX_CLK_DIVIDER); + + writel(DP_PHY_CLOCK_SELECT_540GBPS, dp_sub->base_addr + DP_PHY_CLOCK_SELECT); + + regval = phyval & ~DP_PHY_CONFIG_GT_ALL_RESET_MASK; + writel(regval, dp_sub->base_addr + DP_PHY_CONFIG); + status = wait_phy_ready(dev); + if (status) + return -EINVAL; + + writel(DP_ENABLE, dp_sub->base_addr + DP_ENABLE); + + rate = ~DP_INTR_HPD_PULSE_DETECTED_MASK & ~DP_INTR_HPD_EVENT_MASK + & ~DP_INTR_HPD_IRQ_MASK; + writel(rate, dp_sub->base_addr + DP_INTR_MASK); + return 0; +} + +static int set_nonlive_gfx_format(struct udevice *dev, enum av_buf_video_format format) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + struct av_buf_vid_attribute *ptr = (struct av_buf_vid_attribute *)avbuf_supported_formats; + + while (1) { + dev_dbg(dev, "Format %d\n", ptr->video_format); + + if (!ptr->video_format) + return -EINVAL; + + if (ptr->video_format == format) { + dp_sub->non_live_graphics = ptr; + break; + } + ptr++; + } + dev_dbg(dev, "Video format found. BPP %d\n", dp_sub->non_live_graphics->bpp); + return 0; +} + +/* DP dma setup */ +static void set_qos(struct udevice *dev, u8 qos) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u8 index; + u32 regval = 0, mask; + + regval = (((u32)qos << DPDMA_CH_CNTL_QOS_DATA_RD_SHIFT) | + ((u32)qos << DPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT) | + ((u32)qos << DPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT)); + + mask = DPDMA_CH_CNTL_QOS_DATA_RD_MASK | + DPDMA_CH_CNTL_QOS_DSCR_RD_MASK | + DPDMA_CH_CNTL_QOS_DSCR_WR_MASK; + for (index = 0; index <= DPDMA_AUDIO_CHANNEL1; index++) { + clrsetbits_le32(dp_sub->dp_dma->base_addr + + DPDMA_CH0_CNTL + + (DPDMA_CH_OFFSET * (u32)index), + mask, regval); + } +} + +static void enable_gfx_buffers(struct udevice *dev, u8 enable) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 regval = 0; + + regval = (0xF << AVBUF_CHBUF3_BURST_LEN_SHIFT) | + AVBUF_CHBUF3_FLUSH_MASK; + writel(regval, dp_sub->base_addr + AVBUF_CHBUF3); + if (enable) { + regval = (0xF << AVBUF_CHBUF3_BURST_LEN_SHIFT) | + AVBUF_CHBUF0_EN_MASK; + writel(regval, dp_sub->base_addr + AVBUF_CHBUF3); + } +} + +static void avbuf_video_select(struct udevice *dev, enum av_buf_video_stream vid_stream, + enum av_buf_gfx_stream gfx_stream) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + dp_sub->av_mode.video_src = vid_stream; + dp_sub->av_mode.gfx_src = gfx_stream; + + clrsetbits_le32(dp_sub->base_addr + + AVBUF_BUF_OUTPUT_AUD_VID_SELECT, + AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK | + AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK, + vid_stream | gfx_stream); +} + +static void config_gfx_pipeline(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u16 *csc_matrix, *offset_matrix; + u32 regval = 0, index = 0, *scaling_factors = NULL; + u16 rgb_coeffs[] = { 0x1000, 0x0000, 0x0000, + 0x0000, 0x1000, 0x0000, + 0x0000, 0x0000, 0x1000 }; + u16 rgb_offset[] = { 0x0000, 0x0000, 0x0000 }; + struct av_buf_vid_attribute *video = dp_sub->non_live_graphics; + + scaling_factors = video->sf; + + clrsetbits_le32(dp_sub->base_addr + AVBUF_BUF_FORMAT, + AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK, + (video->value) << AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT); + + for (index = 0; index < 3; index++) { + writel(scaling_factors[index], dp_sub->base_addr + + AVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR + (index * 4)); + } + regval = (video->is_rgb << AVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT) | + video->sampling_en; + writel(regval, dp_sub->base_addr + AVBUF_V_BLEND_LAYER1_CONTROL); + + if (video->is_rgb) { + csc_matrix = rgb_coeffs; + offset_matrix = rgb_offset; + } + /* Program Colorspace conversion coefficients */ + for (index = 9; index < 12; index++) { + writel(offset_matrix[index - 9], dp_sub->base_addr + + AVBUF_V_BLEND_IN2CSC_COEFF0 + (index * 4)); + } + + /* Program Colorspace conversion matrix */ + for (index = 0; index < 9; index++) { + writel(csc_matrix[index], dp_sub->base_addr + + AVBUF_V_BLEND_IN2CSC_COEFF0 + (index * 4)); + } +} + +static void set_blender_alpha(struct udevice *dev, u8 alpha, u8 enable) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 regval; + + regval = enable; + regval |= alpha << AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT; + writel(regval, dp_sub->base_addr + + AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG); +} + +static void config_output_video(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 regval = 0, index; + u16 rgb_coeffs[] = { 0x1000, 0x0000, 0x0000, + 0x0000, 0x1000, 0x0000, + 0x0000, 0x0000, 0x1000 }; + u16 rgb_offset[] = { 0x0000, 0x0000, 0x0000 }; + u16 *matrix_coeff = rgb_coeffs, *matrix_offset = rgb_offset; + + struct av_buf_vid_attribute *output_video = dp_sub->non_live_graphics; + + regval |= output_video->sampling_en << + AVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT; + regval |= output_video->value; + writel(regval, dp_sub->base_addr + AVBUF_V_BLEND_OUTPUT_VID_FORMAT); + + for (index = 0; index < 9; index++) { + writel(matrix_coeff[index], dp_sub->base_addr + + AVBUF_V_BLEND_RGB2YCBCR_COEFF0 + (index * 4)); + } + + for (index = 0; index < 3; index++) { + writel((matrix_offset[index] << + AVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT), + dp_sub->base_addr + + AVBUF_V_BLEND_LUMA_OUTCSC_OFFSET + + (index * 4)); + } + + set_blender_alpha(dev, 0, 0); +} + +static void config_msa_sync_clk_mode(struct udevice *dev, u8 enable) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + struct main_stream_attributes *msa_config; + + msa_config = &dp_sub->msa_config; + msa_config->synchronous_clock_mode = enable; + + if (enable == 1) { + msa_config->misc0 |= (1 << + DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT); + } else { + msa_config->misc0 &= ~(1 << + DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT); + } +} + +static void av_buf_soft_reset(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + writel(AVBUF_BUF_SRST_REG_VID_RST_MASK, + dp_sub->base_addr + AVBUF_BUF_SRST_REG); + writel(0, dp_sub->base_addr + AVBUF_BUF_SRST_REG); +} + +static void set_video_clk_source(struct udevice *dev, u8 video_clk, u8 audio_clk) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 regval = 0; + + if (dp_sub->av_mode.video_src != AVBUF_VIDSTREAM1_LIVE && + dp_sub->av_mode.gfx_src != AVBUF_VIDSTREAM2_LIVE_GFX) { + regval = 1 << AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT; + } else if (dp_sub->av_mode.video_src == AVBUF_VIDSTREAM1_LIVE || + dp_sub->av_mode.gfx_src == AVBUF_VIDSTREAM2_LIVE_GFX) { + video_clk = AVBUF_PL_CLK; + } + + regval |= (video_clk << AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT) | + (audio_clk << AVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT); + writel(regval, dp_sub->base_addr + AVBUF_BUF_AUD_VID_CLK_SOURCE); + + av_buf_soft_reset(dev); +} + +static int init_dpdma_subsys(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + dp_sub->dp_dma->base_addr = DPDMA_BASE_ADDRESS; + dp_sub->dp_dma->gfx.channel.cur = NULL; + dp_sub->dp_dma->gfx.trigger_status = DPDMA_TRIGGER_DONE; + + set_qos(dev, 11); + return 0; +} + +/** + * is_dp_connected() - Check if there is a connected RX device + * @dev: The DP device + * + * + * Return: true if a connected RX device was detected, false otherwise + */ +static bool is_dp_connected(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 status; + u8 retries = 0; + + do { + status = readl(dp_sub->base_addr + + DP_INTERRUPT_SIG_STATE) + & DP_INTERRUPT_SIG_STATE_HPD_STATE_MASK; + + if (retries > DP_IS_CONNECTED_MAX_TIMEOUT_COUNT) + return 0; + + retries++; + udelay(1000); + } while (status == 0); + + return 1; +} + +/** + * aux_wait_ready() - Wait until another request is no longer in progress + * @dev: The DP device + * + * Return: 0 if wait succeeded, -ve if error occurred + */ +static int aux_wait_ready(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 status, timeout = 100; + + do { + status = readl(dp_sub->base_addr + + DP_INTERRUPT_SIG_STATE); + if (!timeout--) + return -ETIMEDOUT; + + udelay(20); + } while (status & DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK); + + return 0; +} + +/** + * aux_wait_reply() - Wait for reply on AUX channel + * @dev: The DP device + * + * Wait for a reply indicating that the most recent AUX request + * has been received by the RX device. + * + * Return: 0 if wait succeeded, -ve if error occurred + */ +static int aux_wait_reply(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 timeout = DP_AUX_MAX_WAIT, status; + + while (timeout > 0) { + status = readl(dp_sub->base_addr + DP_REPLY_STATUS); + if (status & DP_REPLY_STATUS_REPLY_ERROR_MASK) + return -ETIMEDOUT; + + if ((status & DP_REPLY_STATUS_REPLY_RECEIVED_MASK) && + !(status & DP_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) && + !(status & DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK)) { + return 0; + } + timeout--; + udelay(20); + } + return -ETIMEDOUT; +} + +/** + * aux_request_send() - Send request on the AUX channel + * @dev: The DP device + * @request: The request to send + * + * Submit the supplied AUX request to the RX device over the AUX + * channel by writing the command, the destination address, (the write buffer + * for write commands), and the data size to the DisplayPort TX core. + * + * This is the lower-level sending routine, which is called by aux_request(). + * + * Return: 0 if request was sent successfully, -ve on error + */ +static int aux_request_send(struct udevice *dev, struct aux_transaction *request) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 timeout_count = 0, status; + u8 index; + + do { + status = readl(dp_sub->base_addr + + DP_REPLY_STATUS); + + udelay(20); + timeout_count++; + if (timeout_count >= DP_AUX_MAX_TIMEOUT_COUNT) + return -ETIMEDOUT; + + } while ((status & DP_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK) || + (status & DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK)); + /* Set the address for the request. */ + writel(request->address, dp_sub->base_addr + DP_AUX_ADDRESS); + + if (request->cmd_code == DP_AUX_CMD_WRITE || + request->cmd_code == DP_AUX_CMD_I2C_WRITE || + request->cmd_code == DP_AUX_CMD_I2C_WRITE_MOT) { + /* Feed write data into the DisplayPort TX core's write FIFO. */ + for (index = 0; index < request->num_bytes; index++) { + writel(request->data[index], + dp_sub->base_addr + + DP_AUX_WRITE_FIFO); + } + } + + status = ((request->cmd_code << DP_AUX_CMD_SHIFT) | + ((request->num_bytes - 1) & + DP_AUX_CMD_NBYTES_TRANSFER_MASK)); + + /* Submit the command and the data size. */ + writel(((request->cmd_code << DP_AUX_CMD_SHIFT) | + ((request->num_bytes - 1) & DP_AUX_CMD_NBYTES_TRANSFER_MASK)), + dp_sub->base_addr + DP_AUX_CMD); + + /* Check for a reply from the RX device to the submitted request. */ + status = aux_wait_reply(dev); + if (status) + /* Waiting for a reply timed out. */ + return -ETIMEDOUT; + + /* Analyze the reply. */ + status = readl(dp_sub->base_addr + DP_AUX_REPLY_CODE); + if (status == DP_AUX_REPLY_CODE_DEFER || + status == DP_AUX_REPLY_CODE_I2C_DEFER) { + /* The request was deferred. */ + return -EAGAIN; + } else if (status == DP_AUX_REPLY_CODE_NACK || + status == DP_AUX_REPLY_CODE_I2C_NACK) { + /* The request was not acknowledged. */ + return -EIO; + } + + /* The request was acknowledged. */ + if (request->cmd_code == DP_AUX_CMD_READ || + request->cmd_code == DP_AUX_CMD_I2C_READ || + request->cmd_code == DP_AUX_CMD_I2C_READ_MOT) { + /* Wait until all data has been received. */ + timeout_count = 0; + do { + status = readl(dp_sub->base_addr + + DP_REPLY_DATA_COUNT); + udelay(100); + timeout_count++; + if (timeout_count >= DP_AUX_MAX_TIMEOUT_COUNT) + return -ETIMEDOUT; + } while (status != request->num_bytes); + + /* Obtain the read data from the reply FIFO. */ + for (index = 0; index < request->num_bytes; index++) { + request->data[index] = readl(dp_sub->base_addr + + DP_AUX_REPLY_DATA); + } + } + return 0; +} + +/** + * aux_request() - Submit request on the AUX channel + * @dev: The DP device + * @request: The request to submit + * + * Submit the supplied AUX request to the RX device over the AUX + * channel. If waiting for a reply times out, or if the DisplayPort TX core + * indicates that the request was deferred, the request is sent again (up to a + * maximum specified by DP_AUX_MAX_DEFER_COUNT|DP_AUX_MAX_TIMEOUT_COUNT). + * + * Return: 0 if request was submitted successfully, -ve on error + */ +static int aux_request(struct udevice *dev, struct aux_transaction *request) +{ + u32 status, defer_count = 0, timeout_count = 0; + + do { + status = aux_wait_ready(dev); + if (status) { + /* The RX device isn't ready yet. */ + timeout_count++; + continue; + } + /* Send the request. */ + status = aux_request_send(dev, request); + if (status == -EAGAIN) { + /* The request was deferred. */ + defer_count++; + } else if (status == -ETIMEDOUT) { + /* Waiting for a reply timed out. */ + timeout_count++; + } else { + return status; + } + + udelay(100); + } while ((defer_count < DP_AUX_MAX_DEFER_COUNT) && + (timeout_count < DP_AUX_MAX_TIMEOUT_COUNT)); + + /* The request was not successfully received by the RX device. */ + return -ETIMEDOUT; +} + +/** + * aux_common() - Common (read/write) AUX communication transmission + * @dev: The DP device + * @cmd_type: Command code of the transaction + * @address: The DPCD address of the transaction + * @num_bytes: Number of bytes in the payload data + * @data: The payload data of the AUX command + * + * Common sequence of submitting an AUX command for AUX read, AUX write, + * I2C-over-AUX read, and I2C-over-AUX write transactions. If required, the + * reads and writes are split into multiple requests, each acting on a maximum + * of 16 bytes. + * + * Return: 0 if OK, -ve on error + */ +static int aux_common(struct udevice *dev, u32 cmd_type, u32 address, + u32 num_bytes, u8 *data) +{ + u32 status, bytes_left; + struct aux_transaction request; + + if (!is_dp_connected(dev)) + return -ENODEV; + + /* + * Set the start address for AUX transactions. For I2C transactions, + * this is the address of the I2C bus. + */ + request.address = address; + bytes_left = num_bytes; + while (bytes_left > 0) { + request.cmd_code = cmd_type; + + if (cmd_type == DP_AUX_CMD_READ || + cmd_type == DP_AUX_CMD_WRITE) { + /* Increment address for normal AUX transactions. */ + request.address = address + (num_bytes - bytes_left); + } + + /* Increment the pointer to the supplied data buffer. */ + request.data = &data[num_bytes - bytes_left]; + + if (bytes_left > 16) + request.num_bytes = 16; + else + request.num_bytes = bytes_left; + + bytes_left -= request.num_bytes; + + if (cmd_type == DP_AUX_CMD_I2C_READ && bytes_left > 0) { + /* + * Middle of a transaction I2C read request. Override + * the command code that was set to CmdType. + */ + request.cmd_code = DP_AUX_CMD_I2C_READ_MOT; + } else if (cmd_type == DP_AUX_CMD_I2C_WRITE && bytes_left > 0) { + /* + * Middle of a transaction I2C write request. Override + * the command code that was set to CmdType. + */ + request.cmd_code = DP_AUX_CMD_I2C_WRITE_MOT; + } + + status = aux_request(dev, &request); + if (status) + return status; + } + return 0; +} + +/** + * aux_write() - Issue AUX write request + * @dev: The DP device + * @dpcd_address: The DPCD address to write to + * @bytes_to_write: Number of bytes to write + * @write_data: Buffer containig data to be written + * + * Issue a write request over the AUX channel that will write to + * the RX device's DisplayPort Configuration data (DPCD) address space. The + * write message will be divided into multiple transactions which write a + * maximum of 16 bytes each. + * + * Return: 0 if write operation was successful, -ve on error + */ +static int aux_write(struct udevice *dev, u32 dpcd_address, u32 bytes_to_write, + void *write_data) +{ + return aux_common(dev, DP_AUX_CMD_WRITE, dpcd_address, + bytes_to_write, (u8 *)write_data); +} + +/** + * aux_read() - Issue AUX read request + * @dev: The DP device + * @dpcd_address: The DPCD address to read from + * @bytes_to_read: Number of bytes to read + * @read_data: Buffer to receive the read data + * + * Issue a read request over the AUX channel that will read from the RX + * device's DisplayPort Configuration data (DPCD) address space. The read + * message will be divided into multiple transactions which read a maximum of + * 16 bytes each. + * + * Return: 0 if read operation was successful, -ve on error + */ +static int aux_read(struct udevice *dev, u32 dpcd_address, u32 bytes_to_read, void *read_data) +{ + return aux_common(dev, DP_AUX_CMD_READ, dpcd_address, + bytes_to_read, (u8 *)read_data); +} + +static int dp_tx_wakeup(struct udevice *dev) +{ + u32 status; + u8 aux_data; + + aux_data = 0x1; + status = aux_write(dev, DP_DPCD_SET_POWER_DP_PWR_VOLTAGE, 1, &aux_data); + if (status) + debug("! 1st power wake-up - AUX write failed.\n"); + status = aux_write(dev, DP_DPCD_SET_POWER_DP_PWR_VOLTAGE, 1, &aux_data); + if (status) + debug("! 2nd power wake-up - AUX write failed.\n"); + + return status; +} + +/** + * enable_main_link() - Switch on main link for a device + * @dev: The DP device + */ +static void enable_main_link(struct udevice *dev, u8 enable) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + /* Reset the scrambler. */ + writel(1, dp_sub->base_addr + DP_FORCE_SCRAMBLER_RESET); + /* Enable the main stream. */ + writel(enable, dp_sub->base_addr + DP_ENABLE_MAIN_STREAM); +} + +/** + * get_rx_capabilities() - Check if capabilities of RX device are valid for TX + * device + * @dev: The DP device + * + * Return: 0 if the capabilities of the RX device are valid for the TX device, + * -ve if not, of an error occurred during capability determination + */ +static int get_rx_capabilities(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u8 rx_max_link_rate, rx_max_lane_count, *dpcd = NULL; + u32 status; + struct link_config *link_config = NULL; + + dpcd = dp_sub->dpcd_rx_caps; + link_config = &dp_sub->link_config; + + status = aux_read(dev, DP_DPCD_RECEIVER_CAP_FIELD_START, 16, dpcd); + if (status) + return status; + + rx_max_link_rate = dpcd[DP_DPCD_MAX_LINK_RATE]; + rx_max_lane_count = dpcd[DP_DPCD_MAX_LANE_COUNT] & DP_DPCD_MAX_LANE_COUNT_MASK; + link_config->max_link_rate = (rx_max_link_rate > DP_0_LINK_RATE) ? + DP_0_LINK_RATE : rx_max_link_rate; + link_config->max_lane_count = (rx_max_lane_count > DP_0_LANE_COUNT) ? + DP_0_LANE_COUNT : rx_max_lane_count; + link_config->support_enhanced_framing_mode = dpcd[DP_DPCD_MAX_LANE_COUNT] & + DP_DPCD_ENHANCED_FRAME_SUPPORT_MASK; + link_config->support_downspread_control = dpcd[DP_DPCD_MAX_DOWNSPREAD] & + DP_DPCD_MAX_DOWNSPREAD_MASK; + + return 0; +} + +/** + * set_enhanced_frame_mode() - Enable/Disable enhanced frame mode + * @dev: The DP device + * @enable: Flag to determine whether to enable (1) or disable (0) the enhanced + * frame mode + * + * Enable or disable the enhanced framing symbol sequence for + * both the DisplayPort TX core and the RX device. + * + * Return: 0 if enabling/disabling the enhanced frame mode was successful, -ve + * on error + */ +static int set_enhanced_frame_mode(struct udevice *dev, u8 enable) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 status; + u8 regval; + + dp_sub->link_config.enhanced_framing_mode = enable; + /* Write enhanced frame mode enable to the DisplayPort TX core. */ + writel(dp_sub->link_config.enhanced_framing_mode, + dp_sub->base_addr + DP_ENHANCED_FRAME_EN); + + /* Preserve the current RX device settings. */ + status = aux_read(dev, DP_DPCD_LANE_COUNT_SET, 0x1, ®val); + if (status) + return status; + + if (dp_sub->link_config.enhanced_framing_mode) + regval |= DP_DPCD_ENHANCED_FRAME_EN_MASK; + else + regval &= ~DP_DPCD_ENHANCED_FRAME_EN_MASK; + + /* Write enhanced frame mode enable to the RX device. */ + return aux_write(dev, DP_DPCD_LANE_COUNT_SET, 0x1, ®val); +} + +/** + * set_lane_count() - Set the lane count + * @dev: The DP device + * @lane_count: Lane count to set + * + * Set the number of lanes to be used by the main link for both + * the DisplayPort TX core and the RX device. + * + * Return: 0 if setting the lane count was successful, -ve on error + */ +static int set_lane_count(struct udevice *dev, u8 lane_count) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 status; + u8 regval; + + dp_sub->link_config.lane_count = lane_count; + /* Write the new lane count to the DisplayPort TX core. */ + writel(dp_sub->link_config.lane_count, + dp_sub->base_addr + DP_LANE_COUNT_SET); + + /* Preserve the current RX device settings. */ + status = aux_read(dev, DP_DPCD_LANE_COUNT_SET, 0x1, ®val); + if (status) + return status; + + regval &= ~DP_DPCD_LANE_COUNT_SET_MASK; + regval |= dp_sub->link_config.lane_count; + + /* Write the new lane count to the RX device. */ + return aux_write(dev, DP_DPCD_LANE_COUNT_SET, 0x1, ®val); +} + +/** + * set_clk_speed() - Set DP phy clock speed + * @dev: The DP device + * @speed: The clock frquency to set (one of PHY_CLOCK_SELECT_*) + * + * Set the clock frequency for the DisplayPort PHY corresponding to a desired + * data rate. + * + * Return: 0 if setting the DP phy clock speed was successful, -ve on error + */ +static int set_clk_speed(struct udevice *dev, u32 speed) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 regval; + + /* Disable the DisplayPort TX core first. */ + regval = readl(dp_sub->base_addr + DP_ENABLE); + writel(0, dp_sub->base_addr + DP_ENABLE); + + /* Change speed of the feedback clock. */ + writel(speed, dp_sub->base_addr + DP_PHY_CLOCK_SELECT); + + /* Re-enable the DisplayPort TX core if it was previously enabled. */ + if (regval) + writel(regval, dp_sub->base_addr + DP_ENABLE); + + /* Wait until the PHY is ready. */ + return wait_phy_ready(dev); +} + +/** + * set_link_rate() - Set the link rate + * @dev: The DP device + * @link_rate: The link rate to set (one of LINK_BW_SET_*) + * + * Set the data rate to be used by the main link for both the DisplayPort TX + * core and the RX device. + * + * Return: 0 if setting the link rate was successful, -ve on error + */ +static int set_link_rate(struct udevice *dev, u8 link_rate) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 status; + + /* Write a corresponding clock frequency to the DisplayPort TX core. */ + switch (link_rate) { + case DP_LINK_BW_SET_162GBPS: + status = set_clk_speed(dev, DP_PHY_CLOCK_SELECT_162GBPS); + break; + case DP_LINK_BW_SET_270GBPS: + status = set_clk_speed(dev, DP_PHY_CLOCK_SELECT_270GBPS); + break; + case DP_LINK_BW_SET_540GBPS: + status = set_clk_speed(dev, DP_PHY_CLOCK_SELECT_540GBPS); + break; + default: + status = -EINVAL; + break; + } + if (status) + return status; + + dp_sub->link_config.link_rate = link_rate; + /* Write new link rate to the DisplayPort TX core. */ + writel(dp_sub->link_config.link_rate, + dp_sub->base_addr + + DP_LINK_BW_SET); + + /* Write new link rate to the RX device. */ + return aux_write(dev, DP_DPCD_LINK_BW_SET, 0x1, + &dp_sub->link_config.link_rate); +} + +static int set_downspread(struct udevice *dev, u8 enable) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 status; + u8 regval; + + dp_sub->link_config.support_downspread_control = enable; + /* Write downspread enable to the DisplayPort TX core. */ + writel(dp_sub->link_config.support_downspread_control, + dp_sub->base_addr + DP_DOWNSPREAD_CTRL); + + /* Preserve the current RX device settings. */ + status = aux_read(dev, DP_DPCD_DOWNSPREAD_CTRL, 0x1, ®val); + if (status) + return status; + + if (dp_sub->link_config.support_downspread_control) + regval |= DP_DPCD_SPREAD_AMP_MASK; + else + regval &= ~DP_DPCD_SPREAD_AMP_MASK; + + /* Write downspread enable to the RX device. */ + return aux_write(dev, DP_DPCD_DOWNSPREAD_CTRL, 0x1, ®val); +} + +static void set_serdes_vswing_preemp(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u8 index; + u8 vs_level_rx = dp_sub->link_config.vs_level; + u8 pe_level_rx = dp_sub->link_config.pe_level; + + for (index = 0; index < dp_sub->link_config.lane_count; index++) { + /* Write new voltage swing levels to the TX registers. */ + writel(vs[pe_level_rx][vs_level_rx], (ulong)SERDES_BASEADDR + + SERDES_L0_TX_MARGININGF + index * SERDES_LANE_OFFSET); + /* Write new pre-emphasis levels to the TX registers. */ + writel(pe[pe_level_rx][vs_level_rx], (ulong)SERDES_BASEADDR + + SERDES_L0_TX_DEEMPHASIS + index * SERDES_LANE_OFFSET); + } +} + +/** + * set_vswing_preemp() - Build AUX data to set voltage swing and pre-emphasis + * @dev: The DP device + * @aux_data: Buffer to receive the built AUX data + * + * Build AUX data to set current voltage swing and pre-emphasis level settings; + * the necessary data is taken from the link_config structure. + */ +static void set_vswing_preemp(struct udevice *dev, u8 *aux_data) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u8 data = 0; + u8 vs_level_rx = dp_sub->link_config.vs_level; + u8 pe_level_rx = dp_sub->link_config.pe_level; + + if (vs_level_rx >= DP_MAXIMUM_VS_LEVEL) + data |= DP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK; + + /* The maximum pre-emphasis level has been reached. */ + if (pe_level_rx >= DP_MAXIMUM_PE_LEVEL) + data |= DP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK; + + /* Set up the data buffer for writing to the RX device. */ + data |= (pe_level_rx << DP_DPCD_TRAINING_LANEX_SET_PE_SHIFT) | + vs_level_rx; + memset(aux_data, data, 4); + + set_serdes_vswing_preemp(dev); +} + +static int set_training_pattern(struct udevice *dev, u32 pattern) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u8 aux_data[5]; + + writel(pattern, dp_sub->base_addr + TRAINING_PATTERN_SET); + + aux_data[0] = pattern; + switch (pattern) { + case TRAINING_PATTERN_SET_OFF: + writel(0, dp_sub->base_addr + SCRAMBLING_DISABLE); + dp_sub->link_config.scrambler_en = 1; + break; + case TRAINING_PATTERN_SET_TP1: + case TRAINING_PATTERN_SET_TP2: + case TRAINING_PATTERN_SET_TP3: + aux_data[0] |= DP_DPCD_TP_SET_SCRAMB_DIS_MASK; + writel(1, dp_sub->base_addr + SCRAMBLING_DISABLE); + dp_sub->link_config.scrambler_en = 0; + break; + default: + break; + } + /* + * Make the adjustments to both the DisplayPort TX core and the RX + * device. + */ + set_vswing_preemp(dev, &aux_data[1]); + /* + * Write the voltage swing and pre-emphasis levels for each lane to the + * RX device. + */ + if (pattern == TRAINING_PATTERN_SET_OFF) + return aux_write(dev, DP_DPCD_TP_SET, 1, aux_data); + else + return aux_write(dev, DP_DPCD_TP_SET, 5, aux_data); +} + +static int get_lane_status_adj_reqs(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 status; + u8 aux_data[8]; + + status = aux_read(dev, DP_DPCD_SINK_COUNT, 8, aux_data); + if (status) + return status; + + /* Save XDPPSU_DPCD_SINK_COUNT contents. */ + dp_sub->sink_count = + ((aux_data[0] & DP_DPCD_SINK_COUNT_HIGH_MASK) >> + DP_DPCD_SINK_COUNT_HIGH_LOW_SHIFT) | + (aux_data[0] & DP_DPCD_SINK_COUNT_LOW_MASK); + memcpy(dp_sub->lane_status_ajd_reqs, &aux_data[2], 6); + return 0; +} + +/** + * check_clock_recovery() - Check clock recovery success + * @dev: The LogiCore DP TX device in question + * @lane_count: The number of lanes for which to check clock recovery success + * + * Check if the RX device's DisplayPort Configuration data (DPCD) indicates + * that the clock recovery sequence during link training was successful - the + * RX device's link clock and data recovery unit has realized and maintained + * the frequency lock for all lanes currently in use. + * + * Return: 0 if clock recovery was successful on all lanes in question, -ve if + * not + */ +static int check_clock_recovery(struct udevice *dev, u8 lane_count) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u8 *lane_status = dp_sub->lane_status_ajd_reqs; + + switch (lane_count) { + case DP_LANE_COUNT_SET_2: + if (!(lane_status[0] & DP_DPCD_STATUS_LANE_1_CR_DONE_MASK)) + return -EINVAL; + case DP_LANE_COUNT_SET_1: + if (!(lane_status[0] & DP_DPCD_STATUS_LANE_0_CR_DONE_MASK)) + return -EINVAL; + default: + /* All (LaneCount) lanes have achieved clock recovery. */ + break; + } + return 0; +} + +/** + * adj_vswing_preemp() - Adjust voltage swing and pre-emphasis + * @dev: The DP device + * + * Set new voltage swing and pre-emphasis levels using the + * adjustment requests obtained from the RX device. + * + * Return: 0 if voltage swing and pre-emphasis could be adjusted successfully, + * -ve on error + */ +static int adj_vswing_preemp(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u8 index, vs_level_adj_req[4], pe_level_adj_req[4]; + u8 aux_data[4]; + u8 *adj_reqs = &dp_sub->lane_status_ajd_reqs[4]; + + /* + * Analyze the adjustment requests for changes in voltage swing and + * pre-emphasis levels. + */ + vs_level_adj_req[0] = adj_reqs[0] & DP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK; + vs_level_adj_req[1] = (adj_reqs[0] & DP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK) >> + DP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT; + pe_level_adj_req[0] = (adj_reqs[0] & DP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK) >> + DP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT; + pe_level_adj_req[1] = (adj_reqs[0] & DP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK) >> + DP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT; + + /* + * Change the drive settings to match the adjustment requests. Use the + * greatest level requested. + */ + dp_sub->link_config.vs_level = 0; + dp_sub->link_config.pe_level = 0; + for (index = 0; index < dp_sub->link_config.lane_count; index++) { + if (vs_level_adj_req[index] > dp_sub->link_config.vs_level) + dp_sub->link_config.vs_level = vs_level_adj_req[index]; + + if (pe_level_adj_req[index] > dp_sub->link_config.pe_level) + dp_sub->link_config.pe_level = pe_level_adj_req[index]; + } + + if (dp_sub->link_config.pe_level > DP_MAXIMUM_PE_LEVEL) + dp_sub->link_config.pe_level = DP_MAXIMUM_PE_LEVEL; + + if (dp_sub->link_config.vs_level > DP_MAXIMUM_VS_LEVEL) + dp_sub->link_config.vs_level = DP_MAXIMUM_VS_LEVEL; + + if (dp_sub->link_config.pe_level > + (4 - dp_sub->link_config.vs_level)) { + dp_sub->link_config.pe_level = + 4 - dp_sub->link_config.vs_level; + } + /* + * Make the adjustments to both the DisplayPort TX core and the RX + * device. + */ + set_vswing_preemp(dev, aux_data); + /* + * Write the voltage swing and pre-emphasis levels for each lane to the + * RX device. + */ + return aux_write(dev, DP_DPCD_TRAINING_LANE0_SET, 2, aux_data); +} + +/** + * get_training_delay() - Get training delay + * @dev: The DP device + * @training_state: The training state for which the required training delay + * should be queried + * + * Determine what the RX device's required training delay is for + * link training. + * + * Return: The training delay in us + */ +static u32 get_training_delay(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u8 *dpcd = dp_sub->dpcd_rx_caps; + + if (dpcd[DP_DPCD_TRAIN_AUX_RD_INTERVAL]) + return 400 * dpcd[DP_DPCD_TRAIN_AUX_RD_INTERVAL] * 10; + + return 400; +} + +/** + * training_state_clock_recovery() - Run clock recovery part of link training + * @dev: The DP device + * + * Run the clock recovery sequence as part of link training. The + * sequence is as follows: + * + * 0) Start signaling at the minimum voltage swing, pre-emphasis, and + * post- cursor levels. + * 1) Transmit training pattern 1 over the main link with symbol + * scrambling disabled. + * 2) The clock recovery loop. If clock recovery is unsuccessful after + * MaxIterations loop iterations, return. + * 2a) Wait for at least the period of time specified in the RX device's + * DisplayPort Configuration data (DPCD) register, + * TRAINING_AUX_RD_INTERVAL. + * 2b) Check if all lanes have achieved clock recovery lock. If so, + * return. + * 2c) Check if the same voltage swing level has been used 5 consecutive + * times or if the maximum level has been reached. If so, return. + * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as + * requested by the RX device. + * 2e) Loop back to 2a. + * + * For a more detailed description of the clock recovery sequence, see section + * 3.5.1.2.1 of the DisplayPort 1.2a specification document. + * + * Return: The next state machine state to advance to + */ +static enum link_training_states training_state_clock_recovery(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 status, delay_us; + u8 prev_vs_level = 0, same_vs_level_count = 0; + struct link_config *link_config = &dp_sub->link_config; + + delay_us = get_training_delay(dev); + /* Start CRLock. */ + /* Start from minimal voltage swing and pre-emphasis levels. */ + dp_sub->link_config.vs_level = 0; + dp_sub->link_config.pe_level = 0; + /* Transmit training pattern 1. */ + status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP1); + if (status) + return TS_FAILURE; + + while (1) { + /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */ + udelay(delay_us); + /* Get lane and adjustment requests. */ + status = get_lane_status_adj_reqs(dev); + if (status) + /* The AUX read failed. */ + return TS_FAILURE; + + /* + * Check if all lanes have realized and maintained the frequency + * lock and get adjustment requests. + */ + status = check_clock_recovery(dev, dp_sub->link_config.lane_count); + if (status == 0) + return TS_CHANNEL_EQUALIZATION; + /* + * Check if the same voltage swing for each lane has been used 5 + * consecutive times. + */ + if (prev_vs_level == link_config->vs_level) { + same_vs_level_count++; + } else { + same_vs_level_count = 0; + prev_vs_level = link_config->vs_level; + } + if (same_vs_level_count >= 5) + break; + + /* Only try maximum voltage swing once. */ + if (link_config->vs_level == DP_MAXIMUM_VS_LEVEL) + break; + + /* Adjust the drive settings as requested by the RX device. */ + status = adj_vswing_preemp(dev); + if (status) + /* The AUX write failed. */ + return TS_FAILURE; + } + return TS_ADJUST_LINK_RATE; +} + +/** + * check_channel_equalization() - Check channel equalization success + * @dev: The DP device + * @lane_count: The number of lanes for which to check channel equalization + * success + * + * Check if the RX device's DisplayPort Configuration data (DPCD) indicates + * that the channel equalization sequence during link training was successful - + * the RX device has achieved channel equalization, symbol lock, and interlane + * alignment for all lanes currently in use. + * + * Return: 0 if channel equalization was successful on all lanes in question, + * -ve if not + */ +static int check_channel_equalization(struct udevice *dev, u8 lane_count) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u8 *lane_status = dp_sub->lane_status_ajd_reqs; + + /* Check that all LANEx_CHANNEL_EQ_DONE bits are set. */ + switch (lane_count) { + case DP_LANE_COUNT_SET_2: + if (!(lane_status[0] & DP_DPCD_STATUS_LANE_1_CE_DONE_MASK)) + return -EINVAL; + case DP_LANE_COUNT_SET_1: + if (!(lane_status[0] & DP_DPCD_STATUS_LANE_0_CE_DONE_MASK)) + return -EINVAL; + default: + /* All (LaneCount) lanes have achieved channel equalization. */ + break; + } + + /* Check that all LANEx_SYMBOL_LOCKED bits are set. */ + switch (lane_count) { + case DP_LANE_COUNT_SET_2: + if (!(lane_status[0] & DP_DPCD_STATUS_LANE_1_SL_DONE_MASK)) + return -EINVAL; + case DP_LANE_COUNT_SET_1: + if (!(lane_status[0] & DP_DPCD_STATUS_LANE_0_SL_DONE_MASK)) + return -EINVAL; + default: + /* All (LaneCount) lanes have achieved symbol lock. */ + break; + } + + /* Check that interlane alignment is done. */ + if (!(lane_status[2] & DP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK)) + return -EINVAL; + return 0; +} + +/** + * training_state_channel_equalization() - Run channel equalization part of + * link training + * @dev: The DP device + * + * Run the channel equalization sequence as part of link + * training. The sequence is as follows: + * + * 0) Start signaling with the same drive settings used at the end of the + * clock recovery sequence. + * 1) Transmit training pattern 2 (or 3) over the main link with symbol + * scrambling disabled. + * 2) The channel equalization loop. If channel equalization is + * unsuccessful after 5 loop iterations, return. + * 2a) Wait for at least the period of time specified in the RX device's + * DisplayPort Configuration data (DPCD) register, + * TRAINING_AUX_RD_INTERVAL. + * 2b) Check if all lanes have achieved channel equalization, symbol lock, + * and interlane alignment. If so, return. + * 2c) Check if the same voltage swing level has been used 5 consecutive + * times or if the maximum level has been reached. If so, return. + * 2d) Adjust the voltage swing, pre-emphasis, and post-cursor levels as + * requested by the RX device. + * 2e) Loop back to 2a. + * + * For a more detailed description of the channel equalization sequence, see + * section 3.5.1.2.2 of the DisplayPort 1.2a specification document. + * + * Return: The next state machine state to advance to + */ +static enum link_training_states training_state_channel_equalization(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 status, delay_us = 400, iteration_count = 0; + + /* Write the current drive settings. */ + /* Transmit training pattern 2/3. */ + if (dp_sub->dpcd_rx_caps[DP_DPCD_MAX_LANE_COUNT] & + DP_DPCD_TPS3_SUPPORT_MASK) + status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP3); + else + status = set_training_pattern(dev, TRAINING_PATTERN_SET_TP2); + + if (status) + return TS_FAILURE; + + while (iteration_count < 5) { + /* Wait delay specified in TRAINING_AUX_RD_INTERVAL. */ + udelay(delay_us); + + /* Get lane and adjustment requests. */ + status = get_lane_status_adj_reqs(dev); + if (status) + /* The AUX read failed. */ + return TS_FAILURE; + + /* Adjust the drive settings as requested by the RX device. */ + status = adj_vswing_preemp(dev); + if (status) + /* The AUX write failed. */ + return TS_FAILURE; + + /* Check that all lanes still have their clocks locked. */ + status = check_clock_recovery(dev, dp_sub->link_config.lane_count); + if (status) + break; + /* + * Check that all lanes have accomplished channel + * equalization, symbol lock, and interlane alignment. + */ + status = check_channel_equalization(dev, dp_sub->link_config.lane_count); + if (status == 0) + return TS_SUCCESS; + iteration_count++; + } + + /* + * Tried 5 times with no success. Try a reduced bitrate first, then + * reduce the number of lanes. + */ + return TS_ADJUST_LINK_RATE; +} + +static int check_lane_align(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u8 *lane_status = dp_sub->lane_status_ajd_reqs; + + if (!(lane_status[2] & DP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK)) + return -EINVAL; + return 0; +} + +/** + * check_link_status() - Check status of link + * @dev: The DP device + * @lane_count: The lane count to use for the check + * + * Check if the receiver's DisplayPort Configuration data (DPCD) indicates the + * receiver has achieved and maintained clock recovery, channel equalization, + * symbol lock, and interlane alignment for all lanes currently in use. + * + * Return: 0 if the link status is OK, -ve if a error occurred during checking + */ +static int check_link_status(struct udevice *dev, u8 lane_count) +{ + u32 status; + + status = get_lane_status_adj_reqs(dev); + if (status) + /* The AUX read failed. */ + return status; + + /* Check if the link needs training. */ + if ((check_clock_recovery(dev, lane_count) == 0) && + (check_channel_equalization(dev, lane_count) == 0) && + (check_lane_align(dev) == 0)) { + return 0; + } + return -EINVAL; +} + +/** + * run_training() - Run link training + * @dev: The DP device + * + * Run the link training process. It is implemented as a state machine, with + * each state returning the next state. First, the clock recovery sequence will + * be run; if successful, the channel equalization sequence will run. If either + * the clock recovery or channel equalization sequence failed, the link rate or + * the number of lanes used will be reduced and training will be re-attempted. + * If training fails at the minimal data rate, 1.62 Gbps with a single lane, + * training will no longer re-attempt and fail. + * + * There are undocumented timeout constraints in the link training process. In + * DP v1.2a spec, Chapter 3.5.1.2.2 a 10ms limit for the complete training + * process is mentioned. Which individual timeouts are derived and implemented + * by sink manufacturers is unknown. So each step should be as short as + * possible and link training should start as soon as possible after HPD. + * + * Return: 0 if the training sequence ran successfully, -ve if a error occurred + * or the training failed + */ +static int run_training(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 status; + enum link_training_states training_state = TS_CLOCK_RECOVERY; + + while (1) { + switch (training_state) { + case TS_CLOCK_RECOVERY: + training_state = training_state_clock_recovery(dev); + break; + case TS_CHANNEL_EQUALIZATION: + training_state = training_state_channel_equalization(dev); + break; + default: + break; + } + + if (training_state == TS_SUCCESS) + break; + else if (training_state == TS_FAILURE) + return -EINVAL; + + if (training_state == TS_ADJUST_LANE_COUNT || + training_state == TS_ADJUST_LINK_RATE) { + status = set_training_pattern(dev, TRAINING_PATTERN_SET_OFF); + if (status) + return -EINVAL; + } + } + + /* Final status check. */ + return check_link_status(dev, dp_sub->link_config.lane_count); +} + +void reset_dp_phy(struct udevice *dev, u32 reset) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 phyval, regval; + + writel(0, dp_sub->base_addr + DP_ENABLE); + phyval = readl(dp_sub->base_addr + DP_PHY_CONFIG); + regval = phyval | reset; + writel(regval, dp_sub->base_addr + DP_PHY_CONFIG); + /* Remove the reset. */ + writel(phyval, dp_sub->base_addr + DP_PHY_CONFIG); + /* Wait for the PHY to be ready. */ + wait_phy_ready(dev); + + writel(1, dp_sub->base_addr + DP_ENABLE); +} + +/** + * establish_link() - Establish a link + * @dev: The DP device + * + * Check if the link needs training and run the training sequence if training + * is required. + * + * Return: 0 if the link was established successfully, -ve on error + */ +static int establish_link(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 status, re_enable_main_link; + + reset_dp_phy(dev, DP_PHY_CONFIG_TX_PHY_8B10BEN_MASK | + DP_PHY_CONFIG_PHY_RESET_MASK); + + re_enable_main_link = readl(dp_sub->base_addr + DP_ENABLE_MAIN_STREAM); + if (re_enable_main_link) + enable_main_link(dev, 0); + + status = run_training(dev); + if (status) + return status; + + status = set_training_pattern(dev, TRAINING_PATTERN_SET_OFF); + if (status) + return status; + + if (re_enable_main_link) + enable_main_link(dev, 1); + + return check_link_status(dev, dp_sub->link_config.lane_count); +} + +static int dp_hpd_train(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + struct link_config *link_config = &dp_sub->link_config; + u32 status; + + status = get_rx_capabilities(dev); + if (status) { + debug("! Error getting RX caps.\n"); + return status; + } + + status = set_enhanced_frame_mode(dev, link_config->support_enhanced_framing_mode ? 1 : 0); + if (status) { + debug("! EFM set failed.\n"); + return status; + } + + status = set_lane_count(dev, (dp_sub->use_max_lane_count) ? + link_config->max_lane_count : dp_sub->lane_count); + if (status) { + debug("! Lane count set failed.\n"); + return status; + } + + status = set_link_rate(dev, (dp_sub->use_max_link_rate) ? + link_config->max_link_rate : dp_sub->link_rate); + if (status) { + debug("! Link rate set failed.\n"); + return status; + } + + status = set_downspread(dev, link_config->support_downspread_control); + if (status) { + debug("! Setting downspread failed.\n"); + return status; + } + + debug("Lane count =%d\n", dp_sub->link_config.lane_count); + debug("Link rate =%d\n", dp_sub->link_config.link_rate); + + debug("Starting Training...\n"); + status = establish_link(dev); + if (status == 0) + debug("! Training succeeded.\n"); + else + debug("! Training failed.\n"); + + return status; +} + +static void display_gfx_frame_buffer(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + if (!dp_sub->dp_dma->gfx.channel.cur) + dp_sub->dp_dma->gfx.trigger_status = DPDMA_TRIGGER_EN; +} + +static void set_color_encode(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + struct main_stream_attributes *msa_config = &dp_sub->msa_config; + + msa_config->y_cb_cr_colorimetry = 0; + msa_config->dynamic_range = 0; + msa_config->component_format = 0; + msa_config->misc0 = 0; + msa_config->misc1 = 0; + msa_config->component_format = DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_RGB; +} + +static void config_msa_recalculate(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + u32 video_bw, link_bw, words_per_line; + u8 bits_per_pixel; + struct main_stream_attributes *msa_config; + struct link_config *link_config; + + msa_config = &dp_sub->msa_config; + link_config = &dp_sub->link_config; + + msa_config->user_pixel_width = 1; + + /* Compute the rest of the MSA values. */ + msa_config->n_vid = 27 * 1000 * link_config->link_rate; + msa_config->h_start = msa_config->vid_timing_mode.video_timing.h_sync_width + + msa_config->vid_timing_mode.video_timing.h_back_porch; + msa_config->v_start = msa_config->vid_timing_mode.video_timing.f0_pv_sync_width + + msa_config->vid_timing_mode.video_timing.f0_pv_back_porch; + + /* Miscellaneous attributes. */ + if (msa_config->bits_per_color == 6) + msa_config->misc0 = DP_MAIN_STREAM_MISC0_BDC_6BPC; + else if (msa_config->bits_per_color == 8) + msa_config->misc0 = DP_MAIN_STREAM_MISC0_BDC_8BPC; + else if (msa_config->bits_per_color == 10) + msa_config->misc0 = DP_MAIN_STREAM_MISC0_BDC_10BPC; + else if (msa_config->bits_per_color == 12) + msa_config->misc0 = DP_MAIN_STREAM_MISC0_BDC_12BPC; + else if (msa_config->bits_per_color == 16) + msa_config->misc0 = DP_MAIN_STREAM_MISC0_BDC_16BPC; + + msa_config->misc0 <<= DP_MAIN_STREAM_MISC0_BDC_SHIFT; + + /* Need to set this. */ + msa_config->misc0 |= msa_config->component_format << + DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT; + + msa_config->misc0 |= msa_config->dynamic_range << + DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE_SHIFT; + + msa_config->misc0 |= msa_config->y_cb_cr_colorimetry << + DP_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_SHIFT; + + msa_config->misc0 |= msa_config->synchronous_clock_mode; + /* + * Determine the number of bits per pixel for the specified color + * component format. + */ + if (msa_config->misc1 == DP_MAIN_STREAM_MISC1_Y_ONLY_EN_MASK) + bits_per_pixel = msa_config->bits_per_color; + else if (msa_config->component_format == + DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_YCBCR422) + /* YCbCr422 color component format. */ + bits_per_pixel = msa_config->bits_per_color * 2; + else + /* RGB or YCbCr 4:4:4 color component format. */ + bits_per_pixel = msa_config->bits_per_color * 3; + + /* Calculate the data per lane. */ + words_per_line = msa_config->vid_timing_mode.video_timing.h_active * bits_per_pixel; + if (words_per_line % 16) + words_per_line += 16; + + words_per_line /= 16; + msa_config->data_per_lane = words_per_line - link_config->lane_count; + if (words_per_line % link_config->lane_count) + msa_config->data_per_lane += (words_per_line % link_config->lane_count); + + /* Allocate a fixed size for single-stream transport (SST) operation. */ + msa_config->transfer_unit_size = 64; + + /* + * Calculate the average number of bytes per transfer unit. + * Note: Both the integer and the fractional part is stored in + * AvgBytesPerTU. + */ + video_bw = ((msa_config->pixel_clock_hz / 1000) * bits_per_pixel) / 8; + link_bw = (link_config->lane_count * link_config->link_rate * 27); + msa_config->avg_bytes_per_tu = ((10 * + (video_bw * msa_config->transfer_unit_size) + / link_bw) + 5) / 10; + /* + * The number of initial wait cycles at the start of a new line by the + * framing logic. This allows enough data to be buffered in the input + * FIFO before video is sent. + */ + if ((msa_config->avg_bytes_per_tu / 1000) <= 4) + msa_config->init_wait = 64; + else + msa_config->init_wait = msa_config->transfer_unit_size - + (msa_config->avg_bytes_per_tu / 1000); +} + +static void set_msa_bpc(struct udevice *dev, u8 bits_per_color) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + dp_sub->msa_config.bits_per_color = bits_per_color; + /* Calculate the rest of the MSA values. */ + config_msa_recalculate(dev); +} + +const struct video_timing_mode *get_video_mode_data(enum video_mode vm_id) +{ + if (vm_id < VIDC_VM_NUM_SUPPORTED) + return &vidc_video_timing_modes[vm_id]; + + return NULL; +} + +static u64 get_pixelclk_by_vmid(enum video_mode vm_id) +{ + const struct video_timing_mode *vm; + u64 clk_hz; + + vm = get_video_mode_data(vm_id); + /* For progressive mode, use only frame 0 vertical total. */ + clk_hz = vm->video_timing.f0_pv_total; + /* Multiply the number of pixels by the frame rate. */ + clk_hz *= vm->frame_rate; + + /* + * Multiply the vertical total by the horizontal total for number of + * pixels. + */ + clk_hz *= vm->video_timing.h_total; + + return clk_hz; +} + +/** + * config_msa_video_mode() - Enable video output + * @dev: The DP device + * @msa: The MSA values to set for the device + * + * Return: 0 if the video was enabled successfully, -ve on error + */ +static void config_msa_video_mode(struct udevice *dev, enum video_mode videomode) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + struct main_stream_attributes *msa_config; + + msa_config = &dp_sub->msa_config; + + /* Configure the MSA values from the display monitor DMT table. */ + msa_config->vid_timing_mode.vid_mode = vidc_video_timing_modes[videomode].vid_mode; + msa_config->vid_timing_mode.frame_rate = vidc_video_timing_modes[videomode].frame_rate; + msa_config->vid_timing_mode.video_timing.h_active = + vidc_video_timing_modes[videomode].video_timing.h_active; + msa_config->vid_timing_mode.video_timing.h_front_porch = + vidc_video_timing_modes[videomode].video_timing.h_front_porch; + msa_config->vid_timing_mode.video_timing.h_sync_width = + vidc_video_timing_modes[videomode].video_timing.h_sync_width; + msa_config->vid_timing_mode.video_timing.h_back_porch = + vidc_video_timing_modes[videomode].video_timing.h_back_porch; + msa_config->vid_timing_mode.video_timing.h_total = + vidc_video_timing_modes[videomode].video_timing.h_total; + msa_config->vid_timing_mode.video_timing.h_sync_polarity = + vidc_video_timing_modes[videomode].video_timing.h_sync_polarity; + msa_config->vid_timing_mode.video_timing.v_active = + vidc_video_timing_modes[videomode].video_timing.v_active; + msa_config->vid_timing_mode.video_timing.f0_pv_front_porch = + vidc_video_timing_modes[videomode].video_timing.f0_pv_front_porch; + msa_config->vid_timing_mode.video_timing.f0_pv_sync_width = + vidc_video_timing_modes[videomode].video_timing.f0_pv_sync_width; + msa_config->vid_timing_mode.video_timing.f0_pv_back_porch = + vidc_video_timing_modes[videomode].video_timing.f0_pv_back_porch; + msa_config->vid_timing_mode.video_timing.f0_pv_total = + vidc_video_timing_modes[videomode].video_timing.f0_pv_total; + msa_config->vid_timing_mode.video_timing.f1_v_front_porch = + vidc_video_timing_modes[videomode].video_timing.f1_v_front_porch; + msa_config->vid_timing_mode.video_timing.f1_v_sync_width = + vidc_video_timing_modes[videomode].video_timing.f1_v_sync_width; + msa_config->vid_timing_mode.video_timing.f1_v_back_porch = + vidc_video_timing_modes[videomode].video_timing.f1_v_back_porch; + msa_config->vid_timing_mode.video_timing.f1_v_total = + vidc_video_timing_modes[videomode].video_timing.f1_v_total; + msa_config->vid_timing_mode.video_timing.v_sync_polarity = + vidc_video_timing_modes[videomode].video_timing.v_sync_polarity; + msa_config->pixel_clock_hz = get_pixelclk_by_vmid(msa_config->vid_timing_mode.vid_mode); + + /* Calculate the rest of the MSA values. */ + config_msa_recalculate(dev); +} + +static void set_pixel_clock(u64 freq_hz) +{ + u64 ext_divider, vco, vco_int_frac; + u32 pll_assigned, frac_int_fb_div, fraction, regpll = 0; + u8 pll; + + pll_assigned = readl(CLK_FPD_BASEADDR + VIDEO_REF_CTRL) & VIDEO_REF_CTRL_SRCSEL_MASK; + if (pll_assigned) + pll = VPLL; + + ext_divider = PLL_OUT_FREQ / freq_hz; + vco = freq_hz * ext_divider * 2; + vco_int_frac = (vco * INPUT_FREQ_PRECISION * SHIFT_DECIMAL) / + AVBUF_INPUT_REF_CLK; + frac_int_fb_div = vco_int_frac >> PRECISION; + fraction = vco_int_frac & AVBUF_DECIMAL; + + regpll |= ENABLE_BIT << PLL_CTRL_BYPASS_SHIFT; + regpll |= frac_int_fb_div << PLL_CTRL_FBDIV_SHIFT; + regpll |= (1 << PLL_CTRL_DIV2_SHIFT); + regpll |= (PSS_REF_CLK << PLL_CTRL_PRE_SRC_SHIFT); + writel(regpll, CLK_FPD_BASEADDR + VPLL_CTRL); + + regpll = 0; + regpll |= VPLL_CFG_CP << PLL_CFG_CP_SHIFT; + regpll |= VPLL_CFG_RES << PLL_CFG_RES_SHIFT; + regpll |= VPLL_CFG_LFHF << PLL_CFG_LFHF_SHIFT; + regpll |= VPLL_CFG_LOCK_DLY << PLL_CFG_LOCK_DLY_SHIFT; + regpll |= VPLL_CFG_LOCK_CNT << PLL_CFG_LOCK_CNT_SHIFT; + writel(regpll, CLK_FPD_BASEADDR + VPLL_CFG); + + regpll = (1U << PLL_FRAC_CFG_ENABLED_SHIFT) | + (fraction << PLL_FRAC_CFG_DATA_SHIFT); + writel(regpll, CLK_FPD_BASEADDR + VPLL_FRAC_CFG); + + clrsetbits_le32(CLK_FPD_BASEADDR + VPLL_CTRL, + PLL_CTRL_RESET_MASK, + (ENABLE_BIT << PLL_CTRL_RESET_SHIFT)); + + /* Deassert reset to the PLL. */ + clrsetbits_le32(CLK_FPD_BASEADDR + VPLL_CTRL, + PLL_CTRL_RESET_MASK, + (DISABLE_BIT << PLL_CTRL_RESET_SHIFT)); + + while (!(readl(CLK_FPD_BASEADDR + PLL_STATUS) & + (1 << PLL_STATUS_VPLL_LOCK))) + ; + + /* Deassert Bypass. */ + clrsetbits_le32(CLK_FPD_BASEADDR + VPLL_CTRL, + PLL_CTRL_BYPASS_MASK, + (DISABLE_BIT << PLL_CTRL_BYPASS_SHIFT)); + udelay(1); + + clrsetbits_le32(CLK_FPD_BASEADDR + VIDEO_REF_CTRL, + VIDEO_REF_CTRL_CLKACT_MASK, + (DISABLE_BIT << VIDEO_REF_CTRL_CLKACT_SHIFT)); + + clrsetbits_le32(CLK_FPD_BASEADDR + VIDEO_REF_CTRL, + VIDEO_REF_CTRL_DIVISOR1_MASK, + (ENABLE_BIT << VIDEO_REF_CTRL_DIVISOR1_SHIFT)); + + clrsetbits_le32(CLK_FPD_BASEADDR + VIDEO_REF_CTRL, + VIDEO_REF_CTRL_DIVISOR0_MASK, + (ext_divider << VIDEO_REF_CTRL_DIVISOR0_SHIFT)); + + clrsetbits_le32(CLK_FPD_BASEADDR + VIDEO_REF_CTRL, + VIDEO_REF_CTRL_CLKACT_MASK, + (ENABLE_BIT << VIDEO_REF_CTRL_CLKACT_SHIFT)); +} + +/** + * set_msa_values() - Set MSA values + * @dev: The DP device + * + * Set the main stream attributes registers of the DisplayPort TX + * core with the values specified in the main stream attributes configuration + * structure. + */ +static void set_msa_values(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + struct main_stream_attributes *msa_config; + + msa_config = &dp_sub->msa_config; + + /* + * Set the main stream attributes to the associated DisplayPort TX core + * registers. + */ + writel(msa_config->vid_timing_mode.video_timing.h_total, + dp_sub->base_addr + DP_MAIN_STREAM_HTOTAL); + writel(msa_config->vid_timing_mode.video_timing.f0_pv_total, + dp_sub->base_addr + DP_MAIN_STREAM_VTOTAL); + writel(msa_config->vid_timing_mode.video_timing.h_sync_polarity | + (msa_config->vid_timing_mode.video_timing.v_sync_polarity + << DP_MAIN_STREAM_POLARITY_VSYNC_POL_SHIFT), + dp_sub->base_addr + DP_MAIN_STREAM_POLARITY); + writel(msa_config->vid_timing_mode.video_timing.h_sync_width, + dp_sub->base_addr + DP_MAIN_STREAM_HSWIDTH); + writel(msa_config->vid_timing_mode.video_timing.f0_pv_sync_width, + dp_sub->base_addr + DP_MAIN_STREAM_VSWIDTH); + writel(msa_config->vid_timing_mode.video_timing.h_active, + dp_sub->base_addr + DP_MAIN_STREAM_HRES); + writel(msa_config->vid_timing_mode.video_timing.v_active, + dp_sub->base_addr + DP_MAIN_STREAM_VRES); + writel(msa_config->h_start, dp_sub->base_addr + DP_MAIN_STREAM_HSTART); + writel(msa_config->v_start, dp_sub->base_addr + DP_MAIN_STREAM_VSTART); + writel(msa_config->misc0, dp_sub->base_addr + DP_MAIN_STREAM_MISC0); + writel(msa_config->misc1, dp_sub->base_addr + DP_MAIN_STREAM_MISC1); + writel(msa_config->pixel_clock_hz / 1000, dp_sub->base_addr + DP_M_VID); + writel(msa_config->n_vid, dp_sub->base_addr + DP_N_VID); + writel(msa_config->user_pixel_width, dp_sub->base_addr + DP_USER_PIXEL_WIDTH); + writel(msa_config->data_per_lane, dp_sub->base_addr + DP_USER_DATA_COUNT_PER_LANE); + /* + * Set the transfer unit values to the associated DisplayPort TX core + * registers. + */ + writel(msa_config->transfer_unit_size, dp_sub->base_addr + DP_TU_SIZE); + writel(msa_config->avg_bytes_per_tu / 1000, + dp_sub->base_addr + DP_MIN_BYTES_PER_TU); + writel((msa_config->avg_bytes_per_tu % 1000) * 1000, + dp_sub->base_addr + DP_FRAC_BYTES_PER_TU); + writel(msa_config->init_wait, dp_sub->base_addr + DP_INIT_WAIT); +} + +static void setup_video_stream(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + struct main_stream_attributes *msa_config = &dp_sub->msa_config; + + set_color_encode(dev); + set_msa_bpc(dev, dp_sub->bpc); + config_msa_video_mode(dev, dp_sub->video_mode); + + /* Set pixel clock. */ + dp_sub->pix_clk = msa_config->pixel_clock_hz; + set_pixel_clock(dp_sub->pix_clk); + + /* Reset the transmitter. */ + writel(1, dp_sub->base_addr + DP_SOFT_RESET); + udelay(10); + writel(0, dp_sub->base_addr + DP_SOFT_RESET); + + set_msa_values(dev); + + /* Issuing a soft-reset (AV_BUF_SRST_REG). */ + writel(3, dp_sub->base_addr + AVBUF_BUF_SRST_REG); // Assert reset. + udelay(10); + writel(0, dp_sub->base_addr + AVBUF_BUF_SRST_REG); // De-ssert reset. + + enable_main_link(dev, 1); + + debug("DONE!\n"); +} + +static int dp_tx_start_link_training(struct udevice *dev) +{ + u32 status; + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + enable_main_link(dev, 0); + + if (!is_dp_connected(dev)) { + debug("! Disconnected.\n"); + return -ENODEV; + } + + status = dp_tx_wakeup(dev); + if (status) { + debug("! Wakeup failed.\n"); + return -EIO; + } + + do { + mdelay(100); + status = dp_hpd_train(dev); + if (status == -EINVAL) { + debug("Lost connection\n\r"); + return -EIO; + } else if (status) { + continue; + } + display_gfx_frame_buffer(dev); + setup_video_stream(dev); + status = check_link_status(dev, dp_sub->link_config.lane_count); + if (status == -EINVAL) + return -EIO; + } while (status != 0); + + return 0; +} + +static void init_run_config(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + dp_sub->dp_dma = &dp_dma; + dp_sub->video_mode = VIDC_VM_1024x768_60_P; + dp_sub->bpc = VIDC_BPC_8; + dp_sub->color_encode = DP_CENC_RGB; + dp_sub->use_max_cfg_caps = 1; + dp_sub->lane_count = LANE_COUNT_1; + dp_sub->link_rate = LINK_RATE_540GBPS; + dp_sub->en_sync_clk_mode = 0; + dp_sub->use_max_lane_count = 1; + dp_sub->use_max_link_rate = 1; +} + +static int dpdma_setup(struct udevice *dev) +{ + int status; + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + writel(DPDMA_ISR_VSYNC_INT_MASK, dp_sub->dp_dma->base_addr + DPDMA_IEN); + status = wait_for_bit_le32((u32 *)dp_sub->dp_dma->base_addr + DPDMA_ISR, + DPDMA_ISR_VSYNC_INT_MASK, false, 1000, false); + if (status) { + debug("%s: INTR TIMEDOUT\n", __func__); + return status; + } + debug("INTR dma_vsync_intr_handler called...\n"); + dma_vsync_intr_handler(dev); + + return 0; +} + +static int zynqmp_dpsub_init(struct udevice *dev) +{ + int status; + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + /* Initialize the dpdma configuration */ + status = init_dpdma_subsys(dev); + if (status) + return -EINVAL; + + config_msa_sync_clk_mode(dev, dp_sub->en_sync_clk_mode); + set_video_clk_source(dev, AVBUF_PS_CLK, AVBUF_PS_CLK); + + return 0; +} + +static int dp_tx_run(struct udevice *dev) +{ + u32 interrupt_signal_state, interrupt_status, hpd_state, hpd_event; + u32 hpd_pulse_detected, hpd_duration, status; + int attempts = 0; + struct zynqmp_dpsub_priv *dp_sub = dev_get_priv(dev); + + /* Continuously poll for HPD events. */ + while (attempts < 5) { + /* Read interrupt registers. */ + interrupt_signal_state = readl(dp_sub->base_addr + DP_INTERRUPT_SIG_STATE); + interrupt_status = readl(dp_sub->base_addr + DP_INTR_STATUS); + /* Check for HPD events. */ + hpd_state = interrupt_signal_state & DP_INTERRUPT_SIG_STATE_HPD_STATE_MASK; + hpd_event = interrupt_status & DP_INTR_HPD_EVENT_MASK; + hpd_pulse_detected = interrupt_status & DP_INTR_HPD_PULSE_DETECTED_MASK; + if (hpd_pulse_detected) + hpd_duration = readl(dp_sub->base_addr + DP_HPD_DURATION); + else + attempts++; + + /* HPD event handling. */ + if (hpd_state && hpd_event) { + debug("+===> HPD connection event detected.\n"); + /* Initiate link training. */ + status = dp_tx_start_link_training(dev); + if (status) { + debug("Link training failed\n"); + return status; + } + return 0; + } else if (hpd_state && hpd_pulse_detected && (hpd_duration >= 250)) { + debug("===> HPD pulse detected.\n"); + /* Re-train if needed. */ + status = dp_tx_start_link_training(dev); + if (status) { + debug("HPD pulse detection failed\n"); + return status; + } + return 0; + } else if (!hpd_state && hpd_event) { + debug("+===> HPD disconnection event detected.\n\n"); + /* Disable main link. */ + enable_main_link(dev, 0); + break; + } + } + return -EINVAL; +} + +static int zynqmp_dpsub_probe(struct udevice *dev) +{ + struct video_priv *uc_priv = dev_get_uclass_priv(dev); + struct zynqmp_dpsub_priv *priv = dev_get_priv(dev); + struct clk clk; + int ret; + int mode = RGBA8888; + + ret = clk_get_by_name(dev, "dp_apb_clk", &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; + } + + priv->clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(priv->clock)) { + dev_err(dev, "failed to get rate\n"); + return priv->clock; + } + + ret = clk_enable(&clk); + if (ret) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + dev_dbg(dev, "Base addr 0x%x, clock %d\n", (u32)priv->base_addr, + priv->clock); + + /* Initialize the DisplayPort TX core. */ + ret = init_dp_tx(dev); + if (ret) + return -EINVAL; + + /* Initialize the runtime configuration */ + init_run_config(dev); + /* Set the format graphics frame for Video Pipeline */ + ret = set_nonlive_gfx_format(dev, mode); + if (ret) + return ret; + + uc_priv->bpix = ffs(priv->non_live_graphics->bpp) - 1; + dev_dbg(dev, "BPP in bits %d, bpix %d\n", + priv->non_live_graphics->bpp, uc_priv->bpix); + + uc_priv->fb = (void *)gd->fb_base; + uc_priv->xsize = vidc_video_timing_modes[priv->video_mode].video_timing.h_active; + uc_priv->ysize = vidc_video_timing_modes[priv->video_mode].video_timing.v_active; + /* Calculated by core but need it for my own setup */ + uc_priv->line_length = uc_priv->xsize * VNBYTES(uc_priv->bpix); + /* Will be calculated again in video_post_probe() but I need that value now */ + uc_priv->fb_size = uc_priv->line_length * uc_priv->ysize; + + switch (mode) { + case RGBA8888: + uc_priv->format = VIDEO_RGBA8888; + break; + default: + debug("Unsupported mode\n"); + return -EINVAL; + } + + video_set_flush_dcache(dev, true); + debug("Video: WIDTH[%d]xHEIGHT[%d]xBPP[%d/%d] -- line length %d\n", uc_priv->xsize, + uc_priv->ysize, uc_priv->bpix, VNBYTES(uc_priv->bpix), uc_priv->line_length); + + enable_gfx_buffers(dev, 1); + avbuf_video_select(dev, AVBUF_VIDSTREAM1_NONE, AVBUF_VIDSTREAM2_NONLIVE_GFX); + config_gfx_pipeline(dev); + config_output_video(dev); + + ret = zynqmp_dpsub_init(dev); + if (ret) + return ret; + + /* Populate the FrameBuffer structure with the frame attributes */ + priv->frame_buffer.stride = uc_priv->line_length; + priv->frame_buffer.line_size = priv->frame_buffer.stride; + priv->frame_buffer.size = priv->frame_buffer.line_size * uc_priv->ysize; + + ret = dp_tx_run(dev); + if (ret) + return ret; + + return dpdma_setup(dev); +} + +static int zynqmp_dpsub_bind(struct udevice *dev) +{ + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + + /* This is maximum size to allocate - it depends on BPP setting */ + plat->size = WIDTH * HEIGHT * 4; + /* plat->align is not defined that's why 1MB alignment is used */ + + /* + * plat->base can be used for allocating own location for FB + * if not defined then it is allocated by u-boot itself + */ + + return 0; +} + +static int zynqmp_dpsub_of_to_plat(struct udevice *dev) +{ + struct zynqmp_dpsub_priv *priv = dev_get_priv(dev); + struct resource res; + int ret; + + ret = dev_read_resource_byname(dev, "dp", &res); + if (ret) + return ret; + + priv->base_addr = res.start; + + return 0; +} + +static const struct udevice_id zynqmp_dpsub_ids[] = { + { .compatible = "xlnx,zynqmp-dpsub-1.7" }, + { } +}; + +U_BOOT_DRIVER(zynqmp_dpsub_video) = { + .name = "zynqmp_dpsub_video", + .id = UCLASS_VIDEO, + .of_match = zynqmp_dpsub_ids, + .plat_auto = sizeof(struct video_uc_plat), + .bind = zynqmp_dpsub_bind, + .probe = zynqmp_dpsub_probe, + .priv_auto = sizeof(struct zynqmp_dpsub_priv), + .of_to_plat = zynqmp_dpsub_of_to_plat, +}; diff --git a/drivers/video/zynqmp/zynqmp_dpsub.h b/drivers/video/zynqmp/zynqmp_dpsub.h new file mode 100644 index 0000000..7d2737e --- /dev/null +++ b/drivers/video/zynqmp/zynqmp_dpsub.h @@ -0,0 +1,680 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023, Advanced Micro Devices, Inc. + * + */ + +#ifndef _VIDEO_ZYNQMP_DPSUB_H +#define _VIDEO_ZYNQMP_DPSUB_H + +enum video_mode { + VIDC_VM_640x480_60_P = 0, + VIDC_VM_1024x768_60_P = 1, +}; + +enum { + LANE_COUNT_1 = 1, + LANE_COUNT_2 = 2, +}; + +enum { + LINK_RATE_162GBPS = 0x06, + LINK_RATE_270GBPS = 0x0A, + LINK_RATE_540GBPS = 0x14, +}; + +enum video_color_depth { + VIDC_BPC_6 = 6, + VIDC_BPC_8 = 8, + VIDC_BPC_10 = 10, + VIDC_BPC_12 = 12, + VIDC_BPC_14 = 14, + VIDC_BPC_16 = 16, + VIDC_BPC_NUM_SUPPORTED = 6, + VIDC_BPC_UNKNOWN +}; + +enum video_color_encoding { + DP_CENC_RGB = 0, + DP_CENC_YONLY, +}; + +enum dp_dma_channel_type { + VIDEO_CHAN, + GRAPHICS_CHAN, +}; + +enum dp_dma_channel_state { + DPDMA_DISABLE, + DPDMA_ENABLE, + DPDMA_IDLE, + DPDMA_PAUSE +}; + +enum link_training_states { + TS_CLOCK_RECOVERY, + TS_CHANNEL_EQUALIZATION, + TS_ADJUST_LINK_RATE, + TS_ADJUST_LANE_COUNT, + TS_FAILURE, + TS_SUCCESS +}; + +enum video_frame_rate { + VIDC_FR_60HZ = 60, + VIDC_FR_NUM_SUPPORTED = 2, + VIDC_FR_UNKNOWN +}; + +enum av_buf_video_modes { + INTERLEAVED, + SEMIPLANAR +}; + +enum av_buf_video_format { + RGBA8888 = 1, +}; + +enum av_buf_video_stream { + AVBUF_VIDSTREAM1_LIVE, + AVBUF_VIDSTREAM1_NONLIVE, + AVBUF_VIDSTREAM1_TPG, + AVBUF_VIDSTREAM1_NONE, +}; + +enum av_buf_gfx_stream { + AVBUF_VIDSTREAM2_DISABLEGFX = 0x0, + AVBUF_VIDSTREAM2_NONLIVE_GFX = 0x4, + AVBUF_VIDSTREAM2_LIVE_GFX = 0x8, + AVBUF_VIDSTREAM2_NONE = 0xC0, +}; + +/** + * struct aux_transaction - Description of an AUX channel transaction + * @cmd_code: Command code of the transaction + * @num_bytes: The number of bytes in the transaction's payload data + * @address: The DPCD address of the transaction + * @data: Payload data of the AUX channel transaction + */ +struct aux_transaction { + u16 cmd_code; + u8 num_bytes; + u32 address; + u8 *data; +}; + +/** + * struct link_config - Description of link configuration + * @lane_count: Currently selected lane count for this link + * @link_rate: Currently selected link rate for this link + * @scrambler_en: Flag to determine whether the scrambler is + * enabled for this link + * @enhanced_framing_mode: Flag to determine whether enhanced framing + * mode is active for this link + * @max_lane_count: Maximum lane count for this link + * @max_link_rate: Maximum link rate for this link + * @support_enhanced_framing_mode: Flag to indicate whether the link supports + * enhanced framing mode + * @vs_level: Voltage swing for each lane + * @pe_level: Pre-emphasis/cursor level for each lane + * @pattern: The current pattern currently in use over the main link + */ +struct link_config { + u8 lane_count; + u8 link_rate; + u8 scrambler_en; + u8 enhanced_framing_mode; + u8 max_lane_count; + u8 max_link_rate; + u8 support_enhanced_framing_mode; + u8 support_downspread_control; + u8 vs_level; + u8 pe_level; + u8 pattern; +}; + +struct video_timing { + u16 h_active; + u16 h_front_porch; + u16 h_sync_width; + u16 h_back_porch; + u16 h_total; + bool h_sync_polarity; + u16 v_active; + u16 f0_pv_front_porch; + u16 f0_pv_sync_width; + u16 f0_pv_back_porch; + u16 f0_pv_total; + u16 f1_v_front_porch; + u16 f1_v_sync_width; + u16 f1_v_back_porch; + u16 f1_v_total; + bool v_sync_polarity; +}; + +struct video_timing_mode { + enum video_mode vid_mode; + char name[21]; + enum video_frame_rate frame_rate; + struct video_timing video_timing; +}; + +/* + * struct main_stream_attributes - Main Stream Attributes (MSA) + * @pixel_clock_hz: The pixel clock of the stream (in Hz) + * @h_start: Horizontal blank start (in pixels) + * @v_start: Vertical blank start (in lines). + * @misc0: Miscellaneous stream attributes 0 + * @misc1: Miscellaneous stream attributes 1 + * @n_vid N value for the video stream + * @user_pixel_width: The width of the user data input port. + * @data_per_plane: Used to translate the number of pixels per + * line to the native internal 16-bit datapath. + * @avg_bytes_per_tu: Average number of bytes per transfer unit, + * scaled up by a factor of 1000. + * @transfer_unit_size: Size of the transfer unit in the + * framing logic. + * @init_wait: Number of initial wait cycles at the start + * of a new line by the framing logic. + * @bits_per_color: Number of bits per color component. + * @component_format: The component format currently in + * use by the video stream. + * @dynamic_range: The dynamic range currently in use + * by the video stream. + * @y_cb_cr_colorimetry: The YCbCr colorimetry currently in + * use by the video stream. + * @synchronous_clock_mode: Synchronous clock mode is currently + * in use by the video stream. + */ +struct main_stream_attributes { + struct video_timing_mode vid_timing_mode; + u32 pixel_clock_hz; + u32 h_start; + u32 v_start; + u32 misc0; + u32 misc1; + u32 n_vid; + u32 user_pixel_width; + u32 data_per_lane; + u32 avg_bytes_per_tu; + u32 transfer_unit_size; + u32 init_wait; + u32 bits_per_color; + u8 component_format; + u8 dynamic_range; + u8 y_cb_cr_colorimetry; + u8 synchronous_clock_mode; +}; + +struct av_buf_vid_attribute { + enum av_buf_video_format video_format; + u8 value; + enum av_buf_video_modes mode; + u32 sf[3]; + u8 sampling_en; + u8 is_rgb; + u8 swap; + u8 bpp; +}; + +struct av_buf_mode { + enum av_buf_video_stream video_src; + enum av_buf_gfx_stream gfx_src; + u8 video_clk; +}; + +struct dp_dma_descriptor { + u32 control; + u32 dscr_id; + u32 xfer_size; + u32 line_size_stride; + u32 lsb_timestamp; + u32 msb_timestamp; + u32 addr_ext; + u32 next_desr; + u32 src_addr; + u32 addr_ext_23; + u32 addr_ext_45; + u32 src_addr2; + u32 src_addr3; + u32 src_addr4; + u32 src_addr5; + u32 crc; +}; + +struct dp_dma_channel { + struct dp_dma_descriptor *cur; +}; + +struct dp_dma_frame_buffer { + u64 address; + u32 size; + u32 stride; + u32 line_size; +}; + +struct dp_dma_gfx_channel { + struct dp_dma_channel channel; + u8 trigger_status; + u8 av_buf_en; + struct dp_dma_frame_buffer *frame_buffer; +}; + +struct dp_dma { + phys_addr_t base_addr; + struct dp_dma_gfx_channel gfx; +}; + +/** + * struct zynqmp_dpsub_priv - Private structure + * @dev: Device uclass for video_ops + */ +struct zynqmp_dpsub_priv { + phys_addr_t base_addr; + u32 clock; + struct av_buf_vid_attribute *non_live_graphics; + struct av_buf_mode av_mode; + struct dp_dma_frame_buffer frame_buffer; + + struct link_config link_config; + struct main_stream_attributes msa_config; + struct dp_dma *dp_dma; + enum video_mode video_mode; + enum video_color_depth bpc; + enum video_color_encoding color_encode; + u32 pix_clk; + u8 dpcd_rx_caps[16]; + u8 lane_status_ajd_reqs[6]; + u8 sink_count; + u8 use_max_lane_count; + u8 use_max_link_rate; + u8 lane_count; + u8 link_rate; + u8 use_max_cfg_caps; + u8 en_sync_clk_mode; +}; + +/**************************** Variable Definitions ****************************/ +#define TRAINING_PATTERN_SET 0x000C +#define TRAINING_PATTERN_SET_OFF 0x0 +#define SCRAMBLING_DISABLE 0x0014 +#define TRAINING_PATTERN_SET_TP1 0x1 +#define TRAINING_PATTERN_SET_TP2 0x2 +#define TRAINING_PATTERN_SET_TP3 0x3 + +#define AVBUF_BUF_4BIT_SF 0x11111 +#define AVBUF_BUF_5BIT_SF 0x10842 +#define AVBUF_BUF_6BIT_SF 0x10410 +#define AVBUF_BUF_8BIT_SF 0x10101 +#define AVBUF_BUF_10BIT_SF 0x10040 +#define AVBUF_BUF_12BIT_SF 0x10000 +#define AVBUF_BUF_6BPC 0x000 +#define AVBUF_BUF_8BPC 0x001 +#define AVBUF_BUF_10BPC 0x010 +#define AVBUF_BUF_12BPC 0x011 +#define AVBUF_CHBUF3 0x0000B01C +#define AVBUF_CHBUF3_BURST_LEN_SHIFT 2 +#define AVBUF_CHBUF3_FLUSH_MASK 0x00000002 +#define AVBUF_CHBUF0_EN_MASK 0x00000001 +#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT 0x0000B070 +#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM2_SEL_MASK 0x0000000C +#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT_VID_STREAM1_SEL_MASK 0x00000003 +#define AVBUF_BUF_OUTPUT_AUD_VID_SELECT 0x0000B070 +#define AVBUF_BUF_GRAPHICS_COMP0_SCALE_FACTOR 0x0000B200 +#define AVBUF_V_BLEND_LAYER1_CONTROL 0x0000A01C +#define AVBUF_V_BLEND_IN2CSC_COEFF0 0x0000A080 +#define AVBUF_BUF_FORMAT 0x0000B000 +#define AVBUF_BUF_FORMAT_NL_VID_FORMAT_MASK 0x0000001F +#define AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_MASK 0x00000F00 +#define AVBUF_BUF_FORMAT_NL_GRAPHX_FORMAT_SHIFT 8 +#define AVBUF_V_BLEND_LAYER0_CONTROL_RGB_MODE_SHIFT 1 +#define AVBUF_V_BLEND_OUTPUT_VID_FORMAT_EN_DOWNSAMPLE_SHIFT 4 +#define AVBUF_V_BLEND_OUTPUT_VID_FORMAT 0x0000A014 +#define AVBUF_V_BLEND_RGB2YCBCR_COEFF0 0x0000A020 +#define AVBUF_V_BLEND_LUMA_OUTCSC_OFFSET 0x0000A074 +#define AVBUF_V_BLEND_LUMA_IN1CSC_OFFSET_POST_OFFSET_SHIFT 16 +#define AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG_VALUE_SHIFT 1 +#define AVBUF_V_BLEND_SET_GLOBAL_ALPHA_REG 0x0000A00C +#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_SHIFT 1 +#define DP_MAIN_STREAM_MISC0_DYNAMIC_RANGE_SHIFT 3 +#define DP_MAIN_STREAM_MISC0_YCBCR_COLORIMETRY_SHIFT 4 +#define DP_MAIN_STREAM_MISC1_Y_ONLY_EN_MASK 0x00000080 +#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_YCBCR422 0x1 +#define AVBUF_PL_CLK 0x0 +#define AVBUF_PS_CLK 0x1 +#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_TIMING_SRC_SHIFT 2 +#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT 0 +#define AVBUF_BUF_AUD_VID_CLK_SOURCE_AUD_CLK_SRC_SHIFT 1 +#define AVBUF_BUF_AUD_VID_CLK_SOURCE 0x0000B120 +#define AVBUF_BUF_SRST_REG 0x0000B124 +#define AVBUF_BUF_SRST_REG_VID_RST_MASK 0x00000002 +#define AVBUF_CLK_FPD_BASEADDR 0xFD1A0000 +#define AVBUF_CLK_LPD_BASEADDR 0xFF5E0000 +#define AVBUF_LPD_CTRL_OFFSET 16 +#define AVBUF_FPD_CTRL_OFFSET 12 +#define AVBUF_EXTERNAL_DIVIDER 2 +#define AVBUF_VIDEO_REF_CTRL 0x00000070 +#define AVBUF_VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007 +#define AVBUF_VPLL_SRC_SEL 0 +#define AVBUF_DPLL_SRC_SEL 2 +#define AVBUF_RPLL_TO_FPD_SRC_SEL 3 +#define AVBUF_INPUT_REF_CLK 3333333333 +#define AVBUF_PLL_OUT_FREQ 1450000000 +#define AVBUF_INPUT_FREQ_PRECISION 100 +#define AVBUF_PRECISION 16 +#define AVBUF_SHIFT_DECIMAL BIT(16) +#define AVBUF_DECIMAL (AVBUF_SHIFT_DECIMAL - 1) +#define AVBUF_ENABLE_BIT 1 +#define AVBUF_DISABLE_BIT 0 +#define AVBUF_PLL_CTRL_BYPASS_SHIFT 3 +#define AVBUF_PLL_CTRL_FBDIV_SHIFT 8 +#define AVBUF_PLL_CTRL_DIV2_SHIFT 16 +#define AVBUF_PLL_CTRL_PRE_SRC_SHIFT 20 +#define AVBUF_PLL_CTRL 0x00000020 +#define AVBUF_PLL_CFG_CP_SHIFT 5 +#define AVBUF_PLL_CFG_RES_SHIFT 0 +#define AVBUF_PLL_CFG_LFHF_SHIFT 10 +#define AVBUF_PLL_CFG_LOCK_DLY_SHIFT 25 +#define AVBUF_PLL_CFG_LOCK_CNT_SHIFT 13 +#define AVBUF_PLL_FRAC_CFG 0x00000028 +#define AVBUF_PLL_FRAC_CFG_ENABLED_SHIFT 31 +#define AVBUF_PLL_FRAC_CFG_DATA_SHIFT 0 +#define AVBUF_PLL_CTRL_RESET_MASK 0x00000001 +#define AVBUF_PLL_CTRL_RESET_SHIFT 0 +#define AVBUF_PLL_STATUS 0x00000044 +#define AVBUF_REG_OFFSET 4 +#define AVBUF_PLL_CTRL_BYPASS_MASK 0x00000008 +#define AVBUF_PLL_CTRL_BYPASS_SHIFT 3 +#define AVBUF_DOMAIN_SWITCH_CTRL 0x00000044 +#define AVBUF_DOMAIN_SWITCH_DIVISOR0_MASK 0x00003F00 +#define AVBUF_DOMAIN_SWITCH_DIVISOR0_SHIFT 8 +#define AVBUF_PLL_CFG 0x00000024 +#define AVBUF_BUF_AUD_VID_CLK_SOURCE_VID_CLK_SRC_SHIFT 0 +#define AVBUF_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000 +#define AVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define AVBUF_VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000 +#define AVBUF_VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define AVBUF_VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00 +#define AVBUF_VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define AVBUF_VIDEO_REF_CTRL_CLKACT_MASK 0x01000000 +#define AVBUF_VIDEO_REF_CTRL_CLKACT_SHIFT 24 + +#define DP_INTERRUPT_SIG_STATE 0x0130 +#define DP_INTR_STATUS 0x03A0 +#define DP_INTERRUPT_SIG_STATE_HPD_STATE_MASK 0x00000001 +#define DP_INTR_HPD_EVENT_MASK 0x00000002 +#define DP_INTR_HPD_PULSE_DETECTED_MASK 0x00000010 +#define DP_HPD_DURATION 0x0150 +#define DP_FORCE_SCRAMBLER_RESET 0x00C0 +#define DP_ENABLE_MAIN_STREAM 0x0084 +#define DP_IS_CONNECTED_MAX_TIMEOUT_COUNT 50 +#define DP_0_LINK_RATE 20 +#define DP_0_LANE_COUNT 1 +#define DP_ENHANCED_FRAME_EN 0x0008 +#define DP_LANE_COUNT_SET 0x0004 +#define DP_LINK_BW_SET_162GBPS 0x06 +#define DP_LINK_BW_SET_270GBPS 0x0A +#define DP_LINK_BW_SET_540GBPS 0x14 +#define DP_LINK_BW_SET 0x0000 +#define DP_DOWNSPREAD_CTRL 0x0018 +#define DP_SCRAMBLING_DISABLE 0x0014 +#define DP_AUX_CMD_READ 0x9 +#define DP_AUX_CMD_WRITE 0x8 +#define DP_AUX_CMD_I2C_READ 0x1 +#define DP_AUX_CMD_I2C_READ_MOT 0x5 +#define DP_AUX_CMD_I2C_WRITE 0x0 +#define DP_AUX_CMD_I2C_WRITE_MOT 0x4 +#define DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002 +#define DP_REPLY_STATUS_REQUEST_IN_PROGRESS_MASK 0x00000004 +#define DP_REPLY_STATUS 0x014C +#define DP_AUX_MAX_TIMEOUT_COUNT 50 +#define DP_AUX_MAX_DEFER_COUNT 50 +#define DP_AUX_ADDRESS 0x0108 +#define DP_AUX_WRITE_FIFO 0x0104 +#define DP_AUX_CMD 0x0100 +#define DP_AUX_CMD_SHIFT 8 +#define DP_AUX_CMD_NBYTES_TRANSFER_MASK 0x0000000F +#define DP_AUX_REPLY_CODE 0x0138 +#define DP_AUX_REPLY_CODE_DEFER 0x2 +#define DP_AUX_REPLY_CODE_I2C_DEFER 0x8 +#define DP_AUX_REPLY_CODE_NACK 0x1 +#define DP_AUX_REPLY_CODE_I2C_NACK 0x4 +#define DP_REPLY_DATA_COUNT 0x0148 +#define DP_AUX_REPLY_DATA 0x0134 +#define DP_LANE_COUNT_SET_1 0x01 +#define DP_LANE_COUNT_SET_2 0x02 +#define DP_MAXIMUM_PE_LEVEL 2 +#define DP_MAXIMUM_VS_LEVEL 3 +#define DP_MAIN_STREAM_MISC0_COMPONENT_FORMAT_RGB 0x0 +#define DP_MAIN_STREAM_MISC0_BDC_6BPC 0x0 +#define DP_MAIN_STREAM_MISC0_BDC_8BPC 0x1 +#define DP_MAIN_STREAM_MISC0_BDC_10BPC 0x2 +#define DP_MAIN_STREAM_MISC0_BDC_12BPC 0x3 +#define DP_MAIN_STREAM_MISC0_BDC_16BPC 0x4 +#define DP_MAIN_STREAM_MISC0_BDC_SHIFT 5 +#define DP_PHY_CONFIG_TX_PHY_8B10BEN_MASK 0x0010000 +#define DP_PHY_CONFIG_PHY_RESET_MASK 0x0000001 +#define DP_ENABLE_MAIN_STREAM 0x0084 +#define DP_SOFT_RESET 0x001C +#define DP_MAIN_STREAM_HTOTAL 0x0180 +#define DP_MAIN_STREAM_VTOTAL 0x0184 +#define DP_MAIN_STREAM_POLARITY 0x0188 +#define DP_MAIN_STREAM_POLARITY_VSYNC_POL_SHIFT 1 +#define DP_MAIN_STREAM_HSWIDTH 0x018C +#define DP_MAIN_STREAM_VSWIDTH 0x0190 +#define DP_MAIN_STREAM_HRES 0x0194 +#define DP_MAIN_STREAM_VRES 0x0198 +#define DP_MAIN_STREAM_HSTART 0x019C +#define DP_MAIN_STREAM_VSTART 0x01A0 +#define DP_MAIN_STREAM_MISC0 0x01A4 +#define DP_MAIN_STREAM_MISC1 0x01A8 +#define DP_M_VID 0x01AC +#define DP_N_VID 0x01B4 +#define DP_USER_PIXEL_WIDTH 0x01B8 +#define DP_USER_DATA_COUNT_PER_LANE 0x01BC +#define DP_TU_SIZE 0x01B0 +#define DP_MIN_BYTES_PER_TU 0x01C4 +#define DP_FRAC_BYTES_PER_TU 0x01C8 +#define DP_INIT_WAIT 0x01CC +#define DP_PHY_CLOCK_SELECT_162GBPS 0x1 +#define DP_PHY_CLOCK_SELECT_270GBPS 0x3 +#define DP_PHY_CLOCK_SELECT_540GBPS 0x5 +#define DP_PHY_STATUS 0x0280 +#define DP_PHY_STATUS_ALL_LANES_READY_MASK 0x00000013 +#define DP_PHY_STATUS_GT_PLL_LOCK_MASK 0x00000010 +#define DP_PHY_STATUS_RESET_LANE_0_DONE_MASK 0x00000001 +#define DP_INTR_HPD_IRQ_MASK 0x00000001 +#define DP_INTR_MASK 0x03A4 +#define DP_DP_ENABLE 0x1 +#define DP_PHY_CONFIG_GT_ALL_RESET_MASK 0x0000003 +#define DP_PHY_CLOCK_SELECT 0x0234 +#define DP_AUX_CLK_DIVIDER_VAL_MASK 0x000000FF +#define DP_AUX_CLK_DIVIDER 0x010C +#define DP_DISABLE 0x0 +#define DP_ENABLE 0x0080 +#define DP_SOFT_RESET_EN 0x1 +#define DP_PHY_CONFIG 0x0200 +#define DP_REPLY_STATUS_REPLY_RECEIVED_MASK 0x00000001 +#define DP_REPLY_STATUS_REPLY_IN_PROGRESS_MASK 0x00000002 +#define DP_REPLY_STATUS_REPLY_ERROR_MASK 0x00000008 +#define DP_AUX_MAX_WAIT 20000 + +#define DP_DPCD_SINK_COUNT 0x00200 +#define DP_DPCD_TP_SET_SCRAMB_DIS_MASK 0x20 +#define DP_DPCD_STATUS_LANE_1_CR_DONE_MASK 0x10 +#define DP_DPCD_STATUS_LANE_0_CR_DONE_MASK 0x01 +#define DP_DPCD_STATUS_LANE_1_CE_DONE_MASK 0x20 +#define DP_DPCD_STATUS_LANE_0_CE_DONE_MASK 0x02 +#define DP_DPCD_STATUS_LANE_1_SL_DONE_MASK 0x40 +#define DP_DPCD_STATUS_LANE_0_SL_DONE_MASK 0x04 +#define DP_DPCD_LANE_ALIGN_STATUS_UPDATED_IA_DONE_MASK 0x01 +#define DP_DPCD_ADJ_REQ_LANE_0_2_VS_MASK 0x03 +#define DP_DPCD_ADJ_REQ_LANE_1_3_VS_MASK 0x30 +#define DP_DPCD_ADJ_REQ_LANE_1_3_VS_SHIFT 4 +#define DP_DPCD_ADJ_REQ_LANE_0_2_PE_MASK 0x0C +#define DP_DPCD_ADJ_REQ_LANE_0_2_PE_SHIFT 2 +#define DP_DPCD_ADJ_REQ_LANE_1_3_PE_MASK 0xC0 +#define DP_DPCD_ADJ_REQ_LANE_1_3_PE_SHIFT 6 +#define DP_DPCD_TRAINING_LANE0_SET 0x00103 +#define DP_DPCD_TRAINING_LANEX_SET_MAX_VS_MASK 0x04 +#define DP_DPCD_TRAINING_LANEX_SET_MAX_PE_MASK 0x20 +#define DP_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 +#define DP_DPCD_SET_POWER_DP_PWR_VOLTAGE 0x00600 +#define DP_DPCD_RECEIVER_CAP_FIELD_START 0x00000 +#define DP_DPCD_MAX_LINK_RATE 0x00001 +#define DP_DPCD_MAX_LANE_COUNT 0x00002 +#define DP_DPCD_MAX_LANE_COUNT_MASK 0x1F +#define DP_DPCD_ENHANCED_FRAME_SUPPORT_MASK 0x80 +#define DP_DPCD_MAX_DOWNSPREAD 0x00003 +#define DP_DPCD_MAX_DOWNSPREAD_MASK 0x01 +#define DP_DPCD_LANE_COUNT_SET 0x00101 +#define DP_DPCD_ENHANCED_FRAME_EN_MASK 0x80 +#define DP_DPCD_LINK_BW_SET 0x00100 +#define DP_DPCD_DOWNSPREAD_CTRL 0x00107 +#define DP_DPCD_SPREAD_AMP_MASK 0x10 +#define DP_DPCD_LANE_COUNT_SET_MASK 0x1F +#define DP_DPCD_TPS3_SUPPORT_MASK 0x40 +#define DP_DPCD_TRAIN_AUX_RD_INTERVAL 0x0000E +#define DP_DPCD_SINK_COUNT_HIGH_MASK 0x80 +#define DP_DPCD_SINK_COUNT_HIGH_LOW_SHIFT 1 +#define DP_DPCD_SINK_COUNT_LOW_MASK 0x3F +#define DP_DPCD_TP_SET 0x00102 + +#define SERDES_BASEADDR 0xFD400000 +#define SERDES_L0_TX_MARGININGF 0x0CC0 +#define SERDES_L0_TX_DEEMPHASIS 0x0048 +#define SERDES_LANE_OFFSET 0x4000 + +#define DPDMA_TRIGGER_EN 1U +#define DPDMA_RETRIGGER_EN 2U +#define DPDMA_DESC_PREAMBLE 0xA5U +#define DPDMA_DESC_IGNR_DONE 0x400U +#define DPDMA_DESC_LAST_FRAME 0x200000U +#define DPDMA_DESCRIPTOR_LINE_SIZE_STRIDE_SHIFT 18 +#define DPDMA_DESCRIPTOR_SRC_ADDR_WIDTH 32U +#define DPDMA_DESCRIPTOR_ADDR_EXT_SRC_ADDR_EXT_SHIFT 16U +#define DPDMA_CH0_DSCR_STRT_ADDR 0X0204U +#define DPDMA_CH_OFFSET 0x100U +#define DPDMA_CH0_CNTL 0x0218U +#define DPDMA_CH3_CNTL 0x0518U +#define DPDMA_CH0_DSCR_STRT_ADDRE 0x0200U +#define DPDMA_CH3_DSCR_STRT_ADDR 0x0504 +#define DPDMA_CH3_DSCR_STRT_ADDRE 0x0500 +#define DPDMA_CH_CNTL_EN_MASK 0x1U +#define DPDMA_CH_CNTL_PAUSE_MASK 0x2U +#define DPDMA_GBL 0x0104U +#define DPDMA_GBL_TRG_CH3_MASK 0x8 +#define DPDMA_TRIGGER_DONE 0U +#define DPDMA_CH_CNTL_EN_MASK 0x1U +#define DPDMA_CH_CNTL_PAUSE_MASK 0x2U +#define DPDMA_CH_CNTL_QOS_DATA_RD_SHIFT 10U +#define DPDMA_CH_CNTL_QOS_DATA_RD_MASK 0x3C00U +#define DPDMA_CH_CNTL_QOS_DSCR_RD_SHIFT 6U +#define DPDMA_CH_CNTL_QOS_DSCR_RD_MASK 0x03C0U +#define DPDMA_CH_CNTL_QOS_DSCR_WR_SHIFT 2U +#define DPDMA_CH_CNTL_QOS_DSCR_WR_MASK 0x3CU +#define DPDMA_CH_OFFSET 0x100U +#define DPDMA_WAIT_TIMEOUT 10000U +#define DPDMA_AUDIO_ALIGNMENT 128U +#define DPDMA_VIDEO_CHANNEL0 0U +#define DPDMA_VIDEO_CHANNEL1 1U +#define DPDMA_VIDEO_CHANNEL2 2U +#define DPDMA_GRAPHICS_CHANNEL 3U +#define DPDMA_AUDIO_CHANNEL0 4U +#define DPDMA_AUDIO_CHANNEL1 5U +#define DPDMA_DESC_PREAMBLE 0xA5U +#define DPDMA_DESC_IGNR_DONE 0x400U +#define DPDMA_DESC_UPDATE 0x200U +#define DPDMA_DESC_COMP_INTR 0x100U +#define DPDMA_DESC_LAST_FRAME 0x200000U +#define DPDMA_DESC_DONE_SHIFT 31U +#define DPDMA_QOS_MIN 4U +#define DPDMA_QOS_MAX 11U +#define DPDMA_BASE_ADDRESS 0xFD4C0000 +#define DPDMA_ISR 0x0004U +#define DPDMA_IEN 0x000CU +#define DPDMA_ISR_VSYNC_INT_MASK 0x08000000 + +#define CLK_FPD_BASEADDR 0xFD1A0000 +#define VIDEO_REF_CTRL 0x00000070 +#define VIDEO_REF_CTRL_SRCSEL_MASK 0x00000007 +#define PLL_OUT_FREQ 1450000000 +#define INPUT_FREQ_PRECISION 100 +#define PRECISION 16 +#define SHIFT_DECIMAL BIT(16) +#define ENABLE_BIT 1 +#define DISABLE_BIT 0 +#define PLL_CTRL_BYPASS_SHIFT 3 +#define PLL_CTRL_FBDIV_SHIFT 8 +#define PLL_CTRL_DIV2_SHIFT 16 +#define PLL_CTRL_PRE_SRC_SHIFT 20 +#define PLL_CTRL 0x00000020 +#define VPLL_CTRL 0x00000038 +#define PLL_CFG 0x00000024 +#define VPLL 2 +#define VPLL_CFG 0x0000003C +#define VPLL_CFG_CP 4 +#define VPLL_CFG_RES 6 +#define VPLL_CFG_LFHF 3 +#define VPLL_CFG_LOCK_DLY 63 +#define VPLL_CFG_LOCK_CNT 600 +#define PLL_STATUS_VPLL_LOCK 2 +#define PLL_CFG_CP_SHIFT 5 +#define PLL_CFG_RES_SHIFT 0 +#define PLL_CFG_LFHF_SHIFT 10 +#define PLL_CFG_LOCK_DLY_SHIFT 25 +#define PLL_CFG_LOCK_CNT_SHIFT 13 +#define PLL_FRAC_CFG 0x00000028 +#define VPLL_FRAC_CFG 0x00000040 +#define PLL_FRAC_CFG_ENABLED_SHIFT 31 +#define PLL_FRAC_CFG_DATA_SHIFT 0 +#define PLL_CTRL_RESET_MASK 0x00000001 +#define PLL_CTRL_RESET_SHIFT 0 +#define PLL_STATUS 0x00000044 +#define REG_OFFSET 4 +#define PLL_CTRL_BYPASS_MASK 0x00000008 +#define PLL_CTRL_BYPASS_SHIFT 3 +#define DOMAIN_SWITCH_CTRL 0x00000044 +#define DOMAIN_SWITCH_DIVISOR0_MASK 0x00003F00 +#define DOMAIN_SWITCH_DIVISOR0_SHIFT 8 +#define VIDEO_REF_CTRL_CLKACT_MASK 0x01000000 +#define VIDEO_REF_CTRL_CLKACT_SHIFT 24 +#define VIDEO_REF_CTRL_DIVISOR1_MASK 0x003F0000 +#define VIDEO_REF_CTRL_DIVISOR1_SHIFT 16 +#define VIDEO_REF_CTRL_DIVISOR0_MASK 0x00003F00 +#define VIDEO_REF_CTRL_DIVISOR0_SHIFT 8 +#define PSS_REF_CLK 0 +#define FPD_CTRL_OFFSET 12 +#define VIDC_VM_NUM_SUPPORTED 2 + +static const u32 vs[4][4] = { + { 0x2a, 0x27, 0x24, 0x20 }, + { 0x27, 0x23, 0x20, 0xff }, + { 0x24, 0x20, 0xff, 0xff }, + { 0xff, 0xff, 0xff, 0xff }, +}; + +static const u32 pe[4][4] = { + { 0x02, 0x02, 0x02, 0x02 }, + { 0x01, 0x01, 0x01, 0xff }, + { 0x00, 0x00, 0xff, 0xff }, + { 0xff, 0xff, 0xff, 0xff }, +}; + +const struct video_timing_mode vidc_video_timing_modes[VIDC_VM_NUM_SUPPORTED] = { + { VIDC_VM_640x480_60_P, "640x480@60Hz", VIDC_FR_60HZ, + {640, 16, 96, 48, 800, 0, + 480, 10, 2, 33, 525, 0, 0, 0, 0, 0} }, + { VIDC_VM_1024x768_60_P, "1024x768@60Hz", VIDC_FR_60HZ, + {1024, 24, 136, 160, 1344, 0, + 768, 3, 6, 29, 806, 0, 0, 0, 0, 0} }, +}; + +const struct av_buf_vid_attribute avbuf_supported_formats[] = { + /* Non-Live Graphics formats */ + { RGBA8888, 0, INTERLEAVED, + {AVBUF_BUF_8BIT_SF, AVBUF_BUF_8BIT_SF, AVBUF_BUF_8BIT_SF}, + 0, 1, 0, 32}, +}; + +#endif diff --git a/drivers/video/zynqmp_dpsub.c b/drivers/video/zynqmp_dpsub.c deleted file mode 100644 index 4ead663..0000000 --- a/drivers/video/zynqmp_dpsub.c +++ /dev/null @@ -1,66 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2021 Xilinx Inc. - */ - -#include <common.h> -#include <cpu_func.h> -#include <dm.h> -#include <errno.h> -#include <video.h> -#include <dm/device_compat.h> - -#define WIDTH 640 -#define HEIGHT 480 - -/** - * struct zynqmp_dpsub_priv - Private structure - * @dev: Device uclass for video_ops - */ -struct zynqmp_dpsub_priv { - struct udevice *dev; -}; - -static int zynqmp_dpsub_probe(struct udevice *dev) -{ - struct video_priv *uc_priv = dev_get_uclass_priv(dev); - struct zynqmp_dpsub_priv *priv = dev_get_priv(dev); - - uc_priv->bpix = VIDEO_BPP16; - uc_priv->xsize = WIDTH; - uc_priv->ysize = HEIGHT; - uc_priv->rot = 0; - - priv->dev = dev; - - /* Only placeholder for power domain driver */ - return 0; -} - -static int zynqmp_dpsub_bind(struct udevice *dev) -{ - struct video_uc_plat *plat = dev_get_uclass_plat(dev); - - plat->size = WIDTH * HEIGHT * 16; - - return 0; -} - -static const struct video_ops zynqmp_dpsub_ops = { -}; - -static const struct udevice_id zynqmp_dpsub_ids[] = { - { .compatible = "xlnx,zynqmp-dpsub-1.7" }, - { } -}; - -U_BOOT_DRIVER(zynqmp_dpsub_video) = { - .name = "zynqmp_dpsub_video", - .id = UCLASS_VIDEO, - .of_match = zynqmp_dpsub_ids, - .ops = &zynqmp_dpsub_ops, - .plat_auto = sizeof(struct video_uc_plat), - .bind = zynqmp_dpsub_bind, - .probe = zynqmp_dpsub_probe, - .priv_auto = sizeof(struct zynqmp_dpsub_priv), -}; diff --git a/dts/Kconfig b/dts/Kconfig index 3b7489f..9152f58 100644 --- a/dts/Kconfig +++ b/dts/Kconfig @@ -171,7 +171,7 @@ config OF_LIST default DEFAULT_DEVICE_TREE help This option specifies a list of device tree files to use for DT - control. These will be packaged into a FIT. At run-time, U-boot + control. These will be packaged into a FIT. At run-time, U-Boot or SPL will select the correct DT to use by examining the hardware (e.g. reading a board ID value). This is a list of device tree files (without the directory or .dtb suffix) @@ -254,7 +254,7 @@ config DTB_RESELECT config MULTI_DTB_FIT bool "Support embedding several DTBs in a FIT image for u-boot" help - This option provides hooks to allow U-boot to parse an + This option provides hooks to allow U-Boot to parse an appended FIT image and enable board specific code to then select the correct DTB to be used. Use this if you need to support multiple DTBs but don't use the SPL. diff --git a/dts/Makefile b/dts/Makefile index cb31113..3437e54 100644 --- a/dts/Makefile +++ b/dts/Makefile @@ -63,4 +63,6 @@ spl_dtbs: $(obj)/dt-$(SPL_NAME).dtb clean-files := dt.dtb.S # Let clean descend into dts directories -subdir- += ../arch/arm/dts ../arch/microblaze/dts ../arch/mips/dts ../arch/sandbox/dts ../arch/x86/dts ../arch/powerpc/dts ../arch/riscv/dts +subdir- += ../arch/arc/dts ../arch/arm/dts ../arch/m68k/dts ../arch/microblaze/dts \ + ../arch/mips/dts ../arch/nios2/dts ../arch/powerpc/dts ../arch/riscv/dts \ + ../arch/sandbox/dts ../arch/sh/dts ../arch/x86/dts ../arch/xtensa/dts diff --git a/env/Kconfig b/env/Kconfig index 2bbe4c4..7342397 100644 --- a/env/Kconfig +++ b/env/Kconfig @@ -55,20 +55,23 @@ config ENV_MAX_ENTRIES be generous and should work in most cases. This setting can be used to tune behaviour; see lib/hashtable.c for details. -config ENV_IS_NOWHERE - bool "Environment is not stored" - default y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \ +config ENV_IS_DEFAULT + def_bool y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \ !ENV_IS_IN_FAT && !ENV_IS_IN_FLASH && \ !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \ !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \ !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \ !ENV_IS_IN_UBI + select ENV_IS_NOWHERE + +config ENV_IS_NOWHERE + bool "Environment is not stored" help - Define this if you don't want to or can't have an environment stored + Define this if you don't care whether or not an environment is stored on a storage medium. In this case the environment will still exist - while U-Boot is running, but once U-Boot exits it will not be - stored. U-Boot will therefore always start up with a default - environment. + while U-Boot is running, but once U-Boot exits it may not be + stored. If no other ENV_IS_IN_ is defined, U-Boot will always start + up with the default environment. config ENV_IS_IN_EEPROM bool "Environment in EEPROM" @@ -217,9 +217,7 @@ int env_load(void) printf("OK\n"); gd->env_load_prio = prio; -#if !CONFIG_IS_ENABLED(ENV_APPEND) return 0; -#endif } else if (ret == -ENOMSG) { /* Handle "bad CRC" case */ if (best_prio == -1) diff --git a/fs/btrfs/compat.h b/fs/btrfs/compat.h index 9cf8a10..02173de 100644 --- a/fs/btrfs/compat.h +++ b/fs/btrfs/compat.h @@ -46,7 +46,7 @@ /* * Read data from device specified by @desc and @part * - * U-boot equivalent of pread(). + * U-Boot equivalent of pread(). * * Return the bytes of data read. * Return <0 for error. diff --git a/fs/btrfs/crypto/hash.c b/fs/btrfs/crypto/hash.c index 891a297..0a0b35f 100644 --- a/fs/btrfs/crypto/hash.c +++ b/fs/btrfs/crypto/hash.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0+ +#include <asm/unaligned.h> #include <linux/xxhash.h> -#include <linux/unaligned/access_ok.h> #include <linux/types.h> #include <u-boot/sha256.h> #include <u-boot/blake2.h> diff --git a/fs/btrfs/extent-io.h b/fs/btrfs/extent-io.h index 6b0c87d..5c5c579 100644 --- a/fs/btrfs/extent-io.h +++ b/fs/btrfs/extent-io.h @@ -8,7 +8,7 @@ * Use pointer to provide better alignment. * - Remove max_cache_size related interfaces * Includes free_extent_buffer_nocache() - * As we don't cache eb in U-boot. + * As we don't cache eb in U-Boot. * - Include headers * * Write related functions are kept as we still need to modify dummy extent diff --git a/fs/semihostingfs.c b/fs/semihostingfs.c index 96eb334..3592338 100644 --- a/fs/semihostingfs.c +++ b/fs/semihostingfs.c @@ -57,8 +57,12 @@ static int smh_fs_write_at(const char *filename, loff_t pos, void *buffer, { long fd, size, ret; + /* Try to open existing file */ fd = smh_open(filename, MODE_READ | MODE_BINARY | MODE_PLUS); if (fd < 0) + /* Create new file */ + fd = smh_open(filename, MODE_WRITE | MODE_BINARY); + if (fd < 0) return fd; ret = smh_seek(fd, pos); if (ret < 0) { diff --git a/include/.gitignore b/include/.gitignore deleted file mode 100644 index 8e41a95..0000000 --- a/include/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -/autoconf.mk* -/bmp_logo.h -/bmp_logo_data.h -/config.h diff --git a/include/ali512x.h b/include/ali512x.h deleted file mode 100644 index 6bb6700..0000000 --- a/include/ali512x.h +++ /dev/null @@ -1,37 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>. - */ - -#ifndef __ASM_IC_ALI512X_H_ -#define __ASM_IC_ALI512X_H_ - -# define ALI_INDEX 0x3f0 -# define ALI_DATA 0x3f1 - -# define ALI_ENABLED 1 -# define ALI_DISABLED 0 - -# define ALI_UART1 0 -# define ALI_UART2 1 - -/* setup functions */ -void ali512x_init(void); -void ali512x_set_fdc(int enabled, u16 io, u8 irq, u8 dma_channel); -void ali512x_set_pp(int enabled, u16 io, u8 irq, u8 dma_channel); -void ali512x_set_uart(int enabled, int index, u16 io, u8 irq); -void ali512x_set_rtc(int enabled, u16 io, u8 irq); -void ali512x_set_kbc(int enabled, u8 kbc_irq, u8 mouse_irq); -void ali512x_set_cio(int enabled); - - -/* common I/O functions */ -void ali512x_cio_function(int pin, int special, int inv, int input); -void ali512x_cio_out(int pin, int value); -int ali512x_cio_in(int pin); - -/* misc features */ -void ali512x_set_uart2_irda(int enabled); - -#endif diff --git a/include/andestech/andes_pcu.h b/include/andestech/andes_pcu.h deleted file mode 100644 index d24b82d..0000000 --- a/include/andestech/andes_pcu.h +++ /dev/null @@ -1,354 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Andes Technology Corp - * Macpaul Lin <macpaul@andestech.com> - */ - -/* - * Andes Power Control Unit - */ -#ifndef __ANDES_PCU_H -#define __ANDES_PCU_H - -#ifndef __ASSEMBLY__ - -struct pcs { - unsigned int cr; /* PCSx Configuration (clock scaling) */ - unsigned int parm; /* PCSx Parameter*/ - unsigned int stat1; /* PCSx Status 1 */ - unsigned int stat2; /* PCSx Stusts 2 */ - unsigned int pdd; /* PCSx PDD */ -}; - -struct andes_pcu { - unsigned int rev; /* 0x00 - PCU Revision */ - unsigned int spinfo; /* 0x04 - Scratch Pad Info */ - unsigned int rsvd1[2]; /* 0x08-0x0C: Reserved */ - unsigned int soc_id; /* 0x10 - SoC ID */ - unsigned int soc_ahb; /* 0x14 - SoC AHB configuration */ - unsigned int soc_apb; /* 0x18 - SoC APB configuration */ - unsigned int rsvd2; /* 0x1C */ - unsigned int dcsrcr0; /* 0x20 - Driving Capability - and Slew Rate Control 0 */ - unsigned int dcsrcr1; /* 0x24 - Driving Capability - and Slew Rate Control 1 */ - unsigned int dcsrcr2; /* 0x28 - Driving Capability - and Slew Rate Control 2 */ - unsigned int rsvd3; /* 0x2C */ - unsigned int mfpsr0; /* 0x30 - Multi-Func Port Setting 0 */ - unsigned int mfpsr1; /* 0x34 - Multi-Func Port Setting 1 */ - unsigned int dmaes; /* 0x38 - DMA Engine Selection */ - unsigned int rsvd4; /* 0x3C */ - unsigned int oscc; /* 0x40 - OSC Control */ - unsigned int pwmcd; /* 0x44 - PWM Clock divider */ - unsigned int socmisc; /* 0x48 - SoC Misc. */ - unsigned int rsvd5[13]; /* 0x4C-0x7C: Reserved */ - unsigned int bsmcr; /* 0x80 - BSM Controrl */ - unsigned int bsmst; /* 0x84 - BSM Status */ - unsigned int wes; /* 0x88 - Wakeup Event Sensitivity*/ - unsigned int west; /* 0x8C - Wakeup Event Status */ - unsigned int rsttiming; /* 0x90 - Reset Timing */ - unsigned int intr_st; /* 0x94 - PCU Interrupt Status */ - unsigned int rsvd6[2]; /* 0x98-0x9C: Reserved */ - struct pcs pcs1; /* 0xA0-0xB0: PCS1 (clock scaling) */ - unsigned int pcsrsvd1[3]; /* 0xB4-0xBC: Reserved */ - struct pcs pcs2; /* 0xC0-0xD0: PCS2 (AHB clock gating) */ - unsigned int pcsrsvd2[3]; /* 0xD4-0xDC: Reserved */ - struct pcs pcs3; /* 0xE0-0xF0: PCS3 (APB clock gating) */ - unsigned int pcsrsvd3[3]; /* 0xF4-0xFC: Reserved */ - struct pcs pcs4; /* 0x100-0x110: PCS4 main PLL scaling */ - unsigned int pcsrsvd4[3]; /* 0x114-0x11C: Reserved */ - struct pcs pcs5; /* 0x120-0x130: PCS5 PCI PLL scaling */ - unsigned int pcsrsvd5[3]; /* 0x134-0x13C: Reserved */ - struct pcs pcs6; /* 0x140-0x150: PCS6 AC97 PLL scaling */ - unsigned int pcsrsvd6[3]; /* 0x154-0x15C: Reserved */ - struct pcs pcs7; /* 0x160-0x170: PCS7 GMAC PLL scaling */ - unsigned int pcsrsvd7[3]; /* 0x174-0x17C: Reserved */ - struct pcs pcs8; /* 0x180-0x190: PCS8 voltage scaling */ - unsigned int pcsrsvd8[3]; /* 0x194-0x19C: Reserved */ - struct pcs pcs9; /* 0x1A0-0x1B0: PCS9 power control */ - unsigned int pcsrsvd9[93]; /* 0x1B4-0x3FC: Reserved */ - unsigned int pmspdm[40]; /* 0x400-0x4fC: Power Manager - Scratch Pad Memory 0 */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * PCU Revision Register (ro) - */ -#define ANDES_PCU_REV_NUMBER_PCS(x) (((x) >> 0) & 0xff) -#define ANDES_PCU_REV_VER(x) (((x) >> 16) & 0xffff) - -/* - * Scratch Pad Info Register (ro) - */ -#define ANDES_PCU_SPINFO_SIZE(x) (((x) >> 0) & 0xff) -#define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf) - -/* - * SoC ID Register (ro) - */ -#define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf) -#define ANDES_PCU_SOC_ID_VER_MAJOR(x) (((x) >> 4) & 0xfff) -#define ANDES_PCU_SOC_ID_DEVICEID(x) (((x) >> 16) & 0xffff) - -/* - * SoC AHB Configuration Register (ro) - */ -#define ANDES_PCU_SOC_AHB_AHBC(x) ((x) << 0) -#define ANDES_PCU_SOC_AHB_APBREG(x) ((x) << 1) -#define ANDES_PCU_SOC_AHB_APB(x) ((x) << 2) -#define ANDES_PCU_SOC_AHB_DLM1(x) ((x) << 3) -#define ANDES_PCU_SOC_AHB_SPIROM(x) ((x) << 4) -#define ANDES_PCU_SOC_AHB_DDR2C(x) ((x) << 5) -#define ANDES_PCU_SOC_AHB_DDR2MEM(x) ((x) << 6) -#define ANDES_PCU_SOC_AHB_DMAC(x) ((x) << 7) -#define ANDES_PCU_SOC_AHB_DLM2(x) ((x) << 8) -#define ANDES_PCU_SOC_AHB_GPU(x) ((x) << 9) -#define ANDES_PCU_SOC_AHB_GMAC(x) ((x) << 12) -#define ANDES_PCU_SOC_AHB_IDE(x) ((x) << 13) -#define ANDES_PCU_SOC_AHB_USBOTG(x) ((x) << 14) -#define ANDES_PCU_SOC_AHB_INTC(x) ((x) << 15) -#define ANDES_PCU_SOC_AHB_LPCIO(x) ((x) << 16) -#define ANDES_PCU_SOC_AHB_LPCREG(x) ((x) << 17) -#define ANDES_PCU_SOC_AHB_PCIIO(x) ((x) << 18) -#define ANDES_PCU_SOC_AHB_PCIMEM(x) ((x) << 19) -#define ANDES_PCU_SOC_AHB_L2CC(x) ((x) << 20) -#define ANDES_PCU_SOC_AHB_AHB2AHBREG(x) ((x) << 27) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM0(x) ((x) << 28) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM1(x) ((x) << 29) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM2(x) ((x) << 30) -#define ANDES_PCU_SOC_AHB_AHB2AHBMEM3(x) ((x) << 31) - -/* - * SoC APB Configuration Register (ro) - */ -#define ANDES_PCU_SOC_APB_CFC(x) ((x) << 1) -#define ANDES_PCU_SOC_APB_SSP(x) ((x) << 2) -#define ANDES_PCU_SOC_APB_UART1(x) ((x) << 3) -#define ANDES_PCU_SOC_APB_SDC(x) ((x) << 5) -#define ANDES_PCU_SOC_APB_AC97I2S(x) ((x) << 6) -#define ANDES_PCU_SOC_APB_UART2(x) ((x) << 8) -#define ANDES_PCU_SOC_APB_PCU(x) ((x) << 16) -#define ANDES_PCU_SOC_APB_TMR(x) ((x) << 17) -#define ANDES_PCU_SOC_APB_WDT(x) ((x) << 18) -#define ANDES_PCU_SOC_APB_RTC(x) ((x) << 19) -#define ANDES_PCU_SOC_APB_GPIO(x) ((x) << 20) -#define ANDES_PCU_SOC_APB_I2C(x) ((x) << 22) -#define ANDES_PCU_SOC_APB_PWM(x) ((x) << 23) - -/* - * Driving Capability and Slew Rate Control Register 0 (rw) - */ -#define ANDES_PCU_DCSRCR0_TRIAHB(x) (((x) & 0x1f) << 0) -#define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8) -#define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12) -#define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16) -#define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20) - -/* - * Driving Capability and Slew Rate Control Register 1 (rw) - */ -#define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0) - -/* - * Driving Capability and Slew Rate Control Register 2 (rw) - */ -#define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0) -#define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4) -#define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8) -#define ANDES_PCU_DCSRCR2_SPI(x) (((x) & 0xf) << 12) -#define ANDES_PCU_DCSRCR2_SD(x) (((x) & 0xf) << 16) -#define ANDES_PCU_DCSRCR2_CFC(x) (((x) & 0xf) << 20) -#define ANDES_PCU_DCSRCR2_GPIO(x) (((x) & 0xf) << 24) -#define ANDES_PCU_DCSRCR2_PCU(x) (((x) & 0xf) << 28) - -/* - * Multi-function Port Setting Register 0 (rw) - */ -#define ANDES_PCU_MFPSR0_PCIMODE(x) ((x) << 0) -#define ANDES_PCU_MFPSR0_IDEMODE(x) ((x) << 1) -#define ANDES_PCU_MFPSR0_MINI_TC01(x) ((x) << 2) -#define ANDES_PCU_MFPSR0_AHB_DEBUG(x) ((x) << 3) -#define ANDES_PCU_MFPSR0_AHB_TARGET(x) ((x) << 4) -#define ANDES_PCU_MFPSR0_DEFAULT_IVB(x) (((x) & 0x7) << 28) -#define ANDES_PCU_MFPSR0_DEFAULT_ENDIAN(x) ((x) << 31) - -/* - * Multi-function Port Setting Register 1 (rw) - */ -#define ANDES_PCU_MFPSR1_SUSPEND(x) ((x) << 0) -#define ANDES_PCU_MFPSR1_PWM0(x) ((x) << 1) -#define ANDES_PCU_MFPSR1_PWM1(x) ((x) << 2) -#define ANDES_PCU_MFPSR1_AC97CLKOUT(x) ((x) << 3) -#define ANDES_PCU_MFPSR1_PWREN(x) ((x) << 4) -#define ANDES_PCU_MFPSR1_PME(x) ((x) << 5) -#define ANDES_PCU_MFPSR1_I2C(x) ((x) << 6) -#define ANDES_PCU_MFPSR1_UART1(x) ((x) << 7) -#define ANDES_PCU_MFPSR1_UART2(x) ((x) << 8) -#define ANDES_PCU_MFPSR1_SPI(x) ((x) << 9) -#define ANDES_PCU_MFPSR1_SD(x) ((x) << 10) -#define ANDES_PCU_MFPSR1_GPUPLLSRC(x) ((x) << 27) -#define ANDES_PCU_MFPSR1_DVOMODE(x) ((x) << 28) -#define ANDES_PCU_MFPSR1_HSMP_FAST_REQ(x) ((x) << 29) -#define ANDES_PCU_MFPSR1_AHB_FAST_REQ(x) ((x) << 30) -#define ANDES_PCU_MFPSR1_PMUR_EXT_INT(x) ((x) << 31) - -/* - * DMA Engine Selection Register (rw) - */ -#define ANDES_PCU_DMAES_AC97RX(x) ((x) << 2) -#define ANDES_PCU_DMAES_AC97TX(x) ((x) << 3) -#define ANDES_PCU_DMAES_UART1RX(x) ((x) << 4) -#define ANDES_PCU_DMAES_UART1TX(x) ((x) << 5) -#define ANDES_PCU_DMAES_UART2RX(x) ((x) << 6) -#define ANDES_PCU_DMAES_UART2TX(x) ((x) << 7) -#define ANDES_PCU_DMAES_SDDMA(x) ((x) << 8) -#define ANDES_PCU_DMAES_CFCDMA(x) ((x) << 9) - -/* - * OSC Control Register (rw) - */ -#define ANDES_PCU_OSCC_OSCH_OFF(x) ((x) << 0) -#define ANDES_PCU_OSCC_OSCH_STABLE(x) ((x) << 1) -#define ANDES_PCU_OSCC_OSCH_TRI(x) ((x) << 2) -#define ANDES_PCU_OSCC_OSCH_RANGE(x) (((x) & 0x3) << 4) -#define ANDES_PCU_OSCC_OSCH2_RANGE(x) (((x) & 0x3) << 6) -#define ANDES_PCU_OSCC_OSCH3_RANGE(x) (((x) & 0x3) << 8) - -/* - * PWM Clock Divider Register (rw) - */ -#define ANDES_PCU_PWMCD_PWMDIV(x) (((x) & 0xf) << 0) - -/* - * SoC Misc. Register (rw) - */ -#define ANDES_PCU_SOCMISC_RSCPUA(x) ((x) << 0) -#define ANDES_PCU_SOCMISC_RSCPUB(x) ((x) << 1) -#define ANDES_PCU_SOCMISC_RSPCI(x) ((x) << 2) -#define ANDES_PCU_SOCMISC_USBWAKE(x) ((x) << 3) -#define ANDES_PCU_SOCMISC_EXLM_WAITA(x) (((x) & 0x3) << 4) -#define ANDES_PCU_SOCMISC_EXLM_WAITB(x) (((x) & 0x3) << 6) -#define ANDES_PCU_SOCMISC_DDRPLL_BYPASS(x) (((x) << 8) -#define ANDES_PCU_SOCMISC_300MHZSEL(x) (((x) << 9) -#define ANDES_PCU_SOCMISC_DDRDLL_SRST(x) (((x) << 10) -#define ANDES_PCU_SOCMISC_DDRDDQ_TEST(x) (((x) << 11) -#define ANDES_PCU_SOCMISC_DDRDLL_TEST(x) (((x) << 12) -#define ANDES_PCU_SOCMISC_GPUPLL_BYPASS(x) (((x) << 13) -#define ANDES_PCU_SOCMISC_ENCPUA(x) (((x) << 14) -#define ANDES_PCU_SOCMISC_ENCPUB(x) (((x) << 15) -#define ANDES_PCU_SOCMISC_PWON_PWBTN(x) (((x) << 16) -#define ANDES_PCU_SOCMISC_PWON_GPIO1(x) (((x) << 17) -#define ANDES_PCU_SOCMISC_PWON_GPIO2(x) (((x) << 18) -#define ANDES_PCU_SOCMISC_PWON_GPIO3(x) (((x) << 19) -#define ANDES_PCU_SOCMISC_PWON_GPIO4(x) (((x) << 20) -#define ANDES_PCU_SOCMISC_PWON_GPIO5(x) (((x) << 21) -#define ANDES_PCU_SOCMISC_PWON_WOL(x) (((x) << 22) -#define ANDES_PCU_SOCMISC_PWON_RTC(x) (((x) << 23) -#define ANDES_PCU_SOCMISC_PWON_RTCALM(x) (((x) << 24) -#define ANDES_PCU_SOCMISC_PWON_XDBGIN(x) (((x) << 25) -#define ANDES_PCU_SOCMISC_PWON_PME(x) (((x) << 26) -#define ANDES_PCU_SOCMISC_PWON_PWFAIL(x) (((x) << 27) -#define ANDES_PCU_SOCMISC_CPUA_SRSTED(x) (((x) << 28) -#define ANDES_PCU_SOCMISC_CPUB_SRSTED(x) (((x) << 29) -#define ANDES_PCU_SOCMISC_WD_RESET(x) (((x) << 30) -#define ANDES_PCU_SOCMISC_HW_RESET(x) (((x) << 31) - -/* - * BSM Control Register (rw) - */ -#define ANDES_PCU_BSMCR_LINK0(x) (((x) & 0xf) << 0) -#define ANDES_PCU_BSMCR_LINK1(x) (((x) & 0xf) << 4) -#define ANDES_PCU_BSMCR_SYNCSRC(x) (((x) & 0xf) << 24) -#define ANDES_PCU_BSMCR_CMD(x) (((x) & 0x7) << 28) -#define ANDES_PCU_BSMCR_IE(x) ((x) << 31) - -/* - * BSM Status Register - */ -#define ANDES_PCU_BSMSR_CI0(x) (((x) & 0xf) << 0) -#define ANDES_PCU_BSMSR_CI1(x) (((x) & 0xf) << 4) -#define ANDES_PCU_BSMSR_SYNCSRC(x) (((x) & 0xf) << 24) -#define ANDES_PCU_BSMSR_BSMST(x) (((x) & 0xf) << 28) - -/* - * Wakeup Event Sensitivity Register (rw) - */ -#define ANDES_PCU_WESR_POLOR(x) (((x) & 0xff) << 0) - -/* - * Wakeup Event Status Register (ro) - */ -#define ANDES_PCU_WEST_SIG(x) (((x) & 0xff) << 0) - -/* - * Reset Timing Register - */ -#define ANDES_PCU_RSTTIMING_RG0(x) (((x) & 0xff) << 0) -#define ANDES_PCU_RSTTIMING_RG1(x) (((x) & 0xff) << 8) -#define ANDES_PCU_RSTTIMING_RG2(x) (((x) & 0xff) << 16) -#define ANDES_PCU_RSTTIMING_RG3(x) (((x) & 0xff) << 24) - -/* - * PCU Interrupt Status Register - */ -#define ANDES_PCU_INTR_ST_BSM(x) ((x) << 0) -#define ANDES_PCU_INTR_ST_PCS1(x) ((x) << 1) -#define ANDES_PCU_INTR_ST_PCS2(x) ((x) << 2) -#define ANDES_PCU_INTR_ST_PCS3(x) ((x) << 3) -#define ANDES_PCU_INTR_ST_PCS4(x) ((x) << 4) -#define ANDES_PCU_INTR_ST_PCS5(x) ((x) << 5) -#define ANDES_PCU_INTR_ST_PCS6(x) ((x) << 6) -#define ANDES_PCU_INTR_ST_PCS7(x) ((x) << 7) -#define ANDES_PCU_INTR_ST_PCS8(x) ((x) << 8) -#define ANDES_PCU_INTR_ST_PCS9(x) ((x) << 9) - -/* - * PCSx Configuration Register - */ -#define ANDES_PCU_PCSX_CR_WAKEUP_EN(x) (((x) & 0xff) << 0) -#define ANDES_PCU_PCSX_CR_LW(x) (((x) & 0xf) << 16) -#define ANDES_PCU_PCSX_CR_LS(x) (((x) & 0xf) << 20) -#define ANDES_PCU_PCSX_CR_TYPE(x) (((x) >> 28) & 0x7) /* (ro) */ - -/* - * PCSx Parameter Register (rw) - */ -#define ANDES_PCU_PCSX_PARM_NEXT(x) (((x) & 0xffffff) << 0) -#define ANDES_PCU_PCSX_PARM_SYNCSRC(x) (((x) & 0xf) << 24) -#define ANDES_PCU_PCSX_PARM_PCSCMD(x) (((x) & 0x7) << 28) -#define ANDES_PCU_PCSX_PARM_IE(x) (((x) << 31) - -/* - * PCSx Status Register 1 - */ -#define ANDES_PCU_PCSX_STAT1_ERRNO(x) (((x) & 0xf) << 0) -#define ANDES_PCU_PCSX_STAT1_ST(x) (((x) & 0x7) << 28) - -/* - * PCSx Status Register 2 - */ -#define ANDES_PCU_PCSX_STAT2_CRNTPARM(x) (((x) & 0xffffff) << 0) -#define ANDES_PCU_PCSX_STAT2_SYNCSRC(x) (((x) & 0xf) << 24) - -/* - * PCSx PDD Register - * This is reserved for PCS(1-7) - */ -#define ANDES_PCU_PCS8_PDD_1BYTE(x) (((x) & 0xff) << 0) -#define ANDES_PCU_PCS8_PDD_2BYTE(x) (((x) & 0xff) << 8) -#define ANDES_PCU_PCS8_PDD_3BYTE(x) (((x) & 0xff) << 16) -#define ANDES_PCU_PCS8_PDD_4BYTE(x) (((x) & 0xff) << 24) - -#define ANDES_PCU_PCS9_PDD_TIME1(x) (((x) & 0x3f) << 0) -#define ANDES_PCU_PCS9_PDD_TIME2(x) (((x) & 0x3f) << 6) -#define ANDES_PCU_PCS9_PDD_TIME3(x) (((x) & 0x3f) << 12) -#define ANDES_PCU_PCS9_PDD_TIME4(x) (((x) & 0x3f) << 18) -#define ANDES_PCU_PCS9_PDD_TICKTYPE(x) ((x) << 24) -#define ANDES_PCU_PCS9_PDD_GPU_SRST(x) ((x) << 27) -#define ANDES_PCU_PCS9_PDD_PWOFFTIME(x) (((x) & 0x3) << 28) -#define ANDES_PCU_PCS9_PDD_SUS2DRAM(x) ((x) << 30) -#define ANDES_PCU_PCS9_PDD_CLRPWOFF_FLAG(x) ((x) << 31) - -#endif /* __ANDES_PCU_H */ diff --git a/include/asm-generic/types.h b/include/asm-generic/types.h deleted file mode 100644 index 7c076c5..0000000 --- a/include/asm-generic/types.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _ASM_GENERIC_TYPES_H -#define _ASM_GENERIC_TYPES_H -/* - * int-ll64 is used everywhere now. - */ -#include <asm-generic/int-ll64.h> - -#endif /* _ASM_GENERIC_TYPES_H */ diff --git a/include/asm-generic/unaligned.h b/include/asm-generic/unaligned.h index 3d33a5a..9e5d93e 100644 --- a/include/asm-generic/unaligned.h +++ b/include/asm-generic/unaligned.h @@ -1,24 +1,81 @@ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef _GENERIC_UNALIGNED_H #define _GENERIC_UNALIGNED_H #include <asm/byteorder.h> -#include <linux/unaligned/le_byteshift.h> -#include <linux/unaligned/be_byteshift.h> -#include <linux/unaligned/generic.h> - -/* - * Select endianness - */ -#if defined(__LITTLE_ENDIAN) -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#elif defined(__BIG_ENDIAN) -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#else -#error invalid endian -#endif +#define __get_unaligned_t(type, ptr) ({ \ + const struct { type x; } __packed * __pptr = (typeof(__pptr))(ptr); \ + __pptr->x; \ +}) + +#define __put_unaligned_t(type, val, ptr) do { \ + struct { type x; } __packed * __pptr = (typeof(__pptr))(ptr); \ + __pptr->x = (val); \ +} while (0) + +#define get_unaligned(ptr) __get_unaligned_t(typeof(*(ptr)), (ptr)) +#define put_unaligned(val, ptr) __put_unaligned_t(typeof(*(ptr)), (val), (ptr)) + +static inline u16 get_unaligned_le16(const void *p) +{ + return le16_to_cpu(__get_unaligned_t(__le16, p)); +} + +static inline u32 get_unaligned_le32(const void *p) +{ + return le32_to_cpu(__get_unaligned_t(__le32, p)); +} + +static inline u64 get_unaligned_le64(const void *p) +{ + return le64_to_cpu(__get_unaligned_t(__le64, p)); +} + +static inline void put_unaligned_le16(u16 val, void *p) +{ + __put_unaligned_t(__le16, cpu_to_le16(val), p); +} + +static inline void put_unaligned_le32(u32 val, void *p) +{ + __put_unaligned_t(__le32, cpu_to_le32(val), p); +} + +static inline void put_unaligned_le64(u64 val, void *p) +{ + __put_unaligned_t(__le64, cpu_to_le64(val), p); +} + +static inline u16 get_unaligned_be16(const void *p) +{ + return be16_to_cpu(__get_unaligned_t(__be16, p)); +} + +static inline u32 get_unaligned_be32(const void *p) +{ + return be32_to_cpu(__get_unaligned_t(__be32, p)); +} + +static inline u64 get_unaligned_be64(const void *p) +{ + return be64_to_cpu(__get_unaligned_t(__be64, p)); +} + +static inline void put_unaligned_be16(u16 val, void *p) +{ + __put_unaligned_t(__be16, cpu_to_be16(val), p); +} + +static inline void put_unaligned_be32(u32 val, void *p) +{ + __put_unaligned_t(__be32, cpu_to_be32(val), p); +} + +static inline void put_unaligned_be64(u64 val, void *p) +{ + __put_unaligned_t(__be64, cpu_to_be64(val), p); +} /* Allow unaligned memory access */ void allow_unaligned(void); diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h index 9d2a225..2a136b9 100644 --- a/include/config_distro_bootcmd.h +++ b/include/config_distro_bootcmd.h @@ -35,11 +35,15 @@ #devtypel "_boot=" \ BOOTENV_SHARED_BLKDEV_BODY(devtypel) +#define BOOTENV_DEV_BLKDEV_NONE(devtypeu, devtypel, instance) + #define BOOTENV_DEV_BLKDEV(devtypeu, devtypel, instance) \ "bootcmd_" #devtypel #instance "=" \ "devnum=" #instance "; " \ "run " #devtypel "_boot\0" +#define BOOTENV_DEV_NAME_BLKDEV_NONE(devtypeu, devtypel, instance) + #define BOOTENV_DEV_NAME_BLKDEV(devtypeu, devtypel, instance) \ #devtypel #instance " " @@ -59,6 +63,10 @@ #define BOOTENV_SHARED_MMC BOOTENV_SHARED_BLKDEV(mmc) #define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_SHARED_MMC +#define BOOTENV_DEV_MMC BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_MMC BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_SHARED_MMC #define BOOTENV_DEV_MMC \ @@ -190,6 +198,10 @@ #define BOOTENV_SHARED_SATA BOOTENV_SHARED_BLKDEV(sata) #define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_SHARED_SATA +#define BOOTENV_DEV_SATA BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_SATA BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_SHARED_SATA #define BOOTENV_DEV_SATA \ @@ -293,6 +305,11 @@ BOOTENV_SHARED_BLKDEV_BODY(usb) #define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV #define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_RUN_NET_USB_START +#define BOOTENV_SHARED_USB +#define BOOTENV_DEV_USB BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_USB BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_RUN_NET_USB_START #define BOOTENV_SHARED_USB @@ -395,6 +412,9 @@ "\0" #define BOOTENV_DEV_NAME_DHCP(devtypeu, devtypel, instance) \ "dhcp " +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_DEV_DHCP BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_DHCP BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_DEV_DHCP \ BOOT_TARGET_DEVICES_references_DHCP_without_CONFIG_CMD_DHCP @@ -413,6 +433,9 @@ "fi\0" #define BOOTENV_DEV_NAME_PXE(devtypeu, devtypel, instance) \ "pxe " +#elif defined(CONFIG_SPL_BUILD) +#define BOOTENV_DEV_PXE BOOTENV_DEV_BLKDEV_NONE +#define BOOTENV_DEV_NAME_PXE BOOTENV_DEV_NAME_BLKDEV_NONE #else #define BOOTENV_DEV_PXE \ BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_DHCP_or_PXE diff --git a/include/configs/ae350.h b/include/configs/ae350.h index b566ecf..23e4801 100644 --- a/include/configs/ae350.h +++ b/include/configs/ae350.h @@ -83,11 +83,15 @@ #include <config_distro_bootcmd.h> #define CFG_EXTRA_ENV_SETTINGS \ - "kernel_addr_r=0x00080000\0" \ - "pxefile_addr_r=0x01f00000\0" \ - "scriptaddr=0x01f00000\0" \ - "fdt_addr_r=0x02000000\0" \ - "ramdisk_addr_r=0x02800000\0" \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "kernel_addr_r=0x00600000\0" \ + "kernel_comp_addr_r=0x04600000\0" \ + "kernel_comp_size=0x04000000\0" \ + "pxefile_addr_r=0x08600000\0" \ + "scriptaddr=0x08700000\0" \ + "fdt_addr_r=0x08800000\0" \ + "ramdisk_addr_r=0x08900000\0" \ BOOTENV #endif /* __CONFIG_H */ diff --git a/include/configs/eagle.h b/include/configs/eagle.h deleted file mode 100644 index c751f75..0000000 --- a/include/configs/eagle.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * include/configs/eagle.h - * This file is Eagle board configuration. - * - * Copyright (C) 2015 Renesas Electronics Corporation - */ - -#ifndef __EAGLE_H -#define __EAGLE_H - -#include "rcar-gen3-common.h" - -/* Environment compatibility */ - -/* Board Clock */ -/* XTAL_CLK : 33.33MHz */ - -#endif /* __EAGLE_H */ diff --git a/include/configs/lx2160ardb.h b/include/configs/lx2160ardb.h index 8cc4e0d..6404b35 100644 --- a/include/configs/lx2160ardb.h +++ b/include/configs/lx2160ardb.h @@ -11,6 +11,11 @@ /* RTC */ #define CFG_SYS_RTC_BUS_NUM 4 +#if defined(CONFIG_FSL_MC_ENET) +#define AQR113C_PHY_ADDR1 0x0 +#define AQR113C_PHY_ADDR2 0x08 +#endif + /* EMC2305 */ #define I2C_MUX_CH_EMC2305 0x09 #define I2C_EMC2305_ADDR 0x4D diff --git a/include/configs/meson64.h b/include/configs/meson64.h index 92446012..801cdae 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -11,6 +11,9 @@ #if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A)) #define GICD_BASE 0xffc01000 #define GICC_BASE 0xffc02000 +#elif defined(CONFIG_MESON_A1) +#define GICD_BASE 0xff901000 +#define GICC_BASE 0xff902000 #else /* MESON GXL and GXBB */ #define GICD_BASE 0xc4301000 #define GICC_BASE 0xc4302000 diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index 34856d3..9bf01ca 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -36,6 +36,4 @@ #define CFG_SYS_UBOOT_BASE (CFG_SYS_FLASH_BASE + \ CONFIG_SPL_PAD_TO) -/* For splashcreen */ - #endif /* __CONFIG_H */ diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 7db72a1..29a1197 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -92,19 +92,6 @@ "run distro_bootcmd;" \ "fi;\0" -#ifdef CONFIG_FASTBOOT_CMD_OEM_FORMAT -/* eMMC default partitions for fastboot command: oem format */ -#define STM32MP_PARTS_DEFAULT \ - "partitions=" \ - "name=ssbl,size=2M;" \ - "name=bootfs,size=64MB,bootable;" \ - "name=vendorfs,size=16M;" \ - "name=rootfs,size=746M;" \ - "name=userfs,size=-\0" -#else -#define STM32MP_PARTS_DEFAULT -#endif - #define STM32MP_EXTRA \ "env_check=if env info -p -d -q; then env save; fi\0" \ "boot_net_usb_start=true\0" @@ -138,7 +125,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ STM32MP_BOOTCMD \ - STM32MP_PARTS_DEFAULT \ BOOTENV \ STM32MP_EXTRA \ STM32MP_BOARD_EXTRA_ENV diff --git a/include/configs/stm32mp15_st_common.h b/include/configs/stm32mp15_st_common.h index 866cd7a..b45982a 100644 --- a/include/configs/stm32mp15_st_common.h +++ b/include/configs/stm32mp15_st_common.h @@ -47,7 +47,6 @@ #define CFG_EXTRA_ENV_SETTINGS \ STM32MP_MEM_LAYOUT \ ST_STM32MP1_BOOTCMD \ - STM32MP_PARTS_DEFAULT \ BOOTENV \ STM32MP_EXTRA \ STM32MP_BOARD_EXTRA_ENV diff --git a/include/configs/synquacer.h b/include/configs/synquacer.h index 8f44c6f..cd7359c 100644 --- a/include/configs/synquacer.h +++ b/include/configs/synquacer.h @@ -40,19 +40,29 @@ /* Since U-Boot 64bit PCIe support is limited, disable 64bit MMIO support */ +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE +#define DEFAULT_DFU_ALT_INFO +#else #define DEFAULT_DFU_ALT_INFO "dfu_alt_info=" \ "mtd nor1=u-boot.bin raw 200000 100000;" \ "fip.bin raw 180000 78000;" \ "optee.bin raw 500000 100000\0" +#endif /* GUIDs for capsule updatable firmware images */ #define DEVELOPERBOX_UBOOT_IMAGE_GUID \ EFI_GUID(0x53a92e83, 0x4ef4, 0x473a, 0x8b, 0x0d, \ 0xb5, 0xd8, 0xc7, 0xb2, 0xd6, 0x00) +#ifdef CONFIG_FWU_MULTI_BANK_UPDATE +#define DEVELOPERBOX_FIP_IMAGE_GUID \ + EFI_GUID(0x7d6dc310, 0x52ca, 0x43b8, 0xb7, 0xb9, \ + 0xf9, 0xd6, 0xc5, 0x01, 0xd1, 0x08) +#else #define DEVELOPERBOX_FIP_IMAGE_GUID \ EFI_GUID(0x880866e9, 0x84ba, 0x4793, 0xa9, 0x08, \ 0x33, 0xe0, 0xb9, 0x16, 0xf3, 0x98) +#endif #define DEVELOPERBOX_OPTEE_IMAGE_GUID \ EFI_GUID(0xc1b629f1, 0xce0e, 0x4894, 0x82, 0xbf, \ diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h deleted file mode 100644 index ac6d46f..0000000 --- a/include/configs/ti816x_evm.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * ti816x_evm.h - * - * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> - * Antoine Tenart, <atenart@adeneo-embedded.com> - */ - -#ifndef __CONFIG_TI816X_EVM_H -#define __CONFIG_TI816X_EVM_H - -#include <configs/ti_armv7_omap.h> -#include <asm/arch/omap.h> - -#define CFG_EXTRA_ENV_SETTINGS \ - DEFAULT_LINUX_BOOT_ENV - -/* Clock Defines */ -#define V_OSCK 24000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) - -#define CFG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */ -#define CFG_SYS_SDRAM_BASE 0x80000000 - -/** - * Platform/Board specific defs - */ -#define CFG_SYS_TIMERBASE 0x4802E000 - -/* - * NS16550 Configuration - */ -#define CFG_SYS_NS16550_CLK (48000000) -#define CFG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */ - -/* allow overwriting serial config and ethaddr */ - - -/* - * GPMC NAND block. We support 1 device and the physical address to - * access CS0 at is 0x8000000. - */ -#define CFG_SYS_NAND_BASE 0x8000000 - -/* NAND: SPL related configs */ - -/* NAND: device related configs */ -/* NAND: driver related configs */ -#define CFG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ - 10, 11, 12, 13, 14, 15, 16, 17, \ - 18, 19, 20, 21, 22, 23, 24, 25, \ - 26, 27, 28, 29, 30, 31, 32, 33, \ - 34, 35, 36, 37, 38, 39, 40, 41, \ - 42, 43, 44, 45, 46, 47, 48, 49, \ - 50, 51, 52, 53, 54, 55, 56, 57, } - -#define CFG_SYS_NAND_ECCSIZE 512 -#define CFG_SYS_NAND_ECCBYTES 14 - -/* SPL */ -/* Defines for SPL */ - -#endif diff --git a/include/configs/v3hsk.h b/include/configs/v3hsk.h new file mode 100644 index 0000000..58c2e88 --- /dev/null +++ b/include/configs/v3hsk.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * include/configs/v3hsk.h + * This file is V3HSK board configuration. + * + * Copyright (C) 2019 Renesas Electronics Corporation + * Copyright (C) 2019 Cogent Embedded, Inc. + */ + +#ifndef __V3HSK_H +#define __V3HSK_H + +#include "rcar-gen3-common.h" + +/* Environment compatibility */ + +/* SH Ether */ +#define CFG_SH_ETHER_USE_PORT 0 +#define CFG_SH_ETHER_PHY_ADDR 0x0 +#define CFG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID +#define CFG_SH_ETHER_CACHE_WRITEBACK +#define CFG_SH_ETHER_CACHE_INVALIDATE +#define CFG_SH_ETHER_ALIGNE_SIZE 64 + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ + +#endif /* __V3HSK_H */ diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index 011f003..995427d 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -60,6 +60,9 @@ "scriptaddr=0x20000000\0" \ "ramdisk_addr_r=0x02100000\0" \ "script_size_f=0x80000\0" \ + "stdin=serial\0" \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" \ #if defined(CONFIG_MMC_SDHCI_ZYNQ) # define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) func(MMC, mmc, 1) diff --git a/include/dp83848.h b/include/dp83848.h deleted file mode 100644 index f1bc3d8..0000000 --- a/include/dp83848.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * DP83848 ethernet Physical layer - * - * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> - * - */ - - -/* National Semiconductor PHYSICAL LAYER TRANSCEIVER DP83848 */ - -#define DP83848_CTL_REG 0x0 /* Basic Mode Control Reg */ -#define DP83848_STAT_REG 0x1 /* Basic Mode Status Reg */ -#define DP83848_PHYID1_REG 0x2 /* PHY Idendifier Reg 1 */ -#define DP83848_PHYID2_REG 0x3 /* PHY Idendifier Reg 2 */ -#define DP83848_ANA_REG 0x4 /* Auto_Neg Advt Reg */ -#define DP83848_ANLPA_REG 0x5 /* Auto_neg Link Partner Ability Reg */ -#define DP83848_ANE_REG 0x6 /* Auto-neg Expansion Reg */ -#define DP83848_PHY_STAT_REG 0x10 /* PHY Status Register */ -#define DP83848_PHY_INTR_CTRL_REG 0x11 /* PHY Interrupt Control Register */ -#define DP83848_PHY_CTRL_REG 0x19 /* PHY Status Register */ - -/*--Bit definitions: DP83848_CTL_REG */ -#define DP83848_RESET (1 << 15) /* 1= S/W Reset */ -#define DP83848_LOOPBACK (1 << 14) /* 1=loopback Enabled */ -#define DP83848_SPEED_SELECT (1 << 13) -#define DP83848_AUTONEG (1 << 12) -#define DP83848_POWER_DOWN (1 << 11) -#define DP83848_ISOLATE (1 << 10) -#define DP83848_RESTART_AUTONEG (1 << 9) -#define DP83848_DUPLEX_MODE (1 << 8) -#define DP83848_COLLISION_TEST (1 << 7) - -/*--Bit definitions: DP83848_STAT_REG */ -#define DP83848_100BASE_T4 (1 << 15) -#define DP83848_100BASE_TX_FD (1 << 14) -#define DP83848_100BASE_TX_HD (1 << 13) -#define DP83848_10BASE_T_FD (1 << 12) -#define DP83848_10BASE_T_HD (1 << 11) -#define DP83848_MF_PREAMB_SUPPR (1 << 6) -#define DP83848_AUTONEG_COMP (1 << 5) -#define DP83848_RMT_FAULT (1 << 4) -#define DP83848_AUTONEG_ABILITY (1 << 3) -#define DP83848_LINK_STATUS (1 << 2) -#define DP83848_JABBER_DETECT (1 << 1) -#define DP83848_EXTEND_CAPAB (1 << 0) - -/*--definitions: DP83848_PHYID1 */ -#define DP83848_PHYID1_OUI 0x2000 -#define DP83848_PHYID2_OUI 0x5c90 - -/*--Bit definitions: DP83848_ANAR, DP83848_ANLPAR */ -#define DP83848_NP (1 << 15) -#define DP83848_ACK (1 << 14) -#define DP83848_RF (1 << 13) -#define DP83848_PAUSE (1 << 10) -#define DP83848_T4 (1 << 9) -#define DP83848_TX_FDX (1 << 8) -#define DP83848_TX_HDX (1 << 7) -#define DP83848_10_FDX (1 << 6) -#define DP83848_10_HDX (1 << 5) -#define DP83848_AN_IEEE_802_3 0x0001 - -/*--Bit definitions: DP83848_ANER */ -#define DP83848_PDF (1 << 4) -#define DP83848_LP_NP_ABLE (1 << 3) -#define DP83848_NP_ABLE (1 << 2) -#define DP83848_PAGE_RX (1 << 1) -#define DP83848_LP_AN_ABLE (1 << 0) - -/*--Bit definitions: DP83848_PHY_STAT */ -#define DP83848_RX_ERR_LATCH (1 << 13) -#define DP83848_POLARITY_STAT (1 << 12) -#define DP83848_FALSE_CAR_SENSE (1 << 11) -#define DP83848_SIG_DETECT (1 << 10) -#define DP83848_DESCRAM_LOCK (1 << 9) -#define DP83848_PAGE_RCV (1 << 8) -#define DP83848_PHY_RMT_FAULT (1 << 6) -#define DP83848_JABBER (1 << 5) -#define DP83848_AUTONEG_COMPLETE (1 << 4) -#define DP83848_LOOPBACK_STAT (1 << 3) -#define DP83848_DUPLEX (1 << 2) -#define DP83848_SPEED (1 << 1) -#define DP83848_LINK (1 << 0) diff --git a/include/ds1722.h b/include/ds1722.h deleted file mode 100644 index e115696..0000000 --- a/include/ds1722.h +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ - -#ifndef _DS1722_H_ -#define _DS1722_H_ - -#define DS1722_RESOLUTION_8BIT 0x0 -#define DS1722_RESOLUTION_9BIT 0x1 -#define DS1722_RESOLUTION_10BIT 0x2 -#define DS1722_RESOLUTION_11BIT 0x3 -#define DS1722_RESOLUTION_12BIT 0x4 - -int ds1722_probe(int dev); - -#endif /* _DS1722_H_ */ diff --git a/include/dt-bindings/clock/microchip-mpfs-clock.h b/include/dt-bindings/clock/microchip-mpfs-clock.h index c7ed0a8..79775a5 100644 --- a/include/dt-bindings/clock/microchip-mpfs-clock.h +++ b/include/dt-bindings/clock/microchip-mpfs-clock.h @@ -1,7 +1,7 @@ -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ /* - * Copyright (C) 2020 Microchip Technology Inc. - * Padmarao Begari <padmarao.begari@microchip.com> + * Daire McNamara,<daire.mcnamara@microchip.com> + * Copyright (C) 2020-2022 Microchip Technology Inc. All rights reserved. */ #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ @@ -45,4 +45,27 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +/* Clock Conditioning Circuitry Clock IDs */ + +#define CLK_CCC_PLL0 0 +#define CLK_CCC_PLL1 1 +#define CLK_CCC_DLL0 2 +#define CLK_CCC_DLL1 3 + +#define CLK_CCC_PLL0_OUT0 4 +#define CLK_CCC_PLL0_OUT1 5 +#define CLK_CCC_PLL0_OUT2 6 +#define CLK_CCC_PLL0_OUT3 7 + +#define CLK_CCC_PLL1_OUT0 8 +#define CLK_CCC_PLL1_OUT1 9 +#define CLK_CCC_PLL1_OUT2 10 +#define CLK_CCC_PLL1_OUT3 11 + +#define CLK_CCC_DLL0_OUT0 12 +#define CLK_CCC_DLL0_OUT1 13 + +#define CLK_CCC_DLL1_OUT0 14 +#define CLK_CCC_DLL1_OUT1 15 + #endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ diff --git a/include/dt-bindings/clock/stm32mp13-clks.h b/include/dt-bindings/clock/stm32mp13-clks.h index 799dee5..da4cb75 100644 --- a/include/dt-bindings/clock/stm32mp13-clks.h +++ b/include/dt-bindings/clock/stm32mp13-clks.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Copyright (C) STMicroelectronics 2020 - All Rights Reserved * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. */ diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h new file mode 100644 index 0000000..40e57a5 --- /dev/null +++ b/include/dt-bindings/gpio/meson-a1-gpio.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ +/* + * Copyright (c) 2019 Amlogic, Inc. All rights reserved. + * Author: Qianggui Song <qianggui.song@amlogic.com> + */ + +#ifndef _DT_BINDINGS_MESON_A1_GPIO_H +#define _DT_BINDINGS_MESON_A1_GPIO_H + +#define GPIOP_0 0 +#define GPIOP_1 1 +#define GPIOP_2 2 +#define GPIOP_3 3 +#define GPIOP_4 4 +#define GPIOP_5 5 +#define GPIOP_6 6 +#define GPIOP_7 7 +#define GPIOP_8 8 +#define GPIOP_9 9 +#define GPIOP_10 10 +#define GPIOP_11 11 +#define GPIOP_12 12 +#define GPIOB_0 13 +#define GPIOB_1 14 +#define GPIOB_2 15 +#define GPIOB_3 16 +#define GPIOB_4 17 +#define GPIOB_5 18 +#define GPIOB_6 19 +#define GPIOX_0 20 +#define GPIOX_1 21 +#define GPIOX_2 22 +#define GPIOX_3 23 +#define GPIOX_4 24 +#define GPIOX_5 25 +#define GPIOX_6 26 +#define GPIOX_7 27 +#define GPIOX_8 28 +#define GPIOX_9 29 +#define GPIOX_10 30 +#define GPIOX_11 31 +#define GPIOX_12 32 +#define GPIOX_13 33 +#define GPIOX_14 34 +#define GPIOX_15 35 +#define GPIOX_16 36 +#define GPIOF_0 37 +#define GPIOF_1 38 +#define GPIOF_2 39 +#define GPIOF_3 40 +#define GPIOF_4 41 +#define GPIOF_5 42 +#define GPIOF_6 43 +#define GPIOF_7 44 +#define GPIOF_8 45 +#define GPIOF_9 46 +#define GPIOF_10 47 +#define GPIOF_11 48 +#define GPIOF_12 49 +#define GPIOA_0 50 +#define GPIOA_1 51 +#define GPIOA_2 52 +#define GPIOA_3 53 +#define GPIOA_4 54 +#define GPIOA_5 55 +#define GPIOA_6 56 +#define GPIOA_7 57 +#define GPIOA_8 58 +#define GPIOA_9 59 +#define GPIOA_10 60 +#define GPIOA_11 61 + +#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */ diff --git a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h b/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h deleted file mode 100644 index eba1bac..0000000 --- a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h +++ /dev/null @@ -1,196 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (c) 2020-2021 Microchip Technology Inc */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H - -#define PLIC_INT_INVALID 0 -#define PLIC_INT_L2_METADATA_CORR 1 -#define PLIC_INT_L2_METADATA_UNCORR 2 -#define PLIC_INT_L2_DATA_CORR 3 -#define PLIC_INT_L2_DATA_UNCORR 4 -#define PLIC_INT_DMA_CH0_DONE 5 -#define PLIC_INT_DMA_CH0_ERR 6 -#define PLIC_INT_DMA_CH1_DONE 7 -#define PLIC_INT_DMA_CH1_ERR 8 -#define PLIC_INT_DMA_CH2_DONE 9 -#define PLIC_INT_DMA_CH2_ERR 10 -#define PLIC_INT_DMA_CH3_DONE 11 -#define PLIC_INT_DMA_CH3_ERR 12 - -#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0 13 -#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1 14 -#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2 15 -#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3 16 -#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4 17 -#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5 18 -#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6 19 -#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7 20 -#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8 21 -#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9 22 -#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10 23 -#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11 24 -#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12 25 -#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13 26 -#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14 27 -#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15 28 -#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16 29 -#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17 30 -#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18 31 -#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19 32 -#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20 33 -#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21 34 -#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22 35 -#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23 36 -#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24 37 -#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25 38 -#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26 39 -#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27 40 -#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28 41 -#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29 42 -#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30 43 -#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31 44 -#define PLIC_INT_GPIO1_BIT18 45 -#define PLIC_INT_GPIO1_BIT19 46 -#define PLIC_INT_GPIO1_BIT20 47 -#define PLIC_INT_GPIO1_BIT21 48 -#define PLIC_INT_GPIO1_BIT22 49 -#define PLIC_INT_GPIO1_BIT23 50 -#define PLIC_INT_GPIO0_NON_DIRECT 51 -#define PLIC_INT_GPIO1_NON_DIRECT 52 -#define PLIC_INT_GPIO2_NON_DIRECT 53 -#define PLIC_INT_SPI0 54 -#define PLIC_INT_SPI1 55 -#define PLIC_INT_CAN0 56 -#define PLIC_INT_CAN1 57 -#define PLIC_INT_I2C0_MAIN 58 -#define PLIC_INT_I2C0_ALERT 59 -#define PLIC_INT_I2C0_SUS 60 -#define PLIC_INT_I2C1_MAIN 61 -#define PLIC_INT_I2C1_ALERT 62 -#define PLIC_INT_I2C1_SUS 63 -#define PLIC_INT_MAC0_INT 64 -#define PLIC_INT_MAC0_QUEUE1 65 -#define PLIC_INT_MAC0_QUEUE2 66 -#define PLIC_INT_MAC0_QUEUE3 67 -#define PLIC_INT_MAC0_EMAC 68 -#define PLIC_INT_MAC0_MMSL 69 -#define PLIC_INT_MAC1_INT 70 -#define PLIC_INT_MAC1_QUEUE1 71 -#define PLIC_INT_MAC1_QUEUE2 72 -#define PLIC_INT_MAC1_QUEUE3 73 -#define PLIC_INT_MAC1_EMAC 74 -#define PLIC_INT_MAC1_MMSL 75 -#define PLIC_INT_DDRC_TRAIN 76 -#define PLIC_INT_SCB_INTERRUPT 77 -#define PLIC_INT_ECC_ERROR 78 -#define PLIC_INT_ECC_CORRECT 79 -#define PLIC_INT_RTC_WAKEUP 80 -#define PLIC_INT_RTC_MATCH 81 -#define PLIC_INT_TIMER1 82 -#define PLIC_INT_TIMER2 83 -#define PLIC_INT_ENVM 84 -#define PLIC_INT_QSPI 85 -#define PLIC_INT_USB_DMA 86 -#define PLIC_INT_USB_MC 87 -#define PLIC_INT_MMC_MAIN 88 -#define PLIC_INT_MMC_WAKEUP 89 -#define PLIC_INT_MMUART0 90 -#define PLIC_INT_MMUART1 91 -#define PLIC_INT_MMUART2 92 -#define PLIC_INT_MMUART3 93 -#define PLIC_INT_MMUART4 94 -#define PLIC_INT_G5C_DEVRST 95 -#define PLIC_INT_G5C_MESSAGE 96 -#define PLIC_INT_USOC_VC_INTERRUPT 97 -#define PLIC_INT_USOC_SMB_INTERRUPT 98 -#define PLIC_INT_E51_0_MAINTENACE 99 -#define PLIC_INT_WDOG0_MRVP 100 -#define PLIC_INT_WDOG1_MRVP 101 -#define PLIC_INT_WDOG2_MRVP 102 -#define PLIC_INT_WDOG3_MRVP 103 -#define PLIC_INT_WDOG4_MRVP 104 -#define PLIC_INT_WDOG0_TOUT 105 -#define PLIC_INT_WDOG1_TOUT 106 -#define PLIC_INT_WDOG2_TOUT 107 -#define PLIC_INT_WDOG3_TOUT 108 -#define PLIC_INT_WDOG4_TOUT 109 -#define PLIC_INT_G5C_MSS_SPI 110 -#define PLIC_INT_VOLT_TEMP_ALARM 111 -#define PLIC_INT_ATHENA_COMPLETE 112 -#define PLIC_INT_ATHENA_ALARM 113 -#define PLIC_INT_ATHENA_BUS_ERROR 114 -#define PLIC_INT_USOC_AXIC_US 115 -#define PLIC_INT_USOC_AXIC_DS 116 -#define PLIC_INT_SPARE 117 -#define PLIC_INT_FABRIC_F2H_0 118 -#define PLIC_INT_FABRIC_F2H_1 119 -#define PLIC_INT_FABRIC_F2H_2 120 -#define PLIC_INT_FABRIC_F2H_3 121 -#define PLIC_INT_FABRIC_F2H_4 122 -#define PLIC_INT_FABRIC_F2H_5 123 -#define PLIC_INT_FABRIC_F2H_6 124 -#define PLIC_INT_FABRIC_F2H_7 125 -#define PLIC_INT_FABRIC_F2H_8 126 -#define PLIC_INT_FABRIC_F2H_9 127 -#define PLIC_INT_FABRIC_F2H_10 128 -#define PLIC_INT_FABRIC_F2H_11 129 -#define PLIC_INT_FABRIC_F2H_12 130 -#define PLIC_INT_FABRIC_F2H_13 131 -#define PLIC_INT_FABRIC_F2H_14 132 -#define PLIC_INT_FABRIC_F2H_15 133 -#define PLIC_INT_FABRIC_F2H_16 134 -#define PLIC_INT_FABRIC_F2H_17 135 -#define PLIC_INT_FABRIC_F2H_18 136 -#define PLIC_INT_FABRIC_F2H_19 137 -#define PLIC_INT_FABRIC_F2H_20 138 -#define PLIC_INT_FABRIC_F2H_21 139 -#define PLIC_INT_FABRIC_F2H_22 140 -#define PLIC_INT_FABRIC_F2H_23 141 -#define PLIC_INT_FABRIC_F2H_24 142 -#define PLIC_INT_FABRIC_F2H_25 143 -#define PLIC_INT_FABRIC_F2H_26 144 -#define PLIC_INT_FABRIC_F2H_27 145 -#define PLIC_INT_FABRIC_F2H_28 146 -#define PLIC_INT_FABRIC_F2H_29 147 -#define PLIC_INT_FABRIC_F2H_30 148 -#define PLIC_INT_FABRIC_F2H_31 149 -#define PLIC_INT_FABRIC_F2H_32 150 -#define PLIC_INT_FABRIC_F2H_33 151 -#define PLIC_INT_FABRIC_F2H_34 152 -#define PLIC_INT_FABRIC_F2H_35 153 -#define PLIC_INT_FABRIC_F2H_36 154 -#define PLIC_INT_FABRIC_F2H_37 155 -#define PLIC_INT_FABRIC_F2H_38 156 -#define PLIC_INT_FABRIC_F2H_39 157 -#define PLIC_INT_FABRIC_F2H_40 158 -#define PLIC_INT_FABRIC_F2H_41 159 -#define PLIC_INT_FABRIC_F2H_42 160 -#define PLIC_INT_FABRIC_F2H_43 161 -#define PLIC_INT_FABRIC_F2H_44 162 -#define PLIC_INT_FABRIC_F2H_45 163 -#define PLIC_INT_FABRIC_F2H_46 164 -#define PLIC_INT_FABRIC_F2H_47 165 -#define PLIC_INT_FABRIC_F2H_48 166 -#define PLIC_INT_FABRIC_F2H_49 167 -#define PLIC_INT_FABRIC_F2H_50 168 -#define PLIC_INT_FABRIC_F2H_51 169 -#define PLIC_INT_FABRIC_F2H_52 170 -#define PLIC_INT_FABRIC_F2H_53 171 -#define PLIC_INT_FABRIC_F2H_54 172 -#define PLIC_INT_FABRIC_F2H_55 173 -#define PLIC_INT_FABRIC_F2H_56 174 -#define PLIC_INT_FABRIC_F2H_57 175 -#define PLIC_INT_FABRIC_F2H_58 176 -#define PLIC_INT_FABRIC_F2H_59 177 -#define PLIC_INT_FABRIC_F2H_60 178 -#define PLIC_INT_FABRIC_F2H_61 179 -#define PLIC_INT_FABRIC_F2H_62 180 -#define PLIC_INT_FABRIC_F2H_63 181 -#define PLIC_INT_BUS_ERROR_UNIT_HART_0 182 -#define PLIC_INT_BUS_ERROR_UNIT_HART_1 183 -#define PLIC_INT_BUS_ERROR_UNIT_HART_2 184 -#define PLIC_INT_BUS_ERROR_UNIT_HART_3 185 -#define PLIC_INT_BUS_ERROR_UNIT_HART_4 186 - -#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */ diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h b/include/dt-bindings/interrupt-controller/riscv-hart.h deleted file mode 100644 index c4331b8..0000000 --- a/include/dt-bindings/interrupt-controller/riscv-hart.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */ -/* Copyright (c) 2020-2021 Microchip Technology Inc */ - -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H - -#define HART_INT_U_SOFT 0 -#define HART_INT_S_SOFT 1 -#define HART_INT_M_SOFT 3 -#define HART_INT_U_TIMER 4 -#define HART_INT_S_TIMER 5 -#define HART_INT_M_TIMER 7 -#define HART_INT_U_EXT 8 -#define HART_INT_S_EXT 9 -#define HART_INT_M_EXT 11 - -#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */ diff --git a/include/dt-bindings/media/video-interfaces.h b/include/dt-bindings/media/video-interfaces.h new file mode 100644 index 0000000..68ac4e0 --- /dev/null +++ b/include/dt-bindings/media/video-interfaces.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Copyright (C) 2022 Laurent Pinchart <laurent.pinchart@ideasonboard.com> + */ + +#ifndef __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ +#define __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ + +#define MEDIA_BUS_TYPE_CSI2_CPHY 1 +#define MEDIA_BUS_TYPE_CSI1 2 +#define MEDIA_BUS_TYPE_CCP2 3 +#define MEDIA_BUS_TYPE_CSI2_DPHY 4 +#define MEDIA_BUS_TYPE_PARALLEL 5 +#define MEDIA_BUS_TYPE_BT656 6 + +#endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */ diff --git a/include/dt-bindings/memory/bcm-ns3-mc.h b/include/dt-bindings/memory/bcm-ns3-mc.h index 84795ec..d2478d9 100644 --- a/include/dt-bindings/memory/bcm-ns3-mc.h +++ b/include/dt-bindings/memory/bcm-ns3-mc.h @@ -28,7 +28,7 @@ #define BCM_NS3_MEM_SHARE_START 0x8d000000 #define BCM_NS3_MEM_SHARE_LEN 0x020fffff -/* ATF/U-boot/Linux error logs */ +/* ATF/U-Boot/Linux error logs */ #define BCM_NS3_MEM_ELOG_START 0x8f113000 #define BCM_NS3_MEM_ELOG_LEN 0x00100000 diff --git a/include/dt-bindings/power/meson-a1-power.h b/include/dt-bindings/power/meson-a1-power.h new file mode 100644 index 0000000..8e39dfc --- /dev/null +++ b/include/dt-bindings/power/meson-a1-power.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2023 SberDevices, Inc. + * Author: Alexey Romanov <avromanov@sberdevices.ru> + */ + +#ifndef _DT_BINDINGS_MESON_A1_POWER_H +#define _DT_BINDINGS_MESON_A1_POWER_H + +#define PWRC_DSPA_ID 8 +#define PWRC_DSPB_ID 9 +#define PWRC_UART_ID 10 +#define PWRC_DMC_ID 11 +#define PWRC_I2C_ID 12 +#define PWRC_PSRAM_ID 13 +#define PWRC_ACODEC_ID 14 +#define PWRC_AUDIO_ID 15 +#define PWRC_OTP_ID 16 +#define PWRC_DMA_ID 17 +#define PWRC_SD_EMMC_ID 18 +#define PWRC_RAMA_ID 19 +#define PWRC_RAMB_ID 20 +#define PWRC_IR_ID 21 +#define PWRC_SPICC_ID 22 +#define PWRC_SPIFC_ID 23 +#define PWRC_USB_ID 24 +#define PWRC_NIC_ID 25 +#define PWRC_PDMIN_ID 26 +#define PWRC_RSA_ID 27 +#define PWRC_MAX_ID 28 + +#endif diff --git a/include/dt-bindings/reset/stm32mp13-resets.h b/include/dt-bindings/reset/stm32mp13-resets.h index 18ccb05..1b83a01 100644 --- a/include/dt-bindings/reset/stm32mp13-resets.h +++ b/include/dt-bindings/reset/stm32mp13-resets.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later or BSD-3-Clause */ /* - * Copyright (C) STMicroelectronics 2022 - All Rights Reserved + * Copyright (C) STMicroelectronics 2018 - All Rights Reserved * Author: Gabriel Fernandez <gabriel.fernandez@foss.st.com> for STMicroelectronics. */ diff --git a/include/efi_loader.h b/include/efi_loader.h index 38d7f66..11e08a8 100644 --- a/include/efi_loader.h +++ b/include/efi_loader.h @@ -1078,15 +1078,16 @@ struct efi_fw_image { * platforms which enable capsule updates * * @dfu_string: String used to populate dfu_alt_info + * @num_images: The number of images array entries * @images: Pointer to an array of updatable images */ struct efi_capsule_update_info { const char *dfu_string; + int num_images; struct efi_fw_image *images; }; extern struct efi_capsule_update_info update_info; -extern u8 num_image_type_guids; /** * Install the ESRT system table. diff --git a/include/exynos_lcd.h b/include/exynos_lcd.h deleted file mode 100644 index 484bd36..0000000 --- a/include/exynos_lcd.h +++ /dev/null @@ -1,81 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * exynos_lcd.h - Exynos LCD Controller structures - * - * (C) Copyright 2001 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - */ - -#ifndef _EXYNOS_LCD_H_ -#define _EXYNOS_LCD_H_ - -enum { - FIMD_RGB_INTERFACE = 1, - FIMD_CPU_INTERFACE = 2, -}; - -enum exynos_fb_rgb_mode_t { - MODE_RGB_P = 0, - MODE_BGR_P = 1, - MODE_RGB_S = 2, - MODE_BGR_S = 3, -}; - -typedef struct vidinfo { - ushort vl_col; /* Number of columns (i.e. 640) */ - ushort vl_row; /* Number of rows (i.e. 480) */ - ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ - ushort vl_width; /* Width of display area in millimeters */ - ushort vl_height; /* Height of display area in millimeters */ - - /* LCD configuration register */ - u_char vl_freq; /* Frequency */ - u_char vl_clkp; /* Clock polarity */ - u_char vl_oep; /* Output Enable polarity */ - u_char vl_hsp; /* Horizontal Sync polarity */ - u_char vl_vsp; /* Vertical Sync polarity */ - u_char vl_dp; /* Data polarity */ - u_char vl_bpix; /* Bits per pixel */ - - /* Horizontal control register. Timing from data sheet */ - u_char vl_hspw; /* Horz sync pulse width */ - u_char vl_hfpd; /* Wait before of line */ - u_char vl_hbpd; /* Wait end of line */ - - /* Vertical control register. */ - u_char vl_vspw; /* Vertical sync pulse width */ - u_char vl_vfpd; /* Wait before of frame */ - u_char vl_vbpd; /* Wait end of frame */ - u_char vl_cmd_allow_len; /* Wait end of frame */ - - unsigned int win_id; - unsigned int init_delay; - unsigned int power_on_delay; - unsigned int reset_delay; - unsigned int interface_mode; - unsigned int mipi_enabled; - unsigned int dp_enabled; - unsigned int cs_setup; - unsigned int wr_setup; - unsigned int wr_act; - unsigned int wr_hold; - unsigned int logo_on; - unsigned int logo_width; - unsigned int logo_height; - int logo_x_offset; - int logo_y_offset; - unsigned long logo_addr; - unsigned int rgb_mode; - unsigned int resolution; - - /* parent clock name(MPLL, EPLL or VPLL) */ - unsigned int pclk_name; - /* ratio value for source clock from parent clock. */ - unsigned int sclk_div; - - unsigned int dual_lcd_enabled; - struct exynos_fb *reg; - struct exynos_platform_mipi_dsim *dsim_platform_data_dt; -} vidinfo_t; - -#endif diff --git a/include/faraday/ftahbc020s.h b/include/faraday/ftahbc020s.h deleted file mode 100644 index e628156..0000000 --- a/include/faraday/ftahbc020s.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2011 Andes Technology Corporation - * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> - */ - -/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */ -#ifndef __FTAHBC020S_H -#define __FTAHBC202S_H - -/* Registers Offsets */ - -/* - * AHB Slave BSR, offset: n * 4, n=0~31 - */ -#ifndef __ASSEMBLY__ -struct ftahbc02s { - unsigned int s_bsr[32]; /* 0x00-0x7c - Slave n Base/Size Reg */ - unsigned int pcr; /* 0x80 - Priority Ctrl Reg */ - unsigned int tcrg; /* 0x84 - Transfer Ctrl Reg */ - unsigned int cr; /* 0x88 - Ctrl Reg */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register - */ -#define FTAHBC020S_SLAVE_BSR_BASE(x) (((x) & 0xfff) << 20) -#define FTAHBC020S_SLAVE_BSR_SIZE(x) (((x) & 0xf) << 16) -/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */ -#define FTAHBC020S_BSR_SIZE(x) (ffs(x) - 1) /* size of Addr Space */ - -/* - * FTAHBC020S_PCR - Priority Control Register - */ -#define FTAHBC020S_PCR_PLEVEL_(x) (1 << (x)) /* x: 1-15 */ - -/* - * FTAHBC020S_CR - Interrupt Control Register - */ -#define FTAHBC020S_CR_INTSTS (1 << 24) -#define FTAHBC020S_CR_RESP(x) (((x) & 0x3) << 20) -#define FTAHBC020S_CR_INTSMASK (1 << 16) -#define FTAHBC020S_CR_REMAP (1 << 0) - -#endif /* __FTAHBC020S_H */ diff --git a/include/faraday/ftpci100.h b/include/faraday/ftpci100.h deleted file mode 100644 index 8801bd1..0000000 --- a/include/faraday/ftpci100.h +++ /dev/null @@ -1,84 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation - * - * Copyright (C) 2010 Andes Technology Corporation - * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com> - * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> - */ - -#ifndef __FTPCI100_H -#define __FTPCI100_H - -/* AHB Control Registers */ -#include <linux/bitops.h> -struct ftpci100_ahbc { - unsigned int iosize; /* 0x00 - I/O Space Size Signal */ - unsigned int prot; /* 0x04 - AHB Protection */ - unsigned int rsved[8]; /* 0x08-0x24 - Reserved */ - unsigned int conf; /* 0x28 - PCI Configuration */ - unsigned int data; /* 0x2c - PCI Configuration DATA */ -}; - -/* - * FTPCI100_IOSIZE_REG's constant definitions - */ -#define FTPCI100_BASE_IO_SIZE(x) (ffs(x) - 1) /* 1M - 2048M */ - -/* - * PCI Configuration Register - */ -#define PCI_INT_MASK 0x4c -#define PCI_MEM_BASE_SIZE1 0x50 -#define PCI_MEM_BASE_SIZE2 0x54 -#define PCI_MEM_BASE_SIZE3 0x58 - -/* - * PCI_INT_MASK's bit definitions - */ -#define PCI_INTA_ENABLE (1 << 22) -#define PCI_INTB_ENABLE (1 << 23) -#define PCI_INTC_ENABLE (1 << 24) -#define PCI_INTD_ENABLE (1 << 25) - -/* - * PCI_MEM_BASE_SIZE1's constant definitions - */ -#define FTPCI100_BASE_ADR_SIZE(x) ((ffs(x) - 1) << 16) /* 1M - 2048M */ - -#define FTPCI100_MAX_FUNCTIONS 20 -#define PCI_IRQ_LINES 4 - -#define MAX_BUS_NUM 256 -#define MAX_DEV_NUM 32 -#define MAX_FUN_NUM 8 - -#define PCI_MAX_BAR_PER_FUNC 6 - -/* - * PCI_MEM_SIZE - */ -#define FTPCI100_MEM_SIZE(x) (ffs(x) << 24) - -/* This definition is used by pci_ftpci_init() */ -#define FTPCI100_BRIDGE_VENDORID 0x159b -#define FTPCI100_BRIDGE_DEVICEID 0x4321 - -void pci_ftpci_init(void); - -struct pcibar { - unsigned int size; - unsigned int addr; -}; - -struct pci_config { - unsigned int bus; - unsigned int dev; /* device */ - unsigned int func; - unsigned int pin; - unsigned short v_id; /* vendor id */ - unsigned short d_id; /* device id */ - struct pcibar bar[PCI_MAX_BAR_PER_FUNC + 1]; -}; - -#endif diff --git a/include/faraday/ftsdmc020.h b/include/faraday/ftsdmc020.h deleted file mode 100644 index d74da16..0000000 --- a/include/faraday/ftsdmc020.h +++ /dev/null @@ -1,90 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - */ - -/* - * SDRAM Controller - */ -#ifndef __FTSDMC020_H -#define __FTSDMC020_H - -#define FTSDMC020_OFFSET_TP0 0x00 -#define FTSDMC020_OFFSET_TP1 0x04 -#define FTSDMC020_OFFSET_CR 0x08 -#define FTSDMC020_OFFSET_BANK0_BSR 0x0C -#define FTSDMC020_OFFSET_BANK1_BSR 0x10 -#define FTSDMC020_OFFSET_BANK2_BSR 0x14 -#define FTSDMC020_OFFSET_BANK3_BSR 0x18 -#define FTSDMC020_OFFSET_BANK4_BSR 0x1C -#define FTSDMC020_OFFSET_BANK5_BSR 0x20 -#define FTSDMC020_OFFSET_BANK6_BSR 0x24 -#define FTSDMC020_OFFSET_BANK7_BSR 0x28 -#define FTSDMC020_OFFSET_ACR 0x34 - -/* - * Timing Parametet 0 Register - */ -#define FTSDMC020_TP0_TCL(x) ((x) & 0x3) -#define FTSDMC020_TP0_TWR(x) (((x) & 0x3) << 4) -#define FTSDMC020_TP0_TRF(x) (((x) & 0xf) << 8) -#define FTSDMC020_TP0_TRCD(x) (((x) & 0x7) << 12) -#define FTSDMC020_TP0_TRP(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP0_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parametet 1 Register - */ -#define FTSDMC020_TP1_REF_INTV(x) ((x) & 0xffff) -#define FTSDMC020_TP1_INI_REFT(x) (((x) & 0xf) << 16) -#define FTSDMC020_TP1_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * Configuration Register - */ -#define FTSDMC020_CR_SREF (1 << 0) -#define FTSDMC020_CR_PWDN (1 << 1) -#define FTSDMC020_CR_ISMR (1 << 2) -#define FTSDMC020_CR_IREF (1 << 3) -#define FTSDMC020_CR_IPREC (1 << 4) -#define FTSDMC020_CR_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC020_BANK_ENABLE (1 << 28) - -#define FTSDMC020_BANK_BASE(addr) (((addr) >> 20) << 16) - -#define FTSDMC020_BANK_DDW_X4 (0 << 12) -#define FTSDMC020_BANK_DDW_X8 (1 << 12) -#define FTSDMC020_BANK_DDW_X16 (2 << 12) -#define FTSDMC020_BANK_DDW_X32 (3 << 12) - -#define FTSDMC020_BANK_DSZ_16M (0 << 8) -#define FTSDMC020_BANK_DSZ_64M (1 << 8) -#define FTSDMC020_BANK_DSZ_128M (2 << 8) -#define FTSDMC020_BANK_DSZ_256M (3 << 8) - -#define FTSDMC020_BANK_MBW_8 (0 << 4) -#define FTSDMC020_BANK_MBW_16 (1 << 4) -#define FTSDMC020_BANK_MBW_32 (2 << 4) - -#define FTSDMC020_BANK_SIZE_1M 0x0 -#define FTSDMC020_BANK_SIZE_2M 0x1 -#define FTSDMC020_BANK_SIZE_4M 0x2 -#define FTSDMC020_BANK_SIZE_8M 0x3 -#define FTSDMC020_BANK_SIZE_16M 0x4 -#define FTSDMC020_BANK_SIZE_32M 0x5 -#define FTSDMC020_BANK_SIZE_64M 0x6 -#define FTSDMC020_BANK_SIZE_128M 0x7 -#define FTSDMC020_BANK_SIZE_256M 0x8 - -/* - * Arbiter Control Register - */ -#define FTSDMC020_ACR_TOC(x) ((x) & 0x1f) -#define FTSDMC020_ACR_TOE (1 << 8) - -#endif /* __FTSDMC020_H */ diff --git a/include/faraday/ftsdmc021.h b/include/faraday/ftsdmc021.h deleted file mode 100644 index e0e5eb3..0000000 --- a/include/faraday/ftsdmc021.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2009 Faraday Technology - * Po-Yu Chuang <ratbert@faraday-tech.com> - * - * (C) Copyright 2011 Andes Technology Corp - * Macpaul Lin <macpaul@andestech.com> - */ - -/* - * FTSDMC021 - SDRAM Controller - */ -#ifndef __FTSDMC021_H -#define __FTSDMC021_H - -#ifndef __ASSEMBLY__ -#include <linux/bitops.h> -struct ftsdmc021 { - unsigned int tp1; /* 0x00 - SDRAM Timing Parameter 1 */ - unsigned int tp2; /* 0x04 - SDRAM Timing Parameter 2 */ - unsigned int cr1; /* 0x08 - SDRAM Configuration Reg 1 */ - unsigned int cr2; /* 0x0c - SDRAM Configuration Reg 2 */ - unsigned int bank0_bsr; /* 0x10 - Ext. Bank Base/Size Reg 0 */ - unsigned int bank1_bsr; /* 0x14 - Ext. Bank Base/Size Reg 1 */ - unsigned int bank2_bsr; /* 0x18 - Ext. Bank Base/Size Reg 2 */ - unsigned int bank3_bsr; /* 0x1c - Ext. Bank Base/Size Reg 3 */ - unsigned int bank4_bsr; /* 0x20 - Ext. Bank Base/Size Reg 4 */ - unsigned int bank5_bsr; /* 0x24 - Ext. Bank Base/Size Reg 5 */ - unsigned int bank6_bsr; /* 0x28 - Ext. Bank Base/Size Reg 6 */ - unsigned int bank7_bsr; /* 0x2c - Ext. Bank Base/Size Reg 7 */ - unsigned int ragr; /* 0x30 - Read Arbitration Group Reg */ - unsigned int frr; /* 0x34 - Flush Request Register */ - unsigned int ebisr; /* 0x38 - EBI Support Register */ - unsigned int rsved[25]; /* 0x3c-0x9c - Reserved */ - unsigned int crr; /* 0x100 - Controller Revision Reg */ - unsigned int cfr; /* 0x104 - Controller Feature Reg */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * Timing Parameter 1 Register - */ -#define FTSDMC021_TP1_TCL(x) ((x) & 0x3) /* CAS Latency */ -#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4) /* W-Recovery Time */ -#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8) /* Auto-Refresh Cycle */ -#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12) /* RAS-to-CAS Delay */ -#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16) /* Precharge Cycle */ -#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20) - -/* - * Timing Parameter 2 Register - */ -#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff) /* Refresh interval */ -/* b(16:19) - Initial Refresh Times */ -#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16) -/* b(20:23) - Initial Pre-Charge Times */ -#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20) - -/* - * SDRAM Configuration Register 1 - */ -#define FTSDMC021_CR1_BNKSIZE(x) ((x) & 0xf) /* Bank Size */ -#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4) /* Bus Width */ -#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8) /* SDRAM Size */ -#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12) /* Data Width */ -/* b(16) MA2T: Double Memory Address Cycle Enable */ -#define FTSDMC021_CR1_MA2T(x) (1 << 16) -/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */ -#define FTSDMC021_BANK_SIZE(x) (ffs(x) - 1) - -/* - * Configuration Register 2 - */ -#define FTSDMC021_CR2_SREF (1 << 0) /* Self-Refresh Mode */ -#define FTSDMC021_CR2_PWDN (1 << 1) /* Power Down Operation Mode */ -#define FTSDMC021_CR2_ISMR (1 << 2) /* Start Set-Mode-Register */ -#define FTSDMC021_CR2_IREF (1 << 3) /* Init Refresh Start Flag */ -#define FTSDMC021_CR2_IPREC (1 << 4) /* Init Pre-Charge Start Flag */ -#define FTSDMC021_CR2_REFTYPE (1 << 5) - -/* - * SDRAM External Bank Base/Size Register - */ -#define FTSDMC021_BANK_ENABLE (1 << 12) - -/* 12-bit base address of external bank. - * Default value is 0x800. - * The 12-bit equals to the haddr[31:20] of AHB address bus. */ -#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff) - -/* - * Read Arbitration Grant Window Register - */ -#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0) -#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4) -#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8) -#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12) -#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16) -#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20) -#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24) -#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28) - -/* - * Flush Request Register - */ -#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0) -#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3) /* Flush Req Flag */ - -/* - * External Bus Interface Support Register (EBISR) - */ -#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff) /* Far-end mode */ -#define FTSDMC021_EBISR_PRSMR (1 << 12) /* Pre-SMR */ -#define FTSDMC021_EBISR_POPREC (1 << 13) -#define FTSDMC021_EBISR_POSMR (1 << 14) /* Post-SMR */ - -/* - * Controller Revision Register (CRR, Read Only) - */ -#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff) -#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff) -#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff) - -/* - * Controller Feature Register (CFR, Read Only) - */ -#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf) -#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf) -#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1) -#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1) -#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1) -#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1) -#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1) -#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1) -#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1) -#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1) -#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1) - -#endif /* __FTSDMC021_H */ diff --git a/include/fdt_support.h b/include/fdt_support.h index 5638bd4..2cd8366 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -7,7 +7,8 @@ #ifndef __FDT_SUPPORT_H #define __FDT_SUPPORT_H -#if defined(CONFIG_OF_LIBFDT) && !defined(USE_HOSTCC) +#if (defined(CONFIG_OF_LIBFDT) || defined(CONFIG_OF_CONTROL)) && \ + !defined(USE_HOSTCC) #include <asm/u-boot.h> #include <linux/libfdt.h> @@ -255,6 +256,14 @@ static inline void fdt_fixup_mtdparts(void *fdt, } #endif +/** + * copy the fixed-partition nodes from U-Boot device tree to external blob + * + * @param blob FDT blob to update + * Return: 0 if ok, or non-zero on error + */ +int fdt_copy_fixed_partitions(void *blob); + void fdt_del_node_and_alias(void *blob, const char *alias); /** diff --git a/include/fsl-mc/fsl_dpbp.h b/include/fsl-mc/fsl_dpbp.h index 2278ac9..3f3e6c4 100644 --- a/include/fsl-mc/fsl_dpbp.h +++ b/include/fsl-mc/fsl_dpbp.h @@ -1,14 +1,13 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Freescale Layerscape MC I/O wrapper + * Data Path Buffer Pool API + * Contains initialization APIs and runtime control APIs for DPBP * * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP - */ -/*! - * @file fsl_dpbp.h - * @brief Data Path Buffer Pool API + * Copyright 2017-2023 NXP */ + #ifndef __FSL_DPBP_H #define __FSL_DPBP_H @@ -27,160 +26,50 @@ #define DPBP_CMDID_DISABLE 0x0031 #define DPBP_CMDID_GET_ATTR 0x0041 #define DPBP_CMDID_RESET 0x0051 -#define DPBP_CMDID_IS_ENABLED 0x0061 -/* cmd, param, offset, width, type, arg_name */ -#define DPBP_CMD_OPEN(cmd, dpbp_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpbp_id) +#pragma pack(push, 1) + +struct dpbp_cmd_open { + __le32 dpbp_id; +}; -/* cmd, param, offset, width, type, arg_name */ -#define DPBP_RSP_GET_ATTRIBUTES(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 16, 16, uint16_t, attr->bpid); \ - MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ -} while (0) +struct dpbp_cmd_destroy { + __le32 object_id; +}; -/* Data Path Buffer Pool API - * Contains initialization APIs and runtime control APIs for DPBP - */ +struct dpbp_rsp_get_attributes { + __le16 pad; + __le16 bpid; + __le32 id; +}; + +#pragma pack(pop) struct fsl_mc_io; -/** - * dpbp_open() - Open a control session for the specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpbp_id: DPBP unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpbp_create function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpbp_id, - uint16_t *token); +int dpbp_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpbp_id, u16 *token); -/** - * dpbp_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpbp_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpbp_cfg - Structure representing DPBP configuration * @options: place holder */ struct dpbp_cfg { - uint32_t options; + u32 options; }; -/** - * dpbp_create() - Create the DPBP object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @token: Returned token; use in subsequent API calls - * - * Create the DPBP object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpbp_open function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_create(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - const struct dpbp_cfg *cfg, - uint32_t *obj_id); +int dpbp_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpbp_cfg *cfg, u32 *obj_id); -/** - * dpbp_destroy() - Destroy the DPBP object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; error code otherwise. - */ -int dpbp_destroy(struct fsl_mc_io *mc_io, - uint16_t dprc_token, - uint32_t cmd_flags, - uint32_t obj_id); +int dpbp_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 obj_id); -/** - * dpbp_enable() - Enable the DPBP. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpbp_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -/** - * dpbp_disable() - Disable the DPBP. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); - -/** - * dpbp_is_enabled() - Check if the DPBP is enabled. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * @en: Returns '1' if object is enabled; '0' otherwise - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_is_enabled(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int *en); - -/** - * dpbp_reset() - Reset the DPBP, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpbp_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); +int dpbp_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpbp_attr - Structure representing DPBP attributes @@ -190,40 +79,14 @@ int dpbp_reset(struct fsl_mc_io *mc_io, * acquire/release operations on buffers */ struct dpbp_attr { - uint32_t id; - uint16_t bpid; + u32 id; + u16 bpid; }; -/** - * dpbp_get_attributes - Retrieve DPBP attributes. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPBP object - * @attr: Returned object's attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpbp_attr *attr); - -/** - * dpbp_get_api_version - Retrieve DPBP Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPBP major version - * @minor_ver: DPBP minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpbp_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dpbp_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpbp_attr *attr); -/** @} */ +int dpbp_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* __FSL_DPBP_H */ diff --git a/include/fsl-mc/fsl_dpio.h b/include/fsl-mc/fsl_dpio.h index 7788e19..375590f 100644 --- a/include/fsl-mc/fsl_dpio.h +++ b/include/fsl-mc/fsl_dpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #ifndef _FSL_DPIO_H @@ -21,31 +21,53 @@ #define DPIO_CMDID_ENABLE 0x0021 #define DPIO_CMDID_DISABLE 0x0031 #define DPIO_CMDID_GET_ATTR 0x0041 -#define DPIO_CMDID_RESET 0x0051 - -/* cmd, param, offset, width, type, arg_name */ -#define DPIO_CMD_OPEN(cmd, dpio_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpio_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPIO_CMD_CREATE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 2, enum dpio_channel_mode, \ - cfg->channel_mode);\ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->num_priorities);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPIO_RSP_GET_ATTR(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->id);\ - MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->qbman_portal_id);\ - MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->num_priorities);\ - MC_RSP_OP(cmd, 0, 56, 4, enum dpio_channel_mode, attr->channel_mode);\ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, attr->qbman_portal_ce_offset);\ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, attr->qbman_portal_ci_offset);\ - MC_RSP_OP(cmd, 3, 32, 32, uint32_t, attr->qbman_version);\ -} while (0) + +/* Macros for accessing command fields smaller than 1byte */ +#define DPIO_MASK(field) \ + GENMASK(DPIO_##field##_SHIFT + DPIO_##field##_SIZE - 1, \ + DPIO_##field##_SHIFT) +#define dpio_set_field(var, field, val) \ + ((var) |= (((val) << DPIO_##field##_SHIFT) & DPIO_MASK(field))) +#define dpio_get_field(var, field) \ + (((var) & DPIO_MASK(field)) >> DPIO_##field##_SHIFT) + +#pragma pack(push, 1) +struct dpio_cmd_open { + __le32 dpio_id; +}; + +#define DPIO_CHANNEL_MODE_SHIFT 0 +#define DPIO_CHANNEL_MODE_SIZE 2 + +struct dpio_cmd_create { + __le16 pad1; + /* from LSB: channel_mode:2 */ + u8 channel_mode; + u8 pad2; + u8 num_priorities; +}; + +struct dpio_cmd_destroy { + __le32 dpio_id; +}; + +#define DPIO_ATTR_CHANNEL_MODE_SHIFT 0 +#define DPIO_ATTR_CHANNEL_MODE_SIZE 4 + +struct dpio_rsp_get_attr { + __le32 id; + __le16 qbman_portal_id; + u8 num_priorities; + /* from LSB: channel_mode:4 */ + u8 channel_mode; + __le64 qbman_portal_ce_offset; + __le64 qbman_portal_ci_offset; + __le32 qbman_version; + __le32 pad; + __le32 clk; +}; + +#pragma pack(pop) /* Data Path I/O Portal API * Contains initialization APIs and runtime control APIs for DPIO @@ -53,44 +75,15 @@ do { \ struct fsl_mc_io; -/** - * dpio_open() - Open a control session for the specified object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpio_id: DPIO unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpio_create() function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint32_t dpio_id, - uint16_t *token); +int dpio_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpio_id, + u16 *token); -/** - * dpio_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpio_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * enum dpio_channel_mode - DPIO notification channel mode - * @DPIO_NO_CHANNEL: No support for notification channel - * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a + * @DPIO_NO_CHANNEL: No support for notification channel + * @DPIO_LOCAL_CHANNEL: Notifications on data availability can be received by a * dedicated channel in the DPIO; user should point the queue's * destination in the relevant interface to this DPIO */ @@ -101,143 +94,52 @@ enum dpio_channel_mode { /** * struct dpio_cfg - Structure representing DPIO configuration - * @channel_mode: Notification channel mode - * @num_priorities: Number of priorities for the notification channel (1-8); + * @channel_mode: Notification channel mode + * @num_priorities: Number of priorities for the notification channel (1-8); * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' */ struct dpio_cfg { - enum dpio_channel_mode channel_mode; - uint8_t num_priorities; + enum dpio_channel_mode channel_mode; + u8 num_priorities; }; -/** - * dpio_create() - Create the DPIO object. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Create the DPIO object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpio_open() function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_create(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - const struct dpio_cfg *cfg, - uint32_t *obj_id); - -/** - * dpio_destroy() - Destroy the DPIO object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @obj_id: Object ID of DPIO - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_destroy(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - uint32_t obj_id); +int dpio_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpio_cfg *cfg, u32 *obj_id); -/** - * dpio_enable() - Enable the DPIO, allow I/O portal operations. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpio_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id); -/** - * dpio_disable() - Disable the DPIO, stop any I/O portal operation. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpio_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -/** - * dpio_reset() - Reset the DPIO, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpio_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpio_attr - Structure representing DPIO attributes - * @id: DPIO object ID - * @version: DPIO version - * @qbman_portal_ce_offset: offset of the software portal cache-enabled area - * @qbman_portal_ci_offset: offset of the software portal cache-inhibited area - * @qbman_portal_id: Software portal ID - * @channel_mode: Notification channel mode - * @num_priorities: Number of priorities for the notification channel (1-8); - * relevant only if 'channel_mode = DPIO_LOCAL_CHANNEL' - * @qbman_version: QBMAN version + * @id: DPIO object ID + * @qbman_portal_ce_offset: Offset of the software portal cache-enabled area + * @qbman_portal_ci_offset: Offset of the software portal + * cache-inhibited area + * @qbman_portal_id: Software portal ID + * @channel_mode: Notification channel mode + * @num_priorities: Number of priorities for the notification + * channel (1-8); relevant only if + * 'channel_mode = DPIO_LOCAL_CHANNEL' + * @qbman_version: QBMAN version */ struct dpio_attr { - uint32_t id; - uint64_t qbman_portal_ce_offset; - uint64_t qbman_portal_ci_offset; - uint16_t qbman_portal_id; + int id; + u64 qbman_portal_ce_offset; + u64 qbman_portal_ci_offset; + u16 qbman_portal_id; enum dpio_channel_mode channel_mode; - uint8_t num_priorities; - uint32_t qbman_version; + u8 num_priorities; + u32 qbman_version; + u32 clk; }; -/** - * dpio_get_attributes() - Retrieve DPIO attributes - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPIO object - * @attr: Returned object's attributes - * - * Return: '0' on Success; Error code otherwise - */ -int dpio_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpio_attr *attr); - -/** - * dpio_get_api_version - Retrieve DPIO Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPIO major version - * @minor_ver: DPIO minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpio_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dpio_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpio_attr *attr); +int dpio_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* _FSL_DPIO_H */ diff --git a/include/fsl-mc/fsl_dpmac.h b/include/fsl-mc/fsl_dpmac.h index 1cea123..a8e9e46 100644 --- a/include/fsl-mc/fsl_dpmac.h +++ b/include/fsl-mc/fsl_dpmac.h @@ -21,74 +21,59 @@ #define DPMAC_CMDID_DESTROY 0x98c1 #define DPMAC_CMDID_GET_API_VERSION 0xa0c1 -#define DPMAC_CMDID_GET_ATTR 0x0041 #define DPMAC_CMDID_RESET 0x0051 -#define DPMAC_CMDID_MDIO_READ 0x0c01 -#define DPMAC_CMDID_MDIO_WRITE 0x0c11 -#define DPMAC_CMDID_GET_LINK_CFG 0x0c21 #define DPMAC_CMDID_SET_LINK_STATE 0x0c31 #define DPMAC_CMDID_GET_COUNTER 0x0c41 -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_CREATE(cmd, cfg) \ - MC_CMD_OP(cmd, 0, 0, 16, uint16_t, cfg->mac_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_OPEN(cmd, dpmac_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpmac_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_GET_ATTRIBUTES(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->phy_id);\ - MC_RSP_OP(cmd, 0, 32, 32, int, attr->id);\ - MC_RSP_OP(cmd, 1, 32, 8, enum dpmac_link_type, attr->link_type);\ - MC_RSP_OP(cmd, 1, 40, 8, enum dpmac_eth_if, attr->eth_if);\ - MC_RSP_OP(cmd, 2, 0, 32, uint32_t, attr->max_rate);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_MDIO_READ(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_MDIO_READ(cmd, data) \ - MC_RSP_OP(cmd, 0, 16, 16, uint16_t, data) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_MDIO_WRITE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->phy_addr); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, cfg->reg); \ - MC_CMD_OP(cmd, 0, 16, 16, uint16_t, cfg->data); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_GET_LINK_CFG(cmd, cfg) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_SET_LINK_STATE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 64, uint64_t, cfg->options); \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate); \ - MC_CMD_OP(cmd, 2, 0, 1, int, cfg->up); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_CMD_GET_COUNTER(cmd, type) \ - MC_CMD_OP(cmd, 1, 0, 64, enum dpmac_counter, type) - -/* cmd, param, offset, width, type, arg_name */ -#define DPMAC_RSP_GET_COUNTER(cmd, counter) \ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, counter) +/* Macros for accessing command fields smaller than 1byte */ +#define DPMAC_MASK(field) \ + GENMASK(DPMAC_##field##_SHIFT + DPMAC_##field##_SIZE - 1, \ + DPMAC_##field##_SHIFT) +#define dpmac_set_field(var, field, val) \ + ((var) |= (((val) << DPMAC_##field##_SHIFT) & DPMAC_MASK(field))) +#define dpmac_get_field(var, field) \ + (((var) & DPMAC_MASK(field)) >> DPMAC_##field##_SHIFT) + +#pragma pack(push, 1) +struct dpmac_cmd_open { + __le32 dpmac_id; +}; + +struct dpmac_cmd_create { + __le32 mac_id; +}; + +struct dpmac_cmd_destroy { + __le32 dpmac_id; +}; + +#define DPMAC_STATE_SIZE 1 +#define DPMAC_STATE_SHIFT 0 +#define DPMAC_STATE_VALID_SIZE 1 +#define DPMAC_STATE_VALID_SHIFT 1 + +struct dpmac_cmd_set_link_state { + __le64 options; + __le32 rate; + __le32 pad; + /* only least significant bit is valid */ + u8 up; + u8 pad0[7]; + __le64 supported; + __le64 advertising; +}; + +struct dpmac_cmd_get_counter { + u8 type; +}; + +struct dpmac_rsp_get_counter { + __le64 pad; + __le64 counter; +}; + +#pragma pack(pop) /* Data Path MAC API * Contains initialization APIs and runtime control APIs for DPMAC @@ -96,42 +81,27 @@ do { \ struct fsl_mc_io; -/** - * dpmac_open() - Open a control session for the specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpmac_id: DPMAC unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpmac_create function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpmac_id, - uint16_t *token); +int dpmac_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpmac_id, u16 *token); + +int dpmac_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** - * dpmac_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. + * struct dpmac_cfg - Structure representing DPMAC configuration + * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP, + * the MAC IDs are continuous. + * For example: 2 WRIOPs, 16 MACs in each: + * MAC IDs for the 1st WRIOP: 1-16, + * MAC IDs for the 2nd WRIOP: 17-32. */ -int dpmac_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +struct dpmac_cfg { + int mac_id; +}; + +int dpmac_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpmac_cfg *cfg, u32 *obj_id); + +int dpmac_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id); /** * enum dpmac_link_type - DPMAC link type @@ -171,60 +141,6 @@ enum dpmac_eth_if { DPMAC_ETH_IF_XFI }; -/** - * struct dpmac_cfg - Structure representing DPMAC configuration - * @mac_id: Represents the Hardware MAC ID; in case of multiple WRIOP, - * the MAC IDs are continuous. - * For example: 2 WRIOPs, 16 MACs in each: - * MAC IDs for the 1st WRIOP: 1-16, - * MAC IDs for the 2nd WRIOP: 17-32. - */ -struct dpmac_cfg { - int mac_id; -}; - -/** - * dpmac_create() - Create the DPMAC object. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Create the DPMAC object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpmac_open function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_create(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - const struct dpmac_cfg *cfg, - uint32_t *obj_id); - -/** - * dpmac_destroy() - Destroy the DPMAC object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @obj_id: DPMAC object id - * - * Return: '0' on Success; error code otherwise. - */ -int dpmac_destroy(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - uint32_t obj_id); - /* DPMAC IRQ Index and Events */ /* IRQ index */ @@ -248,65 +164,9 @@ struct dpmac_attr { int phy_id; enum dpmac_link_type link_type; enum dpmac_eth_if eth_if; - uint32_t max_rate; + u32 max_rate; }; -/** - * dpmac_get_attributes - Retrieve DPMAC attributes. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @attr: Returned object's attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_attr *attr); - -/** - * struct dpmac_mdio_cfg - DPMAC MDIO read/write parameters - * @phy_addr: MDIO device address - * @reg: Address of the register within the Clause 45 PHY device from which data - * is to be read - * @data: Data read/write from/to MDIO - */ -struct dpmac_mdio_cfg { - uint8_t phy_addr; - uint8_t reg; - uint16_t data; -}; - -/** - * dpmac_mdio_read() - Perform MDIO read transaction - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @cfg: Structure with MDIO transaction parameters - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_mdio_read(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_mdio_cfg *cfg); - -/** - * dpmac_mdio_write() - Perform MDIO write transaction - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @cfg: Structure with MDIO transaction parameters - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_mdio_write(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_mdio_cfg *cfg); - /* DPMAC link configuration/state options */ /* Enable auto-negotiation */ @@ -319,55 +179,25 @@ int dpmac_mdio_write(struct fsl_mc_io *mc_io, #define DPMAC_LINK_OPT_ASYM_PAUSE 0x0000000000000008ULL /** - * struct dpmac_link_cfg - Structure representing DPMAC link configuration - * @rate: Link's rate - in Mbps - * @options: Enable/Disable DPMAC link cfg features (bitmap) - */ -struct dpmac_link_cfg { - uint32_t rate; - uint64_t options; -}; - -/** - * dpmac_get_link_cfg() - Get Ethernet link configuration - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @cfg: Returned structure with the link configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_get_link_cfg(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_link_cfg *cfg); - -/** * struct dpmac_link_state - DPMAC link configuration request * @rate: Rate in Mbps * @options: Enable/Disable DPMAC link cfg features (bitmap) * @up: Link state + * @state_valid: Ignore/Update the state of the link + * @supported: Speeds capability of the phy (bitmap) + * @advertising: Speeds that are advertised for autoneg (bitmap) */ struct dpmac_link_state { - uint32_t rate; - uint64_t options; - int up; + u32 rate; + u64 options; + int up; + int state_valid; + u64 supported; + u64 advertising; }; -/** - * dpmac_set_link_state() - Set the Ethernet link status - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @link_state: Link state configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_set_link_state(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpmac_link_state *link_state); - +int dpmac_set_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpmac_link_state *link_state); /** * enum dpni_counter - DPNI counter types * @DPMAC_CNT_ING_FRAME_64: counts 64-octet frame, good or bad. @@ -412,6 +242,8 @@ int dpmac_set_link_state(struct fsl_mc_io *mc_io, * @DPMAC_CNT_EGR_ERR_FRAME: counts frame transmitted with an error * @DPMAC_CNT_ING_GOOD_FRAME: counts frame received without error, including * pause frames. + * @DPMAC_CNT_EGR_GOOD_FRAME: counts frames transmitted without error, including + * pause frames. */ enum dpmac_counter { DPMAC_CNT_ING_FRAME_64, @@ -440,37 +272,14 @@ enum dpmac_counter { DPMAC_CNT_EGR_BCAST_FRAME, DPMAC_CNT_EGR_UCAST_FRAME, DPMAC_CNT_EGR_ERR_FRAME, - DPMAC_CNT_ING_GOOD_FRAME + DPMAC_CNT_ING_GOOD_FRAME, + DPMAC_CNT_EGR_GOOD_FRAME, }; -/** - * dpmac_get_counter() - Read a specific DPMAC counter - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPMAC object - * @type: The requested counter - * @counter: Returned counter value - * - * Return: The requested counter; '0' otherwise. - */ -int dpmac_get_counter(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpmac_counter type, - uint64_t *counter); -/** - * dpmac_get_api_version - Retrieve DPMAC Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPMAC major version - * @minor_ver: DPMAC minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpmac_get_api_version(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t *major_ver, - uint16_t *minor_ver); +int dpmac_get_counter(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpmac_counter type, u64 *counter); + +int dpmac_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* __FSL_DPMAC_H */ diff --git a/include/fsl-mc/fsl_dpmng.h b/include/fsl-mc/fsl_dpmng.h index 2148601..5dfc9ec 100644 --- a/include/fsl-mc/fsl_dpmng.h +++ b/include/fsl-mc/fsl_dpmng.h @@ -30,17 +30,6 @@ struct mc_version { uint32_t revision; }; -/** - * mc_get_version() - Retrieves the Management Complex firmware - * version information - * @mc_io: Pointer to opaque I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @mc_ver_info: Returned version information structure - * - * Return: '0' on Success; Error code otherwise. - */ -int mc_get_version(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - struct mc_version *mc_ver_info); +int mc_get_version(struct fsl_mc_io *mc_io, uint32_t cmd_flags, struct mc_version *mc_ver_info); #endif /* __FSL_DPMNG_H */ diff --git a/include/fsl-mc/fsl_dpni.h b/include/fsl-mc/fsl_dpni.h index e5e7338..9bc4754 100644 --- a/include/fsl-mc/fsl_dpni.h +++ b/include/fsl-mc/fsl_dpni.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #ifndef _FSL_DPNI_H #define _FSL_DPNI_H @@ -24,303 +24,243 @@ #define DPNI_CMDID_SET_POOLS 0x2002 #define DPNI_CMDID_SET_BUFFER_LAYOUT 0x2651 -#define DPNI_CMDID_GET_BUFFER_LAYOUT 0x2641 -#define DPNI_CMDID_SET_ERRORS_BEHAVIOR 0x20B1 #define DPNI_CMDID_GET_QDID 0x2101 #define DPNI_CMDID_GET_TX_DATA_OFFSET 0x2121 #define DPNI_CMDID_GET_LINK_STATE 0x2151 #define DPNI_CMDID_SET_LINK_CFG 0x21A1 -#define DPNI_CMDID_SET_PRIM_MAC 0x2241 -#define DPNI_CMDID_GET_PRIM_MAC 0x2251 #define DPNI_CMDID_ADD_MAC_ADDR 0x2261 -#define DPNI_CMDID_REMOVE_MAC_ADDR 0x2271 #define DPNI_CMDID_GET_STATISTICS 0x25D1 -#define DPNI_CMDID_RESET_STATISTICS 0x25E1 #define DPNI_CMDID_GET_QUEUE 0x25F1 #define DPNI_CMDID_SET_QUEUE 0x2601 #define DPNI_CMDID_SET_TX_CONFIRMATION_MODE 0x2661 -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_OPEN(cmd, dpni_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, dpni_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_PREP_CFG(param, cfg) \ -do { \ - MC_PREP_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \ - MC_PREP_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \ - MC_PREP_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \ - MC_PREP_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \ - MC_PREP_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \ - MC_PREP_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \ - MC_PREP_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_EXT_CFG(param, cfg) \ -do { \ - MC_EXT_OP(param, 0, 0, 32, uint16_t, cfg->adv.options); \ - MC_EXT_OP(param, 0, 32, 8, uint16_t, cfg->adv.num_queues); \ - MC_EXT_OP(param, 0, 40, 8, uint16_t, cfg->adv.num_tcs); \ - MC_EXT_OP(param, 0, 48, 8, uint16_t, cfg->adv.mac_entries); \ - MC_EXT_OP(param, 1, 0, 8, uint16_t, cfg->adv.vlan_entries); \ - MC_EXT_OP(param, 1, 16, 8, uint16_t, cfg->adv.qos_entries); \ - MC_EXT_OP(param, 1, 32, 16, uint16_t, cfg->adv.fs_entries); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_CREATE(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->adv.options); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, cfg->adv.num_queues); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, cfg->adv.num_tcs); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, cfg->adv.mac_entries); \ - MC_CMD_OP(cmd, 1, 0, 8, uint8_t, cfg->adv.vlan_entries); \ - MC_CMD_OP(cmd, 1, 16, 8, uint8_t, cfg->adv.qos_entries); \ - MC_CMD_OP(cmd, 1, 32, 16, uint8_t, cfg->adv.fs_entries); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_POOLS(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, cfg->num_dpbp); \ - MC_CMD_OP(cmd, 0, 8, 1, int, cfg->pools[0].backup_pool); \ - MC_CMD_OP(cmd, 0, 9, 1, int, cfg->pools[1].backup_pool); \ - MC_CMD_OP(cmd, 0, 10, 1, int, cfg->pools[2].backup_pool); \ - MC_CMD_OP(cmd, 0, 11, 1, int, cfg->pools[3].backup_pool); \ - MC_CMD_OP(cmd, 0, 12, 1, int, cfg->pools[4].backup_pool); \ - MC_CMD_OP(cmd, 0, 13, 1, int, cfg->pools[5].backup_pool); \ - MC_CMD_OP(cmd, 0, 14, 1, int, cfg->pools[6].backup_pool); \ - MC_CMD_OP(cmd, 0, 15, 1, int, cfg->pools[7].backup_pool); \ - MC_CMD_OP(cmd, 0, 32, 32, int, cfg->pools[0].dpbp_id); \ - MC_CMD_OP(cmd, 4, 32, 16, uint16_t, cfg->pools[0].buffer_size);\ - MC_CMD_OP(cmd, 1, 0, 32, int, cfg->pools[1].dpbp_id); \ - MC_CMD_OP(cmd, 4, 48, 16, uint16_t, cfg->pools[1].buffer_size);\ - MC_CMD_OP(cmd, 1, 32, 32, int, cfg->pools[2].dpbp_id); \ - MC_CMD_OP(cmd, 5, 0, 16, uint16_t, cfg->pools[2].buffer_size);\ - MC_CMD_OP(cmd, 2, 0, 32, int, cfg->pools[3].dpbp_id); \ - MC_CMD_OP(cmd, 5, 16, 16, uint16_t, cfg->pools[3].buffer_size);\ - MC_CMD_OP(cmd, 2, 32, 32, int, cfg->pools[4].dpbp_id); \ - MC_CMD_OP(cmd, 5, 32, 16, uint16_t, cfg->pools[4].buffer_size);\ - MC_CMD_OP(cmd, 3, 0, 32, int, cfg->pools[5].dpbp_id); \ - MC_CMD_OP(cmd, 5, 48, 16, uint16_t, cfg->pools[5].buffer_size);\ - MC_CMD_OP(cmd, 3, 32, 32, int, cfg->pools[6].dpbp_id); \ - MC_CMD_OP(cmd, 6, 0, 16, uint16_t, cfg->pools[6].buffer_size);\ - MC_CMD_OP(cmd, 4, 0, 32, int, cfg->pools[7].dpbp_id); \ - MC_CMD_OP(cmd, 6, 16, 16, uint16_t, cfg->pools[7].buffer_size);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_ATTR(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->options);\ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, attr->max_num_queues); \ - MC_RSP_OP(cmd, 0, 40, 8, uint8_t, attr->max_num_tcs); \ - MC_RSP_OP(cmd, 0, 48, 8, uint8_t, attr->max_mac_entries); \ - MC_RSP_OP(cmd, 1, 0, 8, uint8_t, attr->max_vlan_entries); \ - MC_RSP_OP(cmd, 1, 16, 8, uint8_t, attr->max_qos_entries); \ - MC_RSP_OP(cmd, 1, 32, 16, uint16_t, attr->max_fs_entries); \ - MC_RSP_OP(cmd, 2, 0, 8, uint8_t, attr->max_qos_key_size); \ - MC_RSP_OP(cmd, 2, 8, 8, uint8_t, attr->max_fs_key_size); \ - MC_RSP_OP(cmd, 2, 16, 16, uint16_t, attr->wriop_version); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_ERRORS_BEHAVIOR(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->errors); \ - MC_CMD_OP(cmd, 0, 32, 4, enum dpni_error_action, cfg->error_action); \ - MC_CMD_OP(cmd, 0, 36, 1, int, cfg->set_frame_annotation); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_BUFFER_LAYOUT(cmd, layout, queue) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, queue); \ - MC_CMD_OP(cmd, 1, 0, 16, uint16_t, layout->private_data_size); \ - MC_CMD_OP(cmd, 1, 16, 16, uint16_t, layout->data_align); \ - MC_CMD_OP(cmd, 0, 32, 16, uint16_t, layout->options); \ - MC_CMD_OP(cmd, 0, 48, 1, int, layout->pass_timestamp); \ - MC_CMD_OP(cmd, 0, 49, 1, int, layout->pass_parser_result); \ - MC_CMD_OP(cmd, 0, 50, 1, int, layout->pass_frame_status); \ - MC_CMD_OP(cmd, 1, 32, 16, uint16_t, layout->data_head_room); \ - MC_CMD_OP(cmd, 1, 48, 16, uint16_t, layout->data_tail_room); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_QDID(cmd, qdid) \ - MC_RSP_OP(cmd, 0, 0, 16, uint16_t, qdid) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_TX_DATA_OFFSET(cmd, data_offset) \ - MC_RSP_OP(cmd, 0, 0, 16, uint16_t, data_offset) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_LINK_CFG(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, cfg->rate);\ - MC_CMD_OP(cmd, 2, 0, 64, uint64_t, cfg->options);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_LINK_STATE(cmd, state) \ -do { \ - MC_RSP_OP(cmd, 0, 32, 1, int, state->up);\ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, state->rate);\ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, state->options);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_SET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_PRIMARY_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_RSP_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_RSP_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_RSP_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_RSP_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_RSP_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_RSP_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_ADD_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_REMOVE_MAC_ADDR(cmd, mac_addr) \ -do { \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, mac_addr[5]); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, mac_addr[4]); \ - MC_CMD_OP(cmd, 0, 32, 8, uint8_t, mac_addr[3]); \ - MC_CMD_OP(cmd, 0, 40, 8, uint8_t, mac_addr[2]); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, mac_addr[1]); \ - MC_CMD_OP(cmd, 0, 56, 8, uint8_t, mac_addr[0]); \ -} while (0) - -#define DPNI_CMD_GET_QUEUE(cmd, type, tc, index) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \ -} while (0) - -#define DPNI_RSP_GET_QUEUE(cmd, queue) \ -do { \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ - MC_RSP_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \ - MC_RSP_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \ - MC_RSP_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \ - MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \ - MC_RSP_OP(cmd, 4, 0, 32, uint32_t, (queue)->fqid); \ - MC_RSP_OP(cmd, 4, 32, 16, uint16_t, (queue)->qdbin); \ -} while (0) - -#define DPNI_CMD_SET_QUEUE(cmd, type, tc, index, queue) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 8, enum dpni_queue_type, type); \ - MC_CMD_OP(cmd, 0, 8, 8, uint8_t, tc); \ - MC_CMD_OP(cmd, 0, 16, 8, uint8_t, index); \ - MC_CMD_OP(cmd, 0, 24, 8, uint8_t, (queue)->options); \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ - MC_CMD_OP(cmd, 1, 56, 4, enum dpni_dest, (queue)->destination.type); \ - MC_CMD_OP(cmd, 1, 62, 1, char, (queue)->destination.stash_ctrl); \ - MC_CMD_OP(cmd, 1, 63, 1, char, (queue)->destination.hold_active); \ - MC_CMD_OP(cmd, 1, 0, 32, uint32_t, (queue)->destination.id); \ - MC_CMD_OP(cmd, 2, 0, 64, uint64_t, (queue)->flc); \ - MC_CMD_OP(cmd, 3, 0, 64, uint64_t, (queue)->user_context); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_CMD_GET_STATISTICS(cmd, page) \ - MC_CMD_OP(cmd, 0, 0, 8, uint8_t, page) - -/* cmd, param, offset, width, type, arg_name */ -#define DPNI_RSP_GET_STATISTICS(cmd, stat) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 64, uint64_t, (stat)->counter0); \ - MC_RSP_OP(cmd, 1, 0, 64, uint64_t, (stat)->counter1); \ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, (stat)->counter2); \ - MC_RSP_OP(cmd, 3, 0, 64, uint64_t, (stat)->counter3); \ - MC_RSP_OP(cmd, 4, 0, 64, uint64_t, (stat)->counter4); \ - MC_RSP_OP(cmd, 5, 0, 64, uint64_t, (stat)->counter5); \ - MC_RSP_OP(cmd, 6, 0, 64, uint64_t, (stat)->counter6); \ -} while (0) - -enum net_prot { - NET_PROT_NONE = 0, - NET_PROT_PAYLOAD, - NET_PROT_ETH, - NET_PROT_VLAN, - NET_PROT_IPV4, - NET_PROT_IPV6, - NET_PROT_IP, - NET_PROT_TCP, - NET_PROT_UDP, - NET_PROT_UDP_LITE, - NET_PROT_IPHC, - NET_PROT_SCTP, - NET_PROT_SCTP_CHUNK_DATA, - NET_PROT_PPPOE, - NET_PROT_PPP, - NET_PROT_PPPMUX, - NET_PROT_PPPMUX_SUBFRM, - NET_PROT_L2TPV2, - NET_PROT_L2TPV3_CTRL, - NET_PROT_L2TPV3_SESS, - NET_PROT_LLC, - NET_PROT_LLC_SNAP, - NET_PROT_NLPID, - NET_PROT_SNAP, - NET_PROT_MPLS, - NET_PROT_IPSEC_AH, - NET_PROT_IPSEC_ESP, - NET_PROT_UDP_ENC_ESP, /* RFC 3948 */ - NET_PROT_MACSEC, - NET_PROT_GRE, - NET_PROT_MINENCAP, - NET_PROT_DCCP, - NET_PROT_ICMP, - NET_PROT_IGMP, - NET_PROT_ARP, - NET_PROT_CAPWAP_DATA, - NET_PROT_CAPWAP_CTRL, - NET_PROT_RFC2684, - NET_PROT_ICMPV6, - NET_PROT_FCOE, - NET_PROT_FIP, - NET_PROT_ISCSI, - NET_PROT_GTP, - NET_PROT_USER_DEFINED_L2, - NET_PROT_USER_DEFINED_L3, - NET_PROT_USER_DEFINED_L4, - NET_PROT_USER_DEFINED_L5, - NET_PROT_USER_DEFINED_SHIM1, - NET_PROT_USER_DEFINED_SHIM2, - - NET_PROT_DUMMY_LAST +/* Macros for accessing command fields smaller than 1byte */ +#define DPNI_MASK(field) \ + GENMASK(DPNI_##field##_SHIFT + DPNI_##field##_SIZE - 1, \ + DPNI_##field##_SHIFT) +#define dpni_set_field(var, field, val) \ + ((var) |= (((val) << DPNI_##field##_SHIFT) & DPNI_MASK(field))) +#define dpni_get_field(var, field) \ + (((var) & DPNI_MASK(field)) >> DPNI_##field##_SHIFT) + +#pragma pack(push, 1) +struct dpni_cmd_open { + __le32 dpni_id; }; +struct dpni_cmd_create { + __le32 options; + u8 num_queues; + u8 num_tcs; + u8 mac_filter_entries; + u8 num_channels; + u8 vlan_filter_entries; + u8 pad2; + u8 qos_entries; + u8 pad3; + __le16 fs_entries; + u8 num_rx_tcs; + u8 pad4; + u8 num_cgs; + __le16 num_opr; + u8 dist_key_size; +}; + +struct dpni_cmd_destroy { + __le32 dpni_id; +}; + +#define DPNI_BACKUP_POOL(val, order) (((val) & 0x1) << (order)) + +struct dpni_cmd_pool { + __le16 dpbp_id; + u8 priority_mask; + u8 pad; +}; + +struct dpni_cmd_set_pools { + u8 num_dpbp; + u8 backup_pool_mask; + u8 pad; + u8 pool_options; + struct dpni_cmd_pool pool[8]; + __le16 buffer_size[8]; +}; + +struct dpni_rsp_get_attr { + /* response word 0 */ + __le32 options; + u8 num_queues; + u8 num_rx_tcs; + u8 mac_filter_entries; + u8 num_tx_tcs; + /* response word 1 */ + u8 vlan_filter_entries; + u8 num_channels; + u8 qos_entries; + u8 pad2; + __le16 fs_entries; + __le16 num_opr; + /* response word 2 */ + u8 qos_key_size; + u8 fs_key_size; + __le16 wriop_version; + u8 num_cgs; +}; + +/* There are 3 separate commands for configuring Rx, Tx and Tx confirmation + * buffer layouts, but they all share the same parameters. + * If one of the functions changes, below structure needs to be split. + */ + +#define DPNI_PASS_TS_SHIFT 0 +#define DPNI_PASS_TS_SIZE 1 +#define DPNI_PASS_PR_SHIFT 1 +#define DPNI_PASS_PR_SIZE 1 +#define DPNI_PASS_FS_SHIFT 2 +#define DPNI_PASS_FS_SIZE 1 +#define DPNI_PASS_SWO_SHIFT 3 +#define DPNI_PASS_SWO_SIZE 1 + +struct dpni_cmd_set_buffer_layout { + /* cmd word 0 */ + u8 qtype; + u8 pad0[3]; + __le16 options; + /* from LSB: pass_timestamp:1, parser_result:1, frame_status:1 */ + u8 flags; + u8 pad1; + /* cmd word 1 */ + __le16 private_data_size; + __le16 data_align; + __le16 head_room; + __le16 tail_room; +}; + +struct dpni_cmd_get_qdid { + u8 qtype; +}; + +struct dpni_rsp_get_qdid { + __le16 qdid; +}; + +struct dpni_rsp_get_tx_data_offset { + __le16 data_offset; +}; + +struct dpni_cmd_set_link_cfg { + __le64 pad0; + __le32 rate; + __le32 pad1; + __le64 options; + __le64 advertising; +}; + +#define DPNI_LINK_STATE_SHIFT 0 +#define DPNI_LINK_STATE_SIZE 1 +#define DPNI_STATE_VALID_SHIFT 1 +#define DPNI_STATE_VALID_SIZE 1 + +struct dpni_rsp_get_link_state { + __le32 pad0; + /* from LSB: up:1 */ + u8 flags; + u8 pad1[3]; + __le32 rate; + __le32 pad2; + __le64 options; + __le64 supported; + __le64 advertising; +}; + +struct dpni_cmd_add_mac_addr { + u8 flags; + u8 pad; + u8 mac_addr[6]; + u8 tc_id; + u8 fq_id; +}; + +struct dpni_cmd_get_queue { + u8 qtype; + u8 tc; + u8 index; + u8 channel_id; +}; + +#define DPNI_DEST_TYPE_SHIFT 0 +#define DPNI_DEST_TYPE_SIZE 4 +#define DPNI_CGID_VALID_SHIFT 5 +#define DPNI_CGID_VALID_SIZE 1 +#define DPNI_STASH_CTRL_SHIFT 6 +#define DPNI_STASH_CTRL_SIZE 1 +#define DPNI_HOLD_ACTIVE_SHIFT 7 +#define DPNI_HOLD_ACTIVE_SIZE 1 + +struct dpni_rsp_get_queue { + /* response word 0 */ + __le64 pad0; + /* response word 1 */ + __le32 dest_id; + __le16 pad1; + u8 dest_prio; + /* From LSB: dest_type:4, pad:1, cgid_valid:1, flc_stash_ctrl:1, hold_active:1 */ + u8 flags; + /* response word 2 */ + __le64 flc; + /* response word 3 */ + __le64 user_context; + /* response word 4 */ + __le32 fqid; + __le16 qdbin; + __le16 pad2; + /* response word 5*/ + u8 cgid; +}; + +struct dpni_cmd_set_queue { + /* cmd word 0 */ + u8 qtype; + u8 tc; + u8 index; + u8 options; + __le32 pad0; + /* cmd word 1 */ + __le32 dest_id; + __le16 pad1; + u8 dest_prio; + u8 flags; + /* cmd word 2 */ + __le64 flc; + /* cmd word 3 */ + __le64 user_context; + /* cmd word 4 */ + u8 cgid; + u8 channel_id; +}; + +struct dpni_tx_confirmation_mode { + u8 ceetm_ch_idx; + u8 pad1; + __le16 pad2; + u8 confirmation_mode; +}; + +struct dpni_cmd_get_statistics { + u8 page_number; + __le16 param; +}; + +struct dpni_rsp_get_statistics { + __le64 counter[7]; +}; + +#pragma pack(pop) + /** * Data Path Network Interface API * Contains initialization APIs and runtime control APIs for DPNI @@ -336,50 +276,17 @@ struct fsl_mc_io; #define DPNI_MAX_DPBP 8 /* All traffic classes considered; see dpni_set_rx_flow() */ -#define DPNI_ALL_TCS (uint8_t)(-1) +#define DPNI_ALL_TCS (u8)(-1) /* All flows within traffic class considered; see dpni_set_rx_flow() */ -#define DPNI_ALL_TC_FLOWS (uint16_t)(-1) +#define DPNI_ALL_TC_FLOWS (u16)(-1) /* Generate new flow ID; see dpni_set_tx_flow() */ -#define DPNI_NEW_FLOW_ID (uint16_t)(-1) +#define DPNI_NEW_FLOW_ID (u16)(-1) /* use for common tx-conf queue; see dpni_set_tx_conf_<x>() */ -#define DPNI_COMMON_TX_CONF (uint16_t)(-1) +#define DPNI_COMMON_TX_CONF (u16)(-1) -/** - * dpni_open() - Open a control session for the specified object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @dpni_id: DPNI unique ID - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpni_create() function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int dpni_id, - uint16_t *token); +int dpni_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int dpni_id, u16 *token); -/** - * dpni_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /* DPNI configuration options */ @@ -442,57 +349,84 @@ enum dpni_queue_type { DPNI_QUEUE_RX_ERR, }; -struct dpni_cfg { - uint8_t mac_addr[6]; - struct { - uint32_t options; - uint16_t fs_entries; - uint8_t num_queues; - uint8_t num_tcs; - uint8_t mac_entries; - uint8_t vlan_entries; - uint8_t qos_entries; - } adv; -}; - /** - * struct dpni_extended_cfg - Structure representing extended DPNI configuration - * @tc_cfg: TCs configuration - * @ipr_cfg: IP reassembly configuration + * struct dpni_cfg - Structure representing DPNI configuration + * @options: Any combination of the following options: + * DPNI_OPT_TX_FRM_RELEASE + * DPNI_OPT_NO_MAC_FILTER + * DPNI_OPT_HAS_POLICING + * DPNI_OPT_SHARED_CONGESTION + * DPNI_OPT_HAS_KEY_MASKING + * DPNI_OPT_NO_FS + * DPNI_OPT_SINGLE_SENDER + * DPNI_OPT_STASHING_DIS + * @fs_entries: Number of entries in the flow steering table. + * This table is used to select the ingress queue for + * ingress traffic, targeting a GPP core or another. + * In addition it can be used to discard traffic that + * matches the set rule. It is either an exact match table + * or a TCAM table, depending on DPNI_OPT_ HAS_KEY_MASKING + * bit in OPTIONS field. This field is ignored if + * DPNI_OPT_NO_FS bit is set in OPTIONS field. Otherwise, + * value 0 defaults to 64. Maximum supported value is 1024. + * Note that the total number of entries is limited on the + * SoC to as low as 512 entries if TCAM is used. + * @vlan_filter_entries: Number of entries in the VLAN address filtering + * table. This is an exact match table used to filter + * ingress traffic based on VLAN IDs. Value 0 disables VLAN + * filtering. Maximum supported value is 16. + * @mac_filter_entries: Number of entries in the MAC address filtering + * table. This is an exact match table and allows both + * unicast and multicast entries. The primary MAC address + * of the network interface is not part of this table, + * this contains only entries in addition to it. This + * field is ignored if DPNI_OPT_ NO_MAC_FILTER is set in + * OPTIONS field. Otherwise, value 0 defaults to 80. + * Maximum supported value is 80. + * @num_queues: Number of Tx and Rx queues used for traffic + * distribution. This is orthogonal to QoS and is only + * used to distribute traffic to multiple GPP cores. + * This configuration affects the number of Tx queues + * (logical FQs, all associated with a single CEETM queue), + * Rx queues and Tx confirmation queues, if applicable. + * Value 0 defaults to one queue. Maximum supported value + * is 8. + * @num_tcs: Number of traffic classes (TCs), reserved for the DPNI. + * TCs can have different priority levels for the purpose + * of Tx scheduling (see DPNI_SET_TX_PRIORITIES), different + * BPs (DPNI_ SET_POOLS), policers. There are dedicated QM + * queues for traffic classes (including class queues on + * Tx). Value 0 defaults to one TC. Maximum supported value + * is 16. There are maximum 16 TCs for Tx and 8 TCs for Rx. + * When num_tcs>8 Tx will use this value but Rx will have + * only 8 traffic classes. + * @num_rx_tcs: if set to other value than zero represents number + * of TCs used for Rx. Maximum value is 8. If set to zero the + * number of Rx TCs will be initialized with the value provided + * in num_tcs parameter. + * @qos_entries: Number of entries in the QoS classification table. This + * table is used to select the TC for ingress traffic. It + * is either an exact match or a TCAM table, depending on + * DPNI_OPT_ HAS_KEY_MASKING bit in OPTIONS field. This + * field is ignored if the DPNI has a single TC. Otherwise, + * a value of 0 defaults to 64. Maximum supported value + * is 64. + * @num_channels: Number of egress channels used by this dpni object. If + * set to zero the dpni object will use a single CEETM channel. */ -struct dpni_extended_cfg { - /** - * struct tc_cfg - TC configuration - * @max_dist: Maximum distribution size for Rx traffic class; - * supported values: 1,2,3,4,6,7,8,12,14,16,24,28,32,48,56,64,96, - * 112,128,192,224,256,384,448,512,768,896,1024; - * value '0' will be treated as '1'. - * other unsupported values will be round down to the nearest - * supported value. - * @max_fs_entries: Maximum FS entries for Rx traffic class; - * '0' means no support for this TC; - */ - struct { - uint16_t max_dist; - uint16_t max_fs_entries; - } tc_cfg[DPNI_MAX_TC]; - /** - * struct ipr_cfg - Structure representing IP reassembly configuration - * @max_reass_frm_size: Maximum size of the reassembled frame - * @min_frag_size_ipv4: Minimum fragment size of IPv4 fragments - * @min_frag_size_ipv6: Minimum fragment size of IPv6 fragments - * @max_open_frames_ipv4: Maximum concurrent IPv4 packets in reassembly - * process - * @max_open_frames_ipv6: Maximum concurrent IPv6 packets in reassembly - * process - */ - struct { - uint16_t max_reass_frm_size; - uint16_t min_frag_size_ipv4; - uint16_t min_frag_size_ipv6; - uint16_t max_open_frames_ipv4; - uint16_t max_open_frames_ipv6; - } ipr_cfg; +struct dpni_cfg { + u32 options; + u16 fs_entries; + u8 vlan_filter_entries; + u8 mac_filter_entries; + u8 num_queues; + u8 num_tcs; + u8 num_rx_tcs; + u8 qos_entries; + u8 num_cgs; + u16 num_opr; + u8 dist_key_size; + u8 num_channels; }; /** @@ -503,249 +437,108 @@ struct dpni_extended_cfg { * This function has to be called before dpni_create() */ int dpni_prepare_cfg(const struct dpni_cfg *cfg, - uint8_t *cfg_buf); -/** - * dpni_create() - Create the DPNI object - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @cfg: Configuration structure - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Create the DPNI object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpni_open() function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_create(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - const struct dpni_cfg *cfg, - uint32_t *obj_id); + u8 *cfg_buf); -/** - * dpni_destroy() - Destroy the DPNI object and release all its resources. - * @mc_io: Pointer to MC portal's I/O object - * @token: Authentication token. - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @obj_id: Returned obj_id; use in subsequent API calls - * - * Return: '0' on Success; error code otherwise. - */ -int dpni_destroy(struct fsl_mc_io *mc_io, - uint16_t token, - uint32_t cmd_flags, - uint32_t obj_id); +int dpni_create(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + const struct dpni_cfg *cfg, u32 *obj_id); + +int dpni_destroy(struct fsl_mc_io *mc_io, u16 dprc_token, u32 cmd_flags, + u32 object_id); /** * struct dpni_pools_cfg - Structure representing buffer pools configuration - * @num_dpbp: Number of DPBPs - * @pools: Array of buffer pools parameters; The number of valid entries - * must match 'num_dpbp' value + * @num_dpbp: Number of DPBPs + * @pool_options: Buffer assignment options + * This field is a combination of DPNI_POOL_ASSOC_flags + * @pools: Array of buffer pools parameters; The number of valid entries + * must match 'num_dpbp' value + * @pools.dpbp_id: DPBP object ID + * @pools.priority: Priority mask that indicates TC's used with this buffer. + * I set to 0x00 MC will assume value 0xff. + * @pools.buffer_size: Buffer size + * @pools.backup_pool: Backup pool */ + +#define DPNI_POOL_ASSOC_QPRI 0 +#define DPNI_POOL_ASSOC_QDBIN 1 + struct dpni_pools_cfg { - uint8_t num_dpbp; - /** - * struct pools - Buffer pools parameters - * @dpbp_id: DPBP object ID - * @buffer_size: Buffer size - * @backup_pool: Backup pool - */ + u8 num_dpbp; + u8 pool_options; struct { int dpbp_id; - uint16_t buffer_size; + u8 priority_mask; + u16 buffer_size; int backup_pool; } pools[DPNI_MAX_DPBP]; }; -/** - * dpni_set_pools() - Set buffer pools configuration - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @cfg: Buffer pools configuration - * - * mandatory for DPNI operation - * warning:Allowed only when DPNI is disabled - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_pools(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_pools_cfg *cfg); +int dpni_set_pools(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dpni_pools_cfg *cfg); -/** - * dpni_enable() - Enable the DPNI, allow sending and receiving frames. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_enable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_enable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); -/** - * dpni_disable() - Disable the DPNI, stop sending and receiving frames. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_disable(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_disable(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); - -/** - * dpni_reset() - Reset the DPNI, returns the object to initial state. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_reset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_reset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * struct dpni_attr - Structure representing DPNI attributes - * @options: Mask of available options; reflects the value as was given in - * object's creation - * @max_num_queues: Number of queues available (for both Tx and Rx) - * @max_num_tcs: Maximum number of traffic classes (for both Tx and Rx) - * @max_mac_entries: Maximum number of traffic classes (for both Tx and Rx) - * @max_unicast_filters: Maximum number of unicast filters - * @max_multicast_filters: Maximum number of multicast filters - * @max_vlan_entries: Maximum number of VLAN filters - * @max_qos_entries: if 'max_tcs > 1', declares the maximum entries in QoS table - * @max_fs_entries: declares the maximum entries in flow steering table - * @max_qos_key_size: Maximum key size for the QoS look-up - * @max_fs_key_size: Maximum key size for the flow steering - * @wriop_version: Indicates revision of WRIOP hardware block + * @options: Any combination of the following options: + * DPNI_OPT_TX_FRM_RELEASE + * DPNI_OPT_NO_MAC_FILTER + * DPNI_OPT_HAS_POLICING + * DPNI_OPT_SHARED_CONGESTION + * DPNI_OPT_HAS_KEY_MASKING + * DPNI_OPT_NO_FS + * DPNI_OPT_STASHING_DIS + * @num_queues: Number of Tx and Rx queues used for traffic distribution. + * @num_rx_tcs: Number of RX traffic classes (TCs), reserved for the DPNI. + * @num_tx_tcs: Number of TX traffic classes (TCs), reserved for the DPNI. + * @mac_filter_entries: Number of entries in the MAC address filtering + * table. + * @vlan_filter_entries: Number of entries in the VLAN address filtering + * table. + * @qos_entries: Number of entries in the QoS classification table. + * @fs_entries: Number of entries in the flow steering table. + * @qos_key_size: Size, in bytes, of the QoS look-up key. Defining a key larger + * than this when adding QoS entries will result + * in an error. + * @fs_key_size: Size, in bytes, of the flow steering look-up key. Defining a + * key larger than this when composing the hash + FS key + * will result in an error. + * @wriop_version: Version of WRIOP HW block. + * The 3 version values are stored on 6, 5, 5 bits + * respectively. + * Values returned: + * - 0x400 - WRIOP version 1.0.0, used on LS2080 and + * variants, + * - 0x421 - WRIOP version 1.1.1, used on LS2088 and + * variants, + * - 0x422 - WRIOP version 1.1.2, used on LS1088 and + * variants. + * - 0xC00 - WRIOP version 3.0.0, used on LX2160 and + * variants. */ struct dpni_attr { - uint32_t id; - uint32_t options; - uint8_t max_num_queues; - uint8_t max_num_tcs; - uint8_t max_mac_entries; - uint8_t max_vlan_entries; - uint8_t max_qos_entries; - uint16_t max_fs_entries; - uint8_t max_qos_key_size; - uint8_t max_fs_key_size; - uint16_t wriop_version; -}; - -/** - * dpni_get_attributes() - Retrieve DPNI attributes. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @attr: Object's attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_attr *attr); - -/** - * dpni_extract_cfg() - extract the parameters - * @cfg: cfg structure - * @cfg_buf: 256 bytes of DMA-able memory - * - * This function has to be called after dpni_get_attributes() - */ -int dpni_extract_cfg(struct dpni_cfg *cfg, - const uint8_t *cfg_buf); - -/** - * DPNI errors - */ - -/** - * Extract out of frame header error - */ -#define DPNI_ERROR_EOFHE 0x00020000 -/** - * Frame length error - */ -#define DPNI_ERROR_FLE 0x00002000 -/** - * Frame physical error - */ -#define DPNI_ERROR_FPE 0x00001000 -/** - * Parsing header error - */ -#define DPNI_ERROR_PHE 0x00000020 -/** - * Parser L3 checksum error - */ -#define DPNI_ERROR_L3CE 0x00000004 -/** - * Parser L3 checksum error - */ -#define DPNI_ERROR_L4CE 0x00000001 - -/** - * enum dpni_error_action - Defines DPNI behavior for errors - * @DPNI_ERROR_ACTION_DISCARD: Discard the frame - * @DPNI_ERROR_ACTION_CONTINUE: Continue with the normal flow - * @DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE: Send the frame to the error queue - */ -enum dpni_error_action { - DPNI_ERROR_ACTION_DISCARD = 0, - DPNI_ERROR_ACTION_CONTINUE = 1, - DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE = 2 + u32 options; + u8 num_queues; + u8 num_rx_tcs; + u8 num_tx_tcs; + u8 mac_filter_entries; + u8 vlan_filter_entries; + u8 qos_entries; + u16 fs_entries; + u16 num_opr; + u8 qos_key_size; + u8 fs_key_size; + u16 wriop_version; + u8 num_cgs; + u8 num_channels; }; -/** - * struct dpni_error_cfg - Structure representing DPNI errors treatment - * @errors: Errors mask; use 'DPNI_ERROR__<X> - * @error_action: The desired action for the errors mask - * @set_frame_annotation: Set to '1' to mark the errors in frame annotation - * status (FAS); relevant only for the non-discard action - */ -struct dpni_error_cfg { - uint32_t errors; - enum dpni_error_action error_action; - int set_frame_annotation; -}; - -/** - * dpni_set_errors_behavior() - Set errors behavior - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @cfg: Errors configuration - * - * this function may be called numerous times with different - * error masks - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_error_cfg *cfg); +int dpni_get_attributes(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpni_attr *attr); /* DPNI buffer layout modification options */ @@ -763,93 +556,45 @@ int dpni_set_errors_behavior(struct fsl_mc_io *mc_io, #define DPNI_BUF_LAYOUT_OPT_DATA_HEAD_ROOM 0x00000020 /*!< Select to modify the data-tail-room setting */ #define DPNI_BUF_LAYOUT_OPT_DATA_TAIL_ROOM 0x00000040 +/* Select to modify the sw-opaque value setting */ +#define DPNI_BUF_LAYOUT_OPT_SW_OPAQUE 0x00000080 +/* Select to disable Scatter Gather and use single buffer */ +#define DPNI_BUF_LAYOUT_OPT_NO_SG 0x00000100 /** * struct dpni_buffer_layout - Structure representing DPNI buffer layout - * @options: Flags representing the suggested modifications to the buffer - * layout; Use any combination of 'DPNI_BUF_LAYOUT_OPT_<X>' flags - * @pass_timestamp: Pass timestamp value - * @pass_parser_result: Pass parser results - * @pass_frame_status: Pass frame status - * @private_data_size: Size kept for private data (in bytes) - * @data_align: Data alignment - * @data_head_room: Data head room - * @data_tail_room: Data tail room + * @options: Flags representing the suggested modifications to the + * buffer layout; + * Use any combination of 'DPNI_BUF_LAYOUT_OPT_<X>' flags + * @pass_timestamp: Pass timestamp value + * @pass_parser_result: Pass parser results + * @pass_frame_status: Pass frame status + * @private_data_size: Size kept for private data (in bytes) + * @data_align: Data alignment + * @data_head_room: Data head room + * @data_tail_room: Data tail room */ struct dpni_buffer_layout { - uint16_t options; + u32 options; int pass_timestamp; int pass_parser_result; int pass_frame_status; - uint16_t private_data_size; - uint16_t data_align; - uint16_t data_head_room; - uint16_t data_tail_room; + int pass_sw_opaque; + u16 private_data_size; + u16 data_align; + u16 data_head_room; + u16 data_tail_room; }; -/** - * dpni_get_buffer_layout() - Retrieve buffer layout attributes. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @layout: Returns buffer layout attributes - * @type: DPNI queue type - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_buffer_layout *layout, - enum dpni_queue_type type); - -/** - * dpni_set_buffer_layout() - Set buffer layout configuration. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @layout: Buffer layout configuration - * @type: DPNI queue type - * - * Return: '0' on Success; Error code otherwise. - * - * @warning Allowed only when DPNI is disabled - */ -int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_buffer_layout *layout, - enum dpni_queue_type type); +int dpni_set_buffer_layout(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, + const struct dpni_buffer_layout *layout); -/** - * dpni_get_qdid() - Get the Queuing Destination ID (QDID) that should be used - * for enqueue operations - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @qdid: Returned virtual QDID value that should be used as an argument - * in all enqueue operations - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_qdid(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t *qdid); +int dpni_get_qdid(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 *qdid); -/** - * dpni_get_tx_data_offset() - Get the Tx data offset (from start of buffer) - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @data_offset: Tx data offset (from start of buffer) - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint16_t *data_offset); +int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u16 *data_offset); /* Enable auto-negotiation */ #define DPNI_LINK_OPT_AUTONEG 0x0000000000000001ULL @@ -864,107 +609,44 @@ int dpni_get_tx_data_offset(struct fsl_mc_io *mc_io, * struct - Structure representing DPNI link configuration * @rate: Rate * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values + * @advertising: Speeds that are advertised for autoneg (bitmap) */ struct dpni_link_cfg { - uint32_t rate; - uint64_t options; + u32 rate; + u64 options; + u64 advertising; }; -/** - * dpni_set_link_cfg() - set the link configuration. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @cfg: Link configuration - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_link_cfg(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dpni_link_cfg *cfg); +int dpni_set_link_cfg(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dpni_link_cfg *cfg); /** * struct dpni_link_state - Structure representing DPNI link state - * @rate: Rate - * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values - * @up: Link state; '0' for down, '1' for up + * @rate: Rate + * @options: Mask of available options; use 'DPNI_LINK_OPT_<X>' values + * @up: Link state; '0' for down, '1' for up + * @state_valid: Ignore/Update the state of the link + * @supported: Speeds capability of the phy (bitmap) + * @advertising: Speeds that are advertised for autoneg (bitmap) */ struct dpni_link_state { - uint32_t rate; - uint64_t options; + u32 rate; + u64 options; int up; + int state_valid; + u64 supported; + u64 advertising; }; -/** - * dpni_get_link_state() - Return the link state (either up or down) - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @state: Returned link state; - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_link_state(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dpni_link_state *state); +int dpni_get_link_state(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dpni_link_state *state); -/** - * dpni_set_primary_mac_addr() - Set the primary MAC address - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: MAC address to set as primary address - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_primary_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]); - -/** - * dpni_get_primary_mac_addr() - Get the primary MAC address - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: Returned MAC address - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_primary_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t mac_addr[6]); +int dpni_add_mac_addr(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const u8 mac_addr[6], u8 flags, + u8 tc_id, u8 flow_id); -/** - * dpni_add_mac_addr() - Add MAC address filter - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: MAC address to add - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_add_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]); - -/** - * dpni_remove_mac_addr() - Remove MAC address filter - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mac_addr: MAC address to remove - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_remove_mac_addr(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const uint8_t mac_addr[6]); +int dpni_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); /** * enum dpni_dest - DPNI destination types @@ -985,137 +667,6 @@ enum dpni_dest { DPNI_DEST_DPCON = 2 }; -/** - * struct dpni_dest_cfg - Structure representing DPNI destination parameters - * @dest_type: Destination type - * @dest_id: Either DPIO ID or DPCON ID, depending on the destination type - * @priority: Priority selection within the DPIO or DPCON channel; valid values - * are 0-1 or 0-7, depending on the number of priorities in that - * channel; not relevant for 'DPNI_DEST_NONE' option - */ -struct dpni_dest_cfg { - enum dpni_dest dest_type; - int dest_id; - uint8_t priority; -}; - -/** - * enum dpni_flc_type - DPNI FLC types - * @DPNI_FLC_USER_DEFINED: select the FLC to be used for user defined value - * @DPNI_FLC_STASH: select the FLC to be used for stash control - */ -enum dpni_flc_type { - DPNI_FLC_USER_DEFINED = 0, - DPNI_FLC_STASH = 1, -}; - -/** - * enum dpni_stash_size - DPNI FLC stashing size - * @DPNI_STASH_SIZE_0B: no stash - * @DPNI_STASH_SIZE_64B: stashes 64 bytes - * @DPNI_STASH_SIZE_128B: stashes 128 bytes - * @DPNI_STASH_SIZE_192B: stashes 192 bytes - */ -enum dpni_stash_size { - DPNI_STASH_SIZE_0B = 0, - DPNI_STASH_SIZE_64B = 1, - DPNI_STASH_SIZE_128B = 2, - DPNI_STASH_SIZE_192B = 3, -}; - -/* DPNI FLC stash options */ - -/* stashes the whole annotation area (up to 192 bytes) */ -#define DPNI_FLC_STASH_FRAME_ANNOTATION 0x00000001 - -/** - * struct dpni_flc_cfg - Structure representing DPNI FLC configuration - * @flc_type: FLC type - * @options: Mask of available options; - * use 'DPNI_FLC_STASH_<X>' values - * @frame_data_size: Size of frame data to be stashed - * @flow_context_size: Size of flow context to be stashed - * @flow_context: 1. In case flc_type is 'DPNI_FLC_USER_DEFINED': - * this value will be provided in the frame descriptor - * (FD[FLC]) - * 2. In case flc_type is 'DPNI_FLC_STASH': - * this value will be I/O virtual address of the - * flow-context; - * Must be cacheline-aligned and DMA-able memory - */ -struct dpni_flc_cfg { - enum dpni_flc_type flc_type; - uint32_t options; - enum dpni_stash_size frame_data_size; - enum dpni_stash_size flow_context_size; - uint64_t flow_context; -}; - -/* DPNI queue modification options */ - -/* Select to modify the user's context associated with the queue */ -#define DPNI_QUEUE_OPT_USER_CTX 0x00000001 -/* Select to modify the queue's destination */ -#define DPNI_QUEUE_OPT_DEST 0x00000002 -/** Select to modify the flow-context parameters; - * not applicable for Tx-conf/Err queues as the FD comes from the user - */ -#define DPNI_QUEUE_OPT_FLC 0x00000004 -/* Select to modify the queue's order preservation */ -#define DPNI_QUEUE_OPT_ORDER_PRESERVATION 0x00000008 -/* Select to modify the queue's tail-drop threshold */ -#define DPNI_QUEUE_OPT_TAILDROP_THRESHOLD 0x00000010 - -/** - * struct dpni_queue_cfg - Structure representing queue configuration - * @options: Flags representing the suggested modifications to the queue; - * Use any combination of 'DPNI_QUEUE_OPT_<X>' flags - * @user_ctx: User context value provided in the frame descriptor of each - * dequeued frame; valid only if 'DPNI_QUEUE_OPT_USER_CTX' - * is contained in 'options' - * @dest_cfg: Queue destination parameters; - * valid only if 'DPNI_QUEUE_OPT_DEST' is contained in 'options' - * @flc_cfg: Flow context configuration; in case the TC's distribution - * is either NONE or HASH the FLC's settings of flow#0 are used. - * in the case of FS (flow-steering) the flow's FLC settings - * are used. - * valid only if 'DPNI_QUEUE_OPT_FLC' is contained in 'options' - * @order_preservation_en: enable/disable order preservation; - * valid only if 'DPNI_QUEUE_OPT_ORDER_PRESERVATION' is contained - * in 'options' - * @tail_drop_threshold: set the queue's tail drop threshold in bytes; - * '0' value disable the threshold; maximum value is 0xE000000; - * valid only if 'DPNI_QUEUE_OPT_TAILDROP_THRESHOLD' is contained - * in 'options' - */ -struct dpni_queue_cfg { - uint32_t options; - uint64_t user_ctx; - struct dpni_dest_cfg dest_cfg; - struct dpni_flc_cfg flc_cfg; - int order_preservation_en; - uint32_t tail_drop_threshold; -}; - -/** - * struct dpni_queue_attr - Structure representing queue attributes - * @user_ctx: User context value provided in the frame descriptor of each - * dequeued frame - * @dest_cfg: Queue destination configuration - * @flc_cfg: Flow context configuration - * @order_preservation_en: enable/disable order preservation - * @tail_drop_threshold: queue's tail drop threshold in bytes; - * @fqid: Virtual fqid value to be used for dequeue operations - */ -struct dpni_queue_attr { - uint64_t user_ctx; - struct dpni_dest_cfg dest_cfg; - struct dpni_flc_cfg flc_cfg; - int order_preservation_en; - uint32_t tail_drop_threshold; - uint32_t fqid; -}; - /* DPNI Tx flow modification options */ /* Select to modify the settings for dedicate Tx confirmation/error */ @@ -1126,21 +677,6 @@ struct dpni_queue_attr { #define DPNI_TX_FLOW_OPT_L4_CHKSUM_GEN 0x00000020 /** - * dpni_get_api_version - Retrieve DPNI Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPNI major version - * @minor_ver: DPNI minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); - -/** * enum dpni_confirmation_mode - Defines DPNI options supported for Tx * confirmation * @DPNI_CONF_AFFINE: For each Tx queue set associated with a sender there is @@ -1149,7 +685,7 @@ int dpni_get_api_version(struct fsl_mc_io *mc_io, * confirmation queue * @DPNI_CONF_DISABLE: Tx frames are not confirmed. This must be associated * with proper FD set-up to have buffers release to a Buffer Pool, otherwise - * buffers will be leaked. + * buffers will be leaked */ enum dpni_confirmation_mode { DPNI_CONF_AFFINE, @@ -1157,168 +693,194 @@ enum dpni_confirmation_mode { DPNI_CONF_DISABLE, }; -struct dpni_tx_confirmation_mode { - uint32_t pad; - uint8_t confirmation_mode; -}; +/** + * stashes the whole annotation area (up to 192 bytes) + */ +#define DPNI_FLC_STASH_FRAME_ANNOTATION 0x00000001 /** * struct dpni_queue - Queue structure - * @fqid: FQID used for enqueueing to and/or configuration of this specific FQ - * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. Only relevant - * for Tx queues. - * @flc: FLC value for traffic dequeued from this queue. - * @user_context: User data, presented to the user along with any frames - * from this queue. Not relevant for Tx queues. + * @destination - Destination structure + * @destination.id: ID of the destination, only relevant if DEST_TYPE is > 0. + * Identifies either a DPIO or a DPCON object. + * Not relevant for Tx queues. + * @destination.type: May be one of the following: + * 0 - No destination, queue can be manually + * queried, but will not push traffic or + * notifications to a DPIO; + * 1 - The destination is a DPIO. When traffic + * becomes available in the queue a FQDAN + * (FQ data available notification) will be + * generated to selected DPIO; + * 2 - The destination is a DPCON. The queue is + * associated with a DPCON object for the + * purpose of scheduling between multiple + * queues. The DPCON may be independently + * configured to generate notifications. + * Not relevant for Tx queues. + * @destination.hold_active: Hold active, maintains a queue scheduled for longer + * in a DPIO during dequeue to reduce spread of traffic. + * Only relevant if queues are + * not affined to a single DPIO. + * @user_context: User data, presented to the user along with any frames + * from this queue. Not relevant for Tx queues. + * @flc: FD FLow Context structure + * @flc.value: Default FLC value for traffic dequeued from + * this queue. Please check description of FD + * structure for more information. + * Note that FLC values set using dpni_add_fs_entry, + * if any, take precedence over values per queue. + * @flc.stash_control: Boolean, indicates whether the 6 lowest + * - significant bits are used for stash control. + * significant bits are used for stash control. If set, the 6 + * least significant bits in value are interpreted as follows: + * - bits 0-1: indicates the number of 64 byte units of context + * that are stashed. FLC value is interpreted as a memory address + * in this case, excluding the 6 LS bits. + * - bits 2-3: indicates the number of 64 byte units of frame + * annotation to be stashed. Annotation is placed at FD[ADDR]. + * - bits 4-5: indicates the number of 64 byte units of frame + * data to be stashed. Frame data is placed at FD[ADDR] + + * FD[OFFSET]. + * For more details check the Frame Descriptor section in the + * hardware documentation. + *@cgid :indicate the cgid to set relative to dpni */ struct dpni_queue { - /** - * struct destination - Destination structure - * @id: ID of the destination, only relevant if DEST_TYPE is > 0. - * Identifies either a DPIO or a DPCON object. Not relevant for Tx - * queues. - * @type: May be one of the following: - * 0 - No destination, queue can be manually queried, but won't - * push traffic or notifications to a DPIO; - * 1 - The destination is DPIO. When traffic becomes available in - * the queue a FQDAN (FQ data available notification) will be - * generated to selected DPIO; - * 2 - The destination is a DPCON. The queue is associated with a - * DPCON object for purpose of scheduling between multiple - * queues. The DPCON may be independently configured to - * generate notifications. Not relevant for Tx queues. - * @hold_active: Hold active - */ struct { - uint32_t id; + u16 id; enum dpni_dest type; char hold_active; - char stash_ctrl; + u8 priority; } destination; - uint8_t options; - uint32_t fqid; - uint16_t qdbin; - uint64_t flc; - uint64_t user_context; + u64 user_context; + struct { + u64 value; + char stash_control; + } flc; + int cgid; }; /** - * dpni_set_queue() - Set queue parameters - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @type: Type of queue - * @tc: Traffic class, in range 0 to NUM_TCS - 1 - * @index: Selects the specific queue out of the set allocated for the same - * TC. Value must be in range 0 to NUM_QUEUES - 1 - * @queue: Queue structure - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_queue(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_queue_type type, - uint8_t tc, - uint8_t index, - const struct dpni_queue *queue); - -/** - * dpni_get_queue() - Get queue parameters - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @type: Type of queue - * @tc: Traffic class, in range 0 to NUM_TCS - 1 - * @index: Selects the specific queue out of the set allocated for the same - * TC. Value must be in range 0 to NUM_QUEUES - 1 - * @queue: Queue structure - * - * Return: '0' on Success; Error code otherwise. + * struct dpni_queue_id - Queue identification, used for enqueue commands + * or queue control + * @fqid: FQID used for enqueueing to and/or configuration of this + * specific FQ + * @qdbin: Queueing bin, used to enqueue using QDID, DQBIN, QPRI. + * Only relevant for Tx queues. */ -int dpni_get_queue(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_queue_type type, - uint8_t tc, - uint8_t index, - struct dpni_queue *queue); - -/** - * dpni_set_tx_confirmation_mode() - Set TX conf mode - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @mode: DPNI confirmation mode type - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - enum dpni_confirmation_mode mode); -struct dpni_statistics { - /** - * Page_0 statistics structure - * @ingress_all_frames: Ingress frame count - * @ingress_all_bytes: Ingress byte count - * @ingress_multicast_frames: Ingress multicast frame count - * @ingress_multicast_bytes: Ingress multicast byte count - * @ingress_broadcast_frames: Ingress broadcast frame count - * @ingress_broadcast_bytes: Ingress broadcast byte count - * - * Page_1 statistics structure - * @egress_all_frames: Egress frame count - * @egress_all_bytes: Egress byte count - * @egress_multicast_frames: Egress multicast frame count - * @egress_multicast_bytes: Egress multicast byte count - * @egress_broadcast_frames: Egress broadcast frame count - * @egress_broadcast_bytes: Egress broadcast byte count - * - * Page_2 statistics structure - * @ingress_filtered_frames: Ingress filtered frame count - * @ingress_discarded_frames: Ingress discarded frame count - * @ingress_nobuffer_discards: Ingress discarded frame count due to - * lack of buffers. - * @egress_discarded_frames: Egress discarded frame count - * @egress_confirmed_frames: Egress confirmed frame count - */ - - uint64_t counter0; - uint64_t counter1; - uint64_t counter2; - uint64_t counter3; - uint64_t counter4; - uint64_t counter5; - uint64_t counter6; +struct dpni_queue_id { + u32 fqid; + u16 qdbin; }; -/** - * dpni_get_statistics() - Get DPNI statistics - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * @page: Selects the statistics page to retrieve, see DPNI_GET_STATISTICS - * output. Pages are numbered 0 to 2. - * @stat: Structure containing the statistics - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_get_statistics(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - uint8_t page, - struct dpni_statistics *stat); +int dpni_set_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 param, u8 index, + u8 options, const struct dpni_queue *queue); + +int dpni_get_queue(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + enum dpni_queue_type qtype, u16 param, u8 index, + struct dpni_queue *queue, struct dpni_queue_id *qid); + +int dpni_set_tx_confirmation_mode(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 ceetm_ch_idx, enum dpni_confirmation_mode mode); + +#define DPNI_STATISTICS_CNT 7 + +/** + * union dpni_statistics - Union describing the DPNI statistics + * @page_0: Page_0 statistics structure + * @page_0.ingress_all_frames: Ingress frame count + * @page_0.ingress_all_bytes: Ingress byte count + * @page_0.ingress_multicast_frames: Ingress multicast frame count + * @page_0.ingress_multicast_bytes: Ingress multicast byte count + * @page_0.ingress_broadcast_frames: Ingress broadcast frame count + * @page_0.ingress_broadcast_bytes: Ingress broadcast byte count + * @page_1: Page_1 statistics structure + * @page_1.egress_all_frames: Egress frame count + * @page_1.egress_all_bytes: Egress byte count + * @page_1.egress_multicast_frames: Egress multicast frame count + * @page_1.egress_multicast_bytes: Egress multicast byte count + * @page_1.egress_broadcast_frames: Egress broadcast frame count + * @page_1.egress_broadcast_bytes: Egress broadcast byte count + * @page_2: Page_2 statistics structure + * @page_2.ingress_filtered_frames: Ingress filtered frame count + * @page_2.ingress_discarded_frames: Ingress discarded frame count + * @page_2.ingress_nobuffer_discards: Ingress discarded frame count due to + * lack of buffers + * @page_2.egress_discarded_frames: Egress discarded frame count + * @page_2.egress_confirmed_frames: Egress confirmed frame count + * @page_3: Page_3 statistics structure + * @page_3.egress_dequeue_bytes: Cumulative count of the number of bytes + * dequeued from egress FQs + * @page_3.egress_dequeue_frames: Cumulative count of the number of frames + * dequeued from egress FQs + * @page_3.egress_reject_bytes: Cumulative count of the number of bytes in + * egress frames whose enqueue was rejected + * @page_3.egress_reject_frames: Cumulative count of the number of egress + * frames whose enqueue was rejected + * @page_4: Page_4 statistics structure: congestion points + * @page_4.cgr_reject_frames: number of rejected frames due to congestion point + * @page_4.cgr_reject_bytes: number of rejected bytes due to congestion point + * @page_5: Page_5 statistics structure: policer + * @page_5.policer_cnt_red: NUmber of red colored frames + * @page_5.policer_cnt_yellow: number of yellow colored frames + * @page_5.policer_cnt_green: number of green colored frames + * @page_5.policer_cnt_re_red: number of recolored red frames + * @page_5.policer_cnt_re_yellow: number of recolored yellow frames + * @page_6: Page_6 statistics structure + * @page_6.tx_pending_frames: total number of frames pending in egress FQs + * @raw: raw statistics structure, used to index counters + */ +union dpni_statistics { + struct { + u64 ingress_all_frames; + u64 ingress_all_bytes; + u64 ingress_multicast_frames; + u64 ingress_multicast_bytes; + u64 ingress_broadcast_frames; + u64 ingress_broadcast_bytes; + } page_0; + struct { + u64 egress_all_frames; + u64 egress_all_bytes; + u64 egress_multicast_frames; + u64 egress_multicast_bytes; + u64 egress_broadcast_frames; + u64 egress_broadcast_bytes; + } page_1; + struct { + u64 ingress_filtered_frames; + u64 ingress_discarded_frames; + u64 ingress_nobuffer_discards; + u64 egress_discarded_frames; + u64 egress_confirmed_frames; + } page_2; + struct { + u64 egress_dequeue_bytes; + u64 egress_dequeue_frames; + u64 egress_reject_bytes; + u64 egress_reject_frames; + } page_3; + struct { + u64 cgr_reject_frames; + u64 cgr_reject_bytes; + } page_4; + struct { + u64 policer_cnt_red; + u64 policer_cnt_yellow; + u64 policer_cnt_green; + u64 policer_cnt_re_red; + u64 policer_cnt_re_yellow; + } page_5; + struct { + u64 tx_pending_frames; + } page_6; + struct { + u64 counter[DPNI_STATISTICS_CNT]; + } raw; +}; -/** - * dpni_reset_statistics() - Clears DPNI statistics - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPNI object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpni_reset_statistics(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dpni_get_statistics(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u8 page, u16 param, union dpni_statistics *stat); #endif /* _FSL_DPNI_H */ diff --git a/include/fsl-mc/fsl_dprc.h b/include/fsl-mc/fsl_dprc.h index 950ecb0..fb95ac5 100644 --- a/include/fsl-mc/fsl_dprc.h +++ b/include/fsl-mc/fsl_dprc.h @@ -3,7 +3,7 @@ * Freescale Layerscape MC I/O wrapper * * Copyright 2013-2016 Freescale Semiconductor, Inc. - * Copyright 2017 NXP + * Copyright 2017, 2023 NXP */ #ifndef _FSL_DPRC_H #define _FSL_DPRC_H @@ -15,442 +15,82 @@ /* Command IDs */ #define DPRC_CMDID_CLOSE 0x8001 #define DPRC_CMDID_OPEN 0x8051 -#define DPRC_CMDID_CREATE 0x9051 -#define DPRC_CMDID_GET_ATTR 0x0041 -#define DPRC_CMDID_RESET_CONT 0x0051 #define DPRC_CMDID_GET_API_VERSION 0xa051 #define DPRC_CMDID_CREATE_CONT 0x1511 #define DPRC_CMDID_DESTROY_CONT 0x1521 #define DPRC_CMDID_GET_CONT_ID 0x8301 -#define DPRC_CMDID_GET_OBJ_COUNT 0x1591 -#define DPRC_CMDID_GET_OBJ 0x15A1 -#define DPRC_CMDID_GET_RES_COUNT 0x15B1 -#define DPRC_CMDID_GET_RES_IDS 0x15C1 -#define DPRC_CMDID_GET_OBJ_REG 0x15E1 #define DPRC_CMDID_CONNECT 0x1671 #define DPRC_CMDID_DISCONNECT 0x1681 #define DPRC_CMDID_GET_CONNECTION 0x16C1 -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_CONTAINER_ID(cmd, container_id) \ - MC_RSP_OP(cmd, 0, 0, 32, int, container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_OPEN(cmd, container_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_CREATE_CONTAINER(cmd, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->options); \ - MC_CMD_OP(cmd, 1, 32, 32, int, cfg->portal_id); \ - MC_CMD_OP(cmd, 2, 0, 8, char, cfg->label[0]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, cfg->label[1]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, cfg->label[2]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, cfg->label[3]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, cfg->label[4]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, cfg->label[5]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, cfg->label[6]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, cfg->label[7]);\ - MC_CMD_OP(cmd, 3, 0, 8, char, cfg->label[8]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, cfg->label[9]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, cfg->label[10]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, cfg->label[11]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, cfg->label[12]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, cfg->label[13]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, cfg->label[14]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, cfg->label[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_CREATE_CONTAINER(cmd, child_container_id, child_portal_offset)\ -do { \ - MC_RSP_OP(cmd, 1, 0, 32, int, child_container_id); \ - MC_RSP_OP(cmd, 2, 0, 64, uint64_t, child_portal_offset);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_DESTROY_CONTAINER(cmd, child_container_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_RESET_CONTAINER(cmd, child_container_id) \ - MC_CMD_OP(cmd, 0, 0, 32, int, child_container_id) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_ATTRIBUTES(cmd, attr) \ -do { \ - MC_RSP_OP(cmd, 0, 0, 32, int, attr->container_id); \ - MC_RSP_OP(cmd, 0, 32, 16, uint16_t, attr->icid); \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, attr->options);\ - MC_RSP_OP(cmd, 1, 32, 32, int, attr->portal_id); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ_COUNT(cmd, obj_count) \ - MC_RSP_OP(cmd, 0, 32, 32, int, obj_count) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_OBJ(cmd, obj_index) \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_index) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ(cmd, obj_desc) \ -do { \ - MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ - MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ - MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ - MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ - MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ - MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ - MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ - MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ - MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ - MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ - MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ - MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ - MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ - MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ - MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ - MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ - MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ - MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ - MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ - MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ - MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ - MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ - MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ - MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ - MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\ - MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\ - MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\ - MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\ - MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\ - MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\ - MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\ - MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\ - MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\ - MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\ - MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\ - MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\ - MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\ - MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\ - MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\ - MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_OBJ_DESC(cmd, obj_type, obj_id) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_id);\ - MC_CMD_OP(cmd, 1, 0, 8, char, obj_type[0]);\ - MC_CMD_OP(cmd, 1, 8, 8, char, obj_type[1]);\ - MC_CMD_OP(cmd, 1, 16, 8, char, obj_type[2]);\ - MC_CMD_OP(cmd, 1, 24, 8, char, obj_type[3]);\ - MC_CMD_OP(cmd, 1, 32, 8, char, obj_type[4]);\ - MC_CMD_OP(cmd, 1, 40, 8, char, obj_type[5]);\ - MC_CMD_OP(cmd, 1, 48, 8, char, obj_type[6]);\ - MC_CMD_OP(cmd, 1, 56, 8, char, obj_type[7]);\ - MC_CMD_OP(cmd, 2, 0, 8, char, obj_type[8]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, obj_type[9]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, obj_type[10]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, obj_type[11]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, obj_type[12]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, obj_type[13]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, obj_type[14]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, obj_type[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ_DESC(cmd, obj_desc) \ -do { \ - MC_RSP_OP(cmd, 0, 32, 32, int, obj_desc->id); \ - MC_RSP_OP(cmd, 1, 0, 16, uint16_t, obj_desc->vendor); \ - MC_RSP_OP(cmd, 1, 16, 8, uint8_t, obj_desc->irq_count); \ - MC_RSP_OP(cmd, 1, 24, 8, uint8_t, obj_desc->region_count); \ - MC_RSP_OP(cmd, 1, 32, 32, uint32_t, obj_desc->state);\ - MC_RSP_OP(cmd, 2, 0, 16, uint16_t, obj_desc->ver_major);\ - MC_RSP_OP(cmd, 2, 16, 16, uint16_t, obj_desc->ver_minor);\ - MC_RSP_OP(cmd, 2, 32, 16, uint16_t, obj_desc->flags); \ - MC_RSP_OP(cmd, 3, 0, 8, char, obj_desc->type[0]);\ - MC_RSP_OP(cmd, 3, 8, 8, char, obj_desc->type[1]);\ - MC_RSP_OP(cmd, 3, 16, 8, char, obj_desc->type[2]);\ - MC_RSP_OP(cmd, 3, 24, 8, char, obj_desc->type[3]);\ - MC_RSP_OP(cmd, 3, 32, 8, char, obj_desc->type[4]);\ - MC_RSP_OP(cmd, 3, 40, 8, char, obj_desc->type[5]);\ - MC_RSP_OP(cmd, 3, 48, 8, char, obj_desc->type[6]);\ - MC_RSP_OP(cmd, 3, 56, 8, char, obj_desc->type[7]);\ - MC_RSP_OP(cmd, 4, 0, 8, char, obj_desc->type[8]);\ - MC_RSP_OP(cmd, 4, 8, 8, char, obj_desc->type[9]);\ - MC_RSP_OP(cmd, 4, 16, 8, char, obj_desc->type[10]);\ - MC_RSP_OP(cmd, 4, 24, 8, char, obj_desc->type[11]);\ - MC_RSP_OP(cmd, 4, 32, 8, char, obj_desc->type[12]);\ - MC_RSP_OP(cmd, 4, 40, 8, char, obj_desc->type[13]);\ - MC_RSP_OP(cmd, 4, 48, 8, char, obj_desc->type[14]);\ - MC_RSP_OP(cmd, 4, 56, 8, char, obj_desc->type[15]);\ - MC_RSP_OP(cmd, 5, 0, 8, char, obj_desc->label[0]);\ - MC_RSP_OP(cmd, 5, 8, 8, char, obj_desc->label[1]);\ - MC_RSP_OP(cmd, 5, 16, 8, char, obj_desc->label[2]);\ - MC_RSP_OP(cmd, 5, 24, 8, char, obj_desc->label[3]);\ - MC_RSP_OP(cmd, 5, 32, 8, char, obj_desc->label[4]);\ - MC_RSP_OP(cmd, 5, 40, 8, char, obj_desc->label[5]);\ - MC_RSP_OP(cmd, 5, 48, 8, char, obj_desc->label[6]);\ - MC_RSP_OP(cmd, 5, 56, 8, char, obj_desc->label[7]);\ - MC_RSP_OP(cmd, 6, 0, 8, char, obj_desc->label[8]);\ - MC_RSP_OP(cmd, 6, 8, 8, char, obj_desc->label[9]);\ - MC_RSP_OP(cmd, 6, 16, 8, char, obj_desc->label[10]);\ - MC_RSP_OP(cmd, 6, 24, 8, char, obj_desc->label[11]);\ - MC_RSP_OP(cmd, 6, 32, 8, char, obj_desc->label[12]);\ - MC_RSP_OP(cmd, 6, 40, 8, char, obj_desc->label[13]);\ - MC_RSP_OP(cmd, 6, 48, 8, char, obj_desc->label[14]);\ - MC_RSP_OP(cmd, 6, 56, 8, char, obj_desc->label[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_RES_COUNT(cmd, type) \ -do { \ - MC_CMD_OP(cmd, 1, 0, 8, char, type[0]);\ - MC_CMD_OP(cmd, 1, 8, 8, char, type[1]);\ - MC_CMD_OP(cmd, 1, 16, 8, char, type[2]);\ - MC_CMD_OP(cmd, 1, 24, 8, char, type[3]);\ - MC_CMD_OP(cmd, 1, 32, 8, char, type[4]);\ - MC_CMD_OP(cmd, 1, 40, 8, char, type[5]);\ - MC_CMD_OP(cmd, 1, 48, 8, char, type[6]);\ - MC_CMD_OP(cmd, 1, 56, 8, char, type[7]);\ - MC_CMD_OP(cmd, 2, 0, 8, char, type[8]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, type[9]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, type[10]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, type[11]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, type[12]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, type[13]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, type[14]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, type[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_RES_COUNT(cmd, res_count) \ - MC_RSP_OP(cmd, 0, 0, 32, int, res_count) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_RES_IDS(cmd, range_desc, type) \ -do { \ - MC_CMD_OP(cmd, 0, 42, 7, enum dprc_iter_status, \ - range_desc->iter_status); \ - MC_CMD_OP(cmd, 1, 0, 32, int, range_desc->base_id); \ - MC_CMD_OP(cmd, 1, 32, 32, int, range_desc->last_id);\ - MC_CMD_OP(cmd, 2, 0, 8, char, type[0]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, type[1]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, type[2]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, type[3]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, type[4]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, type[5]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, type[6]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, type[7]);\ - MC_CMD_OP(cmd, 3, 0, 8, char, type[8]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, type[9]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, type[10]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, type[11]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, type[12]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, type[13]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, type[14]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, type[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_RES_IDS(cmd, range_desc) \ -do { \ - MC_RSP_OP(cmd, 0, 42, 7, enum dprc_iter_status, \ - range_desc->iter_status);\ - MC_RSP_OP(cmd, 1, 0, 32, int, range_desc->base_id); \ - MC_RSP_OP(cmd, 1, 32, 32, int, range_desc->last_id);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_OBJ_REGION(cmd, obj_type, obj_id, region_index) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \ - MC_CMD_OP(cmd, 0, 48, 8, uint8_t, region_index);\ - MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\ - MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\ - MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\ - MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\ - MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\ - MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\ - MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\ - MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\ - MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\ -} while (0) - -/* param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_OBJ_REGION(cmd, region_desc) \ -do { \ - MC_RSP_OP(cmd, 1, 0, 32, uint32_t, region_desc->base_offset);\ - MC_RSP_OP(cmd, 2, 0, 32, uint32_t, region_desc->size); \ - MC_RSP_OP(cmd, 2, 32, 4, enum dprc_region_type, region_desc->type);\ - MC_RSP_OP(cmd, 3, 0, 32, uint32_t, region_desc->flags);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_SET_OBJ_LABEL(cmd, obj_type, obj_id, label) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, obj_id); \ - MC_CMD_OP(cmd, 1, 0, 8, char, label[0]);\ - MC_CMD_OP(cmd, 1, 8, 8, char, label[1]);\ - MC_CMD_OP(cmd, 1, 16, 8, char, label[2]);\ - MC_CMD_OP(cmd, 1, 24, 8, char, label[3]);\ - MC_CMD_OP(cmd, 1, 32, 8, char, label[4]);\ - MC_CMD_OP(cmd, 1, 40, 8, char, label[5]);\ - MC_CMD_OP(cmd, 1, 48, 8, char, label[6]);\ - MC_CMD_OP(cmd, 1, 56, 8, char, label[7]);\ - MC_CMD_OP(cmd, 2, 0, 8, char, label[8]);\ - MC_CMD_OP(cmd, 2, 8, 8, char, label[9]);\ - MC_CMD_OP(cmd, 2, 16, 8, char, label[10]);\ - MC_CMD_OP(cmd, 2, 24, 8, char, label[11]);\ - MC_CMD_OP(cmd, 2, 32, 8, char, label[12]);\ - MC_CMD_OP(cmd, 2, 40, 8, char, label[13]);\ - MC_CMD_OP(cmd, 2, 48, 8, char, label[14]);\ - MC_CMD_OP(cmd, 2, 56, 8, char, label[15]);\ - MC_CMD_OP(cmd, 3, 0, 8, char, obj_type[0]);\ - MC_CMD_OP(cmd, 3, 8, 8, char, obj_type[1]);\ - MC_CMD_OP(cmd, 3, 16, 8, char, obj_type[2]);\ - MC_CMD_OP(cmd, 3, 24, 8, char, obj_type[3]);\ - MC_CMD_OP(cmd, 3, 32, 8, char, obj_type[4]);\ - MC_CMD_OP(cmd, 3, 40, 8, char, obj_type[5]);\ - MC_CMD_OP(cmd, 3, 48, 8, char, obj_type[6]);\ - MC_CMD_OP(cmd, 3, 56, 8, char, obj_type[7]);\ - MC_CMD_OP(cmd, 4, 0, 8, char, obj_type[8]);\ - MC_CMD_OP(cmd, 4, 8, 8, char, obj_type[9]);\ - MC_CMD_OP(cmd, 4, 16, 8, char, obj_type[10]);\ - MC_CMD_OP(cmd, 4, 24, 8, char, obj_type[11]);\ - MC_CMD_OP(cmd, 4, 32, 8, char, obj_type[12]);\ - MC_CMD_OP(cmd, 4, 40, 8, char, obj_type[13]);\ - MC_CMD_OP(cmd, 4, 48, 8, char, obj_type[14]);\ - MC_CMD_OP(cmd, 4, 56, 8, char, obj_type[15]);\ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_CONNECT(cmd, endpoint1, endpoint2, cfg) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ - MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ - MC_CMD_OP(cmd, 1, 0, 32, int, endpoint2->id); \ - MC_CMD_OP(cmd, 1, 32, 32, int, endpoint2->if_id); \ - MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[0]); \ - MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[1]); \ - MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[2]); \ - MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[3]); \ - MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[4]); \ - MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[5]); \ - MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[6]); \ - MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[7]); \ - MC_CMD_OP(cmd, 3, 0, 8, char, endpoint1->type[8]); \ - MC_CMD_OP(cmd, 3, 8, 8, char, endpoint1->type[9]); \ - MC_CMD_OP(cmd, 3, 16, 8, char, endpoint1->type[10]); \ - MC_CMD_OP(cmd, 3, 24, 8, char, endpoint1->type[11]); \ - MC_CMD_OP(cmd, 3, 32, 8, char, endpoint1->type[12]); \ - MC_CMD_OP(cmd, 3, 40, 8, char, endpoint1->type[13]); \ - MC_CMD_OP(cmd, 3, 48, 8, char, endpoint1->type[14]); \ - MC_CMD_OP(cmd, 3, 56, 8, char, endpoint1->type[15]); \ - MC_CMD_OP(cmd, 4, 0, 32, uint32_t, cfg->max_rate); \ - MC_CMD_OP(cmd, 4, 32, 32, uint32_t, cfg->committed_rate); \ - MC_CMD_OP(cmd, 5, 0, 8, char, endpoint2->type[0]); \ - MC_CMD_OP(cmd, 5, 8, 8, char, endpoint2->type[1]); \ - MC_CMD_OP(cmd, 5, 16, 8, char, endpoint2->type[2]); \ - MC_CMD_OP(cmd, 5, 24, 8, char, endpoint2->type[3]); \ - MC_CMD_OP(cmd, 5, 32, 8, char, endpoint2->type[4]); \ - MC_CMD_OP(cmd, 5, 40, 8, char, endpoint2->type[5]); \ - MC_CMD_OP(cmd, 5, 48, 8, char, endpoint2->type[6]); \ - MC_CMD_OP(cmd, 5, 56, 8, char, endpoint2->type[7]); \ - MC_CMD_OP(cmd, 6, 0, 8, char, endpoint2->type[8]); \ - MC_CMD_OP(cmd, 6, 8, 8, char, endpoint2->type[9]); \ - MC_CMD_OP(cmd, 6, 16, 8, char, endpoint2->type[10]); \ - MC_CMD_OP(cmd, 6, 24, 8, char, endpoint2->type[11]); \ - MC_CMD_OP(cmd, 6, 32, 8, char, endpoint2->type[12]); \ - MC_CMD_OP(cmd, 6, 40, 8, char, endpoint2->type[13]); \ - MC_CMD_OP(cmd, 6, 48, 8, char, endpoint2->type[14]); \ - MC_CMD_OP(cmd, 6, 56, 8, char, endpoint2->type[15]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_DISCONNECT(cmd, endpoint) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, endpoint->id); \ - MC_CMD_OP(cmd, 0, 32, 16, uint16_t, endpoint->if_id); \ - MC_CMD_OP(cmd, 1, 0, 8, char, endpoint->type[0]); \ - MC_CMD_OP(cmd, 1, 8, 8, char, endpoint->type[1]); \ - MC_CMD_OP(cmd, 1, 16, 8, char, endpoint->type[2]); \ - MC_CMD_OP(cmd, 1, 24, 8, char, endpoint->type[3]); \ - MC_CMD_OP(cmd, 1, 32, 8, char, endpoint->type[4]); \ - MC_CMD_OP(cmd, 1, 40, 8, char, endpoint->type[5]); \ - MC_CMD_OP(cmd, 1, 48, 8, char, endpoint->type[6]); \ - MC_CMD_OP(cmd, 1, 56, 8, char, endpoint->type[7]); \ - MC_CMD_OP(cmd, 2, 0, 8, char, endpoint->type[8]); \ - MC_CMD_OP(cmd, 2, 8, 8, char, endpoint->type[9]); \ - MC_CMD_OP(cmd, 2, 16, 8, char, endpoint->type[10]); \ - MC_CMD_OP(cmd, 2, 24, 8, char, endpoint->type[11]); \ - MC_CMD_OP(cmd, 2, 32, 8, char, endpoint->type[12]); \ - MC_CMD_OP(cmd, 2, 40, 8, char, endpoint->type[13]); \ - MC_CMD_OP(cmd, 2, 48, 8, char, endpoint->type[14]); \ - MC_CMD_OP(cmd, 2, 56, 8, char, endpoint->type[15]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_CMD_GET_CONNECTION(cmd, endpoint1) \ -do { \ - MC_CMD_OP(cmd, 0, 0, 32, int, endpoint1->id); \ - MC_CMD_OP(cmd, 0, 32, 32, int, endpoint1->if_id); \ - MC_CMD_OP(cmd, 1, 0, 8, char, endpoint1->type[0]); \ - MC_CMD_OP(cmd, 1, 8, 8, char, endpoint1->type[1]); \ - MC_CMD_OP(cmd, 1, 16, 8, char, endpoint1->type[2]); \ - MC_CMD_OP(cmd, 1, 24, 8, char, endpoint1->type[3]); \ - MC_CMD_OP(cmd, 1, 32, 8, char, endpoint1->type[4]); \ - MC_CMD_OP(cmd, 1, 40, 8, char, endpoint1->type[5]); \ - MC_CMD_OP(cmd, 1, 48, 8, char, endpoint1->type[6]); \ - MC_CMD_OP(cmd, 1, 56, 8, char, endpoint1->type[7]); \ - MC_CMD_OP(cmd, 2, 0, 8, char, endpoint1->type[8]); \ - MC_CMD_OP(cmd, 2, 8, 8, char, endpoint1->type[9]); \ - MC_CMD_OP(cmd, 2, 16, 8, char, endpoint1->type[10]); \ - MC_CMD_OP(cmd, 2, 24, 8, char, endpoint1->type[11]); \ - MC_CMD_OP(cmd, 2, 32, 8, char, endpoint1->type[12]); \ - MC_CMD_OP(cmd, 2, 40, 8, char, endpoint1->type[13]); \ - MC_CMD_OP(cmd, 2, 48, 8, char, endpoint1->type[14]); \ - MC_CMD_OP(cmd, 2, 56, 8, char, endpoint1->type[15]); \ -} while (0) - -/* cmd, param, offset, width, type, arg_name */ -#define DPRC_RSP_GET_CONNECTION(cmd, endpoint2, state) \ -do { \ - MC_RSP_OP(cmd, 3, 0, 32, int, endpoint2->id); \ - MC_RSP_OP(cmd, 3, 32, 16, uint16_t, endpoint2->if_id); \ - MC_RSP_OP(cmd, 4, 0, 8, char, endpoint2->type[0]); \ - MC_RSP_OP(cmd, 4, 8, 8, char, endpoint2->type[1]); \ - MC_RSP_OP(cmd, 4, 16, 8, char, endpoint2->type[2]); \ - MC_RSP_OP(cmd, 4, 24, 8, char, endpoint2->type[3]); \ - MC_RSP_OP(cmd, 4, 32, 8, char, endpoint2->type[4]); \ - MC_RSP_OP(cmd, 4, 40, 8, char, endpoint2->type[5]); \ - MC_RSP_OP(cmd, 4, 48, 8, char, endpoint2->type[6]); \ - MC_RSP_OP(cmd, 4, 56, 8, char, endpoint2->type[7]); \ - MC_RSP_OP(cmd, 5, 0, 8, char, endpoint2->type[8]); \ - MC_RSP_OP(cmd, 5, 8, 8, char, endpoint2->type[9]); \ - MC_RSP_OP(cmd, 5, 16, 8, char, endpoint2->type[10]); \ - MC_RSP_OP(cmd, 5, 24, 8, char, endpoint2->type[11]); \ - MC_RSP_OP(cmd, 5, 32, 8, char, endpoint2->type[12]); \ - MC_RSP_OP(cmd, 5, 40, 8, char, endpoint2->type[13]); \ - MC_RSP_OP(cmd, 5, 48, 8, char, endpoint2->type[14]); \ - MC_RSP_OP(cmd, 5, 56, 8, char, endpoint2->type[15]); \ - MC_RSP_OP(cmd, 6, 0, 32, int, state); \ -} while (0) +#pragma pack(push, 1) +struct dprc_cmd_open { + __le32 container_id; +}; + +struct dprc_cmd_create_container { + __le32 options; + __le32 icid; + __le32 pad1; + __le32 portal_id; + u8 label[16]; +}; + +struct dprc_rsp_create_container { + __le64 pad0; + __le32 child_container_id; + __le32 pad1; + __le64 child_portal_addr; +}; + +struct dprc_cmd_destroy_container { + __le32 child_container_id; +}; + +struct dprc_cmd_connect { + __le32 ep1_id; + __le16 ep1_interface_id; + __le16 pad0; + + __le32 ep2_id; + __le16 ep2_interface_id; + __le16 pad1; + + u8 ep1_type[16]; + + __le32 max_rate; + __le32 committed_rate; + + u8 ep2_type[16]; +}; + +struct dprc_cmd_disconnect { + __le32 id; + __le32 interface_id; + u8 type[16]; +}; + +struct dprc_cmd_get_connection { + __le32 ep1_id; + __le16 ep1_interface_id; + __le16 pad; + + u8 ep1_type[16]; +}; + +struct dprc_rsp_get_connection { + __le64 pad[3]; + __le32 ep2_id; + __le16 ep2_interface_id; + __le16 pad1; + u8 ep2_type[16]; + __le32 state; +}; + +#pragma pack(pop) /* Data Path Resource Container API * Contains DPRC API for managing and querying DPAA resources @@ -463,7 +103,7 @@ struct fsl_mc_io; * container, in case the ICID is not selected by the user and should be * allocated by the DPRC from the pool of ICIDs. */ -#define DPRC_GET_ICID_FROM_POOL (uint16_t)(~(0)) +#define DPRC_GET_ICID_FROM_POOL (u16)(~(0)) /** * Set this value as the portal_id value in dprc_cfg structure when creating a @@ -472,48 +112,11 @@ struct fsl_mc_io; */ #define DPRC_GET_PORTAL_ID_FROM_POOL (int)(~(0)) -/** - * dprc_get_container_id() - Get container ID associated with a given portal. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @container_id: Requested container ID - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_container_id(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int *container_id); +int dprc_get_container_id(struct fsl_mc_io *mc_io, u32 cmd_flags, int *container_id); -/** - * dprc_open() - Open DPRC object for use - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @container_id: Container ID to open - * @token: Returned token of DPRC object - * - * Return: '0' on Success; Error code otherwise. - * - * @warning Required before any operation on the object. - */ -int dprc_open(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - int container_id, - uint16_t *token); +int dprc_open(struct fsl_mc_io *mc_io, u32 cmd_flags, int container_id, u16 *token); -/** - * dprc_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_close(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token); +int dprc_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); /** * Container general options @@ -563,395 +166,57 @@ int dprc_close(struct fsl_mc_io *mc_io, * @label: Object's label */ struct dprc_cfg { - uint16_t icid; - int portal_id; - uint64_t options; - char label[16]; -}; - -/** - * dprc_create_container() - Create child container - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @cfg: Child container configuration - * @child_container_id: Returned child container ID - * @child_portal_offset: Returned child portal offset from MC portal base - * - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_create_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dprc_cfg *cfg, - int *child_container_id, - uint64_t *child_portal_offset); - -/** - * dprc_destroy_container() - Destroy child container. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @child_container_id: ID of the container to destroy - * - * This function terminates the child container, so following this call the - * child container ID becomes invalid. - * - * Notes: - * - All resources and objects of the destroyed container are returned to the - * parent container or destroyed if were created be the destroyed container. - * - This function destroy all the child containers of the specified - * container prior to destroying the container itself. - * - * warning: Only the parent container is allowed to destroy a child policy - * Container 0 can't be destroyed - * - * Return: '0' on Success; Error code otherwise. - * - */ -int dprc_destroy_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int child_container_id); - -/** - * dprc_reset_container - Reset child container. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @child_container_id: ID of the container to reset - * - * In case a software context crashes or becomes non-responsive, the parent - * may wish to reset its resources container before the software context is - * restarted. - * - * This routine informs all objects assigned to the child container that the - * container is being reset, so they may perform any cleanup operations that are - * needed. All objects handles that were owned by the child container shall be - * closed. - * - * Note that such request may be submitted even if the child software context - * has not crashed, but the resulting object cleanup operations will not be - * aware of that. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_reset_container(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int child_container_id); - -/** - * struct dprc_attributes - Container attributes - * @container_id: Container's ID - * @icid: Container's ICID - * @portal_id: Container's portal ID - * @options: Container's options as set at container's creation - * @version: DPRC version - */ -struct dprc_attributes { - int container_id; - uint16_t icid; + u16 icid; int portal_id; uint64_t options; -}; - -/** - * dprc_get_attributes() - Obtains container attributes - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @attributes: Returned container attributes - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_attributes(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - struct dprc_attributes *attributes); - -/** - * dprc_get_obj_count() - Obtains the number of objects in the DPRC - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_count: Number of objects assigned to the DPRC - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj_count(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int *obj_count); - -/* Objects Attributes Flags */ - -/* Opened state - Indicates that an object is open by at least one owner */ -#define DPRC_OBJ_STATE_OPEN 0x00000001 -/* Plugged state - Indicates that the object is plugged */ -#define DPRC_OBJ_STATE_PLUGGED 0x00000002 - -/** - * Shareability flag - Object flag indicating no memory shareability. - * the object generates memory accesses that are non coherent with other - * masters; - * user is responsible for proper memory handling through IOMMU configuration. - */ -#define DPRC_OBJ_FLAG_NO_MEM_SHAREABILITY 0x0001 - -/** - * struct dprc_obj_desc - Object descriptor, returned from dprc_get_obj() - * @type: Type of object: NULL terminated string - * @id: ID of logical object resource - * @vendor: Object vendor identifier - * @ver_major: Major version number - * @ver_minor: Minor version number - * @irq_count: Number of interrupts supported by the object - * @region_count: Number of mappable regions supported by the object - * @state: Object state: combination of DPRC_OBJ_STATE_ states - * @label: Object label - * @flags: Object's flags - */ -struct dprc_obj_desc { - char type[16]; - int id; - uint16_t vendor; - uint16_t ver_major; - uint16_t ver_minor; - uint8_t irq_count; - uint8_t region_count; - uint32_t state; char label[16]; - uint16_t flags; }; -/** - * dprc_get_obj() - Get general information on an object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_index: Index of the object to be queried (< obj_count) - * @obj_desc: Returns the requested object descriptor - * - * The object descriptors are retrieved one by one by incrementing - * obj_index up to (not including) the value of obj_count returned - * from dprc_get_obj_count(). dprc_get_obj_count() must - * be called prior to dprc_get_obj(). - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - int obj_index, - struct dprc_obj_desc *obj_desc); - -/** - * dprc_get_res_count() - Obtains the number of free resources that are - * assigned to this container, by pool type - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @type: pool type - * @res_count: Returned number of free resources of the given - * resource type that are assigned to this DPRC - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_res_count(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *type, - int *res_count); - -/** - * enum dprc_iter_status - Iteration status - * @DPRC_ITER_STATUS_FIRST: Perform first iteration - * @DPRC_ITER_STATUS_MORE: Indicates more/next iteration is needed - * @DPRC_ITER_STATUS_LAST: Indicates last iteration - */ -enum dprc_iter_status { - DPRC_ITER_STATUS_FIRST = 0, - DPRC_ITER_STATUS_MORE = 1, - DPRC_ITER_STATUS_LAST = 2 -}; - -/** - * struct dprc_res_ids_range_desc - Resource ID range descriptor - * @base_id: Base resource ID of this range - * @last_id: Last resource ID of this range - * @iter_status: Iteration status - should be set to DPRC_ITER_STATUS_FIRST at - * first iteration; while the returned marker is DPRC_ITER_STATUS_MORE, - * additional iterations are needed, until the returned marker is - * DPRC_ITER_STATUS_LAST - */ -struct dprc_res_ids_range_desc { - int base_id; - int last_id; - enum dprc_iter_status iter_status; -}; - -/** - * dprc_get_res_ids() - Obtains IDs of free resources in the container - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @type: pool type - * @range_desc: range descriptor - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_res_ids(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *type, - struct dprc_res_ids_range_desc *range_desc); - -/* Region flags */ -/* Cacheable - Indicates that region should be mapped as cacheable */ -#define DPRC_REGION_CACHEABLE 0x00000001 +int dprc_create_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + struct dprc_cfg *cfg, int *child_container_id, + uint64_t *child_portal_offset); -/** - * enum dprc_region_type - Region type - * @DPRC_REGION_TYPE_MC_PORTAL: MC portal region - * @DPRC_REGION_TYPE_QBMAN_PORTAL: Qbman portal region - */ -enum dprc_region_type { - DPRC_REGION_TYPE_MC_PORTAL, - DPRC_REGION_TYPE_QBMAN_PORTAL -}; +int dprc_destroy_container(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + int child_container_id); /** - * struct dprc_region_desc - Mappable region descriptor - * @base_offset: Region offset from region's base address. - * For DPMCP and DPRC objects, region base is offset from SoC MC portals - * base address; For DPIO, region base is offset from SoC QMan portals - * base address - * @size: Region size (in bytes) - * @flags: Region attributes - * @type: Portal region type + * struct dprc_connection_cfg - Connection configuration. + * Used for virtual connections only + * @committed_rate: Committed rate (Mbits/s) + * @max_rate: Maximum rate (Mbits/s) */ -struct dprc_region_desc { - uint32_t base_offset; - uint32_t size; - uint32_t flags; - enum dprc_region_type type; +struct dprc_connection_cfg { + u32 committed_rate; + u32 max_rate; }; /** - * dprc_get_obj_region() - Get region information for a specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @obj_type: Object type as returned in dprc_get_obj() - * @obj_id: Unique object instance as returned in dprc_get_obj() - * @region_index: The specific region to query - * @region_desc: Returns the requested region descriptor - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_obj_region(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - char *obj_type, - int obj_id, - uint8_t region_index, - struct dprc_region_desc *region_desc); -/** * struct dprc_endpoint - Endpoint description for link connect/disconnect * operations - * @type: Endpoint object type: NULL terminated string - * @id: Endpoint object ID - * @if_id: Interface ID; should be set for endpoints with multiple + * @type: Endpoint object type: NULL terminated string + * @id: Endpoint object ID + * @if_id: Interface ID; should be set for endpoints with multiple * interfaces ("dpsw", "dpdmux"); for others, always set to 0 */ struct dprc_endpoint { - char type[16]; - int id; - uint16_t if_id; -}; - -/** - * struct dprc_connection_cfg - Connection configuration. - * Used for virtual connections only - * @committed_rate: Committed rate (Mbits/s) - * @max_rate: Maximum rate (Mbits/s) - */ -struct dprc_connection_cfg { - uint32_t committed_rate; - uint32_t max_rate; + char type[16]; + int id; + u16 if_id; }; -/** - * dprc_connect() - Connect two endpoints to create a network link between them - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @endpoint1: Endpoint 1 configuration parameters - * @endpoint2: Endpoint 2 configuration parameters - * @cfg: Connection configuration. The connection configuration is ignored for - * connections made to DPMAC objects, where rate is retrieved from the - * MAC configuration. - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_connect(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dprc_endpoint *endpoint1, - const struct dprc_endpoint *endpoint2, - const struct dprc_connection_cfg *cfg); +int dprc_connect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dprc_endpoint *endpoint1, + const struct dprc_endpoint *endpoint2, + const struct dprc_connection_cfg *cfg); -/** - * dprc_disconnect() - Disconnect one endpoint to remove its network connection - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPRC object - * @endpoint: Endpoint configuration parameters - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_disconnect(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dprc_endpoint *endpoint); +int dprc_disconnect(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dprc_endpoint *endpoint); -/** -* dprc_get_connection() - Get connected endpoint and link status if connection -* exists. -* @mc_io: Pointer to MC portal's I/O object -* @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' -* @token: Token of DPRC object -* @endpoint1: Endpoint 1 configuration parameters -* @endpoint2: Returned endpoint 2 configuration parameters -* @state: Returned link state: -* 1 - link is up; -* 0 - link is down; -* -1 - no connection (endpoint2 information is irrelevant) -* -* Return: '0' on Success; -ENAVAIL if connection does not exist. -*/ -int dprc_get_connection(struct fsl_mc_io *mc_io, - uint32_t cmd_flags, - uint16_t token, - const struct dprc_endpoint *endpoint1, - struct dprc_endpoint *endpoint2, - int *state); +int dprc_get_connection(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + const struct dprc_endpoint *endpoint1, + struct dprc_endpoint *endpoint2, int *state); -/** - * dprc_get_api_version - Retrieve DPRC Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPRC major version - * @minor_ver: DPRC minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dprc_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dprc_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* _FSL_DPRC_H */ diff --git a/include/fsl-mc/fsl_dpsparser.h b/include/fsl-mc/fsl_dpsparser.h index 48fb495..9619bb1 100644 --- a/include/fsl-mc/fsl_dpsparser.h +++ b/include/fsl-mc/fsl_dpsparser.h @@ -2,7 +2,7 @@ /* * Data Path Soft Parser API * - * Copyright 2018 NXP + * Copyright 2018, 2023 NXP */ #ifndef _FSL_DPSPARSER_H #define _FSL_DPSPARSER_H @@ -20,13 +20,26 @@ #define DPSPARSER_CMDID_APPLY_SPB 0x1181 -/* cmd, param, offset, width, type, arg_name */ -#define DPSPARSER_CMD_BLOB_SET_ADDR(cmd, addr) \ - MC_CMD_OP(cmd, 0, 0, 64, u64, addr) +#pragma pack(push, 1) -/* cmd, param, offset, width, type, arg_name */ -#define DPSPARSER_CMD_BLOB_REPORT_ERROR(cmd, err) \ - MC_RSP_OP(cmd, 0, 0, 16, u16, err) +struct dpsparser_cmd_destroy { + __le32 dpsparser_id; +}; + +struct dpsparser_cmd_blob_set_address { + __le64 blob_addr; +}; + +struct dpsparser_rsp_blob_report_error { + __le16 error; +}; + +struct dpsparser_rsp_get_api_version { + __le16 major; + __le16 minor; +}; + +#pragma pack(pop) /* Data Path Soft Parser API * Contains initialization APIs and runtime control APIs for DPSPARSER @@ -99,110 +112,20 @@ struct fsl_mc_io; NULL, \ } -/** - * dpsparser_open() - Open a control session for the specified object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Returned token; use in subsequent API calls - * - * This function can be used to open a control session for an - * already created object; an object may have been declared in - * the DPL or by calling the dpsparser_create function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent commands for - * this specific object - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_open(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *token); - -/** - * dpsparser_close() - Close the control session of the object - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPSPARSER object - * - * After this function is called, no further operations are - * allowed on the object without opening a new control session. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_close(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token); - -/** - * dpsparser_create() - Create the DPSPARSER object. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Returned token; use in subsequent API calls - * - * Create the DPSPARSER object, allocate required resources and - * perform required initialization. - * - * The object can be created either by declaring it in the - * DPL file, or by calling this function. - * This function returns a unique authentication token, - * associated with the specific object ID and the specific MC - * portal; this token must be used in all subsequent calls to - * this specific object. For objects that are created using the - * DPL file, call dpsparser_open function to get an authentication - * token first. - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_create(struct fsl_mc_io *mc_io, - u16 token, - u32 cmd_flags, +int dpsparser_open(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 *token); + +int dpsparser_close(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token); + +int dpsparser_create(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags, u32 *obj_id); -/** - * dpsparser_destroy() - Destroy the DPSPARSER object and release all its - * resources. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPSPARSER object - * - * Return: '0' on Success; error code otherwise. - */ -int dpsparser_destroy(struct fsl_mc_io *mc_io, - u16 token, - u32 cmd_flags, +int dpsparser_destroy(struct fsl_mc_io *mc_io, u16 token, u32 cmd_flags, u32 obj_id); -/** - * dpsparser_apply_spb() - Applies the Soft Parser Blob loaded at specified - * address. - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @token: Token of DPSPARSER object - * @blob_addr: Blob loading address - * @error: Error reported by MC related to SP Blob parsing and apply - * - * Return: '0' on Success; error code otherwise. - */ -int dpsparser_apply_spb(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 token, - u64 blob_addr, - u16 *error); - -/** - * dpsparser_get_api_version - Retrieve DPSPARSER Major and Minor version info. - * - * @mc_io: Pointer to MC portal's I/O object - * @cmd_flags: Command flags; one or more of 'MC_CMD_FLAG_' - * @major_ver: DPSPARSER major version - * @minor_ver: DPSPARSER minor version - * - * Return: '0' on Success; Error code otherwise. - */ -int dpsparser_get_api_version(struct fsl_mc_io *mc_io, - u32 cmd_flags, - u16 *major_ver, - u16 *minor_ver); +int dpsparser_apply_spb(struct fsl_mc_io *mc_io, u32 cmd_flags, u16 token, + u64 blob_addr, u16 *error); + +int dpsparser_get_api_version(struct fsl_mc_io *mc_io, u32 cmd_flags, + u16 *major_ver, u16 *minor_ver); #endif /* _FSL_DPSPARSER_H */ diff --git a/include/fsl-mc/fsl_mc_cmd.h b/include/fsl-mc/fsl_mc_cmd.h index 591cda9..c239595 100644 --- a/include/fsl-mc/fsl_mc_cmd.h +++ b/include/fsl-mc/fsl_mc_cmd.h @@ -19,6 +19,15 @@ static inline uint64_t mc_dec(uint64_t val, int lsoffset, int width) return (uint64_t)((val >> lsoffset) & MAKE_UMASK64(width)); } +struct mc_cmd_header { + u8 src_id; + u8 flags_hw; + u8 status; + u8 flags_sw; + __le16 token; + __le16 cmd_id; +}; + struct mc_command { uint64_t header; uint64_t params[MC_CMD_NUM_OF_PARAMS]; @@ -74,29 +83,6 @@ enum mc_cmd_status { ((enum mc_cmd_status)mc_dec((_hdr), \ MC_CMD_HDR_STATUS_O, MC_CMD_HDR_STATUS_S)) -#define MC_CMD_HDR_READ_TOKEN(_hdr) \ - ((uint16_t)mc_dec((_hdr), MC_CMD_HDR_TOKEN_O, MC_CMD_HDR_TOKEN_S)) - -#define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ - ((_ext)[_param] |= cpu_to_le64(mc_enc((_offset), (_width), _arg))) - -#define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ - (_arg = (_type)mc_dec(cpu_to_le64(_ext[_param]), (_offset), (_width))) - -#define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ - ((_cmd).params[_param] |= mc_enc((_offset), (_width), _arg)) - -#define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ - (_arg = (_type)mc_dec(_cmd.params[_param], (_offset), (_width))) - -/* cmd, param, offset, width, type, arg_name */ -#define MC_CMD_READ_OBJ_ID(cmd, obj_id) \ - MC_RSP_OP(cmd, 0, 0, 32, uint32_t, obj_id) - -/* cmd, param, offset, width, type, arg_name */ -#define CMD_DESTROY_SET_OBJ_ID_PARAM0(cmd, object_id) \ - MC_CMD_OP(cmd, 0, 0, 32, uint32_t, object_id) - static inline uint64_t mc_encode_cmd_header(uint16_t cmd_id, uint32_t cmd_flags, uint16_t token) @@ -179,4 +165,19 @@ static inline void mc_cmd_read_api_version(struct mc_command *cmd, *minor_ver = le16_to_cpu(rsp_params->minor_ver); } +static inline uint16_t mc_cmd_hdr_read_token(struct mc_command *cmd) +{ + struct mc_cmd_header *hdr = (struct mc_cmd_header *)&cmd->header; + u16 token = le16_to_cpu(hdr->token); + + return token; +} + +static inline uint32_t mc_cmd_read_object_id(struct mc_command *cmd) +{ + struct mc_rsp_create *rsp_params; + + rsp_params = (struct mc_rsp_create *)cmd->params; + return le32_to_cpu(rsp_params->object_id); +} #endif /* __FSL_MC_CMD_H */ diff --git a/include/fsl_validate.h b/include/fsl_validate.h index fbcbd424..66a5883 100644 --- a/include/fsl_validate.h +++ b/include/fsl_validate.h @@ -275,9 +275,9 @@ int fsl_check_boot_mode_secure(void); int fsl_setenv_chain_of_trust(void); /* - * This function is used to validate the main U-boot binary from + * This function is used to validate the main U-Boot binary from * SPL just before passing control to it using QorIQ Trust - * Architecture header (appended to U-boot image). + * Architecture header (appended to U-Boot image). */ void spl_validate_uboot(uint32_t hdr_addr, uintptr_t img_addr); diff --git a/include/fwu.h b/include/fwu.h index 0919ced..ac5c5de 100644 --- a/include/fwu.h +++ b/include/fwu.h @@ -8,6 +8,8 @@ #include <blk.h> #include <efi.h> +#include <mtd.h> +#include <uuid.h> #include <linux/types.h> @@ -18,83 +20,32 @@ struct fwu_mdata_gpt_blk_priv { struct udevice *blk_dev; }; -/** - * @mdata_check: check the validity of the FWU metadata partitions - * @get_mdata() - Get a FWU metadata copy - * @update_mdata() - Update the FWU metadata copy - */ -struct fwu_mdata_ops { - /** - * check_mdata() - Check if the FWU metadata is valid - * @dev: FWU device - * - * Validate both copies of the FWU metadata. If one of the copies - * has gone bad, restore it from the other copy. - * - * Return: 0 if OK, -ve on error - */ - int (*check_mdata)(struct udevice *dev); - - /** - * get_mdata() - Get a FWU metadata copy - * @dev: FWU device - * @mdata: Pointer to FWU metadata - * - * Get a valid copy of the FWU metadata. - * - * Return: 0 if OK, -ve on error - */ - int (*get_mdata)(struct udevice *dev, struct fwu_mdata *mdata); - - /** - * update_mdata() - Update the FWU metadata - * @dev: FWU device - * @mdata: Copy of the FWU metadata - * - * Update the FWU metadata structure by writing to the - * FWU metadata partitions. - * - * Return: 0 if OK, -ve on error - */ - int (*update_mdata)(struct udevice *dev, struct fwu_mdata *mdata); - - /** - * get_mdata_part_num() - Get the FWU metadata partition numbers - * @dev: FWU metadata device - * @mdata_parts: array for storing the metadata partition numbers - * - * Get the partition numbers on the storage device on which the - * FWU metadata is stored. Two partition numbers will be returned. - * - * Return: 0 if OK, -ve on error - */ - int (*get_mdata_part_num)(struct udevice *dev, uint *mdata_parts); +struct fwu_mtd_image_info { + u32 start, size; + int bank_num, image_num; + char uuidbuf[UUID_STR_LEN + 1]; +}; +struct fwu_mdata_ops { /** - * read_mdata_partition() - Read the FWU metadata from a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number from which FWU metadata is to be read - * - * Read the FWU metadata from the specified partition number + * read_mdata() - Populate the asked FWU metadata copy + * @dev: FWU metadata device + * @mdata: Output FWU mdata read + * @primary: If primary or secondary copy of metadata is to be read * * Return: 0 if OK, -ve on error */ - int (*read_mdata_partition)(struct udevice *dev, - struct fwu_mdata *mdata, uint part_num); + int (*read_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary); /** - * write_mdata_partition() - Write the FWU metadata to a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number to which FWU metadata is to be written - * - * Write the FWU metadata to the specified partition number + * write_mdata() - Write the given FWU metadata copy + * @dev: FWU metadata device + * @mdata: Copy of the FWU metadata to write + * @primary: If primary or secondary copy of metadata is to be written * * Return: 0 if OK, -ve on error */ - int (*write_mdata_partition)(struct udevice *dev, - struct fwu_mdata *mdata, uint part_num); + int (*write_mdata)(struct udevice *dev, struct fwu_mdata *mdata, bool primary); }; #define FWU_MDATA_VERSION 0x1 @@ -127,100 +78,25 @@ struct fwu_mdata_ops { 0xe1, 0xfc, 0xed, 0xf1, 0xc6, 0xf8) /** - * fwu_check_mdata_validity() - Check for validity of the FWU metadata copies - * - * Read both the metadata copies from the storage media, verify their - * checksum, and ascertain that both copies match. If one of the copies - * has gone bad, restore it from the good copy. - * - * Return: 0 if OK, -ve on error - * + * fwu_read_mdata() - Wrapper around fwu_mdata_ops.read_mdata() */ -int fwu_check_mdata_validity(void); +int fwu_read_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); /** - * fwu_get_mdata_part_num() - Get the FWU metadata partition numbers - * @dev: FWU metadata device - * @mdata_parts: array for storing the metadata partition numbers - * - * Get the partition numbers on the storage device on which the - * FWU metadata is stored. Two partition numbers will be returned - * through the array. - * - * Return: 0 if OK, -ve on error - * + * fwu_write_mdata() - Wrapper around fwu_mdata_ops.write_mdata() */ -int fwu_get_mdata_part_num(struct udevice *dev, uint *mdata_parts); +int fwu_write_mdata(struct udevice *dev, struct fwu_mdata *mdata, bool primary); /** - * fwu_read_mdata_partition() - Read the FWU metadata from a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number from which FWU metadata is to be read + * fwu_get_mdata() - Read, verify and return the FWU metadata * - * Read the FWU metadata from the specified partition number + * Read both the metadata copies from the storage media, verify their checksum, + * and ascertain that both copies match. If one of the copies has gone bad, + * restore it from the good copy. * * Return: 0 if OK, -ve on error - * - */ -int fwu_read_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata, - uint part_num); - -/** - * fwu_write_mdata_partition() - Write the FWU metadata to a partition - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * @part_num: Partition number to which FWU metadata is to be written - * - * Write the FWU metadata to the specified partition number - * - * Return: 0 if OK, -ve on error - * */ -int fwu_write_mdata_partition(struct udevice *dev, struct fwu_mdata *mdata, - uint part_num); - -/** - * fwu_get_mdata() - Get a FWU metadata copy - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * - * Get a valid copy of the FWU metadata. - * - * Note: This function is to be called first when modifying any fields - * in the metadata. The sequence of calls to modify any field in the - * metadata would be 1) fwu_get_mdata 2) Modify metadata, followed by - * 3) fwu_update_mdata - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_get_mdata(struct udevice *dev, struct fwu_mdata *mdata); - -/** - * fwu_update_mdata() - Update the FWU metadata - * @dev: FWU metadata device - * @mdata: Copy of the FWU metadata - * - * Update the FWU metadata structure by writing to the - * FWU metadata partitions. - * - * Note: This function is not to be called directly to update the - * metadata fields. The sequence of function calls should be - * 1) fwu_get_mdata() 2) Modify the medata fields 3) fwu_update_mdata() - * - * The sequence of updating the partitions should be, update the - * primary metadata partition (first partition encountered), followed - * by updating the secondary partition. With this update sequence, in - * the rare scenario that the two metadata partitions are valid but do - * not match, maybe due to power outage at the time of updating the - * metadata copies, the secondary partition can be updated from the - * primary. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_update_mdata(struct udevice *dev, struct fwu_mdata *mdata); +int fwu_get_mdata(struct fwu_mdata *mdata); /** * fwu_get_active_index() - Get active_index from the FWU metadata @@ -263,18 +139,6 @@ int fwu_set_active_index(uint active_idx); int fwu_get_image_index(u8 *image_index); /** - * fwu_mdata_check() - Check if the FWU metadata is valid - * @dev: FWU metadata device - * - * Validate both copies of the FWU metadata. If one of the copies - * has gone bad, restore it from the other copy. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_mdata_check(struct udevice *dev); - -/** * fwu_revert_boot_index() - Revert the active index in the FWU metadata * * Revert the active_index value in the FWU metadata, by swapping the values @@ -287,20 +151,6 @@ int fwu_mdata_check(struct udevice *dev); int fwu_revert_boot_index(void); /** - * fwu_verify_mdata() - Verify the FWU metadata - * @mdata: FWU metadata structure - * @pri_part: FWU metadata partition is primary or secondary - * - * Verify the FWU metadata by computing the CRC32 for the metadata - * structure and comparing it against the CRC32 value stored as part - * of the structure. - * - * Return: 0 if OK, -ve on error - * - */ -int fwu_verify_mdata(struct fwu_mdata *mdata, bool pri_part); - -/** * fwu_accept_image() - Set the Acceptance bit for the image * @img_type_id: GUID of the image type for which the accepted bit is to be * cleared @@ -409,4 +259,28 @@ u8 fwu_empty_capsule_checks_pass(void); */ int fwu_trial_state_ctr_start(void); +/** + * fwu_gen_alt_info_from_mtd() - Parse dfu_alt_info from metadata in mtd + * @buf: Buffer into which the dfu_alt_info is filled + * @len: Maximum characters that can be written in buf + * @mtd: Pointer to underlying MTD device + * + * Parse dfu_alt_info from metadata in mtd. Used for setting the env. + * + * Return: 0 if OK, -ve on error + */ +int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd); + +/** + * fwu_mtd_get_alt_num() - Mapping of fwu_plat_get_alt_num for MTD device + * @image_guid: Image GUID for which DFU alt number needs to be retrieved + * @alt_num: Pointer to the alt_num + * @mtd_dev: Name of mtd device instance + * + * To map fwu_plat_get_alt_num onto mtd based metadata implementation. + * + * Return: 0 if OK, -ve on error + */ +int fwu_mtd_get_alt_num(efi_guid_t *image_guid, u8 *alt_num, const char *mtd_dev); + #endif /* _FWU_H_ */ diff --git a/include/fwu_mdata.h b/include/fwu_mdata.h index 8fda4f4..56189e2 100644 --- a/include/fwu_mdata.h +++ b/include/fwu_mdata.h @@ -6,6 +6,7 @@ #if !defined _FWU_MDATA_H_ #define _FWU_MDATA_H_ +#include <linux/compiler_attributes.h> #include <efi.h> /** @@ -22,7 +23,7 @@ struct fwu_image_bank_info { efi_guid_t image_uuid; uint32_t accepted; uint32_t reserved; -}; +} __packed; /** * struct fwu_image_entry - information for a particular type of image @@ -38,7 +39,7 @@ struct fwu_image_entry { efi_guid_t image_type_uuid; efi_guid_t location_uuid; struct fwu_image_bank_info img_bank_info[CONFIG_FWU_NUM_BANKS]; -}; +} __packed; /** * struct fwu_mdata - FWU metadata structure for multi-bank updates @@ -62,6 +63,6 @@ struct fwu_mdata { uint32_t previous_active_index; struct fwu_image_entry img_entry[CONFIG_FWU_NUM_IMAGES_PER_BANK]; -}; +} __packed; #endif /* _FWU_MDATA_H_ */ diff --git a/include/imx_sip.h b/include/imx_sip.h index 1b873f2..ebbb3a1 100644 --- a/include/imx_sip.h +++ b/include/imx_sip.h @@ -4,7 +4,7 @@ */ #ifndef _IMX_SIP_H__ -#define _IMX_SIP_H_ +#define _IMX_SIP_H__ #define IMX_SIP_GPC 0xC2000000 #define IMX_SIP_GPC_PM_DOMAIN 0x03 diff --git a/include/lcd_console.h b/include/lcd_console.h deleted file mode 100644 index 061a6a4..0000000 --- a/include/lcd_console.h +++ /dev/null @@ -1,102 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/ - */ - -/* By default we scroll by a single line */ - -struct console_t { - short curr_col, curr_row; - short cols, rows; - void *fbbase; - u32 lcdsizex, lcdsizey, lcdrot; - void (*fp_putc_xy)(struct console_t *pcons, ushort x, ushort y, char c); - void (*fp_console_moverow)(struct console_t *pcons, - u32 rowdst, u32 rowsrc); - void (*fp_console_setrow)(struct console_t *pcons, u32 row, int clr); -}; - -/** - * console_calc_rowcol() - calculate available rows / columns wihtin a given - * screen-size based on used VIDEO_FONT. - * - * @pcons: Pointer to struct console_t - * @sizex: size X of the screen in pixel - * @sizey: size Y of the screen in pixel - */ -void console_calc_rowcol(struct console_t *pcons, u32 sizex, u32 sizey); -/** - * lcd_init_console() - Initialize lcd console parameters - * - * Setup the address of console base, and the number of rows and columns the - * console has. - * - * @address: Console base address - * @vl_rows: Number of rows in the console - * @vl_cols: Number of columns in the console - * @vl_rot: Rotation of display in degree (0 - 90 - 180 - 270) counterlockwise - */ -void lcd_init_console(void *address, int vl_cols, int vl_rows, int vl_rot); -/** - * lcd_set_col() - Set the number of the current lcd console column - * - * Set the number of the console column where the cursor is. - * - * @col: Column number - */ -void lcd_set_col(short col); - -/** - * lcd_set_row() - Set the number of the current lcd console row - * - * Set the number of the console row where the cursor is. - * - * @row: Row number - */ -void lcd_set_row(short row); - -/** - * lcd_position_cursor() - Position the cursor on the screen - * - * Position the cursor at the given coordinates on the screen. - * - * @col: Column number - * @row: Row number - */ -void lcd_position_cursor(unsigned col, unsigned row); - -/** - * lcd_get_screen_rows() - Get the total number of screen rows - * - * @return: Number of screen rows - */ -int lcd_get_screen_rows(void); - -/** - * lcd_get_screen_columns() - Get the total number of screen columns - * - * @return: Number of screen columns - */ -int lcd_get_screen_columns(void); - -/** - * lcd_putc() - Print to screen a single character at the location of the cursor - * - * @c: The character to print - */ -void lcd_putc(const char c); - -/** - * lcd_puts() - Print to screen a string at the location of the cursor - * - * @s: The string to print - */ -void lcd_puts(const char *s); - -/** - * lcd_printf() - Print to screen a formatted string at location of the cursor - * - * @fmt: The formatted string to print - * @...: The arguments for the formatted string - */ -void lcd_printf(const char *fmt, ...); diff --git a/include/lcdvideo.h b/include/lcdvideo.h deleted file mode 100644 index f0640a5..0000000 --- a/include/lcdvideo.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * MPC823 LCD and Video Controller - * Copyright (c) 1999 Dan Malek (dmalek@jlc.net) - */ -#ifndef __LCDVIDEO_H__ -#define __LCDVIDEO_H__ - - -/* LCD Controller Configuration Register. -*/ -#define LCCR_BNUM ((uint)0xfffe0000) -#define LCCR_EIEN ((uint)0x00010000) -#define LCCR_IEN ((uint)0x00008000) -#define LCCR_IRQL ((uint)0x00007000) -#define LCCR_CLKP ((uint)0x00000800) -#define LCCR_OEP ((uint)0x00000400) -#define LCCR_HSP ((uint)0x00000200) -#define LCCR_VSP ((uint)0x00000100) -#define LCCR_DP ((uint)0x00000080) -#define LCCR_BPIX ((uint)0x00000060) -#define LCCR_LBW ((uint)0x00000010) -#define LCCR_SPLT ((uint)0x00000008) -#define LCCR_CLOR ((uint)0x00000004) -#define LCCR_TFT ((uint)0x00000002) -#define LCCR_PON ((uint)0x00000001) - -/* Define the bit shifts to load values into the register. -*/ -#define LCDBIT(BIT, VAL) ((VAL) << (31 - BIT)) - -#define LCCR_BNUM_BIT ((uint)14) -#define LCCR_EIEN_BIT ((uint)15) -#define LCCR_IEN_BIT ((uint)16) -#define LCCR_IROL_BIT ((uint)19) -#define LCCR_CLKP_BIT ((uint)20) -#define LCCR_OEP_BIT ((uint)21) -#define LCCR_HSP_BIT ((uint)22) -#define LCCR_VSP_BIT ((uint)23) -#define LCCR_DP_BIT ((uint)24) -#define LCCR_BPIX_BIT ((uint)26) -#define LCCR_LBW_BIT ((uint)27) -#define LCCR_SPLT_BIT ((uint)28) -#define LCCR_CLOR_BIT ((uint)29) -#define LCCR_TFT_BIT ((uint)30) -#define LCCR_PON_BIT ((uint)31) - -/* LCD Horizontal control register. -*/ -#define LCHCR_BO ((uint)0x01000000) -#define LCHCR_AT ((uint)0x00e00000) -#define LCHCR_HPC ((uint)0x001ffc00) -#define LCHCR_WBL ((uint)0x000003ff) - -#define LCHCR_AT_BIT ((uint)10) -#define LCHCR_HPC_BIT ((uint)21) -#define LCHCR_WBL_BIT ((uint)31) - -/* LCD Vertical control register. -*/ -#define LCVCR_VPW ((uint)0xf0000000) -#define LCVCR_LCD_AC ((uint)0x01e00000) -#define LCVCR_VPC ((uint)0x001ff800) -#define LCVCR_WBF ((uint)0x000003ff) - -#define LCVCR_VPW_BIT ((uint)3) -#define LCVCR_LCD_AC_BIT ((uint)10) -#define LCVCR_VPC_BIT ((uint)20) - -#endif /* __LCDVIDEO_H__ */ diff --git a/include/linux/build_bug.h b/include/linux/build_bug.h index 9c7088b..20c2dc7 100644 --- a/include/linux/build_bug.h +++ b/include/linux/build_bug.h @@ -4,15 +4,16 @@ #include <linux/compiler.h> #ifdef __CHECKER__ -#define __BUILD_BUG_ON_NOT_POWER_OF_2(n) (0) -#define BUILD_BUG_ON_NOT_POWER_OF_2(n) (0) #define BUILD_BUG_ON_ZERO(e) (0) -#define BUILD_BUG_ON_NULL(e) ((void *)0) -#define BUILD_BUG_ON_INVALID(e) (0) -#define BUILD_BUG_ON_MSG(cond, msg) (0) -#define BUILD_BUG_ON(condition) (0) -#define BUILD_BUG() (0) #else /* __CHECKER__ */ +/* + * Force a compilation error if condition is true, but also produce a + * result (of value 0 and type int), so the expression can be used + * e.g. in a structure initializer (or where-ever else comma expressions + * aren't permitted). + */ +#define BUILD_BUG_ON_ZERO(e) ((int)sizeof(struct { int:(-!!(e)); })) +#endif /* __CHECKER__ */ /* Force a compilation error if a constant expression is not a power of 2 */ #define __BUILD_BUG_ON_NOT_POWER_OF_2(n) \ @@ -21,15 +22,6 @@ BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0)) /* - * Force a compilation error if condition is true, but also produce a - * result (of value 0 and type size_t), so the expression can be used - * e.g. in a structure initializer (or where-ever else comma expressions - * aren't permitted). - */ -#define BUILD_BUG_ON_ZERO(e) (sizeof(struct { int:(-!!(e)); })) -#define BUILD_BUG_ON_NULL(e) ((void *)sizeof(struct { int:(-!!(e)); })) - -/* * BUILD_BUG_ON_INVALID() permits the compiler to check the validity of the * expression but avoids the generation of any code, even if that expression * has side-effects. @@ -52,23 +44,9 @@ * If you have some code which relies on certain constants being equal, or * some other compile-time-evaluated condition, you should use BUILD_BUG_ON to * detect if someone changes it. - * - * The implementation uses gcc's reluctance to create a negative array, but gcc - * (as of 4.4) only emits that error for obvious cases (e.g. not arguments to - * inline functions). Luckily, in 4.3 they added the "error" function - * attribute just for this type of case. Thus, we use a negative sized array - * (should always create an error on gcc versions older than 4.4) and then call - * an undefined function with the error attribute (should always create an - * error on gcc 4.3 and later). If for some reason, neither creates a - * compile-time error, we'll still have a link-time error, which is harder to - * track down. */ -#ifndef __OPTIMIZE__ -#define BUILD_BUG_ON(condition) ((void)sizeof(char[1 - 2*!!(condition)])) -#else #define BUILD_BUG_ON(condition) \ BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition) -#endif /** * BUILD_BUG - break compile if used. @@ -98,6 +76,4 @@ #define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) #define __static_assert(expr, msg, ...) _Static_assert(expr, msg) -#endif /* __CHECKER__ */ - #endif /* _LINUX_BUILD_BUG_H */ diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h deleted file mode 100644 index 0644d92..0000000 --- a/include/linux/mc146818rtc.h +++ /dev/null @@ -1,86 +0,0 @@ -/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM - * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993 - * derived from Data Sheet, Copyright Motorola 1984 (!). - * It was written to be part of the Linux operating system. - */ -/* permission is hereby granted to copy, modify and redistribute this code - * in terms of the GNU Library General Public License, Version 2 or later, - * at your option. - */ - -#ifndef _MC146818RTC_H -#define _MC146818RTC_H - -#include <asm/io.h> -#include <linux/rtc.h> /* get the user-level API */ -#include <asm/mc146818rtc.h> /* register access macros */ - -/********************************************************************** - * register summary - **********************************************************************/ -#define RTC_SECONDS 0 -#define RTC_SECONDS_ALARM 1 -#define RTC_MINUTES 2 -#define RTC_MINUTES_ALARM 3 -#define RTC_HOURS 4 -#define RTC_HOURS_ALARM 5 -/* RTC_*_alarm is always true if 2 MSBs are set */ -# define RTC_ALARM_DONT_CARE 0xC0 - -#define RTC_DAY_OF_WEEK 6 -#define RTC_DAY_OF_MONTH 7 -#define RTC_MONTH 8 -#define RTC_YEAR 9 - -/* control registers - Moto names - */ -#define RTC_REG_A 10 -#define RTC_REG_B 11 -#define RTC_REG_C 12 -#define RTC_REG_D 13 - -/********************************************************************** - * register details - **********************************************************************/ -#define RTC_FREQ_SELECT RTC_REG_A - -/* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, - * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, - * totalling to a max high interval of 2.228 ms. - */ -# define RTC_UIP 0x80 -# define RTC_DIV_CTL 0x70 - /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ -# define RTC_REF_CLCK_4MHZ 0x00 -# define RTC_REF_CLCK_1MHZ 0x10 -# define RTC_REF_CLCK_32KHZ 0x20 - /* 2 values for divider stage reset, others for "testing purposes only" */ -# define RTC_DIV_RESET1 0x60 -# define RTC_DIV_RESET2 0x70 - /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ -# define RTC_RATE_SELECT 0x0F - -/**********************************************************************/ -#define RTC_CONTROL RTC_REG_B -# define RTC_SET 0x80 /* disable updates for clock setting */ -# define RTC_PIE 0x40 /* periodic interrupt enable */ -# define RTC_AIE 0x20 /* alarm interrupt enable */ -# define RTC_UIE 0x10 /* update-finished interrupt enable */ -# define RTC_SQWE 0x08 /* enable square-wave output */ -# define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ -# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ -# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ - -/**********************************************************************/ -#define RTC_INTR_FLAGS RTC_REG_C -/* caution - cleared by read */ -# define RTC_IRQF 0x80 /* any of the following 3 is active */ -# define RTC_PF 0x40 -# define RTC_AF 0x20 -# define RTC_UF 0x10 - -/**********************************************************************/ -#define RTC_VALID RTC_REG_D -# define RTC_VRT 0x80 /* valid RAM and time */ -/**********************************************************************/ -#endif /* _MC146818RTC_H */ diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h deleted file mode 100644 index a72cb7d..0000000 --- a/include/linux/mtd/doc2000.h +++ /dev/null @@ -1,207 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Linux driver for Disk-On-Chip devices - * - * Copyright © 1999 Machine Vision Holdings, Inc. - * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> - * Copyright © 2002-2003 Greg Ungerer <gerg@snapgear.com> - * Copyright © 2002-2003 SnapGear Inc - * - */ - -#ifndef __MTD_DOC2000_H__ -#define __MTD_DOC2000_H__ - -#include <linux/mtd/mtd.h> -#if 0 -#include <linux/mutex.h> -#endif - -#define DoC_Sig1 0 -#define DoC_Sig2 1 - -#define DoC_ChipID 0x1000 -#define DoC_DOCStatus 0x1001 -#define DoC_DOCControl 0x1002 -#define DoC_FloorSelect 0x1003 -#define DoC_CDSNControl 0x1004 -#define DoC_CDSNDeviceSelect 0x1005 -#define DoC_ECCConf 0x1006 -#define DoC_2k_ECCStatus 0x1007 - -#define DoC_CDSNSlowIO 0x100d -#define DoC_ECCSyndrome0 0x1010 -#define DoC_ECCSyndrome1 0x1011 -#define DoC_ECCSyndrome2 0x1012 -#define DoC_ECCSyndrome3 0x1013 -#define DoC_ECCSyndrome4 0x1014 -#define DoC_ECCSyndrome5 0x1015 -#define DoC_AliasResolution 0x101b -#define DoC_ConfigInput 0x101c -#define DoC_ReadPipeInit 0x101d -#define DoC_WritePipeTerm 0x101e -#define DoC_LastDataRead 0x101f -#define DoC_NOP 0x1020 - -#define DoC_Mil_CDSN_IO 0x0800 -#define DoC_2k_CDSN_IO 0x1800 - -#define DoC_Mplus_NOP 0x1002 -#define DoC_Mplus_AliasResolution 0x1004 -#define DoC_Mplus_DOCControl 0x1006 -#define DoC_Mplus_AccessStatus 0x1008 -#define DoC_Mplus_DeviceSelect 0x1008 -#define DoC_Mplus_Configuration 0x100a -#define DoC_Mplus_OutputControl 0x100c -#define DoC_Mplus_FlashControl 0x1020 -#define DoC_Mplus_FlashSelect 0x1022 -#define DoC_Mplus_FlashCmd 0x1024 -#define DoC_Mplus_FlashAddress 0x1026 -#define DoC_Mplus_FlashData0 0x1028 -#define DoC_Mplus_FlashData1 0x1029 -#define DoC_Mplus_ReadPipeInit 0x102a -#define DoC_Mplus_LastDataRead 0x102c -#define DoC_Mplus_LastDataRead1 0x102d -#define DoC_Mplus_WritePipeTerm 0x102e -#define DoC_Mplus_ECCSyndrome0 0x1040 -#define DoC_Mplus_ECCSyndrome1 0x1041 -#define DoC_Mplus_ECCSyndrome2 0x1042 -#define DoC_Mplus_ECCSyndrome3 0x1043 -#define DoC_Mplus_ECCSyndrome4 0x1044 -#define DoC_Mplus_ECCSyndrome5 0x1045 -#define DoC_Mplus_ECCConf 0x1046 -#define DoC_Mplus_Toggle 0x1046 -#define DoC_Mplus_DownloadStatus 0x1074 -#define DoC_Mplus_CtrlConfirm 0x1076 -#define DoC_Mplus_Power 0x1fff - -/* How to access the device? - * On ARM, it'll be mmap'd directly with 32-bit wide accesses. - * On PPC, it's mmap'd and 16-bit wide. - * Others use readb/writeb - */ -#if defined(__arm__) -#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)))) -#define WriteDOC_(d, adr, reg) do{ *(volatile __u32 *)(((unsigned long)adr)+((reg)<<2)) = (__u32)d; wmb();} while(0) -#define DOC_IOREMAP_LEN 0x8000 -#elif defined(__ppc__) -#define ReadDOC_(adr, reg) ((unsigned char)(*(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)))) -#define WriteDOC_(d, adr, reg) do{ *(volatile __u16 *)(((unsigned long)adr)+((reg)<<1)) = (__u16)d; wmb();} while(0) -#define DOC_IOREMAP_LEN 0x4000 -#else -#define ReadDOC_(adr, reg) readb((void __iomem *)(adr) + (reg)) -#define WriteDOC_(d, adr, reg) writeb(d, (void __iomem *)(adr) + (reg)) -#define DOC_IOREMAP_LEN 0x2000 - -#endif - -#if defined(__i386__) || defined(__x86_64__) -#define USE_MEMCPY -#endif - -/* These are provided to directly use the DoC_xxx defines */ -#define ReadDOC(adr, reg) ReadDOC_(adr,DoC_##reg) -#define WriteDOC(d, adr, reg) WriteDOC_(d,adr,DoC_##reg) - -#define DOC_MODE_RESET 0 -#define DOC_MODE_NORMAL 1 -#define DOC_MODE_RESERVED1 2 -#define DOC_MODE_RESERVED2 3 - -#define DOC_MODE_CLR_ERR 0x80 -#define DOC_MODE_RST_LAT 0x10 -#define DOC_MODE_BDECT 0x08 -#define DOC_MODE_MDWREN 0x04 - -#define DOC_ChipID_Doc2k 0x20 -#define DOC_ChipID_Doc2kTSOP 0x21 /* internal number for MTD */ -#define DOC_ChipID_DocMil 0x30 -#define DOC_ChipID_DocMilPlus32 0x40 -#define DOC_ChipID_DocMilPlus16 0x41 - -#define CDSN_CTRL_FR_B 0x80 -#define CDSN_CTRL_FR_B0 0x40 -#define CDSN_CTRL_FR_B1 0x80 - -#define CDSN_CTRL_ECC_IO 0x20 -#define CDSN_CTRL_FLASH_IO 0x10 -#define CDSN_CTRL_WP 0x08 -#define CDSN_CTRL_ALE 0x04 -#define CDSN_CTRL_CLE 0x02 -#define CDSN_CTRL_CE 0x01 - -#define DOC_ECC_RESET 0 -#define DOC_ECC_ERROR 0x80 -#define DOC_ECC_RW 0x20 -#define DOC_ECC__EN 0x08 -#define DOC_TOGGLE_BIT 0x04 -#define DOC_ECC_RESV 0x02 -#define DOC_ECC_IGNORE 0x01 - -#define DOC_FLASH_CE 0x80 -#define DOC_FLASH_WP 0x40 -#define DOC_FLASH_BANK 0x02 - -/* We have to also set the reserved bit 1 for enable */ -#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV) -#define DOC_ECC_DIS (DOC_ECC_RESV) - -struct Nand { - char floor, chip; - unsigned long curadr; - unsigned char curmode; - /* Also some erase/write/pipeline info when we get that far */ -}; - -#define MAX_FLOORS 4 -#define MAX_CHIPS 4 - -#define MAX_FLOORS_MIL 1 -#define MAX_CHIPS_MIL 1 - -#define MAX_FLOORS_MPLUS 2 -#define MAX_CHIPS_MPLUS 1 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -struct DiskOnChip { - unsigned long physadr; - void __iomem *virtadr; - unsigned long totlen; - unsigned char ChipID; /* Type of DiskOnChip */ - int ioreg; - - unsigned long mfr; /* Flash IDs - only one type of flash per device */ - unsigned long id; - int chipshift; - char page256; - char pageadrlen; - char interleave; /* Internal interleaving - Millennium Plus style */ - unsigned long erasesize; - - int curfloor; - int curchip; - - int numchips; - struct Nand *chips; - struct mtd_info *nextdoc; -/* XXX U-BOOT XXX */ -#if 0 - struct mutex lock; -#endif -}; - -int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]); - -/* XXX U-BOOT XXX */ -#if 1 -/* - * NAND Flash Manufacturer ID Codes - */ -#define NAND_MFR_TOSHIBA 0x98 -#define NAND_MFR_SAMSUNG 0xec -#endif - -#endif /* __MTD_DOC2000_H__ */ diff --git a/include/linux/mtd/ndfc.h b/include/linux/mtd/ndfc.h deleted file mode 100644 index d0558a9..0000000 --- a/include/linux/mtd/ndfc.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * linux/include/linux/mtd/ndfc.h - * - * Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Info: - * Contains defines, datastructures for ndfc nand controller - * - */ -#ifndef __LINUX_MTD_NDFC_H -#define __LINUX_MTD_NDFC_H - -/* NDFC Register definitions */ -#define NDFC_CMD 0x00 -#define NDFC_ALE 0x04 -#define NDFC_DATA 0x08 -#define NDFC_ECC 0x10 -#define NDFC_BCFG0 0x30 -#define NDFC_BCFG1 0x34 -#define NDFC_BCFG2 0x38 -#define NDFC_BCFG3 0x3c -#define NDFC_CCR 0x40 -#define NDFC_STAT 0x44 -#define NDFC_HWCTL 0x48 -#define NDFC_REVID 0x50 - -#define NDFC_STAT_IS_READY 0x01000000 - -#define NDFC_CCR_RESET_CE 0x80000000 /* CE Reset */ -#define NDFC_CCR_RESET_ECC 0x40000000 /* ECC Reset */ -#define NDFC_CCR_RIE 0x20000000 /* Interrupt Enable on Device Rdy */ -#define NDFC_CCR_REN 0x10000000 /* Enable wait for Rdy in LinearR */ -#define NDFC_CCR_ROMEN 0x08000000 /* Enable ROM In LinearR */ -#define NDFC_CCR_ARE 0x04000000 /* Auto-Read Enable */ -#define NDFC_CCR_BS(x) (((x) & 0x3) << 24) /* Select Bank on CE[x] */ -#define NDFC_CCR_BS_MASK 0x03000000 /* Select Bank */ -#define NDFC_CCR_ARAC0 0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */ -#define NDFC_CCR_ARAC1 0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */ -#define NDFC_CCR_ARAC2 0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */ -#define NDFC_CCR_ARAC3 0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */ -#define NDFC_CCR_ARAC_MASK 0x00003000 /* Auto-Read mode Addr Cycles */ -#define NDFC_CCR_RPG 0x0000C000 /* Auto-Read Page */ -#define NDFC_CCR_EBCC 0x00000004 /* EBC Configuration Completed */ -#define NDFC_CCR_DHC 0x00000002 /* Direct Hardware Control Enable */ - -#define NDFC_BxCFG_EN 0x80000000 /* Bank Enable */ -#define NDFC_BxCFG_CED 0x40000000 /* nCE Style */ -#define NDFC_BxCFG_SZ_MASK 0x08000000 /* Bank Size */ -#define NDFC_BxCFG_SZ_8BIT 0x00000000 /* 8bit */ -#define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */ - -#define NDFC_MAX_BANKS 4 - -struct ndfc_controller_settings { - uint32_t ccr_settings; - uint64_t ndfc_erpn; -}; - -struct ndfc_chip_settings { - uint32_t bank_settings; -}; - -#endif diff --git a/include/linux/stddef.h b/include/linux/stddef.h index a7f546f..c732eef 100644 --- a/include/linux/stddef.h +++ b/include/linux/stddef.h @@ -14,13 +14,7 @@ #include <linux/types.h> #endif -#ifndef __CHECKER__ #undef offsetof -#ifdef __compiler_offsetof -#define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE, MEMBER) -#else -#define offsetof(TYPE, MEMBER) ((size_t)&((TYPE *)0)->MEMBER) -#endif -#endif +#define offsetof(TYPE, MEMBER) __builtin_offsetof(TYPE, MEMBER) #endif diff --git a/include/linux/unaligned/access_ok.h b/include/linux/unaligned/access_ok.h deleted file mode 100644 index 5f46eee..0000000 --- a/include/linux/unaligned/access_ok.h +++ /dev/null @@ -1,66 +0,0 @@ -#ifndef _LINUX_UNALIGNED_ACCESS_OK_H -#define _LINUX_UNALIGNED_ACCESS_OK_H - -#include <asm/byteorder.h> - -static inline u16 get_unaligned_le16(const void *p) -{ - return le16_to_cpup((__le16 *)p); -} - -static inline u32 get_unaligned_le32(const void *p) -{ - return le32_to_cpup((__le32 *)p); -} - -static inline u64 get_unaligned_le64(const void *p) -{ - return le64_to_cpup((__le64 *)p); -} - -static inline u16 get_unaligned_be16(const void *p) -{ - return be16_to_cpup((__be16 *)p); -} - -static inline u32 get_unaligned_be32(const void *p) -{ - return be32_to_cpup((__be32 *)p); -} - -static inline u64 get_unaligned_be64(const void *p) -{ - return be64_to_cpup((__be64 *)p); -} - -static inline void put_unaligned_le16(u16 val, void *p) -{ - *((__le16 *)p) = cpu_to_le16(val); -} - -static inline void put_unaligned_le32(u32 val, void *p) -{ - *((__le32 *)p) = cpu_to_le32(val); -} - -static inline void put_unaligned_le64(u64 val, void *p) -{ - *((__le64 *)p) = cpu_to_le64(val); -} - -static inline void put_unaligned_be16(u16 val, void *p) -{ - *((__be16 *)p) = cpu_to_be16(val); -} - -static inline void put_unaligned_be32(u32 val, void *p) -{ - *((__be32 *)p) = cpu_to_be32(val); -} - -static inline void put_unaligned_be64(u64 val, void *p) -{ - *((__be64 *)p) = cpu_to_be64(val); -} - -#endif /* _LINUX_UNALIGNED_ACCESS_OK_H */ diff --git a/include/linux_logo.h b/include/linux_logo.h deleted file mode 100644 index 9aa712e..0000000 --- a/include/linux_logo.h +++ /dev/null @@ -1,1445 +0,0 @@ -/* $Id: linux_logo.h,v 1.5 1998/07/30 16:30:58 jj Exp $ - * include/linux/linux_logo.h: This is a linux logo - * to be displayed on boot. - * - * Copyright (C) 1996 Larry Ewing (lewing@isc.tamu.edu) - * Copyright (C) 1996,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) - * - * You can put anything here, but: - * LINUX_LOGO_COLORS has to be less than 224 - * image size has to be 80x80 - * values have to start from 0x20 - * (i.e. RGB(linux_logo_red[0], - * linux_logo_green[0], - * linux_logo_blue[0]) is color 0x20) - * BW image has to be 80x80 as well, with MS bit - * on the left - * Serial_console ascii image can be any size, - * but should contain %s to display the version - */ - -#if LINUX_LOGO_COLORS == 214 - -unsigned char linux_logo_red[] __initdata = { - 0x02, 0x9E, 0xE9, 0xC4, 0x50, 0xC9, 0xC4, 0xE9, - 0x65, 0xE3, 0xC2, 0x25, 0xA4, 0xEC, 0x90, 0xA6, - 0xC4, 0x6A, 0xD1, 0xF3, 0x12, 0xED, 0xA0, 0xC2, - 0xB8, 0xD5, 0xDB, 0xD2, 0x3E, 0x16, 0xEB, 0x54, - 0xA9, 0xCD, 0xF5, 0x0A, 0xBA, 0xB3, 0xDC, 0x74, - 0xCE, 0xF6, 0xD3, 0xC5, 0xEA, 0xB8, 0xED, 0x5E, - 0xE5, 0x26, 0xF4, 0xA9, 0x82, 0x94, 0xE6, 0x38, - 0xF2, 0x0F, 0x7F, 0x49, 0xE5, 0xF4, 0xD3, 0xC3, - 0xC2, 0x1E, 0xD5, 0xC6, 0xA4, 0xFA, 0x0A, 0xBA, - 0xD4, 0xEB, 0xEA, 0xEC, 0xA8, 0xBC, 0xB4, 0xDC, - 0x84, 0xE4, 0xCE, 0xEC, 0x92, 0xCD, 0xDC, 0x8B, - 0xCC, 0x1E, 0xF6, 0xB2, 0x60, 0x2A, 0x96, 0x52, - 0x0F, 0xBD, 0xFA, 0xCC, 0xB8, 0x7A, 0x4C, 0xD2, - 0x06, 0xEF, 0x44, 0x64, 0xF4, 0xBA, 0xCE, 0xE6, - 0x8A, 0x6F, 0x3C, 0x70, 0x7C, 0x9C, 0xBA, 0xDF, - 0x2C, 0x4D, 0x3B, 0xCA, 0xDE, 0xCE, 0xEE, 0x46, - 0x6A, 0xAC, 0x96, 0xE5, 0x96, 0x7A, 0xBA, 0xB6, - 0xE2, 0x7E, 0xAA, 0xC5, 0x96, 0x9E, 0xC2, 0xAA, - 0xDA, 0x35, 0xB6, 0x82, 0x88, 0xBE, 0xC2, 0x9E, - 0xB4, 0xD5, 0xDA, 0x9C, 0xA0, 0xD0, 0xA8, 0xC7, - 0x72, 0xF2, 0xDB, 0x76, 0xDC, 0xBE, 0xAA, 0xF4, - 0x87, 0x2F, 0x53, 0x8E, 0x36, 0xCE, 0xE6, 0xCA, - 0xCB, 0xE4, 0xD6, 0xAA, 0x42, 0x5D, 0xB4, 0x59, - 0x1C, 0xC8, 0x96, 0x6C, 0xDA, 0xCE, 0xE6, 0xCB, - 0x96, 0x16, 0xFA, 0xBE, 0xAE, 0xFE, 0x6E, 0xD6, - 0xCE, 0xB6, 0xE5, 0xED, 0xDB, 0xDC, 0xF4, 0x72, - 0x1F, 0xAE, 0xE6, 0xC2, 0xCA, 0xC4 -}; - -unsigned char linux_logo_green[] __initdata = { - 0x02, 0x88, 0xC4, 0x85, 0x44, 0xA2, 0xA8, 0xE5, - 0x65, 0xA6, 0xC2, 0x24, 0xA4, 0xB4, 0x62, 0x86, - 0x94, 0x44, 0xD2, 0xB6, 0x12, 0xD4, 0x73, 0x96, - 0x92, 0x95, 0xB2, 0xC2, 0x36, 0x0E, 0xBC, 0x54, - 0x75, 0xA5, 0xF5, 0x0A, 0xB2, 0x83, 0xC2, 0x74, - 0x9B, 0xBD, 0xA2, 0xCA, 0xDA, 0x8C, 0xCB, 0x42, - 0xAC, 0x12, 0xDA, 0x7B, 0x54, 0x94, 0xD2, 0x24, - 0xBE, 0x06, 0x65, 0x33, 0xBB, 0xBC, 0xAB, 0x8C, - 0x92, 0x1E, 0x9B, 0xB6, 0x6E, 0xFB, 0x04, 0xA2, - 0xC8, 0xBD, 0xAD, 0xEC, 0x92, 0xBC, 0x7B, 0x9D, - 0x84, 0xC4, 0xC4, 0xB4, 0x6C, 0x93, 0xA3, 0x5E, - 0x8D, 0x13, 0xD6, 0x82, 0x4C, 0x2A, 0x7A, 0x5A, - 0x0D, 0x82, 0xBB, 0xCC, 0x8B, 0x6A, 0x3C, 0xBE, - 0x06, 0xC4, 0x44, 0x45, 0xDB, 0x96, 0xB6, 0xDE, - 0x8A, 0x4D, 0x3C, 0x5A, 0x7C, 0x9C, 0xAA, 0xCB, - 0x1C, 0x4D, 0x2E, 0xB2, 0xBE, 0xAA, 0xDE, 0x3E, - 0x6A, 0xAC, 0x82, 0xE5, 0x72, 0x62, 0x92, 0x9E, - 0xCA, 0x4A, 0x8E, 0xBE, 0x86, 0x6B, 0xAA, 0x9A, - 0xBE, 0x34, 0xAB, 0x76, 0x6E, 0x9A, 0x9E, 0x62, - 0x76, 0xCE, 0xD3, 0x92, 0x7C, 0xB8, 0x7E, 0xC6, - 0x5E, 0xE2, 0xC3, 0x54, 0xAA, 0x9E, 0x8A, 0xCA, - 0x63, 0x2D, 0x3B, 0x8E, 0x1A, 0x9E, 0xC2, 0xA6, - 0xCB, 0xDC, 0xD6, 0x8E, 0x26, 0x5C, 0xB4, 0x45, - 0x1C, 0xB8, 0x6E, 0x4C, 0xBC, 0xAE, 0xD6, 0x92, - 0x63, 0x16, 0xF6, 0x8C, 0x7A, 0xFE, 0x6E, 0xBA, - 0xC6, 0x86, 0xAA, 0xAE, 0xDB, 0xA4, 0xD4, 0x56, - 0x0E, 0x6E, 0xB6, 0xB2, 0xBE, 0xBE -}; - -unsigned char linux_logo_blue[] __initdata = { - 0x04, 0x28, 0x10, 0x0B, 0x14, 0x14, 0x74, 0xC7, - 0x64, 0x0E, 0xC3, 0x24, 0xA4, 0x0C, 0x10, 0x20, - 0x0D, 0x04, 0xD1, 0x0D, 0x13, 0x22, 0x0A, 0x40, - 0x14, 0x0C, 0x11, 0x94, 0x0C, 0x08, 0x0B, 0x56, - 0x09, 0x47, 0xF4, 0x0B, 0x9C, 0x07, 0x54, 0x74, - 0x0F, 0x0C, 0x0F, 0xC7, 0x6C, 0x14, 0x14, 0x11, - 0x0B, 0x04, 0x12, 0x0C, 0x05, 0x94, 0x94, 0x0A, - 0x34, 0x09, 0x14, 0x08, 0x2F, 0x15, 0x19, 0x11, - 0x28, 0x0C, 0x0B, 0x94, 0x08, 0xFA, 0x08, 0x7C, - 0xBC, 0x15, 0x0A, 0xEC, 0x64, 0xBB, 0x0A, 0x0C, - 0x84, 0x2C, 0xA0, 0x15, 0x10, 0x0D, 0x0B, 0x0E, - 0x0A, 0x07, 0x10, 0x3C, 0x24, 0x2C, 0x28, 0x5C, - 0x0A, 0x0D, 0x0A, 0xC1, 0x22, 0x4C, 0x10, 0x94, - 0x04, 0x0F, 0x45, 0x08, 0x31, 0x54, 0x3C, 0xBC, - 0x8C, 0x09, 0x3C, 0x18, 0x7C, 0x9C, 0x7C, 0x91, - 0x0C, 0x4D, 0x17, 0x74, 0x0C, 0x48, 0x9C, 0x3C, - 0x6A, 0xAC, 0x5C, 0xE3, 0x29, 0x3C, 0x2C, 0x7C, - 0x6C, 0x04, 0x14, 0xA9, 0x74, 0x07, 0x2C, 0x74, - 0x4C, 0x34, 0x97, 0x5C, 0x38, 0x0C, 0x5C, 0x04, - 0x0C, 0xBA, 0xBC, 0x78, 0x18, 0x88, 0x24, 0xC2, - 0x3C, 0xB4, 0x87, 0x0C, 0x14, 0x4C, 0x3C, 0x10, - 0x17, 0x2C, 0x0A, 0x8C, 0x04, 0x1C, 0x44, 0x2C, - 0xCD, 0xD8, 0xD4, 0x34, 0x0C, 0x5B, 0xB4, 0x1E, - 0x1D, 0xAC, 0x24, 0x18, 0x20, 0x5C, 0xB4, 0x1C, - 0x09, 0x14, 0xFC, 0x0C, 0x10, 0xFC, 0x6C, 0x7C, - 0xB4, 0x1C, 0x15, 0x17, 0xDB, 0x18, 0x21, 0x24, - 0x04, 0x04, 0x44, 0x8C, 0x8C, 0xB7 -}; - -unsigned char linux_logo[] __initdata = { - 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, 0x2C, 0x2C, - 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, 0x2C, 0x95, - 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, 0xD6, 0x2C, - 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, 0x6D, 0xD6, - 0xA1, 0x2C, 0x55, 0x95, 0x2C, 0x2C, 0x55, 0x55, - 0x95, 0xA1, 0xA1, 0xA1, 0x6D, 0xBF, 0x2A, 0x2A, - 0xBF, 0x83, 0xBF, 0x95, 0x90, 0xCB, 0x95, 0xA1, - 0x2C, 0x2C, 0x95, 0x55, 0xCB, 0x90, 0xCB, 0x95, - 0x2C, 0x95, 0xCB, 0x47, 0x94, 0x95, 0xA1, 0xD6, - 0xD6, 0x2C, 0x90, 0x47, 0x70, 0x2C, 0x6D, 0x2A, - 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, 0x2C, 0x95, - 0x55, 0x55, 0xCB, 0x90, 0xCB, 0x55, 0x55, 0xCB, - 0x47, 0xE6, 0x70, 0x95, 0xD6, 0xD6, 0xA1, 0x2C, - 0x55, 0x55, 0x95, 0xD6, 0x6D, 0xD6, 0xA1, 0x2C, - 0x2C, 0x95, 0x55, 0x95, 0x95, 0x95, 0x2C, 0x2C, - 0xA1, 0xA1, 0x2C, 0x2C, 0xA1, 0xD6, 0xD6, 0xD6, - 0xD6, 0xD6, 0x95, 0x47, 0x47, 0x90, 0x2C, 0x2C, - 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0x6D, 0xA1, 0x2C, 0x95, 0x2C, 0xA1, 0xD6, 0xA1, - 0x2C, 0x55, 0x55, 0x95, 0x55, 0x55, 0x55, 0x55, - 0x55, 0x95, 0xD6, 0x6D, 0xBF, 0xD6, 0x55, 0xCB, - 0x55, 0x55, 0x55, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, - 0xA1, 0x95, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x95, - 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, 0xA1, - 0x6D, 0xBF, 0x6D, 0x2C, 0x55, 0x55, 0x95, 0x95, - 0xCB, 0xCB, 0x55, 0x55, 0xCB, 0x55, 0x55, 0x95, - 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xA1, 0x2C, 0x2C, - 0xA1, 0x95, 0xCB, 0xCB, 0x95, 0x95, 0x2C, 0x2C, - 0x2C, 0xA1, 0x2C, 0x2C, 0x2C, 0xA1, 0xA1, 0x2C, - 0x2C, 0x95, 0x55, 0x95, 0x95, 0x2C, 0x2C, 0x2C, - 0x2C, 0xA1, 0x6D, 0xBF, 0x6D, 0xA1, 0x55, 0x55, - 0x95, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x2C, - 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, 0x2C, 0x95, - 0x55, 0x95, 0x2C, 0x2C, 0xA1, 0xA1, 0xD6, 0xD6, - 0x6D, 0x6D, 0xA1, 0x95, 0xCB, 0x55, 0x95, 0x55, - 0x90, 0x70, 0xCB, 0xCB, 0x90, 0xCB, 0x95, 0x95, - 0x2C, 0x2C, 0xA1, 0xD6, 0xA1, 0xA1, 0xA1, 0xA1, - 0xA1, 0xA1, 0x2C, 0x95, 0x95, 0x2C, 0x2C, 0x2C, - 0x2C, 0xA1, 0x2C, 0x95, 0x95, 0x95, 0x2C, 0x2C, - 0x2C, 0x95, 0x55, 0x55, 0x2C, 0x2C, 0xA1, 0xA1, - 0xD6, 0xD6, 0x6D, 0x6D, 0xA1, 0x55, 0xCB, 0x55 -}; - -#endif - -#ifdef INCLUDE_LINUX_LOGOBW - -unsigned char linux_logo_bw[] __initdata = { - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0x00, 0x3F, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F, - 0xFE, 0x1F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFE, 0x3F, 0xFF, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFE, 0x7F, 0xFF, 0xC7, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, 0xFF, 0xC3, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFC, 0xFF, - 0xFB, 0xE3, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFD, 0xFF, 0xFF, 0xE1, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, 0xFF, 0xF1, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xF9, 0xFF, - 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xF9, 0xFF, 0xFF, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xF9, 0xCF, 0xC3, 0xF8, 0xFF, 0xFF, - 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0x88, 0x67, 0x27, 0xa8, 0x9b, 0xbb, 0xbb, 0xbb, - 0xbd, 0xdd, 0xbb, 0xbb, 0x95, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x9b, 0xbb, - 0xbb, 0xbb, 0xbb, 0x96, 0x87, 0x16, 0x68, 0x18, - 0x88, 0x62, 0x31, 0x66, 0x18, 0x88, 0x62, 0x73, - 0x88, 0x63, 0x27, 0x33, 0x65, 0x55, 0x99, 0x9b, - 0xbb, 0xbb, 0xbb, 0x99, 0x55, 0x0a, 0xa1, 0x86, - 0x81, 0x68, 0x88, 0x55, 0x58, 0x85, 0x9b, 0xbb, - 0xbb, 0xbb, 0x95, 0x88, 0x83, 0x66, 0x66, 0x18, - 0x66, 0x82, 0xa1, 0x66, 0x18, 0x88, 0x62, 0x33, - 0x88, 0x81, 0x27, 0x7a, 0x18, 0x58, 0x86, 0x85, - 0x99, 0x99, 0x99, 0x95, 0x53, 0x2a, 0xaa, 0x88, - 0x67, 0x31, 0x68, 0x55, 0x58, 0x85, 0x59, 0xbb, - 0xbb, 0xb9, 0x58, 0x68, 0x83, 0x66, 0x61, 0x16, - 0x66, 0x62, 0x16, 0x66, 0x68, 0x88, 0x62, 0xaa, - 0x88, 0x86, 0x27, 0x77, 0x78, 0x55, 0x88, 0x22, - 0x25, 0x55, 0x95, 0x55, 0x6a, 0xa2, 0x2a, 0x88, - 0x62, 0x27, 0x37, 0x38, 0x88, 0x87, 0x55, 0x59, - 0x95, 0x58, 0x16, 0x88, 0x8a, 0x66, 0x63, 0x68, - 0x86, 0x67, 0x66, 0x66, 0x68, 0x88, 0x12, 0x11, - 0x88, 0x88, 0x72, 0x77, 0x78, 0x85, 0x58, 0x17, - 0x23, 0x32, 0x55, 0x55, 0x81, 0x13, 0x73, 0x66, - 0x62, 0x7a, 0xaa, 0x38, 0x88, 0x58, 0x27, 0x55, - 0x58, 0x32, 0x38, 0x88, 0x81, 0x66, 0xa2, 0x88, - 0x86, 0x61, 0x66, 0x61, 0x66, 0x68, 0x13, 0x11, - 0x88, 0x88, 0x12, 0x22, 0x71, 0x85, 0x58, 0x62, - 0x23, 0xa2, 0x68, 0x88, 0x81, 0x66, 0x88, 0x88, - 0x63, 0x2a, 0xaa, 0x28, 0x88, 0x55, 0x86, 0x61, - 0x66, 0x66, 0x68, 0x88, 0x66, 0x66, 0x77, 0x88, - 0x68, 0x16, 0x66, 0x62, 0x66, 0x68, 0xa1, 0x61, - 0x88, 0x88, 0x62, 0x22, 0x22, 0x85, 0x55, 0x83, - 0x72, 0x37, 0xa8, 0x88, 0x61, 0x66, 0x85, 0x55, - 0x86, 0x23, 0xaa, 0x71, 0x88, 0x85, 0x88, 0x66, - 0x88, 0x86, 0x88, 0x88, 0x16, 0x61, 0x21, 0x88, - 0x66, 0xa6, 0x86, 0x17, 0x66, 0x66, 0x31, 0x61, - 0x88, 0x88, 0x87, 0x72, 0x22, 0x68, 0x55, 0x86, - 0x77, 0x77, 0x36, 0x88, 0x13, 0x68, 0x85, 0x55, - 0x58, 0x12, 0x73, 0x72, 0x76, 0x88, 0x88, 0x68, - 0x88, 0x88, 0x88, 0x66, 0x36, 0x63, 0x26, 0x86, - 0x86, 0x36, 0x86, 0x11, 0x66, 0x66, 0x76, 0x61, - 0x88, 0x88, 0x81, 0x22, 0x22, 0x38, 0x85, 0x58, - 0x37, 0x22, 0x21, 0x68, 0xa2, 0x31, 0x68, 0x55, - 0x55, 0x81, 0x22, 0x22, 0xa8, 0x88, 0x88, 0x68, - 0x86, 0x88, 0x68, 0x81, 0x36, 0x17, 0x21, 0x68, - 0x86, 0x16, 0x66, 0x26, 0x66, 0x61, 0x36, 0x66, - 0x68, 0x88, 0x86, 0x27, 0x22, 0x28, 0x88, 0x88, - 0x17, 0x72, 0x2a, 0x66, 0xa2, 0x22, 0x36, 0x55, - 0x55, 0x58, 0x37, 0x3a, 0x16, 0x66, 0x66, 0x66, - 0x66, 0x18, 0x88, 0x67, 0x16, 0x12, 0x71, 0x68, - 0x81, 0x68, 0x61, 0x76, 0x66, 0x6a, 0x16, 0x66, - 0x88, 0x88, 0x86, 0x77, 0x22, 0x26, 0x88, 0x88, - 0x13, 0x37, 0x71, 0x66, 0xa2, 0x33, 0x2a, 0x85, - 0x55, 0x55, 0x17, 0x73, 0x16, 0x66, 0x66, 0x68, - 0x63, 0x88, 0x88, 0xa2, 0x66, 0xa2, 0xa6, 0x88, - 0x61, 0x68, 0x6a, 0x76, 0x66, 0x6a, 0x66, 0x6a -}; - -#endif diff --git a/include/lxt971a.h b/include/lxt971a.h deleted file mode 100644 index a5dd82b..0000000 --- a/include/lxt971a.h +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*********************************************************************** - * - * Copyright (C) 2004 by FS Forth-Systeme GmbH. - * All rights reserved. - * - * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $ - * @Author: Markus Pietrek - * @References: [1] NS9750 Hardware Reference, December 2003 - * [2] Intel LXT971 Datasheet #249414 Rev. 02 - * [3] NS7520 Linux Ethernet Driver - */ - -#ifndef __LXT971A_H__ -#define __LXT971A_H__ - -/* PHY definitions (LXT971A) [2] */ -#define PHY_LXT971_PORT_CFG (0x10) -#define PHY_LXT971_STAT2 (0x11) -#define PHY_LXT971_INT_ENABLE (0x12) -#define PHY_LXT971_INT_STATUS (0x13) -#define PHY_LXT971_LED_CFG (0x14) -#define PHY_LXT971_DIG_CFG (0x1A) -#define PHY_LXT971_TX_CTRL (0x1E) - -/* PORT_CFG Port Configuration Register Bit Fields */ -#define PHY_LXT971_PORT_CFG_RES1 (0x8000) -#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000) -#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000) -#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000) -#define PHY_LXT971_PORT_CFG_RES2 (0x0800) -#define PHY_LXT971_PORT_CFG_JABBER (0x0400) -#define PHY_LXT971_PORT_CFG_SQE (0x0200) -#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100) -#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080) -#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040) -#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020) -#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018) -#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010) -#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001) -#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000) -#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004) -#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002) -#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001) - -/* STAT2 Status Register #2 Bit Fields */ -#define PHY_LXT971_STAT2_RES1 (0x8000) -#define PHY_LXT971_STAT2_100BTX (0x4000) -#define PHY_LXT971_STAT2_TX_STATUS (0x2000) -#define PHY_LXT971_STAT2_RX_STATUS (0x1000) -#define PHY_LXT971_STAT2_COL_STATUS (0x0800) -#define PHY_LXT971_STAT2_LINK (0x0400) -#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200) -#define PHY_LXT971_STAT2_AUTO_NEG (0x0100) -#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080) -#define PHY_LXT971_STAT2_RES2 (0x0040) -#define PHY_LXT971_STAT2_POLARITY (0x0020) -#define PHY_LXT971_STAT2_PAUSE (0x0010) -#define PHY_LXT971_STAT2_ERROR (0x0008) -#define PHY_LXT971_STAT2_RES3 (0x0007) - -/* INT_ENABLE Interrupt Enable Register Bit Fields */ -#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00) -#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080) -#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040) -#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020) -#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010) -#define PHY_LXT971_INT_ENABLE_RES2 (0x000C) -#define PHY_LXT971_INT_ENABLE_INTEN (0x0002) -#define PHY_LXT971_INT_ENABLE_TINT (0x0001) - -/* INT_STATUS Interrupt Status Register Bit Fields */ -#define PHY_LXT971_INT_STATUS_RES1 (0xFF00) -#define PHY_LXT971_INT_STATUS_ANDONE (0x0080) -#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040) -#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020) -#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010) -#define PHY_LXT971_INT_STATUS_RES2 (0x0008) -#define PHY_LXT971_INT_STATUS_MDINT (0x0004) -#define PHY_LXT971_INT_STATUS_RES3 (0x0003) - -/* LED_CFG Interrupt LED Configuration Register Bit Fields */ -#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C) -#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008) -#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004) -#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C) -#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C) -#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008) -#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004) -#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000) -#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002) -#define PHY_LXT971_LED_CFG_RES1 (0x0001) - -/* only one of these values must be shifted for each SHIFT_LED? */ -#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F) -#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E) -#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D) -#define PHY_LXT971_LED_CFG_LINK_RX (0x000C) -#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B) -#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A) -#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009) -#define PHY_LXT971_LED_CFG_TEST_ON (0x0008) -#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007) -#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006) -#define PHY_LXT971_LED_CFG_DUPLEX (0x0005) -#define PHY_LXT971_LED_CFG_LINK (0x0004) -#define PHY_LXT971_LED_CFG_COLLISION (0x0003) -#define PHY_LXT971_LED_CFG_RECEIVE (0x0002) -#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001) -#define PHY_LXT971_LED_CFG_SPEED (0x0000) - -/* DIG_CFG Digitial Configuration Register Bit Fields */ -#define PHY_LXT971_DIG_CFG_RES1 (0xF000) -#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800) -#define PHY_LXT971_DIG_CFG_RES2 (0x0400) -#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200) -#define PHY_LXT971_DIG_CFG_RES3 (0x01FF) - -#define PHY_LXT971_MDIO_MAX_CLK (8000000) -#define PHY_MDIO_MAX_CLK (2500000) - -/* TX_CTRL Transmit Control Register Bit Fields - documentation is buggy for this register, therefore setting not included */ - -typedef enum -{ - PHY_NONE = 0x0000, /* no PHY detected yet */ - PHY_LXT971A = 0x0013 -} PhyType; - -#endif /* __LXT971A_H__ */ diff --git a/include/mc13783.h b/include/mc13783.h deleted file mode 100644 index c7ee03b..0000000 --- a/include/mc13783.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 - * Helmut Raiger, HALE electronic GmbH, helmut.raiger@hale.at - */ - - -#ifndef __MC13783_H__ -#define __MC13783_H__ - -/* REG_MODE_0 */ -#define VAUDIOEN (1 << 0) -#define VAUDIOSTBY (1 << 1) -#define VAUDIOMODE (1 << 2) -#define VIOHIEN (1 << 3) -#define VIOHISTBY (1 << 4) -#define VIOHIMODE (1 << 5) -#define VIOLOEN (1 << 6) -#define VIOLOSTBY (1 << 7) -#define VIOLOMODE (1 << 8) -#define VDIGEN (1 << 9) -#define VDIGSTBY (1 << 10) -#define VDIGMODE (1 << 11) -#define VGENEN (1 << 12) -#define VGENSTBY (1 << 13) -#define VGENMODE (1 << 14) -#define VRFDIGEN (1 << 15) -#define VRFDIGSTBY (1 << 16) -#define VRFDIGMODE (1 << 17) -#define VRFREFEN (1 << 18) -#define VRFREFSTBY (1 << 19) -#define VRFREFMODE (1 << 20) -#define VRFCPEN (1 << 21) -#define VRFCPSTBY (1 << 22) -#define VRFCPMODE (1 << 23) - -/* REG_MODE_1 */ -#define VSIMEN (1 << 0) -#define VSIMSTBY (1 << 1) -#define VSIMMODE (1 << 2) -#define VESIMEN (1 << 3) -#define VESIMSTBY (1 << 4) -#define VESIMMODE (1 << 5) -#define VCAMEN (1 << 6) -#define VCAMSTBY (1 << 7) -#define VCAMMODE (1 << 8) -#define VRFBGEN (1 << 9) -#define VRFBGSTBY (1 << 10) -#define VVIBEN (1 << 11) -#define VRF1EN (1 << 12) -#define VRF1STBY (1 << 13) -#define VRF1MODE (1 << 14) -#define VRF2EN (1 << 15) -#define VRF2STBY (1 << 16) -#define VRF2MODE (1 << 17) -#define VMMC1EN (1 << 18) -#define VMMC1STBY (1 << 19) -#define VMMC1MODE (1 << 20) -#define VMMC2EN (1 << 21) -#define VMMC2STBY (1 << 22) -#define VMMC2MODE (1 << 23) - -#endif diff --git a/include/mc34704.h b/include/mc34704.h deleted file mode 100644 index b837dda..0000000 --- a/include/mc34704.h +++ /dev/null @@ -1,45 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2012 Freescale Semiconductor, Inc. - */ - -#ifndef __MC34704_H__ -#define __MC34704_H__ - -enum { - MC34704_RESERVED0_REG = 0, /* 0x00 */ - MC34704_GENERAL1_REG, /* 0x01 */ - MC34704_GENERAL2_REG, /* 0x02 */ - MC34704_GENERAL3_REG, /* 0x03 */ - MC34704_RESERVED4_REG, /* 0x04 */ - MC34704_VGSET2_REG, /* 0x05 */ - MC34704_REG2SET1_REG, /* 0x06 */ - MC34704_REG2SET2_REG, /* 0x07 */ - MC34704_REG3SET1_REG, /* 0x08 */ - MC34704_REG3SET2_REG, /* 0x09 */ - MC34704_REG4SET1_REG, /* 0x0a */ - MC34704_REG4SET2_REG, /* 0x0b */ - MC34704_REG5SET1_REG, /* 0x0c */ - MC34704_REG5SET2_REG, /* 0x0d */ - MC34704_REG5SET3_REG, /* 0x0e */ - MC34704_RESERVEDF_REG, /* 0x0f */ - MC34704_RESERVED10_REG, /* 0x10 */ - MC34704_RESERVED11_REG, /* 0x11 */ - MC34704_RESERVED12_REG, /* 0x12 */ - MC34704_FSW2SET_REG, /* 0x13 */ - MC34704_RESERVED14_REG, /* 0x14 */ - MC34704_REG8SET1_REG, /* 0x15 */ - MC34704_REG8SET2_REG, /* 0x16 */ - MC34704_REG8SET3_REG, /* 0x17 */ - MC34704_FAULTS_REG, /* 0x18 */ - MC34704_I2CSET1, /* 0x19 */ - MC34704_NUM_OF_REGS, -}; - -/* GENERAL2 register fields */ -#define ONOFFE (1 << 0) -#define ONOFFD (1 << 1) -#define ONOFFA (1 << 3) -#define ALLOFF (1 << 4) - -#endif /* __MC34704_H__ */ diff --git a/include/mc9sdz60.h b/include/mc9sdz60.h deleted file mode 100644 index ffe376b..0000000 --- a/include/mc9sdz60.h +++ /dev/null @@ -1,66 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2009 Marc Kleine-Budde <mkl@pengutronix.de> - * - * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved. - */ - -#ifndef __ASM_ARCH_MC9SDZ60_H -#define __ASM_ARCH_MC9SDZ60_H - -/** - * Register addresses for the MC9SDZ60 - * - * @note: these match those in the kernel drivers/mxc/mcu_pmic/mc9s08dz60.h - * but not include/linux/mfd/mc9s08dz60/pmic.h - * - */ -enum mc9sdz60_reg { - MC9SDZ60_REG_VERSION = 0x00, - /* reserved 0x01 */ - MC9SDZ60_REG_SECS = 0x02, - MC9SDZ60_REG_MINS = 0x03, - MC9SDZ60_REG_HRS = 0x04, - MC9SDZ60_REG_DAY = 0x05, - MC9SDZ60_REG_DATE = 0x06, - MC9SDZ60_REG_MONTH = 0x07, - MC9SDZ60_REG_YEAR = 0x08, - MC9SDZ60_REG_ALARM_SECS = 0x09, - MC9SDZ60_REG_ALARM_MINS = 0x0a, - MC9SDZ60_REG_ALARM_HRS = 0x0b, - /* reserved 0x0c */ - /* reserved 0x0d */ - MC9SDZ60_REG_TS_CONTROL = 0x0e, - MC9SDZ60_REG_X_LOW = 0x0f, - MC9SDZ60_REG_Y_LOW = 0x10, - MC9SDZ60_REG_XY_HIGH = 0x11, - MC9SDZ60_REG_X_LEFT_LOW = 0x12, - MC9SDZ60_REG_X_LEFT_HIGH = 0x13, - MC9SDZ60_REG_X_RIGHT = 0x14, - MC9SDZ60_REG_Y_TOP_LOW = 0x15, - MC9SDZ60_REG_Y_TOP_HIGH = 0x16, - MC9SDZ60_REG_Y_BOTTOM = 0x17, - /* reserved 0x18 */ - /* reserved 0x19 */ - MC9SDZ60_REG_RESET_1 = 0x1a, - MC9SDZ60_REG_RESET_2 = 0x1b, - MC9SDZ60_REG_POWER_CTL = 0x1c, - MC9SDZ60_REG_DELAY_CONFIG = 0x1d, - /* reserved 0x1e */ - /* reserved 0x1f */ - MC9SDZ60_REG_GPIO_1 = 0x20, - MC9SDZ60_REG_GPIO_2 = 0x21, - MC9SDZ60_REG_KPD_1 = 0x22, - MC9SDZ60_REG_KPD_2 = 0x23, - MC9SDZ60_REG_KPD_CONTROL = 0x24, - MC9SDZ60_REG_INT_ENABLE_1 = 0x25, - MC9SDZ60_REG_INT_ENABLE_2 = 0x26, - MC9SDZ60_REG_INT_FLAG_1 = 0x27, - MC9SDZ60_REG_INT_FLAG_2 = 0x28, - MC9SDZ60_REG_DES_FLAG = 0x29, -}; - -extern u8 mc9sdz60_reg_read(enum mc9sdz60_reg reg); -extern void mc9sdz60_reg_write(enum mc9sdz60_reg reg, u8 val); - -#endif /* __ASM_ARCH_MC9SDZ60_H */ diff --git a/include/mii_phy.h b/include/mii_phy.h deleted file mode 100644 index f0d3e62..0000000 --- a/include/mii_phy.h +++ /dev/null @@ -1,8 +0,0 @@ -#ifndef _MII_PHY_H_ -#define _MII_PHY_H_ - -void mii_discover_phy(void); -unsigned short mii_phy_read(unsigned short reg); -void mii_phy_write(unsigned short reg, unsigned short val); - -#endif diff --git a/include/mk48t59.h b/include/mk48t59.h deleted file mode 100644 index f95d349..0000000 --- a/include/mk48t59.h +++ /dev/null @@ -1,47 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Andreas Heppel <aheppel@sysgo.de> - */ - -/* - * Date & Time support for the MK48T59 RTC - */ - - -#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE) - -#define RTC_PORT_ADDR0 0x70 -#define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1 -#define RTC_PORT_DATA 0x76 - -/* RTC Offsets */ -#define RTC_SECONDS 0x1FF9 -#define RTC_MINUTES 0x1FFA -#define RTC_HOURS 0x1FFB -#define RTC_DAY_OF_WEEK 0x1FFC -#define RTC_DAY_OF_MONTH 0x1FFD -#define RTC_MONTH 0x1FFE -#define RTC_YEAR 0x1FFF - -#define RTC_CONTROLA 0x1FF8 -#define RTC_CA_WRITE 0x80 -#define RTC_CA_READ 0x40 -#define RTC_CA_CALIB_SIGN 0x20 -#define RTC_CA_CALIB_MASK 0x1f - -#define RTC_CONTROLB 0x1FF9 -#define RTC_CB_STOP 0x80 - -#define RTC_WATCHDOG 0x1FF7 -#define RTC_WDS 0x80 -#define RTC_WD_RB_16TH 0x0 -#define RTC_WD_RB_4TH 0x1 -#define RTC_WD_RB_1 0x2 -#define RTC_WD_RB_4 0x3 - -void rtc_set_watchdog(short multi, short res); -void *nvram_read(void *dest, const short src, size_t count); -void nvram_write(short dest, const void *src, size_t count); - -#endif diff --git a/include/mpc106.h b/include/mpc106.h deleted file mode 100644 index 2157b32..0000000 --- a/include/mpc106.h +++ /dev/null @@ -1,140 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Andreas Heppel <aheppel@sysgo.de> - */ - -#ifndef _MPC106_PCI_H -#define _MPC106_PCI_H - -/* - * Defines for the MPC106 PCI Config address and data registers followed by - * defines for the standard PCI device configuration header. - */ -#define PCIDEVID_MPC106 0x0 - -/* - * MPC106 Registers - */ -#define MPC106_REG 0x80000000 - -#ifdef CONFIG_SYS_ADDRESS_MAP_A -#define MPC106_REG_ADDR 0x80000cf8 -#define MPC106_REG_DATA 0x80000cfc -#define MPC106_ISA_IO_PHYS 0x80000000 -#define MPC106_ISA_IO_BUS 0x00000000 -#define MPC106_ISA_IO_SIZE 0x00800000 -#define MPC106_PCI_IO_PHYS 0x81000000 -#define MPC106_PCI_IO_BUS 0x01000000 -#define MPC106_PCI_IO_SIZE 0x3e800000 -#define MPC106_PCI_MEM_PHYS 0xc0000000 -#define MPC106_PCI_MEM_BUS 0x00000000 -#define MPC106_PCI_MEM_SIZE 0x3f000000 -#define MPC106_PCI_MEMORY_PHYS 0x00000000 -#define MPC106_PCI_MEMORY_BUS 0x80000000 -#define MPC106_PCI_MEMORY_SIZE 0x80000000 -#else -#define MPC106_REG_ADDR 0xfec00cf8 -#define MPC106_REG_DATA 0xfee00cfc -#define MPC106_ISA_MEM_PHYS 0xfd000000 -#define MPC106_ISA_MEM_BUS 0x00000000 -#define MPC106_ISA_MEM_SIZE 0x01000000 -#define MPC106_ISA_IO_PHYS 0xfe000000 -#define MPC106_ISA_IO_BUS 0x00000000 -#define MPC106_ISA_IO_SIZE 0x00800000 -#define MPC106_PCI_IO_PHYS 0xfe800000 -#define MPC106_PCI_IO_BUS 0x00800000 -#define MPC106_PCI_IO_SIZE 0x00400000 -#define MPC106_PCI_MEM_PHYS 0x80000000 -#define MPC106_PCI_MEM_BUS 0x80000000 -#define MPC106_PCI_MEM_SIZE 0x7d000000 -#define MPC106_PCI_MEMORY_PHYS 0x00000000 -#define MPC106_PCI_MEMORY_BUS 0x00000000 -#define MPC106_PCI_MEMORY_SIZE 0x40000000 -#endif - -#define CMD_SERR 0x0100 -#define PCI_CMD_MASTER 0x0004 -#define PCI_CMD_MEMEN 0x0002 -#define PCI_CMD_IOEN 0x0001 - -#define PCI_STAT_NO_RSV_BITS 0xffff - -#define PCI_BUSNUM 0x40 -#define PCI_SUBBUSNUM 0x41 -#define PCI_DISCOUNT 0x42 - -#define PCI_PICR1 0xA8 -#define PICR1_CF_CBA(value) ((value & 0xff) << 24) -#define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22) -#define PICR1_PROC_TYPE_603 0x40000 -#define PICR1_PROC_TYPE_604 0x60000 -#define PICR1_MCP_EN 0x800 -#define PICR1_CF_DPARK 0x200 -#define PICR1_CF_LOOP_SNOOP 0x10 -#define PICR1_CF_L2_COPY_BACK 0x2 -#define PICR1_CF_L2_CACHE_MASK 0x3 -#define PICR1_CF_APARK 0x8 -#define PICR1_ADDRESS_MAP 0x10000 -#define PICR1_XIO_MODE 0x80000 -#define PICR1_CF_CACHE_1G 0x200000 - -#define PCI_PICR2 0xAC -#define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18) -#define PICR2_CF_FLUSH_L2 0x10000000 -#define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9) -#define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2) -#define PICR2_CF_INV_MODE 0x00001000 -#define PICR2_CF_MOD_HIGH 0x00020000 -#define PICR2_CF_HIT_HIGH 0x00010000 -#define PICR2_L2_SIZE_256K 0x00000000 -#define PICR2_L2_SIZE_512K 0x00000010 -#define PICR2_L2_SIZE_1MB 0x00000020 -#define PICR2_L2_EN 0x40000000 -#define PICR2_L2_UPDATE_EN 0x80000000 -#define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000 -#define PICR2_CF_FAST_CASTOUT 0x00000080 -#define PICR2_CF_WDATA 0x00000001 -#define PICR2_CF_DATA_RAM_PBURST 0x00400000 - -/* - * Memory controller - */ -#define MPC106_MCCR1 0xF0 -#define MCCR1_TYPE_EDO 0x00020000 -#define MCCR1_BK0_9BITS 0x0 -#define MCCR1_BK0_10BITS 0x1 -#define MCCR1_BK0_11BITS 0x2 -#define MCCR1_BK0_12BITS 0x3 -#define MCCR1_BK1_9BITS 0x0 -#define MCCR1_BK1_10BITS 0x4 -#define MCCR1_BK1_11BITS 0x8 -#define MCCR1_BK1_12BITS 0xC -#define MCCR1_BK2_9BITS 0x00 -#define MCCR1_BK2_10BITS 0x10 -#define MCCR1_BK2_11BITS 0x20 -#define MCCR1_BK2_12BITS 0x30 -#define MCCR1_BK3_9BITS 0x00 -#define MCCR1_BK3_10BITS 0x40 -#define MCCR1_BK3_11BITS 0x80 -#define MCCR1_BK3_12BITS 0xC0 -#define MCCR1_MEMGO 0x00080000 - -#define MPC106_MCCR2 0xF4 -#define MPC106_MCCR3 0xF8 -#define MPC106_MCCR4 0xFC - -#define MPC106_MSAR1 0x80 -#define MPC106_EMSAR1 0x88 -#define MPC106_EMSAR2 0x8C -#define MPC106_MEAR1 0x90 -#define MPC106_EMEAR1 0x98 -#define MPC106_EMEAR2 0x9C - -#define MPC106_MBER 0xA0 -#define MBER_BANK0 0x1 -#define MBER_BANK1 0x2 -#define MBER_BANK2 0x4 -#define MBER_BANK3 0x8 - -#endif diff --git a/include/mpc86xx.h b/include/mpc86xx.h deleted file mode 100644 index ea8d17d..0000000 --- a/include/mpc86xx.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright 2006 Freescale Semiconductor. - * Jeffrey Brown - * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) - */ - -#ifndef __MPC86xx_H__ -#define __MPC86xx_H__ - -#include <asm/fsl_lbc.h> - -#define EXC_OFF_SYS_RESET 0x0100 /* System reset offset */ -#define _START_OFFSET EXC_OFF_SYS_RESET - -/* - * platform register addresses - */ - -#define GUTS_SVR (CFG_SYS_CCSRBAR + 0xE00A4) -#define MCM_ABCR (CFG_SYS_CCSRBAR + 0x01000) -#define MCM_DBCR (CFG_SYS_CCSRBAR + 0x01008) - -/* - * l2cr values. Look in config_<BOARD>.h for the actual setup - */ -#define l2cr 1017 - -#define L2CR_L2E 0x80000000 /* bit 0 - enable */ -#define L2CR_L2PE 0x40000000 /* bit 1 - data parity */ -#define L2CR_L2I 0x00200000 /* bit 10 - global invalidate bit */ -#define L2CR_L2CTL 0x00100000 /* bit 11 - l2 ram control */ -#define L2CR_L2DO 0x00010000 /* bit 15 - data-only mode */ -#define L2CR_REP 0x00001000 /* bit 19 - l2 replacement alg */ -#define L2CR_HWF 0x00000800 /* bit 20 - hardware flush */ -#define L2CR_L2IP 0x00000001 /* global invalidate in progress */ - -#define HID0_XBSEN 0x00000100 -#define HID0_HIGH_BAT_EN 0x00800000 -#define HID0_XAEN 0x00020000 - -#ifndef __ASSEMBLY__ - -typedef struct { - unsigned long freq_processor; - unsigned long freq_systembus; - unsigned long freq_localbus; -} MPC86xx_SYS_INFO; - -#define l1icache_enable icache_enable - -void l2cache_enable(void); -void l1dcache_enable(void); - -static __inline__ unsigned long get_hid0 (void) -{ - unsigned long hid0; - asm volatile("mfspr %0, 1008" : "=r" (hid0) :); - return hid0; -} - -static __inline__ unsigned long get_hid1 (void) -{ - unsigned long hid1; - asm volatile("mfspr %0, 1009" : "=r" (hid1) :); - return hid1; -} - -static __inline__ void set_hid0 (unsigned long hid0) -{ - asm volatile("mtspr 1008, %0" : : "r" (hid0)); -} - -static __inline__ void set_hid1 (unsigned long hid1) -{ - asm volatile("mtspr 1009, %0" : : "r" (hid1)); -} - - -static __inline__ unsigned long get_l2cr (void) -{ - unsigned long l2cr_val; - asm volatile("mfspr %0, 1017" : "=r" (l2cr_val) :); - return l2cr_val; -} - -void setup_ddr_bat(phys_addr_t dram_size); -extern void setup_bats(void); - -#endif /* _ASMLANGUAGE */ -#endif /* __MPC86xx_H__ */ diff --git a/include/mvmfp.h b/include/mvmfp.h deleted file mode 100644 index de86ffd..0000000 --- a/include/mvmfp.h +++ /dev/null @@ -1,99 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2010 - * Marvell Semiconductor <www.marvell.com> - * Written-by: Prafulla Wadaskar <prafulla@marvell.com> - */ - -#ifndef __MVMFP_H -#define __MVMFP_H - -/* - * Header file for MultiFunctionPin (MFP) Configururation framework - * - * Processors Supported: - * 1. Marvell ARMADA100 Processors - * - * processor to be supported should be added here - */ - -/* - * MFP configuration is represented by a 32-bit unsigned integer - */ -#ifdef CONFIG_MVMFP_V2 -#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ - /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ - /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ - /* bit 12..11 - Driver Strength */ (((_drv) & 0x3) << 11) | \ - /* bits 10 - pad driver */ (((_slp) & 0x1) << 10) | \ - /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ - /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ - /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ - /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) -#else -#define MFP(_off, _pull, _drv, _slp, _edge, _sleep, _afn) ( \ - /* bits 31..16 - MFP Register Offset */ (((_off) & 0xffff) << 16) | \ - /* bits 15..13 - Run Mode Pull State */ (((_pull) & 0x7) << 13) | \ - /* bit 12 - Unused */ \ - /* bits 11..10 - Driver Strength */ (((_drv) & 0x3) << 10) | \ - /* bit 09..07 - sleep mode */ (((_sleep) & 0xe) << 6) | \ - /* bits 06..04 - Edge Detection */ (((_edge) & 0x7) << 4) | \ - /* bits 03 - sleep mode */ (((_sleep) & 0x1) << 3) | \ - /* bits 02..00 - Alt-fun select */ ((_afn) & 0x7)) -#endif - -/* - * to facilitate the definition, the following macros are provided - * - * offset, pull,pF, drv,dF, edge,eF ,afn,aF - */ -#define MFP_OFFSET_MASK MFP(0xffff, 0, 0, 0, 0, 0, 0) -#define MFP_REG(x) MFP(x, 0, 0, 0, 0, 0, 0) -#define MFP_REG_GET_OFFSET(x) ((x & MFP_OFFSET_MASK) >> 16) - -#define MFP_AF0 MFP(0x0000, 0, 0, 0, 0, 0, 0) -#define MFP_AF1 MFP(0x0000, 0, 0, 0, 0, 0, 1) -#define MFP_AF2 MFP(0x0000, 0, 0, 0, 0, 0, 2) -#define MFP_AF3 MFP(0x0000, 0, 0, 0, 0, 0, 3) -#define MFP_AF4 MFP(0x0000, 0, 0, 0, 0, 0, 4) -#define MFP_AF5 MFP(0x0000, 0, 0, 0, 0, 0, 5) -#define MFP_AF6 MFP(0x0000, 0, 0, 0, 0, 0, 6) -#define MFP_AF7 MFP(0x0000, 0, 0, 0, 0, 0, 7) -#define MFP_AF_MASK MFP(0x0000, 0, 0, 0, 0, 0, 7) - -#define MFP_SLEEP_CTRL2 MFP(0x0000, 0, 0, 0, 0, 1, 0) -#define MFP_SLEEP_DIR MFP(0x0000, 0, 0, 0, 0, 2, 0) -#define MFP_SLEEP_DATA MFP(0x0000, 0, 0, 0, 0, 4, 0) -#define MFP_SLEEP_CTRL MFP(0x0000, 0, 0, 0, 0, 8, 0) -#define MFP_SLEEP_MASK MFP(0x0000, 0, 0, 0, 0, 0xf, 0) - -#define MFP_LPM_EDGE_NONE MFP(0x0000, 0, 0, 0, 4, 0, 0) -#define MFP_LPM_EDGE_RISE MFP(0x0000, 0, 0, 0, 1, 0, 0) -#define MFP_LPM_EDGE_FALL MFP(0x0000, 0, 0, 0, 2, 0, 0) -#define MFP_LPM_EDGE_BOTH MFP(0x0000, 0, 0, 0, 3, 0, 0) -#define MFP_LPM_EDGE_MASK MFP(0x0000, 0, 0, 0, 7, 0, 0) - -#define MFP_SLP_DI MFP(0x0000, 0, 0, 1, 0, 0, 0) - -#define MFP_DRIVE_VERY_SLOW MFP(0x0000, 0, 0, 0, 0, 0, 0) -#define MFP_DRIVE_SLOW MFP(0x0000, 0, 1, 0, 0, 0, 0) -#define MFP_DRIVE_MEDIUM MFP(0x0000, 0, 2, 0, 0, 0, 0) -#define MFP_DRIVE_FAST MFP(0x0000, 0, 3, 0, 0, 0, 0) -#define MFP_DRIVE_MASK MFP(0x0000, 0, 3, 0, 0, 0, 0) - -#define MFP_PULL_NONE MFP(0x0000, 0, 0, 0, 0, 0, 0) -#define MFP_PULL_LOW MFP(0x0000, 5, 0, 0, 0, 0, 0) -#define MFP_PULL_HIGH MFP(0x0000, 6, 0, 0, 0, 0, 0) -#define MFP_PULL_BOTH MFP(0x0000, 7, 0, 0, 0, 0, 0) -#define MFP_PULL_FLOAT MFP(0x0000, 4, 0, 0, 0, 0, 0) -#define MFP_PULL_MASK MFP(0x0000, 7, 0, 0, 0, 0, 0) - -#define MFP_VALUE_MASK (MFP_PULL_MASK | MFP_DRIVE_MASK | MFP_SLP_DI \ - | MFP_LPM_EDGE_MASK | MFP_SLEEP_MASK \ - | MFP_AF_MASK) -#define MFP_EOC 0xffffffff /* indicates end-of-conf */ - -/* Functions */ -void mfp_config(u32 *mfp_cfgs); - -#endif /* __MVMFP_H */ diff --git a/include/net.h b/include/net.h index 785cb10..e254df7 100644 --- a/include/net.h +++ b/include/net.h @@ -167,6 +167,9 @@ enum eth_recv_flags { * to the network stack. This function should fill in the * eth_pdata::enetaddr field - optional * set_promisc: Enable or Disable promiscuous mode + * get_sset_count: Number of statistics counters + * get_string: Names of the statistic counters + * get_stats: The values of the statistic counters */ struct eth_ops { int (*start)(struct udevice *dev); @@ -178,6 +181,9 @@ struct eth_ops { int (*write_hwaddr)(struct udevice *dev); int (*read_rom_hwaddr)(struct udevice *dev); int (*set_promisc)(struct udevice *dev, bool enable); + int (*get_sset_count)(struct udevice *dev); + void (*get_strings)(struct udevice *dev, u8 *data); + void (*get_stats)(struct udevice *dev, u64 *data); }; #define eth_get_ops(dev) ((struct eth_ops *)(dev)->driver->ops) diff --git a/drivers/mtd/nvmxip/nvmxip.h b/include/nvmxip.h index f4ef377..f4ef377 100644 --- a/drivers/mtd/nvmxip/nvmxip.h +++ b/include/nvmxip.h diff --git a/include/omap3_spi.h b/include/omap3_spi.h index cae3770..5381431 100644 --- a/include/omap3_spi.h +++ b/include/omap3_spi.h @@ -46,6 +46,8 @@ #define OMAP4_MCSPI_REG_OFFSET 0x100 +#define OMAP4_MCSPI_CHAN_NB 4 + /* OMAP3 McSPI registers */ struct mcspi_channel { unsigned int chconf; /* 0x2C, 0x40, 0x54, 0x68 */ @@ -64,7 +66,7 @@ struct mcspi { unsigned int wakeupenable; /* 0x20 */ unsigned int syst; /* 0x24 */ unsigned int modulctrl; /* 0x28 */ - struct mcspi_channel channel[4]; + struct mcspi_channel channel[OMAP4_MCSPI_CHAN_NB]; /* channel0: 0x2C - 0x3C, bus 0 & 1 & 2 & 3 */ /* channel1: 0x40 - 0x50, bus 0 & 1 */ /* channel2: 0x54 - 0x64, bus 0 & 1 */ diff --git a/include/pca9564.h b/include/pca9564.h deleted file mode 100644 index 99e8bcd..0000000 --- a/include/pca9564.h +++ /dev/null @@ -1,35 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * File: include/pca9564.h - * Author: - * - * Created: 2009-06-23 - * Description: PCA9564 i2c bridge driver - * - * Modified: - * Copyright 2009 CJSC "NII STT", http://www.niistt.ru/ - * - * Bugs: - */ - -#ifndef _PCA9564_H -#define _PCA9564_H - -/* Clock speeds for the bus */ -#define PCA_CON_330kHz 0x00 -#define PCA_CON_288kHz 0x01 -#define PCA_CON_217kHz 0x02 -#define PCA_CON_146kHz 0x03 -#define PCA_CON_88kHz 0x04 -#define PCA_CON_59kHz 0x05 -#define PCA_CON_44kHz 0x06 -#define PCA_CON_36kHz 0x07 - -#define PCA_CON_AA 0x80 /* Assert Acknowledge */ -#define PCA_CON_ENSIO 0x40 /* Enable */ -#define PCA_CON_STA 0x20 /* Start */ -#define PCA_CON_STO 0x10 /* Stop */ -#define PCA_CON_SI 0x08 /* Serial Interrupt */ -#define PCA_CON_CR 0x07 /* Clock Rate (MASK) */ - -#endif diff --git a/include/phy.h b/include/phy.h index 247223d..f023a3c 100644 --- a/include/phy.h +++ b/include/phy.h @@ -224,15 +224,6 @@ static inline struct phy_device *fixed_phy_create(ofnode node) #endif /** - * phy_connect_dev() - Associates the given pair of PHY and Ethernet devices - * @phydev: PHY device - * @dev: Ethernet device - * @interface: type of MAC-PHY interface - */ -void phy_connect_dev(struct phy_device *phydev, struct udevice *dev, - phy_interface_t interface); - -/** * phy_connect() - Creates a PHY device for the Ethernet interface * Creates a PHY device for the PHY at the given address, if one doesn't exist * already, and associates it with the Ethernet device. diff --git a/include/power/pmic.h b/include/power/pmic.h index 70f2709..6362216 100644 --- a/include/power/pmic.h +++ b/include/power/pmic.h @@ -86,7 +86,7 @@ struct pmic { #endif /* CONFIG_IS_ENABLED(POWER_LEGACY) */ /* TODO: Change to CONFIG_IS_ENABLED(DM_PMIC) when SPL_DM_PMIC exists */ -#ifdef CONFIG_DM_PMIC +#if defined(CONFIG_DM_PMIC) || !CONFIG_IS_ENABLED(POWER_LEGACY) /** * U-Boot PMIC Framework * ===================== diff --git a/include/sja1000.h b/include/sja1000.h deleted file mode 100644 index 6ceb6f4..0000000 --- a/include/sja1000.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright 2009, Matthias Fuchs <matthias.fuchs@esd.eu> - * - * SJA1000 register layout for basic CAN mode - */ - -#ifndef _SJA1000_H_ -#define _SJA1000_H_ - -/* - * SJA1000 register layout in basic can mode - */ -struct sja1000_basic_s { - u8 cr; - u8 cmr; - u8 sr; - u8 ir; - u8 ac; - u8 am; - u8 btr0; - u8 btr1; - u8 oc; - u8 txb[10]; - u8 rxb[10]; - u8 unused; - u8 cdr; -}; - -/* control register */ -#define CR_RR 0x01 - -/* output control register */ -#define OC_MODE0 0x01 -#define OC_MODE1 0x02 -#define OC_POL0 0x04 -#define OC_TN0 0x08 -#define OC_TP0 0x10 -#define OC_POL1 0x20 -#define OC_TN1 0x40 -#define OC_TP1 0x80 - -#endif diff --git a/include/spl.h b/include/spl.h index 98f5732..658d364 100644 --- a/include/spl.h +++ b/include/spl.h @@ -672,6 +672,9 @@ int spl_load_image_ext(struct spl_image_info *spl_image, int spl_load_image_ext_os(struct spl_image_info *spl_image, struct spl_boot_device *bootdev, struct blk_desc *block_dev, int partition); +int spl_blk_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev, + enum uclass_id uclass_id, int devnum, int partnum); /** * spl_early_init() - Set up device tree and driver model in SPL if enabled diff --git a/include/stdio_dev.h b/include/stdio_dev.h index 3105928..77bf8a8 100644 --- a/include/stdio_dev.h +++ b/include/stdio_dev.h @@ -84,13 +84,6 @@ int stdio_init_tables(void); */ int stdio_add_devices(void); -/** - * stdio_init() - Sets up stdio ready for use - * - * This calls stdio_init_tables() and stdio_add_devices() - */ -int stdio_init(void); - void stdio_print_current_devices(void); /** diff --git a/include/sym53c8xx.h b/include/sym53c8xx.h deleted file mode 100644 index 7628c33..0000000 --- a/include/sym53c8xx.h +++ /dev/null @@ -1,552 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2001 - * Denis Peter, MPL AG Switzerland - * - * Most of these definitions are derived from - * linux/drivers/scsi/sym53c8xx_defs.h - */ - -#ifndef _SYM53C8XX_DEFS_H -#define _SYM53C8XX_DEFS_H - - -#define SCNTL0 0x00 /* full arb., ena parity, par->ATN */ - -#define SCNTL1 0x01 /* no reset */ - #define ISCON 0x10 /* connected to scsi */ - #define CRST 0x08 /* force reset */ - #define IARB 0x02 /* immediate arbitration */ - -#define SCNTL2 0x02 /* no disconnect expected */ - #define SDU 0x80 /* cmd: disconnect will raise error */ - #define CHM 0x40 /* sta: chained mode */ - #define WSS 0x08 /* sta: wide scsi send [W]*/ - #define WSR 0x01 /* sta: wide scsi received [W]*/ - -#define SCNTL3 0x03 /* cnf system clock dependent */ - #define EWS 0x08 /* cmd: enable wide scsi [W]*/ - #define ULTRA 0x80 /* cmd: ULTRA enable */ - /* bits 0-2, 7 rsvd for C1010 */ - -#define SCID 0x04 /* cnf host adapter scsi address */ - #define RRE 0x40 /* r/w:e enable response to resel. */ - #define SRE 0x20 /* r/w:e enable response to select */ - -#define SXFER 0x05 /* ### Sync speed and count */ - /* bits 6-7 rsvd for C1010 */ - -#define SDID 0x06 /* ### Destination-ID */ - -#define GPREG 0x07 /* ??? IO-Pins */ - -#define SFBR 0x08 /* ### First byte in phase */ - -#define SOCL 0x09 - #define CREQ 0x80 /* r/w: SCSI-REQ */ - #define CACK 0x40 /* r/w: SCSI-ACK */ - #define CBSY 0x20 /* r/w: SCSI-BSY */ - #define CSEL 0x10 /* r/w: SCSI-SEL */ - #define CATN 0x08 /* r/w: SCSI-ATN */ - #define CMSG 0x04 /* r/w: SCSI-MSG */ - #define CC_D 0x02 /* r/w: SCSI-C_D */ - #define CI_O 0x01 /* r/w: SCSI-I_O */ - -#define SSID 0x0a - -#define SBCL 0x0b - -#define DSTAT 0x0c - #define DFE 0x80 /* sta: dma fifo empty */ - #define MDPE 0x40 /* int: master data parity error */ - #define BF 0x20 /* int: script: bus fault */ - #define ABRT 0x10 /* int: script: command aborted */ - #define SSI 0x08 /* int: script: single step */ - #define SIR 0x04 /* int: script: interrupt instruct. */ - #define IID 0x01 /* int: script: illegal instruct. */ - -#define SSTAT0 0x0d - #define ILF 0x80 /* sta: data in SIDL register lsb */ - #define ORF 0x40 /* sta: data in SODR register lsb */ - #define OLF 0x20 /* sta: data in SODL register lsb */ - #define AIP 0x10 /* sta: arbitration in progress */ - #define LOA 0x08 /* sta: arbitration lost */ - #define WOA 0x04 /* sta: arbitration won */ - #define IRST 0x02 /* sta: scsi reset signal */ - #define SDP 0x01 /* sta: scsi parity signal */ - -#define SSTAT1 0x0e - #define FF3210 0xf0 /* sta: bytes in the scsi fifo */ - -#define SSTAT2 0x0f - #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/ - #define ORF1 0x40 /* sta: data in SODR register msb[W]*/ - #define OLF1 0x20 /* sta: data in SODL register msb[W]*/ - #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */ - #define LDSC 0x02 /* sta: disconnect & reconnect */ - -#define DSA 0x10 /* --> Base page */ -#define DSA1 0x11 -#define DSA2 0x12 -#define DSA3 0x13 - -#define ISTAT 0x14 /* --> Main Command and status */ - #define CABRT 0x80 /* cmd: abort current operation */ - #define SRST 0x40 /* mod: reset chip */ - #define SIGP 0x20 /* r/w: message from host to ncr */ - #define SEM 0x10 /* r/w: message between host + ncr */ - #define CON 0x08 /* sta: connected to scsi */ - #define INTF 0x04 /* sta: int on the fly (reset by wr)*/ - #define SIP 0x02 /* sta: scsi-interrupt */ - #define DIP 0x01 /* sta: host/script interrupt */ - - -#define CTEST0 0x18 -#define CTEST1 0x19 -#define CTEST2 0x1a - #define CSIGP 0x40 - /* bits 0-2,7 rsvd for C1010 */ - -#define CTEST3 0x1b - #define FLF 0x08 /* cmd: flush dma fifo */ - #define CLF 0x04 /* cmd: clear dma fifo */ - #define FM 0x02 /* mod: fetch pin mode */ - #define WRIE 0x01 /* mod: write and invalidate enable */ - /* bits 4-7 rsvd for C1010 */ - -#define DFIFO 0x20 -#define CTEST4 0x21 - #define BDIS 0x80 /* mod: burst disable */ - #define MPEE 0x08 /* mod: master parity error enable */ - -#define CTEST5 0x22 - #define DFS 0x20 /* mod: dma fifo size */ - /* bits 0-1, 3-7 rsvd for C1010 */ -#define CTEST6 0x23 - -#define DBC 0x24 /* ### Byte count and command */ -#define DNAD 0x28 /* ### Next command register */ -#define DSP 0x2c /* --> Script Pointer */ -#define DSPS 0x30 /* --> Script pointer save/opcode#2 */ - -#define SCRATCHA 0x34 /* Temporary register a */ -#define SCRATCHA1 0x35 -#define SCRATCHA2 0x36 -#define SCRATCHA3 0x37 - -#define DMODE 0x38 - #define BL_2 0x80 /* mod: burst length shift value +2 */ - #define BL_1 0x40 /* mod: burst length shift value +1 */ - #define ERL 0x08 /* mod: enable read line */ - #define ERMP 0x04 /* mod: enable read multiple */ - #define BOF 0x02 /* mod: burst op code fetch */ - #define MAN 0x01 /* mod: manual start */ - -#define DIEN 0x39 -#define SBR 0x3a - -#define DCNTL 0x3b /* --> Script execution control */ - #define CLSE 0x80 /* mod: cache line size enable */ - #define PFF 0x40 /* cmd: pre-fetch flush */ - #define PFEN 0x20 /* mod: pre-fetch enable */ - #define SSM 0x10 /* mod: single step mode */ - #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */ - #define STD 0x04 /* cmd: start dma mode */ - #define IRQD 0x02 /* mod: irq disable */ - #define NOCOM 0x01 /* cmd: protect sfbr while reselect */ - /* bits 0-1 rsvd for C1010 */ - -#define ADDER 0x3c - -#define SIEN 0x40 /* -->: interrupt enable */ -#define SIST 0x42 /* <--: interrupt status */ - #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */ - #define STO 0x0400/* sta: timeout (select) */ - #define GEN 0x0200/* sta: timeout (general) */ - #define HTH 0x0100/* sta: timeout (handshake) */ - #define MA 0x80 /* sta: phase mismatch */ - #define CMP 0x40 /* sta: arbitration complete */ - #define SEL 0x20 /* sta: selected by another device */ - #define RSL 0x10 /* sta: reselected by another device*/ - #define SGE 0x08 /* sta: gross error (over/underflow)*/ - #define UDC 0x04 /* sta: unexpected disconnect */ - #define RST 0x02 /* sta: scsi bus reset detected */ - #define PAR 0x01 /* sta: scsi parity error */ - -#define SLPAR 0x44 -#define SWIDE 0x45 -#define MACNTL 0x46 -#define GPCNTL 0x47 -#define STIME0 0x48 /* cmd: timeout for select&handshake*/ -#define STIME1 0x49 /* cmd: timeout user defined */ -#define RESPID 0x4a /* sta: Reselect-IDs */ - -#define STEST0 0x4c - -#define STEST1 0x4d - #define SCLK 0x80 /* Use the PCI clock as SCSI clock */ - #define DBLEN 0x08 /* clock doubler running */ - #define DBLSEL 0x04 /* clock doubler selected */ - - -#define STEST2 0x4e - #define ROF 0x40 /* reset scsi offset (after gross error!) */ - #define EXT 0x02 /* extended filtering */ - -#define STEST3 0x4f - #define TE 0x80 /* c: tolerAnt enable */ - #define HSC 0x20 /* c: Halt SCSI Clock */ - #define CSF 0x02 /* c: clear scsi fifo */ - -#define SIDL 0x50 /* Lowlevel: latched from scsi data */ -#define STEST4 0x52 - #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */ - #define SMODE_HVD 0x40 /* High Voltage Differential */ - #define SMODE_SE 0x80 /* Single Ended */ - #define SMODE_LVD 0xc0 /* Low Voltage Differential */ - #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */ - /* bits 0-5 rsvd for C1010 */ - -#define SODL 0x54 /* Lowlevel: data out to scsi data */ - -#define SBDL 0x58 /* Lowlevel: data from scsi data */ - - -/*----------------------------------------------------------- -** -** Utility macros for the script. -** -**----------------------------------------------------------- -*/ - -#define REG(r) (r) - -/*----------------------------------------------------------- -** -** SCSI phases -** -** DT phases illegal for ncr driver. -** -**----------------------------------------------------------- -*/ - -#define SCR_DATA_OUT 0x00000000 -#define SCR_DATA_IN 0x01000000 -#define SCR_COMMAND 0x02000000 -#define SCR_STATUS 0x03000000 -#define SCR_DT_DATA_OUT 0x04000000 -#define SCR_DT_DATA_IN 0x05000000 -#define SCR_MSG_OUT 0x06000000 -#define SCR_MSG_IN 0x07000000 - -#define SCR_ILG_OUT 0x04000000 -#define SCR_ILG_IN 0x05000000 - -/*----------------------------------------------------------- -** -** Data transfer via SCSI. -** -**----------------------------------------------------------- -** -** MOVE_ABS (LEN) -** <<start address>> -** -** MOVE_IND (LEN) -** <<dnad_offset>> -** -** MOVE_TBL -** <<dnad_offset>> -** -**----------------------------------------------------------- -*/ - -#define OPC_MOVE 0x08000000 - -#define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l)) -#define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l)) -#define SCR_MOVE_TBL (0x10000000 | OPC_MOVE) - -#define SCR_CHMOV_ABS(l) ((0x00000000) | (l)) -#define SCR_CHMOV_IND(l) ((0x20000000) | (l)) -#define SCR_CHMOV_TBL (0x10000000) - - -/*----------------------------------------------------------- -** -** Selection -** -**----------------------------------------------------------- -** -** SEL_ABS | SCR_ID (0..15) [ | REL_JMP] -** <<alternate_address>> -** -** SEL_TBL | << dnad_offset>> [ | REL_JMP] -** <<alternate_address>> -** -**----------------------------------------------------------- -*/ - -#define SCR_SEL_ABS 0x40000000 -#define SCR_SEL_ABS_ATN 0x41000000 -#define SCR_SEL_TBL 0x42000000 -#define SCR_SEL_TBL_ATN 0x43000000 - - -#define SCR_JMP_REL 0x04000000 -#define SCR_ID(id) (((unsigned long)(id)) << 16) - -/*----------------------------------------------------------- -** -** Waiting for Disconnect or Reselect -** -**----------------------------------------------------------- -** -** WAIT_DISC -** dummy: <<alternate_address>> -** -** WAIT_RESEL -** <<alternate_address>> -** -**----------------------------------------------------------- -*/ - -#define SCR_WAIT_DISC 0x48000000 -#define SCR_WAIT_RESEL 0x50000000 - -/*----------------------------------------------------------- -** -** Bit Set / Reset -** -**----------------------------------------------------------- -** -** SET (flags {|.. }) -** -** CLR (flags {|.. }) -** -**----------------------------------------------------------- -*/ - -#define SCR_SET(f) (0x58000000 | (f)) -#define SCR_CLR(f) (0x60000000 | (f)) - -#define SCR_CARRY 0x00000400 -#define SCR_TRG 0x00000200 -#define SCR_ACK 0x00000040 -#define SCR_ATN 0x00000008 - - -/*----------------------------------------------------------- -** -** Memory to memory move -** -**----------------------------------------------------------- -** -** COPY (bytecount) -** << source_address >> -** << destination_address >> -** -** SCR_COPY sets the NO FLUSH option by default. -** SCR_COPY_F does not set this option. -** -** For chips which do not support this option, -** ncr_copy_and_bind() will remove this bit. -**----------------------------------------------------------- -*/ - -#define SCR_NO_FLUSH 0x01000000 - -#define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n)) -#define SCR_COPY_F(n) (0xc0000000 | (n)) - -/*----------------------------------------------------------- -** -** Register move and binary operations -** -**----------------------------------------------------------- -** -** SFBR_REG (reg, op, data) reg = SFBR op data -** << 0 >> -** -** REG_SFBR (reg, op, data) SFBR = reg op data -** << 0 >> -** -** REG_REG (reg, op, data) reg = reg op data -** << 0 >> -** -**----------------------------------------------------------- -** On 810A, 860, 825A, 875, 895 and 896 chips the content -** of SFBR register can be used as data (SCR_SFBR_DATA). -** The 896 has additionnal IO registers starting at -** offset 0x80. Bit 7 of register offset is stored in -** bit 7 of the SCRIPTS instruction first DWORD. -**----------------------------------------------------------- -*/ - -#define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul)) /* + ((ofs) & 0x80)) */ - -#define SCR_SFBR_REG(reg,op,data) \ - (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - -#define SCR_REG_SFBR(reg,op,data) \ - (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - -#define SCR_REG_REG(reg,op,data) \ - (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul)) - - -#define SCR_LOAD 0x00000000 -#define SCR_SHL 0x01000000 -#define SCR_OR 0x02000000 -#define SCR_XOR 0x03000000 -#define SCR_AND 0x04000000 -#define SCR_SHR 0x05000000 -#define SCR_ADD 0x06000000 -#define SCR_ADDC 0x07000000 - -#define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */ - -/*----------------------------------------------------------- -** -** FROM_REG (reg) SFBR = reg -** << 0 >> -** -** TO_REG (reg) reg = SFBR -** << 0 >> -** -** LOAD_REG (reg, data) reg = <data> -** << 0 >> -** -** LOAD_SFBR(data) SFBR = <data> -** << 0 >> -** -**----------------------------------------------------------- -*/ - -#define SCR_FROM_REG(reg) \ - SCR_REG_SFBR(reg,SCR_OR,0) - -#define SCR_TO_REG(reg) \ - SCR_SFBR_REG(reg,SCR_OR,0) - -#define SCR_LOAD_REG(reg,data) \ - SCR_REG_REG(reg,SCR_LOAD,data) - -#define SCR_LOAD_SFBR(data) \ - (SCR_REG_SFBR (gpreg, SCR_LOAD, data)) - -/*----------------------------------------------------------- -** -** LOAD from memory to register. -** STORE from register to memory. -** -** Only supported by 810A, 860, 825A, 875, 895 and 896. -** -**----------------------------------------------------------- -** -** LOAD_ABS (LEN) -** <<start address>> -** -** LOAD_REL (LEN) (DSA relative) -** <<dsa_offset>> -** -**----------------------------------------------------------- -*/ - -#define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul) -#define SCR_NO_FLUSH2 0x02000000 -#define SCR_DSA_REL2 0x10000000 - -#define SCR_LOAD_R(reg, how, n) \ - (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) - -#define SCR_STORE_R(reg, how, n) \ - (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n)) - -#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n) -#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n) -#define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n) -#define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n) - -#define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n) -#define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n) -#define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n) -#define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n) - - -/*----------------------------------------------------------- -** -** Waiting for Disconnect or Reselect -** -**----------------------------------------------------------- -** -** JUMP [ | IFTRUE/IFFALSE ( ... ) ] -** <<address>> -** -** JUMPR [ | IFTRUE/IFFALSE ( ... ) ] -** <<distance>> -** -** CALL [ | IFTRUE/IFFALSE ( ... ) ] -** <<address>> -** -** CALLR [ | IFTRUE/IFFALSE ( ... ) ] -** <<distance>> -** -** RETURN [ | IFTRUE/IFFALSE ( ... ) ] -** <<dummy>> -** -** INT [ | IFTRUE/IFFALSE ( ... ) ] -** <<ident>> -** -** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ] -** <<ident>> -** -** Conditions: -** WHEN (phase) -** IF (phase) -** CARRYSET -** DATA (data, mask) -** -**----------------------------------------------------------- -*/ - -#define SCR_NO_OP 0x80000000 -#define SCR_JUMP 0x80080000 -#define SCR_JUMP64 0x80480000 -#define SCR_JUMPR 0x80880000 -#define SCR_CALL 0x88080000 -#define SCR_CALLR 0x88880000 -#define SCR_RETURN 0x90080000 -#define SCR_INT 0x98080000 -#define SCR_INT_FLY 0x98180000 - -#define IFFALSE(arg) (0x00080000 | (arg)) -#define IFTRUE(arg) (0x00000000 | (arg)) - -#define WHEN(phase) (0x00030000 | (phase)) -#define IF(phase) (0x00020000 | (phase)) - -#define DATA(D) (0x00040000 | ((D) & 0xff)) -#define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff)) - -#define CARRYSET (0x00200000) - - -#define SIR_COMPLETE 0x10000000 -/* script errors */ -#define SIR_SEL_ATN_NO_MSG_OUT 0x00000001 -#define SIR_CMD_OUT_ILL_PH 0x00000002 -#define SIR_STATUS_ILL_PH 0x00000003 -#define SIR_MSG_RECEIVED 0x00000004 -#define SIR_DATA_IN_ERR 0x00000005 -#define SIR_DATA_OUT_ERR 0x00000006 -#define SIR_SCRIPT_ERROR 0x00000007 -#define SIR_MSG_OUT_NO_CMD 0x00000008 -#define SIR_MSG_OVER7 0x00000009 -/* Fly interrupt */ -#define INT_ON_FY 0x00000080 - -/* Hardware errors are defined in scsi.h */ - -#define SCSI_IDENTIFY 0xC0 - -#endif diff --git a/include/synopsys/dwcddr21mctl.h b/include/synopsys/dwcddr21mctl.h deleted file mode 100644 index 6bb5cff..0000000 --- a/include/synopsys/dwcddr21mctl.h +++ /dev/null @@ -1,324 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2011 Andes Technology Corp - * Macpaul Lin <macpaul@andestech.com> - */ - -/* - * DWCDDR21MCTL - Synopsys DWC DDR2/DDR1 Memory Controller - */ -#ifndef __DWCDDR21MCTL_H -#define __DWCDDR21MCTL_H - -#ifndef __ASSEMBLY__ -struct dwcddr21mctl { - unsigned int ccr; /* Controller Configuration */ - unsigned int dcr; /* DRAM Configuration */ - unsigned int iocr; /* I/O Configuration */ - unsigned int csr; /* Controller Status */ - unsigned int drr; /* DRAM refresh */ - unsigned int tpr0; /* SDRAM Timing Parameters 0 */ - unsigned int tpr1; /* SDRAM Timing Parameters 1 */ - unsigned int tpr2; /* SDRAM Timing Parameters 2 */ - unsigned int gdllcr; /* Global DLL Control */ - unsigned int dllcr[10]; /* DLL Control */ - unsigned int rslr[4]; /* Rank System Lantency */ - unsigned int rdgr[4]; /* Rank DQS Gating */ - unsigned int dqtr[9]; /* DQ Timing */ - unsigned int dqstr; /* DQS Timing */ - unsigned int dqsbtr; /* DQS_b Timing */ - unsigned int odtcr; /* ODT Configuration */ - unsigned int dtr[2]; /* Data Training */ - unsigned int dtar; /* Data Training Address */ - unsigned int rsved[82]; /* Reserved */ - unsigned int mr; /* Mode Register */ - unsigned int emr; /* Extended Mode Register */ - unsigned int emr2; /* Extended Mode Register 2 */ - unsigned int emr3; /* Extended Mode Register 3 */ - unsigned int hpcr[32]; /* Host Port Configurarion */ - unsigned int pqcr[8]; /* Priority Queue Configuration */ - unsigned int mmgcr; /* Memory Manager General Config */ -}; -#endif /* __ASSEMBLY__ */ - -/* - * Control Configuration Register - */ -#define DWCDDR21MCTL_CCR_ECCEN(x) ((x) << 0) -#define DWCDDR21MCTL_CCR_NOMRWR(x) ((x) << 1) -#define DWCDDR21MCTL_CCR_HOSTEN(x) ((x) << 2) -#define DWCDDR21MCTL_CCR_XBISC(x) ((x) << 3) -#define DWCDDR21MCTL_CCR_NOAPD(x) ((x) << 4) -#define DWCDDR21MCTL_CCR_RRB(x) ((x) << 13) -#define DWCDDR21MCTL_CCR_DQSCFG(x) ((x) << 14) -#define DWCDDR21MCTL_CCR_DFTLM(x) (((x) & 0x3) << 15) -#define DWCDDR21MCTL_CCR_DFTCMP(x) ((x) << 17) -#define DWCDDR21MCTL_CCR_FLUSH(x) ((x) << 27) -#define DWCDDR21MCTL_CCR_ITMRST(x) ((x) << 28) -#define DWCDDR21MCTL_CCR_IB(x) ((x) << 29) -#define DWCDDR21MCTL_CCR_DTT(x) ((x) << 30) -#define DWCDDR21MCTL_CCR_IT(x) ((x) << 31) - -/* - * DRAM Configuration Register - */ -#define DWCDDR21MCTL_DCR_DDRMD(x) ((x) << 0) -#define DWCDDR21MCTL_DCR_DIO(x) (((x) & 0x3) << 1) -#define DWCDDR21MCTL_DCR_DSIZE(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DCR_SIO(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DCR_PIO(x) ((x) << 9) -#define DWCDDR21MCTL_DCR_RANKS(x) (((x) & 0x3) << 10) -#define DWCDDR21MCTL_DCR_RNKALL(x) ((x) << 12) -#define DWCDDR21MCTL_DCR_AMAP(x) (((x) & 0x3) << 13) -#define DWCDDR21MCTL_DCR_RANK(x) (((x) & 0x3) << 25) -#define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27) -#define DWCDDR21MCTL_DCR_EXE(x) ((x) << 31) - -/* - * I/O Configuration Register - */ -#define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4) -#define DWCDDR21MCTL_IOCR_TESTEN(x) ((x) << 0x8) -#define DWCDDR21MCTL_IOCR_RTTOH(x) (((x) & 0x7) << 26) -#define DWCDDR21MCTL_IOCR_RTTOE(x) ((x) << 29) -#define DWCDDR21MCTL_IOCR_DQRTT(x) ((x) << 30) -#define DWCDDR21MCTL_IOCR_DQSRTT(x) ((x) << 31) - -/* - * Controller Status Register - */ -#define DWCDDR21MCTL_CSR_DRIFT(x) (((x) & 0x3ff) << 0) -#define DWCDDR21MCTL_CSR_DFTERR(x) ((x) << 18) -#define DWCDDR21MCTL_CSR_ECCERR(x) ((x) << 19) -#define DWCDDR21MCTL_CSR_DTERR(x) ((x) << 20) -#define DWCDDR21MCTL_CSR_DTIERR(x) ((x) << 21) -#define DWCDDR21MCTL_CSR_ECCSEC(x) ((x) << 22) - -/* - * DRAM Refresh Register - */ -#define DWCDDR21MCTL_DRR_TRFC(x) (((x) & 0xff) << 0) -#define DWCDDR21MCTL_DRR_TRFPRD(x) (((x) & 0xffff) << 8) -#define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24) -#define DWCDDR21MCTL_DRR_RD(x) ((x) << 31) - -/* - * SDRAM Timing Parameters Register 0 - */ -#define DWCDDR21MCTL_TPR0_TMRD(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_TPR0_TRTP(x) (((x) & 0x7) << 2) -#define DWCDDR21MCTL_TPR0_TWTR(x) (((x) & 0x7) << 5) -#define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8) -#define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12) -#define DWCDDR21MCTL_TPR0_TRAS(x) (((x) & 0x1f) << 16) -#define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21) -#define DWCDDR21MCTL_TPR0_TRC(x) (((x) & 0x3f) << 25) -#define DWCDDR21MCTL_TPR0_TCCD(x) ((x) << 31) - -/* - * SDRAM Timing Parameters Register 1 - */ -#define DWCDDR21MCTL_TPR1_TAOND(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_TPR1_TRTW(x) ((x) << 2) -#define DWCDDR21MCTL_TPR1_TFAW(x) (((x) & 0x3f) << 3) -#define DWCDDR21MCTL_TPR1_TRNKRTR(x) (((x) & 0x3) << 12) -#define DWCDDR21MCTL_TPR1_TRNKWTW(x) (((x) & 0x3) << 14) -#define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23) -#define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27) -#define DWCDDR21MCTL_TPR1_XTP(x) ((x) << 31) - -/* - * SDRAM Timing Parameters Register 2 - */ -#define DWCDDR21MCTL_TPR2_TXS(x) (((x) & 0x3ff) << 0) -#define DWCDDR21MCTL_TPR2_TXP(x) (((x) & 0x1f) << 10) -#define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15) - -/* - * Global DLL Control Register - */ -#define DWCDDR21MCTL_GDLLCR_DRES(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_GDLLCR_IPUMP(x) (((x) & 0x7) << 2) -#define DWCDDR21MCTL_GDLLCR_TESTEN(x) ((x) << 5) -#define DWCDDR21MCTL_GDLLCR_DTC(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_GDLLCR_ATC(x) (((x) & 0x3) << 9) -#define DWCDDR21MCTL_GDLLCR_TESTSW(x) ((x) << 11) -#define DWCDDR21MCTL_GDLLCR_MBIAS(x) (((x) & 0xff) << 12) -#define DWCDDR21MCTL_GDLLCR_SBIAS(x) (((x) & 0xff) << 20) -#define DWCDDR21MCTL_GDLLCR_LOCKDET(x) ((x) << 29) - -/* - * DLL Control Register 0-9 - */ -#define DWCDDR21MCTL_DLLCR_SFBDLY(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_DLLCR_SFWDLY(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DLLCR_MFBDLY(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DLLCR_MFWDLY(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_DLLCR_SSTART(x) (((x) & 0x3) << 12) -#define DWCDDR21MCTL_DLLCR_PHASE(x) (((x) & 0xf) << 14) -#define DWCDDR21MCTL_DLLCR_ATESTEN(x) ((x) << 18) -#define DWCDDR21MCTL_DLLCR_DRSVD(x) ((x) << 19) -#define DWCDDR21MCTL_DLLCR_DD(x) ((x) << 31) - -/* - * Rank System Lantency Register - */ -#define DWCDDR21MCTL_RSLR_SL0(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_RSLR_SL1(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_RSLR_SL2(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_RSLR_SL3(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_RSLR_SL4(x) (((x) & 0x7) << 12) -#define DWCDDR21MCTL_RSLR_SL5(x) (((x) & 0x7) << 15) -#define DWCDDR21MCTL_RSLR_SL6(x) (((x) & 0x7) << 18) -#define DWCDDR21MCTL_RSLR_SL7(x) (((x) & 0x7) << 21) -#define DWCDDR21MCTL_RSLR_SL8(x) (((x) & 0x7) << 24) - -/* - * Rank DQS Gating Register - */ -#define DWCDDR21MCTL_RDGR_DQSSEL0(x) (((x) & 0x3) << 0) -#define DWCDDR21MCTL_RDGR_DQSSEL1(x) (((x) & 0x3) << 2) -#define DWCDDR21MCTL_RDGR_DQSSEL2(x) (((x) & 0x3) << 4) -#define DWCDDR21MCTL_RDGR_DQSSEL3(x) (((x) & 0x3) << 6) -#define DWCDDR21MCTL_RDGR_DQSSEL4(x) (((x) & 0x3) << 8) -#define DWCDDR21MCTL_RDGR_DQSSEL5(x) (((x) & 0x3) << 10) -#define DWCDDR21MCTL_RDGR_DQSSEL6(x) (((x) & 0x3) << 12) -#define DWCDDR21MCTL_RDGR_DQSSEL7(x) (((x) & 0x3) << 14) -#define DWCDDR21MCTL_RDGR_DQSSEL8(x) (((x) & 0x3) << 16) - -/* - * DQ Timing Register - */ -#define DWCDDR21MCTL_DQTR_DQDLY0(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_DQTR_DQDLY1(x) (((x) & 0xf) << 4) -#define DWCDDR21MCTL_DQTR_DQDLY2(x) (((x) & 0xf) << 8) -#define DWCDDR21MCTL_DQTR_DQDLY3(x) (((x) & 0xf) << 12) -#define DWCDDR21MCTL_DQTR_DQDLY4(x) (((x) & 0xf) << 16) -#define DWCDDR21MCTL_DQTR_DQDLY5(x) (((x) & 0xf) << 20) -#define DWCDDR21MCTL_DQTR_DQDLY6(x) (((x) & 0xf) << 24) -#define DWCDDR21MCTL_DQTR_DQDLY7(x) (((x) & 0xf) << 28) - -/* - * DQS Timing Register - */ -#define DWCDDR21MCTL_DQSTR_DQSDLY0(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_DQSTR_DQSDLY1(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DQSTR_DQSDLY2(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DQSTR_DQSDLY3(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_DQSTR_DQSDLY4(x) (((x) & 0x7) << 12) -#define DWCDDR21MCTL_DQSTR_DQSDLY5(x) (((x) & 0x7) << 15) -#define DWCDDR21MCTL_DQSTR_DQSDLY6(x) (((x) & 0x7) << 18) -#define DWCDDR21MCTL_DQSTR_DQSDLY7(x) (((x) & 0x7) << 21) -#define DWCDDR21MCTL_DQSTR_DQSDLY8(x) (((x) & 0x7) << 24) - -/* - * DQS_b (DQSBTR) Timing Register - */ -#define DWCDDR21MCTL_DQSBTR_DQSDLY0(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_DQSBTR_DQSDLY1(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_DQSBTR_DQSDLY2(x) (((x) & 0x7) << 6) -#define DWCDDR21MCTL_DQSBTR_DQSDLY3(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_DQSBTR_DQSDLY4(x) (((x) & 0x7) << 12) -#define DWCDDR21MCTL_DQSBTR_DQSDLY5(x) (((x) & 0x7) << 15) -#define DWCDDR21MCTL_DQSBTR_DQSDLY6(x) (((x) & 0x7) << 18) -#define DWCDDR21MCTL_DQSBTR_DQSDLY7(x) (((x) & 0x7) << 21) -#define DWCDDR21MCTL_DQSBTR_DQSDLY8(x) (((x) & 0x7) << 24) - -/* - * ODT Configuration Register - */ -#define DWCDDR21MCTL_ODTCR_RDODT0(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_ODTCR_RDODT1(x) (((x) & 0xf) << 4) -#define DWCDDR21MCTL_ODTCR_RDODT2(x) (((x) & 0xf) << 8) -#define DWCDDR21MCTL_ODTCR_RDODT3(x) (((x) & 0xf) << 12) -#define DWCDDR21MCTL_ODTCR_WDODT0(x) (((x) & 0xf) << 16) -#define DWCDDR21MCTL_ODTCR_WDODT1(x) (((x) & 0xf) << 20) -#define DWCDDR21MCTL_ODTCR_WDODT2(x) (((x) & 0xf) << 24) -#define DWCDDR21MCTL_ODTCR_WDODT3(x) (((x) & 0xf) << 28) - -/* - * Data Training Register - */ -#define DWCDDR21MCTL_DTR0_DTBYTE0(x) (((x) & 0xff) << 0) /* def: 0x11 */ -#define DWCDDR21MCTL_DTR0_DTBYTE1(x) (((x) & 0xff) << 8) /* def: 0xee */ -#define DWCDDR21MCTL_DTR0_DTBYTE2(x) (((x) & 0xff) << 16) /* def: 0x22 */ -#define DWCDDR21MCTL_DTR0_DTBYTE3(x) (((x) & 0xff) << 24) /* def: 0xdd */ - -#define DWCDDR21MCTL_DTR1_DTBYTE4(x) (((x) & 0xff) << 0) /* def: 0x44 */ -#define DWCDDR21MCTL_DTR1_DTBYTE5(x) (((x) & 0xff) << 8) /* def: 0xbb */ -#define DWCDDR21MCTL_DTR1_DTBYTE6(x) (((x) & 0xff) << 16) /* def: 0x88 */ -#define DWCDDR21MCTL_DTR1_DTBYTE7(x) (((x) & 0xff) << 24) /* def: 0x77 */ - -/* - * Data Training Address Register - */ -#define DWCDDR21MCTL_DTAR_DTCOL(x) (((x) & 0xfff) << 0) -#define DWCDDR21MCTL_DTAR_DTROW(x) (((x) & 0xffff) << 12) -#define DWCDDR21MCTL_DTAR_DTBANK(x) (((x) & 0x7) << 28) - -/* - * Mode Register - */ -#define DWCDDR21MCTL_MR_BL(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_MR_BT(x) ((x) << 3) -#define DWCDDR21MCTL_MR_CL(x) (((x) & 0x7) << 4) -#define DWCDDR21MCTL_MR_TM(x) ((x) << 7) -#define DWCDDR21MCTL_MR_DR(x) ((x) << 8) -#define DWCDDR21MCTL_MR_WR(x) (((x) & 0x7) << 9) -#define DWCDDR21MCTL_MR_PD(x) ((x) << 12) - -/* - * Extended Mode register - */ -#define DWCDDR21MCTL_EMR_DE(x) ((x) << 0) -#define DWCDDR21MCTL_EMR_ODS(x) ((x) << 1) -#define DWCDDR21MCTL_EMR_RTT2(x) ((x) << 2) -#define DWCDDR21MCTL_EMR_AL(x) (((x) & 0x7) << 3) -#define DWCDDR21MCTL_EMR_RTT6(x) ((x) << 6) -#define DWCDDR21MCTL_EMR_OCD(x) (((x) & 0x7) << 7) -#define DWCDDR21MCTL_EMR_DQS(x) ((x) << 10) -#define DWCDDR21MCTL_EMR_RDQS(x) ((x) << 11) -#define DWCDDR21MCTL_EMR_OE(x) ((x) << 12) - -#define EMR_RTT2(x) DWCDDR21MCTL_EMR_RTT2(x) -#define EMR_RTT6(x) DWCDDR21MCTL_EMR_RTT6(x) - -#define DWCDDR21MCTL_EMR_RTT_DISABLED (EMR_RTT6(0) | EMR_RTT2(0)) -#define DWCDDR21MCTL_EMR_RTT_75 (EMR_RTT6(0) | EMR_RTT2(1)) -#define DWCDDR21MCTL_EMR_RTT_150 (EMR_RTT6(1) | EMR_RTT2(0)) -#define DWCDDR21MCTL_EMR_RTT_50 (EMR_RTT6(1) | EMR_RTT2(1)) - -/* - * Extended Mode register 2 - */ -#define DWCDDR21MCTL_EMR2_PASR(x) (((x) & 0x7) << 0) -#define DWCDDR21MCTL_EMR2_DCC(x) ((x) << 3) -#define DWCDDR21MCTL_EMR2_SRF(x) ((x) << 7) - -/* - * Extended Mode register 3: [15:0] reserved for JEDEC. - */ - -/* - * Host port Configuration register 0-31 - */ -#define DWCDDR21MCTL_HPCR_HPBL(x) (((x) & 0xf) << 0) - -/* - * Priority Queue Configuration register 0-7 - */ -#define DWCDDR21MCTL_HPCR_TOUT(x) (((x) & 0xf) << 0) -#define DWCDDR21MCTL_HPCR_TOUTX(x) (((x) & 0x3) << 8) -#define DWCDDR21MCTL_HPCR_LPQS(x) (((x) & 0x3) << 10) -#define DWCDDR21MCTL_HPCR_PQBL(x) (((x) & 0xff) << 12) -#define DWCDDR21MCTL_HPCR_SWAIT(x) (((x) & 0x1f) << 20) -#define DWCDDR21MCTL_HPCR_INTRPT(x) (((x) & 0x7) << 25) -#define DWCDDR21MCTL_HPCR_APQS(x) ((x) << 28) - -/* - * Memory Manager General Configuration register - */ -#define DWCDDR21MCTL_MMGCR_UHPP(x) (((x) & 0x3) << 0) - -#endif /* __DWCDDR21MCTL_H */ diff --git a/include/test/suites.h b/include/test/suites.h index 7349ce5..1c7dc65 100644 --- a/include/test/suites.h +++ b/include/test/suites.h @@ -28,6 +28,7 @@ int cmd_ut_category(const char *name, const char *prefix, int do_ut_addrmap(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); +int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_bootm(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); int do_ut_bootstd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]); diff --git a/include/version_string.h b/include/version_string.h index a89a6e4..a7d07e4 100644 --- a/include/version_string.h +++ b/include/version_string.h @@ -4,5 +4,7 @@ #define __VERSION_STRING_H__ extern const char version_string[]; +extern const unsigned short version_num; +extern const unsigned char version_num_patch; #endif /* __VERSION_STRING_H__ */ diff --git a/include/video.h b/include/video.h index 29c4f51..03434a8 100644 --- a/include/video.h +++ b/include/video.h @@ -64,6 +64,7 @@ enum video_log2_bpp { enum video_format { VIDEO_UNKNOWN, + VIDEO_RGBA8888, VIDEO_X8B8G8R8, VIDEO_X8R8G8B8, VIDEO_X2R10G10B10, diff --git a/include/video_easylogo.h b/include/video_easylogo.h deleted file mode 100644 index ce93868..0000000 --- a/include/video_easylogo.h +++ /dev/null @@ -1,26 +0,0 @@ -/* -** video easylogo -** ============== -** (C) 2000 by Paolo Scaffardi (arsenio@tin.it) -** AIRVENT SAM s.p.a - RIMINI(ITALY) -** -** This utility is still under construction! -*/ - -#ifndef _EASYLOGO_H_ -#define _EASYLOGO_H_ - -#if 0 -#define ENABLE_ASCII_BANNERS -#endif - -typedef struct { - unsigned char *data; - int width; - int height; - int bpp; - int pixel_size; - int size; -} fastimage_t ; - -#endif /* _EASYLOGO_H_ */ diff --git a/include/zynqmp_firmware.h b/include/zynqmp_firmware.h index f7a4a39..1192d59 100644 --- a/include/zynqmp_firmware.h +++ b/include/zynqmp_firmware.h @@ -35,7 +35,7 @@ enum pm_api_id { PM_FPGA_LOAD = 22, PM_FPGA_GET_STATUS = 23, PM_GET_CHIPID = 24, - /* ID 25 is been used by U-boot to process secure boot images */ + /* ID 25 is been used by U-Boot to process secure boot images */ /* Secure library generic API functions */ PM_SECURE_SHA = 26, PM_SECURE_RSA = 27, diff --git a/lib/acpi/acpi_table.c b/lib/acpi/acpi_table.c index 7c4189e..a8d4b47 100644 --- a/lib/acpi/acpi_table.c +++ b/lib/acpi/acpi_table.c @@ -11,8 +11,7 @@ #include <log.h> #include <mapmem.h> #include <tables_csum.h> -#include <timestamp.h> -#include <version.h> +#include <version_string.h> #include <acpi/acpi_table.h> #include <asm/global_data.h> #include <dm/acpi.h> @@ -25,12 +24,12 @@ * to have valid date. So for U-Boot version 2021.04 OEM_REVISION is set to * value 0x20210401. */ -#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \ - (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \ - (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \ - ((U_BOOT_VERSION_NUM % 10) << 16) | \ - (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \ - ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \ +#define OEM_REVISION ((((version_num / 1000) % 10) << 28) | \ + (((version_num / 100) % 10) << 24) | \ + (((version_num / 10) % 10) << 20) | \ + ((version_num % 10) << 16) | \ + (((version_num_patch / 10) % 10) << 12) | \ + ((version_num_patch % 10) << 8) | \ 0x01) int acpi_create_dmar(struct acpi_dmar *dmar, enum dmar_flags flags) diff --git a/lib/ecdsa/ecdsa-libcrypto.c b/lib/ecdsa/ecdsa-libcrypto.c index d5939af..5fa9be1 100644 --- a/lib/ecdsa/ecdsa-libcrypto.c +++ b/lib/ecdsa/ecdsa-libcrypto.c @@ -111,16 +111,30 @@ static size_t ecdsa_key_size_bytes(const EC_KEY *key) return EC_GROUP_order_bits(group) / 8; } +static int default_password(char *buf, int size, int rwflag, void *u) +{ + strncpy(buf, (char *)u, size); + buf[size - 1] = '\0'; + return strlen(buf); +} + static int read_key(struct signer *ctx, const char *key_name) { FILE *f = fopen(key_name, "r"); + const char *key_pass; if (!f) { fprintf(stderr, "Can not get key file '%s'\n", key_name); return -ENOENT; } - ctx->evp_key = PEM_read_PrivateKey(f, NULL, NULL, NULL); + key_pass = getenv("MKIMAGE_SIGN_PASSWORD"); + if (key_pass) { + ctx->evp_key = PEM_read_PrivateKey(f, NULL, default_password, (void *)key_pass); + + } else { + ctx->evp_key = PEM_read_PrivateKey(f, NULL, NULL, NULL); + } fclose(f); if (!ctx->evp_key) { fprintf(stderr, "Can not read key from '%s'\n", key_name); diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile index 13a35ea..1a8c8d7 100644 --- a/lib/efi_loader/Makefile +++ b/lib/efi_loader/Makefile @@ -23,6 +23,7 @@ CFLAGS_REMOVE_initrddump.o := $(CFLAGS_NON_EFI) ifdef CONFIG_RISCV always += boothart.efi +targets += boothart.o endif ifneq ($(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),) @@ -32,10 +33,12 @@ endif ifeq ($(CONFIG_GENERATE_ACPI_TABLE),) always += dtbdump.efi +targets += dtbdump.o endif ifdef CONFIG_EFI_LOAD_FILE2_INITRD always += initrddump.efi +targets += initrddump.o endif obj-$(CONFIG_CMD_BOOTEFI_HELLO) += helloworld_efi.o diff --git a/lib/efi_loader/efi_firmware.c b/lib/efi_loader/efi_firmware.c index 93e2b01..b557738 100644 --- a/lib/efi_loader/efi_firmware.c +++ b/lib/efi_loader/efi_firmware.c @@ -10,6 +10,7 @@ #include <charset.h> #include <dfu.h> #include <efi_loader.h> +#include <efi_variable.h> #include <fwu.h> #include <image.h> #include <signatures.h> @@ -36,11 +37,52 @@ struct fmp_payload_header { u32 lowest_supported_version; }; +/** + * struct fmp_state - fmp firmware update state + * + * This structure describes the state of the firmware update + * through FMP protocol. + * + * @fw_version: Firmware versions used + * @lowest_supported_version: Lowest supported version + * @last_attempt_version: Last attempt version + * @last_attempt_status: Last attempt status + */ +struct fmp_state { + u32 fw_version; + u32 lowest_supported_version; /* not used */ + u32 last_attempt_version; /* not used */ + u32 last_attempt_status; /* not used */ +}; + __weak void set_dfu_alt_info(char *interface, char *devstr) { env_set("dfu_alt_info", update_info.dfu_string); } +/** + * efi_firmware_get_image_type_id - get image_type_id + * @image_index: image index + * + * Return the image_type_id identified by the image index. + * + * Return: pointer to the image_type_id, NULL if image_index is invalid + */ +static +efi_guid_t *efi_firmware_get_image_type_id(u8 image_index) +{ + int i; + struct efi_fw_image *fw_array; + + fw_array = update_info.images; + for (i = 0; i < update_info.num_images; i++) { + if (fw_array[i].image_index == image_index) + return &fw_array[i].image_type_id; + } + + return NULL; +} + /* Place holder; not supported */ static efi_status_t EFIAPI efi_firmware_get_image_unsupported( @@ -103,6 +145,87 @@ efi_status_t EFIAPI efi_firmware_set_package_info_unsupported( } /** + * efi_firmware_get_lsv_from_dtb - get lowest supported version from dtb + * @image_index: Image index + * @image_type_id: Image type id + * @lsv: Pointer to store the lowest supported version + * + * Read the firmware version information from dtb. + */ +static void efi_firmware_get_lsv_from_dtb(u8 image_index, + efi_guid_t *image_type_id, u32 *lsv) +{ + const void *fdt = gd->fdt_blob; + const fdt32_t *val; + const char *guid_str; + int len, offset, index; + int parent; + + *lsv = 0; + + parent = fdt_subnode_offset(fdt, 0, "firmware-version"); + if (parent < 0) + return; + + fdt_for_each_subnode(offset, fdt, parent) { + efi_guid_t guid; + + guid_str = fdt_getprop(fdt, offset, "image-type-id", &len); + if (!guid_str) + continue; + uuid_str_to_bin(guid_str, guid.b, UUID_STR_FORMAT_GUID); + + val = fdt_getprop(fdt, offset, "image-index", &len); + if (!val) + continue; + index = fdt32_to_cpu(*val); + + if (!guidcmp(&guid, image_type_id) && index == image_index) { + val = fdt_getprop(fdt, offset, + "lowest-supported-version", &len); + if (val) + *lsv = fdt32_to_cpu(*val); + } + } +} + +/** + * efi_firmware_fill_version_info - fill the version information + * @image_info: Image information + * @fw_array: Pointer to size of new image + * + * Fill the version information into image_info strucrure. + * + */ +static +void efi_firmware_fill_version_info(struct efi_firmware_image_descriptor *image_info, + struct efi_fw_image *fw_array) +{ + u16 varname[13]; /* u"FmpStateXXXX" */ + efi_status_t ret; + efi_uintn_t size; + struct fmp_state var_state = { 0 }; + + efi_create_indexed_name(varname, sizeof(varname), "FmpState", + fw_array->image_index); + size = sizeof(var_state); + ret = efi_get_variable_int(varname, &fw_array->image_type_id, + NULL, &size, &var_state, NULL); + if (ret == EFI_SUCCESS) + image_info->version = var_state.fw_version; + else + image_info->version = 0; + + efi_firmware_get_lsv_from_dtb(fw_array->image_index, + &fw_array->image_type_id, + &image_info->lowest_supported_image_version); + + image_info->version_name = NULL; /* not supported */ + image_info->last_attempt_version = 0; + image_info->last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS; +} + +/** * efi_fill_image_desc_array - populate image descriptor array * @image_info_size: Size of @image_info * @image_info: Image information @@ -131,7 +254,7 @@ static efi_status_t efi_fill_image_desc_array( struct efi_fw_image *fw_array; int i; - total_size = sizeof(*image_info) * num_image_type_guids; + total_size = sizeof(*image_info) * update_info.num_images; if (*image_info_size < total_size) { *image_info_size = total_size; @@ -141,21 +264,20 @@ static efi_status_t efi_fill_image_desc_array( *image_info_size = total_size; fw_array = update_info.images; - *descriptor_count = num_image_type_guids; + *descriptor_count = update_info.num_images; *descriptor_version = EFI_FIRMWARE_IMAGE_DESCRIPTOR_VERSION; *descriptor_size = sizeof(*image_info); *package_version = 0xffffffff; /* not supported */ *package_version_name = NULL; /* not supported */ - for (i = 0; i < num_image_type_guids; i++) { + for (i = 0; i < update_info.num_images; i++) { image_info[i].image_index = fw_array[i].image_index; image_info[i].image_type_id = fw_array[i].image_type_id; image_info[i].image_id = fw_array[i].image_index; - image_info[i].image_id_name = fw_array[i].fw_name; - image_info[i].version = 0; /* not supported */ - image_info[i].version_name = NULL; /* not supported */ + efi_firmware_fill_version_info(&image_info[i], &fw_array[i]); + image_info[i].size = 0; image_info[i].attributes_supported = IMAGE_ATTRIBUTE_IMAGE_UPDATABLE | @@ -168,9 +290,6 @@ static efi_status_t efi_fill_image_desc_array( image_info[0].attributes_setting |= IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED; - image_info[i].lowest_supported_image_version = 0; - image_info[i].last_attempt_version = 0; - image_info[i].last_attempt_status = LAST_ATTEMPT_STATUS_SUCCESS; image_info[i].hardware_instance = 1; image_info[i].dependencies = NULL; } @@ -194,8 +313,6 @@ efi_status_t efi_firmware_capsule_authenticate(const void **p_image, { const void *image = *p_image; efi_uintn_t image_size = *p_image_size; - u32 fmp_hdr_signature; - struct fmp_payload_header *header; void *capsule_payload; efi_status_t status; efi_uintn_t capsule_payload_size; @@ -222,27 +339,122 @@ efi_status_t efi_firmware_capsule_authenticate(const void **p_image, debug("Updating capsule without authenticating.\n"); } - fmp_hdr_signature = FMP_PAYLOAD_HDR_SIGNATURE; - header = (void *)image; - - if (!memcmp(&header->signature, &fmp_hdr_signature, - sizeof(fmp_hdr_signature))) { - /* - * When building the capsule with the scripts in - * edk2, a FMP header is inserted above the capsule - * payload. Compensate for this header to get the - * actual payload that is to be updated. - */ - image += header->header_size; - image_size -= header->header_size; - } - *p_image = image; *p_image_size = image_size; return EFI_SUCCESS; } /** + * efi_firmware_set_fmp_state_var - set FmpStateXXXX variable + * @state: Pointer to fmp state + * @image_index: image index + * + * Update the FmpStateXXXX variable with the firmware update state. + * + * Return: status code + */ +static +efi_status_t efi_firmware_set_fmp_state_var(struct fmp_state *state, u8 image_index) +{ + u16 varname[13]; /* u"FmpStateXXXX" */ + efi_status_t ret; + efi_guid_t *image_type_id; + struct fmp_state var_state = { 0 }; + + image_type_id = efi_firmware_get_image_type_id(image_index); + if (!image_type_id) + return EFI_INVALID_PARAMETER; + + efi_create_indexed_name(varname, sizeof(varname), "FmpState", + image_index); + + /* + * Only the fw_version is set here. + * lowest_supported_version in FmpState variable is ignored since + * it can be tampered if the file based EFI variable storage is used. + */ + var_state.fw_version = state->fw_version; + + ret = efi_set_variable_int(varname, image_type_id, + EFI_VARIABLE_READ_ONLY | + EFI_VARIABLE_NON_VOLATILE | + EFI_VARIABLE_BOOTSERVICE_ACCESS | + EFI_VARIABLE_RUNTIME_ACCESS, + sizeof(var_state), &var_state, false); + + return ret; +} + +/** + * efi_firmware_get_fw_version - get fw_version from FMP payload header + * @p_image: Pointer to new image + * @p_image_size: Pointer to size of new image + * @state: Pointer to fmp state + * + * Parse the FMP payload header and fill the fmp_state structure. + * If no FMP payload header is found, fmp_state structure is not updated. + * + */ +static void efi_firmware_get_fw_version(const void **p_image, + efi_uintn_t *p_image_size, + struct fmp_state *state) +{ + const struct fmp_payload_header *header; + u32 fmp_hdr_signature = FMP_PAYLOAD_HDR_SIGNATURE; + + header = *p_image; + if (header->signature == fmp_hdr_signature) { + /* FMP header is inserted above the capsule payload */ + state->fw_version = header->fw_version; + + *p_image += header->header_size; + *p_image_size -= header->header_size; + } +} + +/** + * efi_firmware_verify_image - verify image + * @p_image: Pointer to new image + * @p_image_size: Pointer to size of new image + * @image_index: Image index + * @state: Pointer to fmp state + * + * Verify the capsule authentication and check if the fw_version + * is equal or greater than the lowest supported version. + * + * Return: status code + */ +static +efi_status_t efi_firmware_verify_image(const void **p_image, + efi_uintn_t *p_image_size, + u8 image_index, + struct fmp_state *state) +{ + u32 lsv; + efi_status_t ret; + efi_guid_t *image_type_id; + + ret = efi_firmware_capsule_authenticate(p_image, p_image_size); + if (ret != EFI_SUCCESS) + return ret; + + efi_firmware_get_fw_version(p_image, p_image_size, state); + + image_type_id = efi_firmware_get_image_type_id(image_index); + if (!image_type_id) + return EFI_INVALID_PARAMETER; + + efi_firmware_get_lsv_from_dtb(image_index, image_type_id, &lsv); + if (state->fw_version < lsv) { + log_err("Firmware version %u too low. Expecting >= %u. Aborting update\n", + state->fw_version, lsv); + return EFI_INVALID_PARAMETER; + } + + return ret; +} + +/** * efi_firmware_get_image_info - return information about the current * firmware image * @this: Protocol instance @@ -331,6 +543,7 @@ efi_status_t EFIAPI efi_firmware_fit_set_image( u16 **abort_reason) { efi_status_t status; + struct fmp_state state = { 0 }; EFI_ENTRY("%p %d %p %zu %p %p %p\n", this, image_index, image, image_size, vendor_code, progress, abort_reason); @@ -338,13 +551,16 @@ efi_status_t EFIAPI efi_firmware_fit_set_image( if (!image || image_index != 1) return EFI_EXIT(EFI_INVALID_PARAMETER); - status = efi_firmware_capsule_authenticate(&image, &image_size); + status = efi_firmware_verify_image(&image, &image_size, image_index, + &state); if (status != EFI_SUCCESS) return EFI_EXIT(status); if (fit_update(image)) return EFI_EXIT(EFI_DEVICE_ERROR); + efi_firmware_set_fmp_state_var(&state, image_index); + return EFI_EXIT(EFI_SUCCESS); } @@ -392,6 +608,7 @@ efi_status_t EFIAPI efi_firmware_raw_set_image( { int ret; efi_status_t status; + struct fmp_state state = { 0 }; EFI_ENTRY("%p %d %p %zu %p %p %p\n", this, image_index, image, image_size, vendor_code, progress, abort_reason); @@ -399,7 +616,8 @@ efi_status_t EFIAPI efi_firmware_raw_set_image( if (!image) return EFI_EXIT(EFI_INVALID_PARAMETER); - status = efi_firmware_capsule_authenticate(&image, &image_size); + status = efi_firmware_verify_image(&image, &image_size, image_index, + &state); if (status != EFI_SUCCESS) return EFI_EXIT(status); @@ -419,6 +637,8 @@ efi_status_t EFIAPI efi_firmware_raw_set_image( NULL, NULL)) return EFI_EXIT(EFI_DEVICE_ERROR); + efi_firmware_set_fmp_state_var(&state, image_index); + return EFI_EXIT(EFI_SUCCESS); } diff --git a/lib/fwu_updates/Makefile b/lib/fwu_updates/Makefile index 1993088..c9e3c06 100644 --- a/lib/fwu_updates/Makefile +++ b/lib/fwu_updates/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_FWU_MULTI_BANK_UPDATE) += fwu.o obj-$(CONFIG_FWU_MDATA_GPT_BLK) += fwu_gpt.o +obj-$(CONFIG_FWU_MDATA_MTD) += fwu_mtd.o diff --git a/lib/fwu_updates/fwu.c b/lib/fwu_updates/fwu.c index 5313d07..cd5c3b6 100644 --- a/lib/fwu_updates/fwu.c +++ b/lib/fwu_updates/fwu.c @@ -15,13 +15,13 @@ #include <linux/errno.h> #include <linux/types.h> +#include <u-boot/crc.h> + +static struct fwu_mdata g_mdata; /* = {0} makes uninit crc32 always invalid */ +static struct udevice *g_dev; static u8 in_trial; static u8 boottime_check; -#include <linux/errno.h> -#include <linux/types.h> -#include <u-boot/crc.h> - enum { IMAGE_ACCEPT_SET = 1, IMAGE_ACCEPT_CLEAR, @@ -33,26 +33,6 @@ enum { BOTH_PARTS, }; -static int fwu_get_dev_mdata(struct udevice **dev, struct fwu_mdata *mdata) -{ - int ret; - - ret = uclass_first_device_err(UCLASS_FWU_MDATA, dev); - if (ret) { - log_debug("Cannot find fwu device\n"); - return ret; - } - - if (!mdata) - return 0; - - ret = fwu_get_mdata(*dev, mdata); - if (ret < 0) - log_debug("Unable to get valid FWU metadata\n"); - - return ret; -} - static int trial_counter_update(u16 *trial_state_ctr) { bool delete; @@ -151,7 +131,7 @@ static int fwu_get_image_type_id(u8 *image_index, efi_guid_t *image_type_id) index = *image_index; image = update_info.images; - for (i = 0; i < num_image_type_guids; i++) { + for (i = 0; i < update_info.num_images; i++) { if (index == image[i].image_index) { guidcpy(image_type_id, &image[i].image_type_id); return 0; @@ -162,133 +142,124 @@ static int fwu_get_image_type_id(u8 *image_index, efi_guid_t *image_type_id) } /** - * fwu_verify_mdata() - Verify the FWU metadata + * fwu_sync_mdata() - Update given meta-data partition(s) with the copy provided * @mdata: FWU metadata structure - * @pri_part: FWU metadata partition is primary or secondary - * - * Verify the FWU metadata by computing the CRC32 for the metadata - * structure and comparing it against the CRC32 value stored as part - * of the structure. + * @part: Bitmask of FWU metadata partitions to be written to * * Return: 0 if OK, -ve on error - * */ -int fwu_verify_mdata(struct fwu_mdata *mdata, bool pri_part) +static int fwu_sync_mdata(struct fwu_mdata *mdata, int part) { - u32 calc_crc32; - void *buf; + void *buf = &mdata->version; + int err; + + if (part == BOTH_PARTS) { + err = fwu_sync_mdata(mdata, SECONDARY_PART); + if (err) + return err; + part = PRIMARY_PART; + } - buf = &mdata->version; - calc_crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32)); + /* + * Calculate the crc32 for the updated FWU metadata + * and put the updated value in the FWU metadata crc32 + * field + */ + mdata->crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32)); - if (calc_crc32 != mdata->crc32) { - log_debug("crc32 check failed for %s FWU metadata partition\n", - pri_part ? "primary" : "secondary"); - return -EINVAL; + err = fwu_write_mdata(g_dev, mdata, part == PRIMARY_PART); + if (err) { + log_err("Unable to write %s mdata\n", + part == PRIMARY_PART ? "primary" : "secondary"); + return err; } + /* update the cached copy of meta-data */ + memcpy(&g_mdata, mdata, sizeof(struct fwu_mdata)); + return 0; } +static inline int mdata_crc_check(struct fwu_mdata *mdata) +{ + void *buf = &mdata->version; + u32 calc_crc32 = crc32(0, buf, sizeof(*mdata) - sizeof(u32)); + + return calc_crc32 == mdata->crc32 ? 0 : -EINVAL; +} + /** - * fwu_check_mdata_validity() - Check for validity of the FWU metadata copies + * fwu_get_mdata() - Read, verify and return the FWU metadata + * @mdata: Output FWU metadata read or NULL * * Read both the metadata copies from the storage media, verify their checksum, * and ascertain that both copies match. If one of the copies has gone bad, * restore it from the good copy. * * Return: 0 if OK, -ve on error - * */ -int fwu_check_mdata_validity(void) +int fwu_get_mdata(struct fwu_mdata *mdata) { - int ret; - struct udevice *dev; - struct fwu_mdata pri_mdata; - struct fwu_mdata secondary_mdata; - uint mdata_parts[2]; - uint valid_partitions, invalid_partitions; - - ret = fwu_get_dev_mdata(&dev, NULL); - if (ret) - return ret; - - /* - * Check if the platform has defined its own - * function to check the metadata partitions' - * validity. If so, that takes precedence. - */ - ret = fwu_mdata_check(dev); - if (!ret || ret != -ENOSYS) - return ret; - - /* - * Two FWU metadata partitions are expected. - * If we don't have two, user needs to create - * them first - */ - valid_partitions = 0; - ret = fwu_get_mdata_part_num(dev, mdata_parts); - if (ret < 0) { - log_debug("Error getting the FWU metadata partitions\n"); - return -ENOENT; - } - - ret = fwu_read_mdata_partition(dev, &pri_mdata, mdata_parts[0]); - if (!ret) { - ret = fwu_verify_mdata(&pri_mdata, 1); - if (!ret) - valid_partitions |= PRIMARY_PART; - } - - ret = fwu_read_mdata_partition(dev, &secondary_mdata, mdata_parts[1]); - if (!ret) { - ret = fwu_verify_mdata(&secondary_mdata, 0); - if (!ret) - valid_partitions |= SECONDARY_PART; + int err; + bool parts_ok[2] = { false }; + struct fwu_mdata s, *parts_mdata[2]; + + parts_mdata[0] = &g_mdata; + parts_mdata[1] = &s; + + /* if mdata already read and ready */ + err = mdata_crc_check(parts_mdata[0]); + if (!err) + goto ret_mdata; + /* else read, verify and, if needed, fix mdata */ + + for (int i = 0; i < 2; i++) { + parts_ok[i] = false; + err = fwu_read_mdata(g_dev, parts_mdata[i], !i); + if (!err) { + err = mdata_crc_check(parts_mdata[i]); + if (!err) + parts_ok[i] = true; + else + log_debug("mdata : %s crc32 failed\n", i ? "secondary" : "primary"); + } } - if (valid_partitions == (PRIMARY_PART | SECONDARY_PART)) { + if (parts_ok[0] && parts_ok[1]) { /* * Before returning, check that both the - * FWU metadata copies are the same. If not, - * populate the secondary partition from the + * FWU metadata copies are the same. + */ + err = memcmp(parts_mdata[0], parts_mdata[1], sizeof(struct fwu_mdata)); + if (!err) + goto ret_mdata; + + /* + * If not, populate the secondary partition from the * primary partition copy. */ - if (!memcmp(&pri_mdata, &secondary_mdata, - sizeof(struct fwu_mdata))) { - ret = 0; - } else { - log_info("Both FWU metadata copies are valid but do not match."); - log_info(" Restoring the secondary partition from the primary\n"); - ret = fwu_write_mdata_partition(dev, &pri_mdata, - mdata_parts[1]); - if (ret) - log_debug("Restoring secondary FWU metadata partition failed\n"); - } - goto out; + log_info("Both FWU metadata copies are valid but do not match."); + log_info(" Restoring the secondary partition from the primary\n"); + parts_ok[1] = false; } - if (!(valid_partitions & BOTH_PARTS)) { - log_info("Both FWU metadata partitions invalid\n"); - ret = -EBADMSG; - goto out; - } + for (int i = 0; i < 2; i++) { + if (parts_ok[i]) + continue; - invalid_partitions = valid_partitions ^ BOTH_PARTS; - ret = fwu_write_mdata_partition(dev, - (invalid_partitions == PRIMARY_PART) ? - &secondary_mdata : &pri_mdata, - (invalid_partitions == PRIMARY_PART) ? - mdata_parts[0] : mdata_parts[1]); + memcpy(parts_mdata[i], parts_mdata[1 - i], sizeof(struct fwu_mdata)); + err = fwu_sync_mdata(parts_mdata[i], i ? SECONDARY_PART : PRIMARY_PART); + if (err) { + log_debug("mdata : %s write failed\n", i ? "secondary" : "primary"); + return err; + } + } - if (ret) - log_debug("Restoring %s FWU metadata partition failed\n", - (invalid_partitions == PRIMARY_PART) ? - "primary" : "secondary"); +ret_mdata: + if (!err && mdata) + memcpy(mdata, parts_mdata[0], sizeof(struct fwu_mdata)); -out: - return ret; + return err; } /** @@ -303,19 +274,14 @@ out: */ int fwu_get_active_index(uint *active_idx) { - int ret; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; - - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; + int ret = 0; + struct fwu_mdata *mdata = &g_mdata; /* * Found the FWU metadata partition, now read the active_index * value */ - *active_idx = mdata.active_index; + *active_idx = mdata->active_index; if (*active_idx >= CONFIG_FWU_NUM_BANKS) { log_debug("Active index value read is incorrect\n"); ret = -EINVAL; @@ -336,30 +302,25 @@ int fwu_get_active_index(uint *active_idx) int fwu_set_active_index(uint active_idx) { int ret; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; + struct fwu_mdata *mdata = &g_mdata; if (active_idx >= CONFIG_FWU_NUM_BANKS) { log_debug("Invalid active index value\n"); return -EINVAL; } - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; - /* * Update the active index and previous_active_index fields * in the FWU metadata */ - mdata.previous_active_index = mdata.active_index; - mdata.active_index = active_idx; + mdata->previous_active_index = mdata->active_index; + mdata->active_index = active_idx; /* * Now write this updated FWU metadata to both the * FWU metadata partitions */ - ret = fwu_update_mdata(dev, &mdata); + ret = fwu_sync_mdata(mdata, BOTH_PARTS); if (ret) { log_debug("Failed to update FWU metadata partitions\n"); ret = -EIO; @@ -389,15 +350,10 @@ int fwu_get_image_index(u8 *image_index) u8 alt_num; uint update_bank; efi_guid_t *image_guid, image_type_id; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; + struct fwu_mdata *mdata = &g_mdata; struct fwu_image_entry *img_entry; struct fwu_image_bank_info *img_bank_info; - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; - ret = fwu_plat_get_update_index(&update_bank); if (ret) { log_debug("Failed to get the FWU update bank\n"); @@ -418,11 +374,11 @@ int fwu_get_image_index(u8 *image_index) */ for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { if (!guidcmp(&image_type_id, - &mdata.img_entry[i].image_type_uuid)) { - img_entry = &mdata.img_entry[i]; + &mdata->img_entry[i].image_type_uuid)) { + img_entry = &mdata->img_entry[i]; img_bank_info = &img_entry->img_bank_info[update_bank]; image_guid = &img_bank_info->image_uuid; - ret = fwu_plat_get_alt_num(dev, image_guid, &alt_num); + ret = fwu_plat_get_alt_num(g_dev, image_guid, &alt_num); if (ret) { log_debug("alt_num not found for partition with GUID %pUs\n", image_guid); @@ -436,8 +392,8 @@ int fwu_get_image_index(u8 *image_index) } } - log_debug("Partition with the image type %pUs not found\n", - &image_type_id); + log_err("Partition with the image type %pUs not found\n", + &image_type_id); out: return ret; @@ -457,26 +413,21 @@ int fwu_revert_boot_index(void) { int ret; u32 cur_active_index; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; - - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; + struct fwu_mdata *mdata = &g_mdata; /* * Swap the active index and previous_active_index fields * in the FWU metadata */ - cur_active_index = mdata.active_index; - mdata.active_index = mdata.previous_active_index; - mdata.previous_active_index = cur_active_index; + cur_active_index = mdata->active_index; + mdata->active_index = mdata->previous_active_index; + mdata->previous_active_index = cur_active_index; /* * Now write this updated FWU metadata to both the * FWU metadata partitions */ - ret = fwu_update_mdata(dev, &mdata); + ret = fwu_sync_mdata(mdata, BOTH_PARTS); if (ret) { log_debug("Failed to update FWU metadata partitions\n"); ret = -EIO; @@ -503,16 +454,11 @@ int fwu_revert_boot_index(void) static int fwu_clrset_image_accept(efi_guid_t *img_type_id, u32 bank, u8 action) { int ret, i; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; + struct fwu_mdata *mdata = &g_mdata; struct fwu_image_entry *img_entry; struct fwu_image_bank_info *img_bank_info; - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; - - img_entry = &mdata.img_entry[0]; + img_entry = &mdata->img_entry[0]; for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { if (!guidcmp(&img_entry[i].image_type_uuid, img_type_id)) { img_bank_info = &img_entry[i].img_bank_info[bank]; @@ -521,7 +467,7 @@ static int fwu_clrset_image_accept(efi_guid_t *img_type_id, u32 bank, u8 action) else img_bank_info->accepted = 0; - ret = fwu_update_mdata(dev, &mdata); + ret = fwu_sync_mdata(mdata, BOTH_PARTS); goto out; } } @@ -600,6 +546,24 @@ __weak int fwu_plat_get_update_index(uint *update_idx) } /** + * fwu_plat_get_bootidx() - Get the value of the boot index + * @boot_idx: Boot index value + * + * Get the value of the bank(partition) from which the platform + * has booted. This value is passed to U-Boot from the earlier + * stage bootloader which loads and boots all the relevant + * firmware images + */ +__weak void fwu_plat_get_bootidx(uint *boot_idx) +{ + int ret; + + ret = fwu_get_active_index(boot_idx); + if (ret < 0) + *boot_idx = 0; /* Dummy value */ +} + +/** * fwu_update_checks_pass() - Check if FWU update can be done * * Check if the FWU update can be executed. The updates are @@ -656,8 +620,6 @@ static int fwu_boottime_checks(void *ctx, struct event *event) { int ret; u32 boot_idx, active_idx; - struct udevice *dev; - struct fwu_mdata mdata = { 0 }; /* Don't have boot time checks on sandbox */ if (IS_ENABLED(CONFIG_SANDBOX)) { @@ -665,9 +627,17 @@ static int fwu_boottime_checks(void *ctx, struct event *event) return 0; } - ret = fwu_check_mdata_validity(); - if (ret) - return 0; + ret = uclass_first_device_err(UCLASS_FWU_MDATA, &g_dev); + if (ret) { + log_debug("Cannot find fwu device\n"); + return ret; + } + + ret = fwu_get_mdata(NULL); + if (ret) { + log_debug("Unable to read meta-data\n"); + return ret; + } /* * Get the Boot Index, i.e. the bank from @@ -703,11 +673,7 @@ static int fwu_boottime_checks(void *ctx, struct event *event) if (efi_init_obj_list() != EFI_SUCCESS) return 0; - ret = fwu_get_dev_mdata(&dev, &mdata); - if (ret) - return ret; - - in_trial = in_trial_state(&mdata); + in_trial = in_trial_state(&g_mdata); if (!in_trial || (ret = fwu_trial_count_update()) > 0) ret = trial_counter_update(NULL); diff --git a/lib/fwu_updates/fwu_mtd.c b/lib/fwu_updates/fwu_mtd.c new file mode 100644 index 0000000..b73111a --- /dev/null +++ b/lib/fwu_updates/fwu_mtd.c @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include <dm.h> +#include <dfu.h> +#include <fwu.h> +#include <fwu_mdata.h> +#include <log.h> +#include <malloc.h> +#include <mtd.h> +#include <uuid.h> +#include <vsprintf.h> + +#include <dm/ofnode.h> + +struct fwu_mtd_image_info +fwu_mtd_images[CONFIG_FWU_NUM_BANKS * CONFIG_FWU_NUM_IMAGES_PER_BANK]; + +static struct fwu_mtd_image_info *mtd_img_by_uuid(const char *uuidbuf) +{ + int num_images = ARRAY_SIZE(fwu_mtd_images); + + for (int i = 0; i < num_images; i++) + if (!strcmp(uuidbuf, fwu_mtd_images[i].uuidbuf)) + return &fwu_mtd_images[i]; + + return NULL; +} + +int fwu_mtd_get_alt_num(efi_guid_t *image_id, u8 *alt_num, + const char *mtd_dev) +{ + struct fwu_mtd_image_info *mtd_img_info; + char uuidbuf[UUID_STR_LEN + 1]; + fdt_addr_t offset, size = 0; + struct dfu_entity *dfu; + int i, nalt, ret; + + mtd_probe_devices(); + + uuid_bin_to_str(image_id->b, uuidbuf, UUID_STR_FORMAT_STD); + + mtd_img_info = mtd_img_by_uuid(uuidbuf); + if (!mtd_img_info) { + log_err("%s: Not found partition for image %s\n", __func__, uuidbuf); + return -ENOENT; + } + + offset = mtd_img_info->start; + size = mtd_img_info->size; + + ret = dfu_init_env_entities(NULL, NULL); + if (ret) + return -ENOENT; + + nalt = 0; + list_for_each_entry(dfu, &dfu_list, list) + nalt++; + + if (!nalt) { + log_warning("No entities in dfu_alt_info\n"); + dfu_free_entities(); + return -ENOENT; + } + + ret = -ENOENT; + for (i = 0; i < nalt; i++) { + dfu = dfu_get_entity(i); + + /* Only MTD RAW access */ + if (!dfu || dfu->dev_type != DFU_DEV_MTD || + dfu->layout != DFU_RAW_ADDR || + dfu->data.mtd.start != offset || + dfu->data.mtd.size != size) + continue; + + *alt_num = dfu->alt; + ret = 0; + break; + } + + dfu_free_entities(); + + log_debug("%s: %s -> %d\n", __func__, uuidbuf, *alt_num); + return ret; +} + +/** + * fwu_plat_get_alt_num() - Get the DFU Alt Num for the image from the platform + * @dev: FWU device + * @image_id: Image GUID for which DFU alt number needs to be retrieved + * @alt_num: Pointer to the alt_num + * + * Get the DFU alt number from the platform for the image specified by the + * image GUID. + * + * Note: This is a weak function and platforms can override this with + * their own implementation for obtaining the alt number value. + * + * Return: 0 if OK, -ve on error + */ +__weak int fwu_plat_get_alt_num(struct udevice *dev, efi_guid_t *image_id, + u8 *alt_num) +{ + return fwu_mtd_get_alt_num(image_id, alt_num, "nor1"); +} + +static int gen_image_alt_info(char *buf, size_t len, int sidx, + struct fwu_image_entry *img, struct mtd_info *mtd) +{ + char *p = buf, *end = buf + len; + int i; + + p += snprintf(p, end - p, "mtd %s", mtd->name); + if (end < p) { + log_err("%s:%d Run out of buffer\n", __func__, __LINE__); + return -E2BIG; + } + + /* + * List the image banks in the FWU mdata and search the corresponding + * partition based on partition's uuid. + */ + for (i = 0; i < CONFIG_FWU_NUM_BANKS; i++) { + struct fwu_mtd_image_info *mtd_img_info; + struct fwu_image_bank_info *bank; + char uuidbuf[UUID_STR_LEN + 1]; + u32 offset, size; + + /* Query a partition by image UUID */ + bank = &img->img_bank_info[i]; + uuid_bin_to_str(bank->image_uuid.b, uuidbuf, UUID_STR_FORMAT_STD); + + mtd_img_info = mtd_img_by_uuid(uuidbuf); + if (!mtd_img_info) { + log_err("%s: Not found partition for image %s\n", __func__, uuidbuf); + break; + } + + offset = mtd_img_info->start; + size = mtd_img_info->size; + + p += snprintf(p, end - p, "%sbank%d raw %x %x", + i == 0 ? "=" : ";", i, offset, size); + if (end < p) { + log_err("%s:%d Run out of buffer\n", __func__, __LINE__); + return -E2BIG; + } + } + + if (i == CONFIG_FWU_NUM_BANKS) + return 0; + + return -ENOENT; +} + +int fwu_gen_alt_info_from_mtd(char *buf, size_t len, struct mtd_info *mtd) +{ + struct fwu_mdata mdata; + int i, l, ret; + + ret = fwu_get_mdata(&mdata); + if (ret < 0) { + log_err("Failed to get the FWU mdata.\n"); + return ret; + } + + for (i = 0; i < CONFIG_FWU_NUM_IMAGES_PER_BANK; i++) { + ret = gen_image_alt_info(buf, len, i * CONFIG_FWU_NUM_BANKS, + &mdata.img_entry[i], mtd); + if (ret) + break; + + l = strlen(buf); + /* Replace the last ';' with '&' if there is another image. */ + if (i != CONFIG_FWU_NUM_IMAGES_PER_BANK - 1 && l) + buf[l - 1] = '&'; + len -= l; + buf += l; + } + + return ret; +} diff --git a/net/dsa-uclass.c b/net/dsa-uclass.c index dd78e57..f64c68e 100644 --- a/net/dsa-uclass.c +++ b/net/dsa-uclass.c @@ -381,7 +381,7 @@ static int dsa_post_bind(struct udevice *dev) node = ofnode_find_subnode(node, "ports"); if (!ofnode_valid(node)) - node = ofnode_find_subnode(node, "ethernet-ports"); + node = ofnode_find_subnode(dev_ofnode(dev), "ethernet-ports"); if (!ofnode_valid(node)) { dev_err(dev, "ports node is missing under DSA device!\n"); return -EINVAL; diff --git a/scripts/Makefile.dts b/scripts/Makefile.dts index 2561025..5e2429c 100644 --- a/scripts/Makefile.dts +++ b/scripts/Makefile.dts @@ -1,3 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ -dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_$(SPL_)OF_LIST))) +dtb-y += $(patsubst %,%.dtb,$(subst ",,$(CONFIG_DEFAULT_DEVICE_TREE) $(CONFIG_OF_LIST) $(CONFIG_SPL_OF_LIST))) diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 7b27224..f5ab7af 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -186,7 +186,7 @@ u_boot_dtsi = $(strip $(u_boot_dtsi_options_debug) \ # Modified for U-Boot dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \ $(UBOOTINCLUDE) \ - -I$(srctree)/arch/$(ARCH)/dts \ + -I$(dir $<) \ -I$(srctree)/arch/$(ARCH)/dts/include \ -I$(srctree)/include \ -D__ASSEMBLY__ \ @@ -331,7 +331,7 @@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ ; \ sed "s:$(pre-tmp):$(<):" $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) -$(obj)/%.dtb: $(src)/%.dts FORCE +$(obj)/%.dtb: $(src)/%.dts $(DTC) FORCE $(call if_changed_dep,dtc) pre-tmp = $(subst $(comma),_,$(dot-target).pre.tmp) @@ -351,7 +351,10 @@ cmd_dtco = mkdir -p $(dir ${dtc-tmp}) ; \ -d $(depfile).dtc.tmp $(dtc-tmp) ; \ cat $(depfile).pre.tmp $(depfile).dtc.tmp > $(depfile) -$(obj)/%.dtbo: $(src)/%.dts FORCE +$(obj)/%.dtbo: $(src)/%.dts $(DTC) FORCE + $(call if_changed_dep,dtco) + +$(obj)/%.dtbo: $(src)/%.dtso $(DTC) FORCE $(call if_changed_dep,dtco) # Fonts diff --git a/scripts/dtc-version.sh b/scripts/dtc-version.sh index bfb514e..53ff868 100755 --- a/scripts/dtc-version.sh +++ b/scripts/dtc-version.sh @@ -20,7 +20,7 @@ if ! which $dtc >/dev/null ; then exit 1 fi -MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1) +MAJOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 1 | tr -d v) MINOR=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 2) PATCH=$($dtc -v | head -1 | awk '{print $NF}' | cut -d . -f 3 | cut -d - -f 1) diff --git a/test/cmd/Makefile b/test/cmd/Makefile index 055adc6..a3cf983 100644 --- a/test/cmd/Makefile +++ b/test/cmd/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_PAUSE) += test_pause.o endif obj-y += exit.o mem.o obj-$(CONFIG_CMD_ADDRMAP) += addrmap.o +obj-$(CONFIG_CMD_BDI) += bdinfo.o obj-$(CONFIG_CMD_FDT) += fdt.o obj-$(CONFIG_CONSOLE_TRUETYPE) += font.o obj-$(CONFIG_CMD_LOADM) += loadm.o diff --git a/test/cmd/bdinfo.c b/test/cmd/bdinfo.c new file mode 100644 index 0000000..9068df7 --- /dev/null +++ b/test/cmd/bdinfo.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Tests for bdinfo command + * + * Copyright 2023 Marek Vasut <marek.vasut+renesas@mailbox.org> + */ + +#include <common.h> +#include <console.h> +#include <mapmem.h> +#include <asm/global_data.h> +#include <dm/uclass.h> +#include <test/suites.h> +#include <test/ut.h> +#include <dm.h> +#include <env.h> +#include <lmb.h> +#include <net.h> +#include <video.h> +#include <vsprintf.h> +#include <asm/cache.h> +#include <asm/global_data.h> +#include <display_options.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Declare a new bdinfo test */ +#define BDINFO_TEST(_name, _flags) UNIT_TEST(_name, _flags, bdinfo_test) + +static void bdinfo_test_num_l(struct unit_test_state *uts, + const char *name, ulong value) +{ + ut_assert_nextline("%-12s= 0x%0*lx", name, 2 * (int)sizeof(value), value); +} + +static void bdinfo_test_num_ll(struct unit_test_state *uts, + const char *name, unsigned long long value) +{ + ut_assert_nextline("%-12s= 0x%.*llx", name, 2 * (int)sizeof(ulong), value); +} + +static void test_eth(struct unit_test_state *uts) +{ + const int idx = eth_get_dev_index(); + uchar enetaddr[6]; + char name[10]; + int ret; + + if (idx) + sprintf(name, "eth%iaddr", idx); + else + strcpy(name, "ethaddr"); + + ret = eth_env_get_enetaddr_by_index("eth", idx, enetaddr); + + ut_assert_nextline("current eth = %s", eth_get_name()); + if (!ret) + ut_assert_nextline("%-12s= (not set)", name); + else + ut_assert_nextline("%-12s= %pM", name, enetaddr); + ut_assert_nextline("IP addr = %s", env_get("ipaddr")); +} + +static void test_video_info(struct unit_test_state *uts) +{ + const struct udevice *dev; + struct uclass *uc; + + uclass_id_foreach_dev(UCLASS_VIDEO, dev, uc) { + ut_assert_nextline("%-12s= %s %sactive", "Video", dev->name, + device_active(dev) ? "" : "in"); + if (device_active(dev)) { + struct video_priv *upriv = dev_get_uclass_priv(dev); + struct video_uc_plat *plat = dev_get_uclass_plat(dev); + + bdinfo_test_num_ll(uts, "FB base", (ulong)upriv->fb); + if (upriv->copy_fb) { + bdinfo_test_num_ll(uts, "FB copy", + (ulong)upriv->copy_fb); + bdinfo_test_num_l(uts, " copy size", + plat->copy_size); + } + ut_assert_nextline("%-12s= %dx%dx%d", "FB size", + upriv->xsize, upriv->ysize, + 1 << upriv->bpix); + } + } +} + +static void lmb_test_dump_region(struct unit_test_state *uts, + struct lmb_region *rgn, char *name) +{ + unsigned long long base, size, end; + enum lmb_flags flags; + int i; + + ut_assert_nextline(" %s.cnt = 0x%lx / max = 0x%lx", name, rgn->cnt, rgn->max); + + for (i = 0; i < rgn->cnt; i++) { + base = rgn->region[i].base; + size = rgn->region[i].size; + end = base + size - 1; + flags = rgn->region[i].flags; + + ut_assert_nextline(" %s[%d]\t[0x%llx-0x%llx], 0x%08llx bytes flags: %x", + name, i, base, end, size, flags); + } +} + +static void lmb_test_dump_all(struct unit_test_state *uts, struct lmb *lmb) +{ + ut_assert_nextline("lmb_dump_all:"); + lmb_test_dump_region(uts, &lmb->memory, "memory"); + lmb_test_dump_region(uts, &lmb->reserved, "reserved"); +} + +static int bdinfo_test_move(struct unit_test_state *uts) +{ + struct bd_info *bd = gd->bd; + int i; + + /* Test moving the working BDINFO to a new location */ + ut_assertok(console_record_reset_enable()); + ut_assertok(run_commandf("bdinfo")); + + bdinfo_test_num_l(uts, "boot_params", 0); + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; ++i) { + if (bd->bi_dram[i].size) { + bdinfo_test_num_l(uts, "DRAM bank", i); + bdinfo_test_num_ll(uts, "-> start", bd->bi_dram[i].start); + bdinfo_test_num_ll(uts, "-> size", bd->bi_dram[i].size); + } + } + + /* CONFIG_SYS_HAS_SRAM testing not supported */ + bdinfo_test_num_l(uts, "flashstart", 0); + bdinfo_test_num_l(uts, "flashsize", 0); + bdinfo_test_num_l(uts, "flashoffset", 0); + ut_assert_nextline("baudrate = %lu bps", + env_get_ulong("baudrate", 10, 1234)); + bdinfo_test_num_l(uts, "relocaddr", gd->relocaddr); + bdinfo_test_num_l(uts, "reloc off", gd->reloc_off); + ut_assert_nextline("%-12s= %u-bit", "Build", (uint)sizeof(void *) * 8); + + if (IS_ENABLED(CONFIG_CMD_NET)) + test_eth(uts); + + /* + * Make sure environment variable "fdtcontroladdr" address + * matches mapped control DT address. + */ + ut_assert(map_to_sysmem(gd->fdt_blob) == env_get_hex("fdtcontroladdr", 0x1234)); + bdinfo_test_num_l(uts, "fdt_blob", (ulong)map_to_sysmem(gd->fdt_blob)); + bdinfo_test_num_l(uts, "new_fdt", (ulong)map_to_sysmem(gd->new_fdt)); + bdinfo_test_num_l(uts, "fdt_size", (ulong)gd->fdt_size); + + if (IS_ENABLED(CONFIG_VIDEO)) + test_video_info(uts); + + /* The gd->multi_dtb_fit may not be available, hence, #if below. */ +#if CONFIG_IS_ENABLED(MULTI_DTB_FIT) + bdinfo_test_num_l(uts, "multi_dtb_fit", (ulong)gd->multi_dtb_fit); +#endif + + if (IS_ENABLED(CONFIG_LMB) && gd->fdt_blob) { + struct lmb lmb; + + lmb_init_and_reserve(&lmb, gd->bd, (void *)gd->fdt_blob); + lmb_test_dump_all(uts, &lmb); + if (IS_ENABLED(CONFIG_OF_REAL)) + ut_assert_nextline("devicetree = %s", fdtdec_get_srcname()); + } + + ut_assertok(ut_check_console_end(uts)); + + return 0; +} + +BDINFO_TEST(bdinfo_test_move, UT_TESTF_CONSOLE_REC); + +int do_ut_bdinfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) +{ + struct unit_test *tests = UNIT_TEST_SUITE_START(bdinfo_test); + const int n_ents = UNIT_TEST_SUITE_COUNT(bdinfo_test); + + return cmd_ut_category("bdinfo", "bdinfo_test_", tests, n_ents, argc, argv); +} diff --git a/test/cmd_ut.c b/test/cmd_ut.c index d440da8..0cb5144 100644 --- a/test/cmd_ut.c +++ b/test/cmd_ut.c @@ -54,6 +54,9 @@ int cmd_ut_category(const char *name, const char *prefix, static struct cmd_tbl cmd_ut_sub[] = { U_BOOT_CMD_MKENT(all, CONFIG_SYS_MAXARGS, 1, do_ut_all, "", ""), U_BOOT_CMD_MKENT(info, 1, 1, do_ut_info, "", ""), +#ifdef CONFIG_CMD_BDI + U_BOOT_CMD_MKENT(bdinfo, CONFIG_SYS_MAXARGS, 1, do_ut_bdinfo, "", ""), +#endif #ifdef CONFIG_BOOTSTD U_BOOT_CMD_MKENT(bootstd, CONFIG_SYS_MAXARGS, 1, do_ut_bootstd, "", ""), @@ -176,6 +179,9 @@ static char ut_help_text[] = #ifdef CONFIG_CMD_ADDRMAP "\naddrmap - very basic test of addrmap command" #endif +#ifdef CONFIG_CMD_BDI + "\nbdinfo - bdinfo command" +#endif #ifdef CONFIG_SANDBOX "\nbloblist - bloblist implementation" #endif diff --git a/test/dm/acpi.c b/test/dm/acpi.c index 9634fc2..818f715 100644 --- a/test/dm/acpi.c +++ b/test/dm/acpi.c @@ -11,10 +11,8 @@ #include <dm.h> #include <malloc.h> #include <mapmem.h> -#include <timestamp.h> -#include <version.h> #include <tables_csum.h> -#include <version.h> +#include <version_string.h> #include <acpi/acpigen.h> #include <acpi/acpi_device.h> #include <acpi/acpi_table.h> @@ -26,12 +24,12 @@ #define BUF_SIZE 4096 -#define OEM_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 28) | \ - (((U_BOOT_VERSION_NUM / 100) % 10) << 24) | \ - (((U_BOOT_VERSION_NUM / 10) % 10) << 20) | \ - ((U_BOOT_VERSION_NUM % 10) << 16) | \ - (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 12) | \ - ((U_BOOT_VERSION_NUM_PATCH % 10) << 8) | \ +#define OEM_REVISION ((((version_num / 1000) % 10) << 28) | \ + (((version_num / 100) % 10) << 24) | \ + (((version_num / 10) % 10) << 20) | \ + ((version_num % 10) << 16) | \ + (((version_num_patch / 10) % 10) << 12) | \ + ((version_num_patch % 10) << 8) | \ 0x01) /** diff --git a/test/dm/fwu_mdata.c b/test/dm/fwu_mdata.c index b179a65..8b5c83e 100644 --- a/test/dm/fwu_mdata.c +++ b/test/dm/fwu_mdata.c @@ -98,7 +98,7 @@ static int dm_test_fwu_mdata_read(struct unit_test_state *uts) ut_assertok(populate_mmc_disk_image(uts)); ut_assertok(write_mmc_blk_device(uts)); - ut_assertok(fwu_get_mdata(dev, &mdata)); + ut_assertok(fwu_get_mdata(&mdata)); ut_asserteq(mdata.version, 0x1); @@ -118,30 +118,14 @@ static int dm_test_fwu_mdata_write(struct unit_test_state *uts) ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev)); - ut_assertok(fwu_get_mdata(dev, &mdata)); + ut_assertok(fwu_get_mdata(&mdata)); active_idx = (mdata.active_index + 1) % CONFIG_FWU_NUM_BANKS; ut_assertok(fwu_set_active_index(active_idx)); - ut_assertok(fwu_get_mdata(dev, &mdata)); + ut_assertok(fwu_get_mdata(&mdata)); ut_asserteq(mdata.active_index, active_idx); return 0; } DM_TEST(dm_test_fwu_mdata_write, UT_TESTF_SCAN_FDT); - -static int dm_test_fwu_mdata_check(struct unit_test_state *uts) -{ - struct udevice *dev; - - ut_assertok(setup_blk_device(uts)); - ut_assertok(populate_mmc_disk_image(uts)); - ut_assertok(write_mmc_blk_device(uts)); - - ut_assertok(uclass_first_device_err(UCLASS_FWU_MDATA, &dev)); - - ut_assertok(fwu_check_mdata_validity()); - - return 0; -} -DM_TEST(dm_test_fwu_mdata_check, UT_TESTF_SCAN_FDT); diff --git a/test/dm/nvmxip.c b/test/dm/nvmxip.c index e934748..89bf481 100644 --- a/test/dm/nvmxip.c +++ b/test/dm/nvmxip.c @@ -17,7 +17,7 @@ #include <linux/bitops.h> #include <test/test.h> #include <test/ut.h> -#include "../../drivers/mtd/nvmxip/nvmxip.h" +#include <nvmxip.h> /* NVMXIP devices described in the device tree */ #define SANDBOX_NVMXIP_DEVICES 2 diff --git a/test/py/requirements.txt b/test/py/requirements.txt index 86d6266..f7e76bd 100644 --- a/test/py/requirements.txt +++ b/test/py/requirements.txt @@ -20,8 +20,8 @@ pytest==6.2.5 pytest-xdist==2.5.0 python-mimeparse==1.6.0 python-subunit==1.3.0 -requests==2.27.1 -setuptools==58.3.0 +requests==2.31.0 +setuptools==65.5.1 six==1.16.0 testtools==2.3.0 traceback2==1.4.0 diff --git a/test/py/tests/test_android/test_avb.py b/test/py/tests/test_android/test_avb.py index bc5c5b5..238b48c 100644 --- a/test/py/tests/test_android/test_avb.py +++ b/test/py/tests/test_android/test_avb.py @@ -5,7 +5,7 @@ # Android Verified Boot 2.0 Test """ -This tests Android Verified Boot 2.0 support in U-boot: +This tests Android Verified Boot 2.0 support in U-Boot: For additional details about how to build proper vbmeta partition check doc/android/avb2.rst diff --git a/test/py/tests/test_cat/conftest.py b/test/py/tests/test_cat/conftest.py index 058fe52..fc396f5 100644 --- a/test/py/tests/test_cat/conftest.py +++ b/test/py/tests/test_cat/conftest.py @@ -13,7 +13,7 @@ def cat_data(u_boot_config): """Set up a file system to be used in cat tests Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. """ mnt_point = u_boot_config.persistent_data_dir + '/test_cat' image_path = u_boot_config.persistent_data_dir + '/cat.img' diff --git a/test/py/tests/test_cleanup_build.py b/test/py/tests/test_cleanup_build.py new file mode 100644 index 0000000..5206ff7 --- /dev/null +++ b/test/py/tests/test_cleanup_build.py @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright (c) 2023 Tobias Deiminger <tdmg@linutronix.de> + +"""Test for unexpected leftovers after make clean""" + +import itertools +import os +import pathlib +import shutil +import sys + +import pytest + +# pylint: disable=redefined-outer-name + + +@pytest.fixture +def tmp_copy_of_builddir(u_boot_config, tmp_path): + """For each test, provide a temporary copy of the initial build directory.""" + shutil.copytree( + u_boot_config.build_dir, + tmp_path, + symlinks=True, + dirs_exist_ok=True, + ) + return tmp_path + + +@pytest.fixture(scope="module") +def run_make(u_boot_log): + """Provide function to run and log make without connecting to u-boot console.""" + runner = u_boot_log.get_runner("make", sys.stdout) + + def _run_make(build_dir, target): + cmd = ["make", f"O={build_dir}", target] + runner.run(cmd) + + yield _run_make + runner.close() + + +@pytest.fixture(scope="module") +def most_generated_files(): + """Path.glob style patterns to describe what should be removed by 'make clean'.""" + return ( + "**/*.c", + "**/*.dtb", + "**/*.dtbo", + "**/*.o", + "**/*.py", + "**/*.pyc", + "**/*.so", + "**/*.srec", + "u-boot*", + "[svt]pl/u-boot*", + ) + + +@pytest.fixture(scope="module") +def all_generated_files(most_generated_files): + """Path.glob style patterns to describe what should be removed by 'make mrproper'.""" + return most_generated_files + (".config", "**/*.h") + + +def find_files(search_dir, include_patterns, exclude_dirs=None): + """Find files matching include_patterns, unless it's in one of exclude_dirs. + + include_patterns -- Path.glob style pattern relative to search dir + exclude_dir -- directories to exclude, expected relative to search dir + """ + matches = [] + exclude_dirs = [] if exclude_dirs is None else exclude_dirs + for abs_path in itertools.chain.from_iterable( + pathlib.Path(search_dir).glob(pattern) for pattern in include_patterns + ): + if abs_path.is_dir(): + continue + rel_path = pathlib.Path(os.path.relpath(abs_path, search_dir)) + if not any( + rel_path.is_relative_to(exclude_dir) for exclude_dir in exclude_dirs + ): + matches.append(rel_path) + return matches + + +def test_clean(run_make, tmp_copy_of_builddir, most_generated_files): + """Test if 'make clean' deletes most generated files.""" + run_make(tmp_copy_of_builddir, "clean") + leftovers = find_files( + tmp_copy_of_builddir, + most_generated_files, + exclude_dirs=["scripts", "test/overlay"], + ) + assert not leftovers, f"leftovers: {', '.join(map(str, leftovers))}" + + +def test_mrproper(run_make, tmp_copy_of_builddir, all_generated_files): + """Test if 'make mrproper' deletes current configuration and all generated files.""" + run_make(tmp_copy_of_builddir, "mrproper") + leftovers = find_files( + tmp_copy_of_builddir, + all_generated_files, + exclude_dirs=["test/overlay"], + ) + assert not leftovers, f"leftovers: {', '.join(map(str, leftovers))}" diff --git a/test/py/tests/test_efi_bootmgr/conftest.py b/test/py/tests/test_efi_bootmgr/conftest.py index eabafa5..0eca025 100644 --- a/test/py/tests/test_efi_bootmgr/conftest.py +++ b/test/py/tests/test_efi_bootmgr/conftest.py @@ -12,7 +12,7 @@ def efi_bootmgr_data(u_boot_config): """Set up a file system to be used in UEFI bootmanager tests. Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. Return: A path to disk image to be used for testing diff --git a/test/py/tests/test_efi_capsule/capsule_common.py b/test/py/tests/test_efi_capsule/capsule_common.py new file mode 100644 index 0000000..9eef676 --- /dev/null +++ b/test/py/tests/test_efi_capsule/capsule_common.py @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: GPL-2.0+ +# Copyright (c) 2023, Linaro Limited + + +"""Common function for UEFI capsule test.""" + +from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR + +def setup(u_boot_console, disk_img, osindications): + """setup the test + + Args: + u_boot_console -- A console connection to U-Boot. + disk_img -- A path to disk image to be used for testing. + osindications -- String of osindications value. + """ + u_boot_console.run_command_list([ + f'host bind 0 {disk_img}', + 'printenv -e PlatformLangCodes', # workaround for terminal size determination + 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', + 'efidebug boot order 1', + 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;' + 'u-boot-env raw 0x150000 0x200000"']) + + if osindications is None: + u_boot_console.run_command('env set -e OsIndications') + else: + u_boot_console.run_command(f'env set -e -nv -bs -rt OsIndications ={osindications}') + + u_boot_console.run_command('env save') + +def init_content(u_boot_console, target, filename, expected): + """initialize test content + + Args: + u_boot_console -- A console connection to U-Boot. + target -- Target address to place the content. + filename -- File name of the content. + expected -- Expected string of the content. + """ + output = u_boot_console.run_command_list([ + 'sf probe 0:0', + f'fatload host 0:1 4000000 {CAPSULE_DATA_DIR}/{filename}', + f'sf write 4000000 {target} 10', + 'sf read 5000000 100000 10', + 'md.b 5000000 10']) + assert expected in ''.join(output) + +def place_capsule_file(u_boot_console, filenames): + """place the capsule file + + Args: + u_boot_console -- A console connection to U-Boot. + filenames -- File name array of the target capsule files. + """ + for name in filenames: + u_boot_console.run_command_list([ + f'fatload host 0:1 4000000 {CAPSULE_DATA_DIR}/{name}', + f'fatwrite host 0:1 4000000 {CAPSULE_INSTALL_DIR}/{name} $filesize']) + + output = u_boot_console.run_command(f'fatls host 0:1 {CAPSULE_INSTALL_DIR}') + for name in filenames: + assert name in ''.join(output) + +def exec_manual_update(u_boot_console, disk_img, filenames, need_reboot = True): + """execute capsule update manually + + Args: + u_boot_console -- A console connection to U-Boot. + disk_img -- A path to disk image to be used for testing. + filenames -- File name array of the target capsule files. + need_reboot -- Flag indicates whether system reboot is required. + """ + # make sure that dfu_alt_info exists even persistent variables + # are not available. + output = u_boot_console.run_command_list([ + 'env set dfu_alt_info ' + '"sf 0:0=u-boot-bin raw 0x100000 0x50000;' + 'u-boot-env raw 0x150000 0x200000"', + f'host bind 0 {disk_img}', + f'fatls host 0:1 {CAPSULE_INSTALL_DIR}']) + for name in filenames: + assert name in ''.join(output) + + # need to run uefi command to initiate capsule handling + u_boot_console.run_command( + 'env print -e Capsule0000', wait_for_reboot = need_reboot) + +def check_file_removed(u_boot_console, disk_img, filenames): + """check files are removed + + Args: + u_boot_console -- A console connection to U-Boot. + disk_img -- A path to disk image to be used for testing. + filenames -- File name array of the target capsule files. + """ + output = u_boot_console.run_command_list([ + f'host bind 0 {disk_img}', + f'fatls host 0:1 {CAPSULE_INSTALL_DIR}']) + for name in filenames: + assert name not in ''.join(output) + +def check_file_exist(u_boot_console, disk_img, filenames): + """check files exist + + Args: + u_boot_console -- A console connection to U-Boot. + disk_img -- A path to disk image to be used for testing. + filenames -- File name array of the target capsule files. + """ + output = u_boot_console.run_command_list([ + f'host bind 0 {disk_img}', + f'fatls host 0:1 {CAPSULE_INSTALL_DIR}']) + for name in filenames: + assert name in ''.join(output) + +def verify_content(u_boot_console, target, expected): + """verify the content + + Args: + u_boot_console -- A console connection to U-Boot. + target -- Target address to verify. + expected -- Expected string of the content. + """ + output = u_boot_console.run_command_list([ + 'sf probe 0:0', + f'sf read 4000000 {target} 10', + 'md.b 4000000 10']) + assert expected in ''.join(output) + +def do_reboot_dtb_specified(u_boot_config, u_boot_console, dtb_filename): + """do reboot with specified DTB + + Args: + u_boot_config -- U-boot configuration. + u_boot_console -- A console connection to U-Boot. + dtb_filename -- DTB file name. + """ + mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule' + u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \ + + f'/{dtb_filename}' + u_boot_console.restart_uboot() diff --git a/test/py/tests/test_efi_capsule/conftest.py b/test/py/tests/test_efi_capsule/conftest.py index a337e62..054be1e 100644 --- a/test/py/tests/test_efi_capsule/conftest.py +++ b/test/py/tests/test_efi_capsule/conftest.py @@ -17,7 +17,7 @@ def efi_capsule_data(request, u_boot_config): for testing. request -- Pytest request object. - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. """ mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule' data_dir = mnt_point + CAPSULE_DATA_DIR @@ -62,6 +62,23 @@ def efi_capsule_data(request, u_boot_config): '-out SIGNER2.crt -nodes -days 365' % data_dir, shell=True) + # Update dtb to add the version information + check_call('cd %s; ' + 'cp %s/test/py/tests/test_efi_capsule/version.dts .' + % (data_dir, u_boot_config.source_dir), shell=True) + if capsule_auth_enabled: + check_call('cd %s; ' + 'dtc -@ -I dts -O dtb -o version.dtbo version.dts; ' + 'fdtoverlay -i test_sig.dtb ' + '-o test_ver.dtb version.dtbo' + % (data_dir), shell=True) + else: + check_call('cd %s; ' + 'dtc -@ -I dts -O dtb -o version.dtbo version.dts; ' + 'fdtoverlay -i %s/arch/sandbox/dts/test.dtb ' + '-o test_ver.dtb version.dtbo' + % (data_dir, u_boot_config.build_dir), shell=True) + # Create capsule files # two regions: one for u-boot.bin and the other for u-boot.env check_call('cd %s; echo -n u-boot:Old > u-boot.bin.old; echo -n u-boot:New > u-boot.bin.new; echo -n u-boot-env:Old > u-boot.env.old; echo -n u-boot-env:New > u-boot.env.new' % data_dir, @@ -87,6 +104,26 @@ def efi_capsule_data(request, u_boot_config): check_call('cd %s; %s/tools/mkeficapsule --index 1 --guid 058B7D83-50D5-4C47-A195-60D86AD341C4 uboot_bin_env.itb Test05' % (data_dir, u_boot_config.build_dir), shell=True) + check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 ' + '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test101' % + (data_dir, u_boot_config.build_dir), + shell=True) + check_call('cd %s; %s/tools/mkeficapsule --index 2 --fw-version 10 ' + '--guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 u-boot.env.new Test102' % + (data_dir, u_boot_config.build_dir), + shell=True) + check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 ' + '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 u-boot.bin.new Test103' % + (data_dir, u_boot_config.build_dir), + shell=True) + check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 5 ' + '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test104' % + (data_dir, u_boot_config.build_dir), + shell=True) + check_call('cd %s; %s/tools/mkeficapsule --index 1 --fw-version 2 ' + '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 uboot_bin_env.itb Test105' % + (data_dir, u_boot_config.build_dir), + shell=True) if capsule_auth_enabled: # raw firmware signed with proper key @@ -123,6 +160,51 @@ def efi_capsule_data(request, u_boot_config): 'uboot_bin_env.itb Test14' % (data_dir, u_boot_config.build_dir), shell=True) + # raw firmware signed with proper key with version information + check_call('cd %s; ' + '%s/tools/mkeficapsule --index 1 --monotonic-count 1 ' + '--fw-version 5 ' + '--private-key SIGNER.key --certificate SIGNER.crt ' + '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 ' + 'u-boot.bin.new Test111' + % (data_dir, u_boot_config.build_dir), + shell=True) + # raw firmware signed with proper key with version information + check_call('cd %s; ' + '%s/tools/mkeficapsule --index 2 --monotonic-count 1 ' + '--fw-version 10 ' + '--private-key SIGNER.key --certificate SIGNER.crt ' + '--guid 5A7021F5-FEF2-48B4-AABA-832E777418C0 ' + 'u-boot.env.new Test112' + % (data_dir, u_boot_config.build_dir), + shell=True) + # raw firmware signed with proper key with lower version information + check_call('cd %s; ' + '%s/tools/mkeficapsule --index 1 --monotonic-count 1 ' + '--fw-version 2 ' + '--private-key SIGNER.key --certificate SIGNER.crt ' + '--guid 09D7CF52-0720-4710-91D1-08469B7FE9C8 ' + 'u-boot.bin.new Test113' + % (data_dir, u_boot_config.build_dir), + shell=True) + # FIT firmware signed with proper key with version information + check_call('cd %s; ' + '%s/tools/mkeficapsule --index 1 --monotonic-count 1 ' + '--fw-version 5 ' + '--private-key SIGNER.key --certificate SIGNER.crt ' + '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 ' + 'uboot_bin_env.itb Test114' + % (data_dir, u_boot_config.build_dir), + shell=True) + # FIT firmware signed with proper key with lower version information + check_call('cd %s; ' + '%s/tools/mkeficapsule --index 1 --monotonic-count 1 ' + '--fw-version 2 ' + '--private-key SIGNER.key --certificate SIGNER.crt ' + '--guid 3673B45D-6A7C-46F3-9E60-ADABB03F7937 ' + 'uboot_bin_env.itb Test115' + % (data_dir, u_boot_config.build_dir), + shell=True) # Create a disk image with EFI system partition check_call('virt-make-fs --partition=gpt --size=+1M --type=vfat %s %s' % diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py index 9ee1528..a3094c3 100644 --- a/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_fit.py @@ -7,8 +7,15 @@ This test verifies capsule-on-disk firmware update for FIT images """ import pytest -from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR - +from capsule_common import ( + setup, + init_content, + place_capsule_file, + exec_manual_update, + check_file_removed, + verify_content, + do_reboot_dtb_specified +) @pytest.mark.boardspec('sandbox_flattree') @pytest.mark.buildconfigspec('efi_capsule_firmware_fit') @@ -40,37 +47,12 @@ class TestEfiCapsuleFirmwareFit(): u_boot_console.restart_uboot() disk_img = efi_capsule_data + capsule_files = ['Test05'] with u_boot_console.log.section('Test Case 1-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""', - 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize contents - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR, - 'sf write 4000000 150000 10', - 'sf read 5000000 150000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place a capsule file - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test05' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test05 $filesize' % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test05' in ''.join(output) + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) capsule_early = u_boot_config.buildconfig.get( 'config_efi_capsule_on_disk_early') @@ -80,28 +62,13 @@ class TestEfiCapsuleFirmwareFit(): with u_boot_console.log.section('Test Case 1-b, after reboot'): if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test05' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) + exec_manual_update(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', - 'md.b 4000000 10']) - assert 'u-boot:Old' in ''.join(output) + # deleted anyway + check_file_removed(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'sf read 4000000 150000 10', - 'md.b 4000000 10']) - assert 'u-boot-env:Old' in ''.join(output) + verify_content(u_boot_console, '100000', 'u-boot:Old') + verify_content(u_boot_console, '150000', 'u-boot-env:Old') def test_efi_capsule_fw2( self, u_boot_config, u_boot_console, efi_capsule_data): @@ -112,38 +79,12 @@ class TestEfiCapsuleFirmwareFit(): """ disk_img = efi_capsule_data + capsule_files = ['Test04'] with u_boot_console.log.section('Test Case 2-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'printenv -e PlatformLangCodes', # workaround for terminal size determination - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""', - 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize contents - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR, - 'sf write 4000000 150000 10', - 'sf read 5000000 150000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place a capsule file - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test04' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test04 $filesize' % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test04' in ''.join(output) + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) capsule_early = u_boot_config.buildconfig.get( 'config_efi_capsule_on_disk_early') @@ -155,36 +96,88 @@ class TestEfiCapsuleFirmwareFit(): with u_boot_console.log.section('Test Case 2-b, after reboot'): if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test04' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) + exec_manual_update(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test04' not in ''.join(output) + check_file_removed(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', - 'md.b 4000000 10']) - if capsule_auth: - assert 'u-boot:Old' in ''.join(output) - else: - assert 'u-boot:New' in ''.join(output) + expected = 'u-boot:Old' if capsule_auth else 'u-boot:New' + verify_content(u_boot_console, '100000', expected) + + expected = 'u-boot-env:Old' if capsule_auth else 'u-boot-env:New' + verify_content(u_boot_console, '150000', expected) + + def test_efi_capsule_fw3( + self, u_boot_config, u_boot_console, efi_capsule_data): + """ Test Case 3 + Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version + 0x100000-0x150000: U-Boot binary (but dummy) + 0x150000-0x200000: U-Boot environment (but dummy) + """ + disk_img = efi_capsule_data + capsule_files = ['Test104'] + with u_boot_console.log.section('Test Case 3-a, before reboot'): + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + # reboot + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb') + capsule_early = u_boot_config.buildconfig.get( + 'config_efi_capsule_on_disk_early') + capsule_auth = u_boot_config.buildconfig.get( + 'config_efi_capsule_authenticate') + with u_boot_console.log.section('Test Case 3-b, after reboot'): + if not capsule_early: + exec_manual_update(u_boot_console, disk_img, capsule_files) + + # deleted anyway + check_file_removed(u_boot_console, disk_img, capsule_files) + + # make sure the dfu_alt_info exists because it is required for making ESRT. output = u_boot_console.run_command_list([ - 'sf read 4000000 150000 10', - 'md.b 4000000 10']) + 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;' + 'u-boot-env raw 0x150000 0x200000"', + 'efidebug capsule esrt']) + if capsule_auth: - assert 'u-boot-env:Old' in ''.join(output) + # capsule authentication failed + verify_content(u_boot_console, '100000', 'u-boot:Old') + verify_content(u_boot_console, '150000', 'u-boot-env:Old') else: - assert 'u-boot-env:New' in ''.join(output) + # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT. + assert '3673B45D-6A7C-46F3-9E60-ADABB03F7937' in ''.join(output) + assert 'ESRT: fw_version=5' in ''.join(output) + assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output) + + verify_content(u_boot_console, '100000', 'u-boot:New') + verify_content(u_boot_console, '150000', 'u-boot-env:New') + + def test_efi_capsule_fw4( + self, u_boot_config, u_boot_console, efi_capsule_data): + """ Test Case 4 + Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version + but fw_version is lower than lowest_supported_version + No update should happen + 0x100000-0x150000: U-Boot binary (but dummy) + """ + disk_img = efi_capsule_data + capsule_files = ['Test105'] + with u_boot_console.log.section('Test Case 4-a, before reboot'): + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + # reboot + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb') + + capsule_early = u_boot_config.buildconfig.get( + 'config_efi_capsule_on_disk_early') + with u_boot_console.log.section('Test Case 4-b, after reboot'): + if not capsule_early: + exec_manual_update(u_boot_console, disk_img, capsule_files) + + check_file_removed(u_boot_console, disk_img, capsule_files) + + verify_content(u_boot_console, '100000', 'u-boot:Old') diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py index 92bfb14..80d791e 100644 --- a/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_raw.py @@ -7,7 +7,16 @@ This test verifies capsule-on-disk firmware update for raw images """ import pytest -from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR +from capsule_common import ( + setup, + init_content, + place_capsule_file, + exec_manual_update, + check_file_removed, + check_file_exist, + verify_content, + do_reboot_dtb_specified +) @pytest.mark.boardspec('sandbox') @pytest.mark.buildconfigspec('efi_capsule_firmware_raw') @@ -40,37 +49,12 @@ class TestEfiCapsuleFirmwareRaw: u_boot_console.restart_uboot() disk_img = efi_capsule_data + capsule_files = ['Test03'] with u_boot_console.log.section('Test Case 1-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""', - 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize contents - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR, - 'sf write 4000000 150000 10', - 'sf read 5000000 150000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place a capsule file - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test03' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test03 $filesize' % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test03' in ''.join(output) + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) # reboot u_boot_console.restart_uboot() @@ -80,28 +64,13 @@ class TestEfiCapsuleFirmwareRaw: with u_boot_console.log.section('Test Case 1-b, after reboot'): if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test03' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) + exec_manual_update(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', - 'md.b 4000000 10']) - assert 'u-boot:Old' in ''.join(output) + # deleted anyway + check_file_removed(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'sf read 4000000 150000 10', - 'md.b 4000000 10']) - assert 'u-boot-env:Old' in ''.join(output) + verify_content(u_boot_console, '100000', 'u-boot:Old') + verify_content(u_boot_console, '150000', 'u-boot-env:Old') def test_efi_capsule_fw2( self, u_boot_config, u_boot_console, efi_capsule_data): @@ -112,44 +81,12 @@ class TestEfiCapsuleFirmwareRaw: 0x150000-0x200000: U-Boot environment (but dummy) """ disk_img = efi_capsule_data + capsule_files = ['Test01', 'Test02'] with u_boot_console.log.section('Test Case 2-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'printenv -e PlatformLangCodes', # workaround for terminal size determination - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""', - 'efidebug boot order 1', - 'env set -e OsIndications', - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize contents - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR, - 'sf write 4000000 150000 10', - 'sf read 5000000 150000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place the capsule files - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test01' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test01 $filesize' % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test01' in ''.join(output) - - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test02 $filesize' % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test02' in ''.join(output) + setup(u_boot_console, disk_img, None) + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) # reboot u_boot_console.restart_uboot() @@ -158,35 +95,12 @@ class TestEfiCapsuleFirmwareRaw: 'config_efi_capsule_on_disk_early') with u_boot_console.log.section('Test Case 2-b, after reboot'): if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test01' in ''.join(output) - assert 'Test02' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000') - - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test01' in ''.join(output) - assert 'Test02' in ''.join(output) + exec_manual_update(u_boot_console, disk_img, capsule_files, False) - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', - 'md.b 4000000 10']) - assert 'u-boot:Old' in ''.join(output) + check_file_exist(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'sf read 4000000 150000 10', - 'md.b 4000000 10']) - assert 'u-boot-env:Old' in ''.join(output) + verify_content(u_boot_console, '100000', 'u-boot:Old') + verify_content(u_boot_console, '150000', 'u-boot-env:Old') def test_efi_capsule_fw3( self, u_boot_config, u_boot_console, efi_capsule_data): @@ -195,45 +109,12 @@ class TestEfiCapsuleFirmwareRaw: 0x100000-0x150000: U-Boot binary (but dummy) """ disk_img = efi_capsule_data + capsule_files = ['Test01', 'Test02'] with u_boot_console.log.section('Test Case 3-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'printenv -e PlatformLangCodes', # workaround for terminal size determination - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi -s ""', - 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize contents - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.env.old' % CAPSULE_DATA_DIR, - 'sf write 4000000 150000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place the capsule files - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test01' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test01 $filesize' % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test01' in ''.join(output) - - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test02 $filesize' % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test02' in ''.join(output) + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) capsule_early = u_boot_config.buildconfig.get( 'config_efi_capsule_on_disk_early') @@ -245,18 +126,7 @@ class TestEfiCapsuleFirmwareRaw: with u_boot_console.log.section('Test Case 3-b, after reboot'): if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test01' in ''.join(output) - assert 'Test02' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) + exec_manual_update(u_boot_console, disk_img, capsule_files) # make sure the dfu_alt_info exists because it is required for making ESRT. output = u_boot_console.run_command_list([ @@ -269,26 +139,91 @@ class TestEfiCapsuleFirmwareRaw: # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT. assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output) - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test01' not in ''.join(output) - assert 'Test02' not in ''.join(output) + check_file_removed(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', - 'md.b 4000000 10']) - if capsule_auth: - assert 'u-boot:Old' in ''.join(output) - else: - assert 'u-boot:New' in ''.join(output) + expected = 'u-boot:Old' if capsule_auth else 'u-boot:New' + verify_content(u_boot_console, '100000', expected) + + expected = 'u-boot-env:Old' if capsule_auth else 'u-boot-env:New' + verify_content(u_boot_console, '150000', expected) + def test_efi_capsule_fw4( + self, u_boot_config, u_boot_console, efi_capsule_data): + """ Test Case 4 + Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version + 0x100000-0x150000: U-Boot binary (but dummy) + 0x150000-0x200000: U-Boot environment (but dummy) + """ + disk_img = efi_capsule_data + capsule_files = ['Test101', 'Test102'] + with u_boot_console.log.section('Test Case 4-a, before reboot'): + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + init_content(u_boot_console, '150000', 'u-boot.env.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + # reboot + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb') + + capsule_early = u_boot_config.buildconfig.get( + 'config_efi_capsule_on_disk_early') + capsule_auth = u_boot_config.buildconfig.get( + 'config_efi_capsule_authenticate') + with u_boot_console.log.section('Test Case 4-b, after reboot'): + if not capsule_early: + exec_manual_update(u_boot_console, disk_img, capsule_files) + + # deleted anyway + check_file_removed(u_boot_console, disk_img, capsule_files) + + # make sure the dfu_alt_info exists because it is required for making ESRT. output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 150000 10', - 'md.b 4000000 10']) + 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000' + 'u-boot-env raw 0x150000 0x200000"', + 'efidebug capsule esrt']) + if capsule_auth: - assert 'u-boot-env:Old' in ''.join(output) + # capsule authentication failed + verify_content(u_boot_console, '100000', 'u-boot:Old') + verify_content(u_boot_console, '150000', 'u-boot-env:Old') else: - assert 'u-boot-env:New' in ''.join(output) + # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT. + assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output) + assert 'ESRT: fw_version=5' in ''.join(output) + assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output) + + # ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT. + assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output) + assert 'ESRT: fw_version=10' in ''.join(output) + assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output) + + verify_content(u_boot_console, '100000', 'u-boot:New') + verify_content(u_boot_console, '150000', 'u-boot-env:New') + + def test_efi_capsule_fw5( + self, u_boot_config, u_boot_console, efi_capsule_data): + """ Test Case 5 + Update U-Boot on SPI Flash, raw image format with fw_version and lowest_supported_version + but fw_version is lower than lowest_supported_version + No update should happen + 0x100000-0x150000: U-Boot binary (but dummy) + """ + disk_img = efi_capsule_data + capsule_files = ['Test103'] + with u_boot_console.log.section('Test Case 5-a, before reboot'): + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + # reboot + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb') + + capsule_early = u_boot_config.buildconfig.get( + 'config_efi_capsule_on_disk_early') + with u_boot_console.log.section('Test Case 5-b, after reboot'): + if not capsule_early: + exec_manual_update(u_boot_console, disk_img, capsule_files) + + check_file_removed(u_boot_console, disk_img, capsule_files) + + verify_content(u_boot_console, '100000', 'u-boot:Old') diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py index ba8429e..94d6c3e 100644 --- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_fit.py @@ -10,7 +10,15 @@ with signed capsule files containing FIT images """ import pytest -from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR +from capsule_common import ( + setup, + init_content, + place_capsule_file, + exec_manual_update, + check_file_removed, + verify_content, + do_reboot_dtb_specified +) @pytest.mark.boardspec('sandbox_flattree') @pytest.mark.buildconfigspec('efi_capsule_firmware_fit') @@ -37,70 +45,23 @@ class TestEfiCapsuleFirmwareSignedFit(): should pass and the firmware be updated. """ disk_img = efi_capsule_data + capsule_files = ['Test13'] with u_boot_console.log.section('Test Case 1-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'printenv -e PlatformLangCodes', # workaround for terminal size determination - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', - 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize content - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' - % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place a capsule file - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test13' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test13 $filesize' - % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test13' in ''.join(output) - - # reboot - mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule' - u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \ - + '/test_sig.dtb' - u_boot_console.restart_uboot() + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb') capsule_early = u_boot_config.buildconfig.get( 'config_efi_capsule_on_disk_early') with u_boot_console.log.section('Test Case 1-b, after reboot'): if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test13' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) + exec_manual_update(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test13' not in ''.join(output) + check_file_removed(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', - 'md.b 4000000 10']) - assert 'u-boot:New' in ''.join(output) + verify_content(u_boot_console, '100000', 'u-boot:New') def test_efi_capsule_auth2( self, u_boot_config, u_boot_console, efi_capsule_data): @@ -113,73 +74,26 @@ class TestEfiCapsuleFirmwareSignedFit(): not be updated. """ disk_img = efi_capsule_data + capsule_files = ['Test14'] with u_boot_console.log.section('Test Case 2-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'printenv -e PlatformLangCodes', # workaround for terminal size determination - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', - 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize content - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' - % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place a capsule file - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test14' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test14 $filesize' - % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test14' in ''.join(output) - - # reboot - mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule' - u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \ - + '/test_sig.dtb' - u_boot_console.restart_uboot() + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb') capsule_early = u_boot_config.buildconfig.get( 'config_efi_capsule_on_disk_early') with u_boot_console.log.section('Test Case 2-b, after reboot'): if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test14' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) + exec_manual_update(u_boot_console, disk_img, capsule_files) # deleted any way - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test14' not in ''.join(output) + check_file_removed(u_boot_console, disk_img, capsule_files) # TODO: check CapsuleStatus in CapsuleXXXX - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', - 'md.b 4000000 10']) - assert 'u-boot:Old' in ''.join(output) + verify_content(u_boot_console, '100000', 'u-boot:Old') def test_efi_capsule_auth3( self, u_boot_config, u_boot_console, efi_capsule_data): @@ -191,70 +105,89 @@ class TestEfiCapsuleFirmwareSignedFit(): should fail and the firmware not be updated. """ disk_img = efi_capsule_data + capsule_files = ['Test02'] with u_boot_console.log.section('Test Case 3-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'printenv -e PlatformLangCodes', # workaround for terminal size determination - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', - 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize content - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' - % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place a capsule file - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test02 $filesize' - % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test02' in ''.join(output) - - # reboot - mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule' - u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \ - + '/test_sig.dtb' - u_boot_console.restart_uboot() + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb') capsule_early = u_boot_config.buildconfig.get( 'config_efi_capsule_on_disk_early') with u_boot_console.log.section('Test Case 3-b, after reboot'): if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test02' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) + exec_manual_update(u_boot_console, disk_img, capsule_files) # deleted any way - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test02' not in ''.join(output) + check_file_removed(u_boot_console, disk_img, capsule_files) # TODO: check CapsuleStatus in CapsuleXXXX + verify_content(u_boot_console, '100000', 'u-boot:Old') + + def test_efi_capsule_auth4( + self, u_boot_config, u_boot_console, efi_capsule_data): + """Test Case 4 - Update U-Boot on SPI Flash, raw image format with version information + 0x100000-0x150000: U-Boot binary (but dummy) + + If the capsule is properly signed, the authentication + should pass and the firmware be updated. + """ + disk_img = efi_capsule_data + capsule_files = ['Test114'] + with u_boot_console.log.section('Test Case 4-a, before reboot'): + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb') + + capsule_early = u_boot_config.buildconfig.get( + 'config_efi_capsule_on_disk_early') + with u_boot_console.log.section('Test Case 4-b, after reboot'): + if not capsule_early: + exec_manual_update(u_boot_console, disk_img, capsule_files) + + check_file_removed(u_boot_console, disk_img, capsule_files) + output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', - 'md.b 4000000 10']) - assert 'u-boot:Old' in ''.join(output) + 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;' + 'u-boot-env raw 0x150000 0x200000"', + 'efidebug capsule esrt']) + + # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT. + assert '3673B45D-6A7C-46F3-9E60-ADABB03F7937' in ''.join(output) + assert 'ESRT: fw_version=5' in ''.join(output) + assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output) + + verify_content(u_boot_console, '100000', 'u-boot:New') + verify_content(u_boot_console, '150000', 'u-boot-env:New') + + def test_efi_capsule_auth5( + self, u_boot_config, u_boot_console, efi_capsule_data): + """Test Case 5 - Update U-Boot on SPI Flash, raw image format with version information + 0x100000-0x150000: U-Boot binary (but dummy) + + If the capsule is signed but fw_version is lower than lowest + supported version, the authentication should fail and the firmware + not be updated. + """ + disk_img = efi_capsule_data + capsule_files = ['Test115'] + with u_boot_console.log.section('Test Case 5-a, before reboot'): + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb') + + capsule_early = u_boot_config.buildconfig.get( + 'config_efi_capsule_on_disk_early') + with u_boot_console.log.section('Test Case 5-b, after reboot'): + if not capsule_early: + exec_manual_update(u_boot_console, disk_img, capsule_files) + + check_file_removed(u_boot_console, disk_img, capsule_files) + + verify_content(u_boot_console, '100000', 'u-boot:Old') diff --git a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py index 710d992..ad2b1c6 100644 --- a/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py +++ b/test/py/tests/test_efi_capsule/test_capsule_firmware_signed_raw.py @@ -8,7 +8,15 @@ with signed capsule files containing raw images """ import pytest -from capsule_defs import CAPSULE_DATA_DIR, CAPSULE_INSTALL_DIR +from capsule_common import ( + setup, + init_content, + place_capsule_file, + exec_manual_update, + check_file_removed, + verify_content, + do_reboot_dtb_specified +) @pytest.mark.boardspec('sandbox') @pytest.mark.buildconfigspec('efi_capsule_firmware_raw') @@ -34,69 +42,23 @@ class TestEfiCapsuleFirmwareSignedRaw(): should pass and the firmware be updated. """ disk_img = efi_capsule_data + capsule_files = ['Test11'] with u_boot_console.log.section('Test Case 1-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', - 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize content - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' - % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place a capsule file - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test11' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test11 $filesize' - % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test11' in ''.join(output) - - # reboot - mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule' - u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \ - + '/test_sig.dtb' - u_boot_console.restart_uboot() + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb') capsule_early = u_boot_config.buildconfig.get( 'config_efi_capsule_on_disk_early') with u_boot_console.log.section('Test Case 1-b, after reboot'): if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test11' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) + exec_manual_update(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test11' not in ''.join(output) + check_file_removed(u_boot_console, disk_img, capsule_files) - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', - 'md.b 4000000 10']) - assert 'u-boot:New' in ''.join(output) + verify_content(u_boot_console, '100000', 'u-boot:New') def test_efi_capsule_auth2( self, u_boot_config, u_boot_console, efi_capsule_data): @@ -108,73 +70,25 @@ class TestEfiCapsuleFirmwareSignedRaw(): not be updated. """ disk_img = efi_capsule_data + capsule_files = ['Test12'] with u_boot_console.log.section('Test Case 2-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'printenv -e PlatformLangCodes', # workaround for terminal size determination - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', - 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize content - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' - % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place a capsule file - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test12' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test12 $filesize' - % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test12' in ''.join(output) - - # reboot - mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule' - u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \ - + '/test_sig.dtb' - u_boot_console.restart_uboot() + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb') capsule_early = u_boot_config.buildconfig.get( 'config_efi_capsule_on_disk_early') with u_boot_console.log.section('Test Case 2-b, after reboot'): if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test12' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) - - # deleted any way - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test12' not in ''.join(output) + exec_manual_update(u_boot_console, disk_img, capsule_files) + + check_file_removed(u_boot_console, disk_img, capsule_files) # TODO: check CapsuleStatus in CapsuleXXXX - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', - 'md.b 4000000 10']) - assert 'u-boot:Old' in ''.join(output) + verify_content(u_boot_console, '100000', 'u-boot:Old') def test_efi_capsule_auth3( self, u_boot_config, u_boot_console, efi_capsule_data): @@ -185,70 +99,94 @@ class TestEfiCapsuleFirmwareSignedRaw(): should fail and the firmware not be updated. """ disk_img = efi_capsule_data + capsule_files = ['Test02'] with u_boot_console.log.section('Test Case 3-a, before reboot'): - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'printenv -e PlatformLangCodes', # workaround for terminal size determination - 'efidebug boot add -b 1 TEST host 0:1 /helloworld.efi', - 'efidebug boot order 1', - 'env set -e -nv -bs -rt OsIndications =0x0000000000000004', - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'env save']) - - # initialize content - output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'fatload host 0:1 4000000 %s/u-boot.bin.old' - % CAPSULE_DATA_DIR, - 'sf write 4000000 100000 10', - 'sf read 5000000 100000 10', - 'md.b 5000000 10']) - assert 'Old' in ''.join(output) - - # place a capsule file - output = u_boot_console.run_command_list([ - 'fatload host 0:1 4000000 %s/Test02' % CAPSULE_DATA_DIR, - 'fatwrite host 0:1 4000000 %s/Test02 $filesize' - % CAPSULE_INSTALL_DIR, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test02' in ''.join(output) - - # reboot - mnt_point = u_boot_config.persistent_data_dir + '/test_efi_capsule' - u_boot_console.config.dtb = mnt_point + CAPSULE_DATA_DIR \ - + '/test_sig.dtb' - u_boot_console.restart_uboot() + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_sig.dtb') capsule_early = u_boot_config.buildconfig.get( 'config_efi_capsule_on_disk_early') with u_boot_console.log.section('Test Case 3-b, after reboot'): if not capsule_early: - # make sure that dfu_alt_info exists even persistent variables - # are not available. - output = u_boot_console.run_command_list([ - 'env set dfu_alt_info ' - '"sf 0:0=u-boot-bin raw 0x100000 ' - '0x50000;u-boot-env raw 0x150000 0x200000"', - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test02' in ''.join(output) - - # need to run uefi command to initiate capsule handling - output = u_boot_console.run_command( - 'env print -e Capsule0000', wait_for_reboot = True) + exec_manual_update(u_boot_console, disk_img, capsule_files) # deleted anyway - output = u_boot_console.run_command_list([ - 'host bind 0 %s' % disk_img, - 'fatls host 0:1 %s' % CAPSULE_INSTALL_DIR]) - assert 'Test02' not in ''.join(output) + check_file_removed(u_boot_console, disk_img, capsule_files) # TODO: check CapsuleStatus in CapsuleXXXX + verify_content(u_boot_console, '100000', 'u-boot:Old') + + def test_efi_capsule_auth4( + self, u_boot_config, u_boot_console, efi_capsule_data): + """Test Case 4 - Update U-Boot on SPI Flash, raw image format with version information + 0x100000-0x150000: U-Boot binary (but dummy) + + If the capsule is properly signed, the authentication + should pass and the firmware be updated. + """ + disk_img = efi_capsule_data + capsule_files = ['Test111', 'Test112'] + with u_boot_console.log.section('Test Case 4-a, before reboot'): + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb') + + capsule_early = u_boot_config.buildconfig.get( + 'config_efi_capsule_on_disk_early') + with u_boot_console.log.section('Test Case 4-b, after reboot'): + if not capsule_early: + exec_manual_update(u_boot_console, disk_img, capsule_files) + + check_file_removed(u_boot_console, disk_img, capsule_files) + output = u_boot_console.run_command_list([ - 'sf probe 0:0', - 'sf read 4000000 100000 10', - 'md.b 4000000 10']) - assert 'u-boot:Old' in ''.join(output) + 'env set dfu_alt_info "sf 0:0=u-boot-bin raw 0x100000 0x50000;' + 'u-boot-env raw 0x150000 0x200000"', + 'efidebug capsule esrt']) + + # ensure that SANDBOX_UBOOT_IMAGE_GUID is in the ESRT. + assert '09D7CF52-0720-4710-91D1-08469B7FE9C8' in ''.join(output) + assert 'ESRT: fw_version=5' in ''.join(output) + assert 'ESRT: lowest_supported_fw_version=3' in ''.join(output) + + # ensure that SANDBOX_UBOOT_ENV_IMAGE_GUID is in the ESRT. + assert '5A7021F5-FEF2-48B4-AABA-832E777418C0' in ''.join(output) + assert 'ESRT: fw_version=10' in ''.join(output) + assert 'ESRT: lowest_supported_fw_version=7' in ''.join(output) + + verify_content(u_boot_console, '100000', 'u-boot:New') + verify_content(u_boot_console, '150000', 'u-boot-env:New') + + def test_efi_capsule_auth5( + self, u_boot_config, u_boot_console, efi_capsule_data): + """Test Case 5 - Update U-Boot on SPI Flash, raw image format with version information + 0x100000-0x150000: U-Boot binary (but dummy) + + If the capsule is signed but fw_version is lower than lowest + supported version, the authentication should fail and the firmware + not be updated. + """ + disk_img = efi_capsule_data + capsule_files = ['Test113'] + with u_boot_console.log.section('Test Case 5-a, before reboot'): + setup(u_boot_console, disk_img, '0x0000000000000004') + init_content(u_boot_console, '100000', 'u-boot.bin.old', 'Old') + place_capsule_file(u_boot_console, capsule_files) + + do_reboot_dtb_specified(u_boot_config, u_boot_console, 'test_ver.dtb') + + capsule_early = u_boot_config.buildconfig.get( + 'config_efi_capsule_on_disk_early') + with u_boot_console.log.section('Test Case 5-b, after reboot'): + if not capsule_early: + exec_manual_update(u_boot_console, disk_img, capsule_files) + + check_file_removed(u_boot_console, disk_img, capsule_files) + + verify_content(u_boot_console, '100000', 'u-boot:Old') diff --git a/test/py/tests/test_efi_capsule/version.dts b/test/py/tests/test_efi_capsule/version.dts new file mode 100644 index 0000000..07850cc --- /dev/null +++ b/test/py/tests/test_efi_capsule/version.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0+ + +/dts-v1/; +/plugin/; + +&{/} { + firmware-version { + image1 { + lowest-supported-version = <3>; + image-index = <1>; + image-type-id = "09D7CF52-0720-4710-91D1-08469B7FE9C8"; + }; + image2 { + lowest-supported-version = <7>; + image-index = <2>; + image-type-id = "5A7021F5-FEF2-48B4-AABA-832E777418C0"; + }; + image3 { + lowest-supported-version = <3>; + image-index = <1>; + image-type-id = "3673B45D-6A7C-46F3-9E60-ADABB03F7937"; + }; + }; +}; diff --git a/test/py/tests/test_efi_secboot/conftest.py b/test/py/tests/test_efi_secboot/conftest.py index 30ff702..ff7ac7c 100644 --- a/test/py/tests/test_efi_secboot/conftest.py +++ b/test/py/tests/test_efi_secboot/conftest.py @@ -14,7 +14,7 @@ def efi_boot_env(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A path to disk image to be used for testing @@ -139,7 +139,7 @@ def efi_boot_env_intca(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A path to disk image to be used for testing diff --git a/test/py/tests/test_eficonfig/conftest.py b/test/py/tests/test_eficonfig/conftest.py index f289df0..0a82fbe 100644 --- a/test/py/tests/test_eficonfig/conftest.py +++ b/test/py/tests/test_eficonfig/conftest.py @@ -14,7 +14,7 @@ def efi_eficonfig_data(u_boot_config): tests Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. Return: A path to disk image to be used for testing diff --git a/test/py/tests/test_fs/conftest.py b/test/py/tests/test_fs/conftest.py index 9329ec6..0d87d18 100644 --- a/test/py/tests/test_fs/conftest.py +++ b/test/py/tests/test_fs/conftest.py @@ -97,7 +97,7 @@ def pytest_generate_tests(metafunc): # Helper functions # def fstype_to_ubname(fs_type): - """Convert a file system type to an U-boot specific string + """Convert a file system type to an U-Boot specific string A generated string can be used as part of file system related commands or a config name in u-boot. Currently fat16 and fat32 are handled @@ -217,7 +217,7 @@ def fs_obj_basic(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for basic fs test, i.e. a triplet of file system type, @@ -339,7 +339,7 @@ def fs_obj_ext(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for extended fs test, i.e. a triplet of file system type, @@ -440,7 +440,7 @@ def fs_obj_mkdir(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for mkdir test, i.e. a duplet of file system type and @@ -471,7 +471,7 @@ def fs_obj_unlink(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for unlink test, i.e. a duplet of file system type and @@ -551,7 +551,7 @@ def fs_obj_symlink(request, u_boot_config): Args: request: Pytest request object. - u_boot_config: U-boot configuration. + u_boot_config: U-Boot configuration. Return: A fixture for basic fs test, i.e. a triplet of file system type, diff --git a/test/py/tests/test_scp03.py b/test/py/tests/test_scp03.py index 1f68925..1a104b3 100644 --- a/test/py/tests/test_scp03.py +++ b/test/py/tests/test_scp03.py @@ -5,7 +5,7 @@ # SCP03 command test """ -This tests SCP03 command in U-boot. +This tests SCP03 command in U-Boot. For additional details check doc/usage/scp03.rst """ diff --git a/test/py/tests/test_tpm2.py b/test/py/tests/test_tpm2.py index d2ad6f9..fce689c 100644 --- a/test/py/tests/test_tpm2.py +++ b/test/py/tests/test_tpm2.py @@ -41,11 +41,9 @@ def force_init(u_boot_console, force=False): skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) if skip_test: pytest.skip('skip TPM device test') - output = u_boot_console.run_command('tpm2 init') + output = u_boot_console.run_command('tpm2 autostart') if force or not 'Error' in output: u_boot_console.run_command('echo --- start of init ---') - u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR') - u_boot_console.run_command('tpm2 self_test full') u_boot_console.run_command('tpm2 clear TPM2_RH_LOCKOUT') output = u_boot_console.run_command('echo $?') if not output.endswith('0'): @@ -83,20 +81,13 @@ def tpm2_sandbox_init(u_boot_console): This allows all tests to run in parallel, since no test depends on another. """ u_boot_console.restart_uboot() - u_boot_console.run_command('tpm2 init') + u_boot_console.run_command('tpm2 autostart') output = u_boot_console.run_command('echo $?') assert output.endswith('0') skip_test = u_boot_console.config.env.get('env__tpm_device_test_skip', False) if skip_test: pytest.skip('skip TPM device test') - u_boot_console.run_command('tpm2 startup TPM2_SU_CLEAR') - output = u_boot_console.run_command('echo $?') - assert output.endswith('0') - - u_boot_console.run_command('tpm2 self_test full') - output = u_boot_console.run_command('echo $?') - assert output.endswith('0') @pytest.mark.buildconfigspec('cmd_tpm_v2') def test_tpm2_sandbox_self_test_full(u_boot_console): @@ -281,6 +272,12 @@ def test_tpm2_pcr_extend(u_boot_console): force_init(u_boot_console) ram = u_boot_utils.find_ram_base(u_boot_console) + read_pcr = u_boot_console.run_command('tpm2 pcr_read 0 0x%x' % (ram + 0x20)) + output = u_boot_console.run_command('echo $?') + assert output.endswith('0') + str = re.findall(r'\d+ known updates', read_pcr)[0] + updates = int(re.findall(r'\d+', str)[0]) + u_boot_console.run_command('tpm2 pcr_extend 0 0x%x' % ram) output = u_boot_console.run_command('echo $?') assert output.endswith('0') diff --git a/test/py/tests/test_xxd/conftest.py b/test/py/tests/test_xxd/conftest.py index 59285aa..f35b8f1 100644 --- a/test/py/tests/test_xxd/conftest.py +++ b/test/py/tests/test_xxd/conftest.py @@ -13,7 +13,7 @@ def xxd_data(u_boot_config): """Set up a file system to be used in xxd tests Args: - u_boot_config -- U-boot configuration. + u_boot_config -- U-Boot configuration. """ mnt_point = u_boot_config.persistent_data_dir + '/test_xxd' image_path = u_boot_config.persistent_data_dir + '/xxd.img' diff --git a/test/test-main.c b/test/test-main.c index b3c30d9..2a3b2ba 100644 --- a/test/test-main.c +++ b/test/test-main.c @@ -272,7 +272,7 @@ static int dm_test_restore(struct device_node *of_root) return ret; dm_scan_plat(false); if (!CONFIG_IS_ENABLED(OF_PLATDATA)) - dm_scan_fdt(false); + dm_extended_scan(false); return 0; } diff --git a/tools/.gitignore b/tools/.gitignore index cda3ea6..941d38d 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -34,6 +34,7 @@ /relocate-rela /spl_size_limit /sunxi-spl-image-builder +/tools/generated/**/*.c /update_octeon_header /version.h /xway-swap-bytes diff --git a/tools/Kconfig b/tools/Kconfig index 539708f..6e23f44 100644 --- a/tools/Kconfig +++ b/tools/Kconfig @@ -157,4 +157,13 @@ config LUT_SEQUENCE help Look Up Table Sequence +config TOOLS_MKFWUMDATA + bool "Build mkfwumdata command" + default y if FWU_MULTI_BANK_UPDATE + help + This command allows users to create a raw image of the FWU + metadata for initial installation of the FWU multi bank + update on the board. The installation method depends on + the platform. + endmenu diff --git a/tools/Makefile b/tools/Makefile index d793cf3..3d0c4b0 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -48,20 +48,20 @@ hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo HOSTCFLAGS_bmp_logo.o := -pedantic hostprogs-$(BUILD_ENVCRC) += envcrc -envcrc-objs := envcrc.o lib/crc32.o env/embedded.o lib/sha1.o +envcrc-objs := envcrc.o generated/lib/crc32.o generated/env/embedded.o generated/lib/sha1.o hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr HOSTCFLAGS_gen_eth_addr.o := -pedantic hostprogs-$(CONFIG_CMD_NET) += gen_ethaddr_crc -gen_ethaddr_crc-objs := gen_ethaddr_crc.o lib/crc8.o +gen_ethaddr_crc-objs := gen_ethaddr_crc.o generated/lib/crc8.o HOSTCFLAGS_gen_ethaddr_crc.o := -pedantic hostprogs-$(CONFIG_CMD_LOADS) += img2srec HOSTCFLAGS_img2srec.o := -pedantic hostprogs-y += mkenvimage -mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o +mkenvimage-objs := mkenvimage.o os_support.o generated/lib/crc32.o hostprogs-y += dumpimage mkimage hostprogs-$(CONFIG_TOOLS_LIBCRYPTO) += fit_info fit_check_sign @@ -71,30 +71,30 @@ ifneq ($(CONFIG_CMD_BOOTEFI_SELFTEST)$(CONFIG_FWU_MDATA_GPT_BLK),) hostprogs-y += file2include endif -FIT_OBJS-y := fit_common.o fit_image.o image-host.o boot/image-fit.o -FIT_SIG_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := image-sig-host.o boot/image-fit-sig.o -FIT_CIPHER_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := boot/image-cipher.o +FIT_OBJS-y := fit_common.o fit_image.o image-host.o generated/boot/image-fit.o +FIT_SIG_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := image-sig-host.o generated/boot/image-fit-sig.o +FIT_CIPHER_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := generated/boot/image-cipher.o # The following files are synced with upstream DTC. # Use synced versions from scripts/dtc/libfdt/. LIBFDT_OBJS := $(addprefix libfdt/, fdt.o fdt_ro.o fdt_wip.o fdt_sw.o fdt_rw.o \ fdt_strerror.o fdt_empty_tree.o fdt_addresses.o fdt_overlay.o) -RSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/rsa/, \ +RSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/rsa/, \ rsa-sign.o rsa-verify.o \ rsa-mod-exp.o) -ECDSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/ecdsa/, ecdsa-libcrypto.o) +ECDSA_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/ecdsa/, ecdsa-libcrypto.o) -AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix lib/aes/, \ +AES_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := $(addprefix generated/lib/aes/, \ aes-encrypt.o aes-decrypt.o) # Cryptographic helpers and image types that depend on openssl/libcrypto LIBCRYPTO_OBJS-$(CONFIG_TOOLS_LIBCRYPTO) := \ - lib/fdt-libcrypto.o \ + generated/lib/fdt-libcrypto.o \ sunxi_toc0.o -ROCKCHIP_OBS = lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o +ROCKCHIP_OBS = generated/lib/rc4.o rkcommon.o rkimage.o rksd.o rkspi.o # common objs for dumpimage and mkimage dumpimage-mkimage-objs := aisimage.o \ @@ -102,20 +102,20 @@ dumpimage-mkimage-objs := aisimage.o \ $(FIT_OBJS-y) \ $(FIT_SIG_OBJS-y) \ $(FIT_CIPHER_OBJS-y) \ - boot/fdt_region.o \ - boot/bootm.o \ - lib/crc32.o \ + generated/boot/fdt_region.o \ + generated/boot/bootm.o \ + generated/lib/crc32.o \ default_image.o \ - lib/fdtdec_common.o \ - lib/fdtdec.o \ - boot/image.o \ - boot/image-host.o \ + generated/lib/fdtdec_common.o \ + generated/lib/fdtdec.o \ + generated/boot/image.o \ + generated/boot/image-host.o \ imagetool.o \ imximage.o \ imx8image.o \ imx8mimage.o \ kwbimage.o \ - lib/md5.o \ + generated/lib/md5.o \ lpc32xximage.o \ mxsimage.o \ omapimage.o \ @@ -128,12 +128,12 @@ dumpimage-mkimage-objs := aisimage.o \ $(ROCKCHIP_OBS) \ socfpgaimage.o \ sunxi_egon.o \ - lib/crc16-ccitt.o \ - lib/hash-checksum.o \ - lib/sha1.o \ - lib/sha256.o \ - lib/sha512.o \ - common/hash.o \ + generated/lib/crc16-ccitt.o \ + generated/lib/hash-checksum.o \ + generated/lib/sha1.o \ + generated/lib/sha256.o \ + generated/lib/sha512.o \ + generated/common/hash.o \ ublimage.o \ zynqimage.o \ zynqmpimage.o \ @@ -213,7 +213,7 @@ HOSTCFLAGS_mxsboot.o := -pedantic hostprogs-$(CONFIG_ARCH_SUNXI) += mksunxiboot hostprogs-$(CONFIG_ARCH_SUNXI) += sunxi-spl-image-builder -sunxi-spl-image-builder-objs := sunxi-spl-image-builder.o lib/bch.o +sunxi-spl-image-builder-objs := sunxi-spl-image-builder.o generated/lib/bch.o hostprogs-$(CONFIG_NETCONSOLE) += ncb @@ -221,16 +221,16 @@ hostprogs-$(CONFIG_ARCH_KIRKWOOD) += kwboot hostprogs-$(CONFIG_ARCH_MVEBU) += kwboot hostprogs-y += proftool -proftool-objs = proftool.o lib/abuf.o +proftool-objs = proftool.o generated/lib/abuf.o hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela hostprogs-$(CONFIG_RISCV) += prelink-riscv hostprogs-$(CONFIG_ARCH_OCTEON) += update_octeon_header -update_octeon_header-objs := update_octeon_header.o lib/crc32.o +update_octeon_header-objs := update_octeon_header.o generated/lib/crc32.o hostprogs-y += fdtgrep -fdtgrep-objs += $(LIBFDT_OBJS) boot/fdt_region.o fdtgrep.o +fdtgrep-objs += $(LIBFDT_OBJS) generated/boot/fdt_region.o fdtgrep.o ifneq ($(TOOLS_ONLY),y) hostprogs-y += spl_size_limit @@ -251,6 +251,10 @@ HOSTLDLIBS_mkeficapsule += \ $(shell pkg-config --libs uuid 2> /dev/null || echo "-luuid") hostprogs-$(CONFIG_TOOLS_MKEFICAPSULE) += mkeficapsule +mkfwumdata-objs := mkfwumdata.o generated/lib/crc32.o +HOSTLDLIBS_mkfwumdata += -luuid +hostprogs-$(CONFIG_TOOLS_MKFWUMDATA) += mkfwumdata + # We build some files with extra pedantic flags to try to minimize things # that won't build on some weird host compiler -- though there are lots of # exceptions for files that aren't complaint. @@ -262,12 +266,12 @@ HOSTCFLAGS_sha256.o := -pedantic HOSTCFLAGS_sha512.o := -pedantic -DCONFIG_SHA512 -DCONFIG_SHA384 quiet_cmd_wrap = WRAP $@ -cmd_wrap = echo "\#include <../$(patsubst $(obj)/%,%,$@)>" >$@ +cmd_wrap = echo "\#include <../$(patsubst $(obj)/generated/%,%,$@)>" >$@ -$(obj)/boot/%.c $(obj)/common/%.c $(obj)/env/%.c $(obj)/lib/%.c: +$(obj)/generated/%.c: $(call cmd,wrap) -clean-dirs := lib common +clean-dirs := generated always := $(hostprogs-y) diff --git a/tools/eficapsule.h b/tools/eficapsule.h index 072a4b5..753fb73 100644 --- a/tools/eficapsule.h +++ b/tools/eficapsule.h @@ -113,4 +113,34 @@ struct efi_firmware_image_authentication { struct win_certificate_uefi_guid auth_info; } __packed; +/* fmp payload header */ +#define SIGNATURE_16(A, B) ((A) | ((B) << 8)) +#define SIGNATURE_32(A, B, C, D) \ + (SIGNATURE_16(A, B) | (SIGNATURE_16(C, D) << 16)) + +#define FMP_PAYLOAD_HDR_SIGNATURE SIGNATURE_32('M', 'S', 'S', '1') + +/** + * struct fmp_payload_header - EDK2 header for the FMP payload + * + * This structure describes the header which is preprended to the + * FMP payload by the edk2 capsule generation scripts. + * + * @signature: Header signature used to identify the header + * @header_size: Size of the structure + * @fw_version: Firmware versions used + * @lowest_supported_version: Lowest supported version (not used) + */ +struct fmp_payload_header { + uint32_t signature; + uint32_t header_size; + uint32_t fw_version; + uint32_t lowest_supported_version; +}; + +struct fmp_payload_header_params { + bool have_header; + uint32_t fw_version; +}; + #endif /* _EFI_CAPSULE_H */ diff --git a/tools/env/.gitignore b/tools/env/.gitignore index 8d28b2b..804abac 100644 --- a/tools/env/.gitignore +++ b/tools/env/.gitignore @@ -1,3 +1,2 @@ -embedded.c fw_printenv fw_printenv_unstripped diff --git a/tools/mkeficapsule.c b/tools/mkeficapsule.c index b71537b..52be1f1 100644 --- a/tools/mkeficapsule.c +++ b/tools/mkeficapsule.c @@ -41,6 +41,7 @@ static struct option options[] = { {"guid", required_argument, NULL, 'g'}, {"index", required_argument, NULL, 'i'}, {"instance", required_argument, NULL, 'I'}, + {"fw-version", required_argument, NULL, 'v'}, {"private-key", required_argument, NULL, 'p'}, {"certificate", required_argument, NULL, 'c'}, {"monotonic-count", required_argument, NULL, 'm'}, @@ -60,6 +61,7 @@ static void print_usage(void) "\t-g, --guid <guid string> guid for image blob type\n" "\t-i, --index <index> update image index\n" "\t-I, --instance <instance> update hardware instance\n" + "\t-v, --fw-version <version> firmware version\n" "\t-p, --private-key <privkey file> private key file\n" "\t-c, --certificate <cert file> signer's certificate file\n" "\t-m, --monotonic-count <count> monotonic count\n" @@ -402,6 +404,7 @@ static void free_sig_data(struct auth_context *ctx) */ static int create_fwbin(char *path, char *bin, efi_guid_t *guid, unsigned long index, unsigned long instance, + struct fmp_payload_header_params *fmp_ph_params, uint64_t mcount, char *privkey_file, char *cert_file, uint16_t oemflags) { @@ -410,10 +413,11 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid, struct efi_firmware_management_capsule_image_header image; struct auth_context auth_context; FILE *f; - uint8_t *data; + uint8_t *data, *new_data, *buf; off_t bin_size; uint64_t offset; int ret; + struct fmp_payload_header payload_header; #ifdef DEBUG fprintf(stderr, "For output: %s\n", path); @@ -423,6 +427,7 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid, auth_context.sig_size = 0; f = NULL; data = NULL; + new_data = NULL; ret = -1; /* @@ -431,12 +436,30 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid, if (read_bin_file(bin, &data, &bin_size)) goto err; + buf = data; + + /* insert fmp payload header right before the payload */ + if (fmp_ph_params->have_header) { + new_data = malloc(bin_size + sizeof(payload_header)); + if (!new_data) + goto err; + + payload_header.signature = FMP_PAYLOAD_HDR_SIGNATURE; + payload_header.header_size = sizeof(payload_header); + payload_header.fw_version = fmp_ph_params->fw_version; + payload_header.lowest_supported_version = 0; /* not used */ + memcpy(new_data, &payload_header, sizeof(payload_header)); + memcpy(new_data + sizeof(payload_header), data, bin_size); + buf = new_data; + bin_size += sizeof(payload_header); + } + /* first, calculate signature to determine its size */ if (privkey_file && cert_file) { auth_context.key_file = privkey_file; auth_context.cert_file = cert_file; auth_context.auth.monotonic_count = mcount; - auth_context.image_data = data; + auth_context.image_data = buf; auth_context.image_size = bin_size; if (create_auth_data(&auth_context)) { @@ -536,7 +559,7 @@ static int create_fwbin(char *path, char *bin, efi_guid_t *guid, /* * firmware binary */ - if (write_capsule_file(f, data, bin_size, "Firmware binary")) + if (write_capsule_file(f, buf, bin_size, "Firmware binary")) goto err; ret = 0; @@ -545,6 +568,7 @@ err: fclose(f); free_sig_data(&auth_context); free(data); + free(new_data); return ret; } @@ -644,6 +668,7 @@ int main(int argc, char **argv) unsigned long oemflags; char *privkey_file, *cert_file; int c, idx; + struct fmp_payload_header_params fmp_ph_params = { 0 }; guid = NULL; index = 0; @@ -679,6 +704,10 @@ int main(int argc, char **argv) case 'I': instance = strtoul(optarg, NULL, 0); break; + case 'v': + fmp_ph_params.fw_version = strtoul(optarg, NULL, 0); + fmp_ph_params.have_header = true; + break; case 'p': if (privkey_file) { fprintf(stderr, @@ -751,7 +780,7 @@ int main(int argc, char **argv) exit(EXIT_FAILURE); } } else if (create_fwbin(argv[argc - 1], argv[argc - 2], guid, - index, instance, mcount, privkey_file, + index, instance, &fmp_ph_params, mcount, privkey_file, cert_file, (uint16_t)oemflags) < 0) { fprintf(stderr, "Creating firmware capsule failed\n"); exit(EXIT_FAILURE); diff --git a/tools/mkfwumdata.c b/tools/mkfwumdata.c new file mode 100644 index 0000000..9732a8d --- /dev/null +++ b/tools/mkfwumdata.c @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include <errno.h> +#include <getopt.h> +#include <limits.h> +#include <stdio.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <u-boot/crc.h> +#include <unistd.h> +#include <uuid/uuid.h> + +/* This will dynamically allocate the fwu_mdata */ +#define CONFIG_FWU_NUM_BANKS 0 +#define CONFIG_FWU_NUM_IMAGES_PER_BANK 0 + +/* Since we can not include fwu.h, redefine version here. */ +#define FWU_MDATA_VERSION 1 + +typedef uint8_t u8; +typedef int16_t s16; +typedef uint16_t u16; +typedef uint32_t u32; +typedef uint64_t u64; + +#include <fwu_mdata.h> + +/* TODO: Endianness conversion may be required for some arch. */ + +static const char *opts_short = "b:i:a:p:gh"; + +static struct option options[] = { + {"banks", required_argument, NULL, 'b'}, + {"images", required_argument, NULL, 'i'}, + {"guid", required_argument, NULL, 'g'}, + {"active-bank", required_argument, NULL, 'a'}, + {"previous-bank", required_argument, NULL, 'p'}, + {"help", no_argument, NULL, 'h'}, + {NULL, 0, NULL, 0}, +}; + +static void print_usage(void) +{ + fprintf(stderr, "Usage: mkfwumdata [options] <UUIDs list> <output file>\n"); + fprintf(stderr, "Options:\n" + "\t-i, --images <num> Number of images (mandatory)\n" + "\t-b, --banks <num> Number of banks (mandatory)\n" + "\t-a, --active-bank <num> Active bank (default=0)\n" + "\t-p, --previous-bank <num> Previous active bank (default=active_bank - 1)\n" + "\t-g, --guid Use GUID instead of UUID\n" + "\t-h, --help print a help message\n" + ); + fprintf(stderr, " UUIDs list syntax:\n" + "\t <location uuid>,<image type uuid>,<images uuid list>\n" + "\t images uuid list syntax:\n" + "\t img_uuid_00,img_uuid_01...img_uuid_0b,\n" + "\t img_uuid_10,img_uuid_11...img_uuid_1b,\n" + "\t ...,\n" + "\t img_uuid_i0,img_uuid_i1...img_uuid_ib,\n" + "\t where 'b' and 'i' are number of banks and number\n" + "\t of images in a bank respectively.\n" + ); +} + +struct fwu_mdata_object { + size_t images; + size_t banks; + size_t size; + struct fwu_mdata *mdata; +}; + +static int previous_bank, active_bank; +static bool __use_guid; + +static struct fwu_mdata_object *fwu_alloc_mdata(size_t images, size_t banks) +{ + struct fwu_mdata_object *mobj; + + mobj = calloc(1, sizeof(*mobj)); + if (!mobj) + return NULL; + + mobj->size = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * banks) * images; + mobj->images = images; + mobj->banks = banks; + + mobj->mdata = calloc(1, mobj->size); + if (!mobj->mdata) { + free(mobj); + return NULL; + } + + return mobj; +} + +static struct fwu_image_entry * +fwu_get_image(struct fwu_mdata_object *mobj, size_t idx) +{ + size_t offset; + + offset = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * mobj->banks) * idx; + + return (struct fwu_image_entry *)((char *)mobj->mdata + offset); +} + +static struct fwu_image_bank_info * +fwu_get_bank(struct fwu_mdata_object *mobj, size_t img_idx, size_t bnk_idx) +{ + size_t offset; + + offset = sizeof(struct fwu_mdata) + + (sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * mobj->banks) * img_idx + + sizeof(struct fwu_image_entry) + + sizeof(struct fwu_image_bank_info) * bnk_idx; + + return (struct fwu_image_bank_info *)((char *)mobj->mdata + offset); +} + +/** + * convert_uuid_to_guid() - convert UUID to GUID + * @buf: UUID binary + * + * UUID and GUID have the same data structure, but their binary + * formats are different due to the endianness. See lib/uuid.c. + * Since uuid_parse() can handle only UUID, this function must + * be called to get correct data for GUID when parsing a string. + * + * The correct data will be returned in @buf. + */ +static void convert_uuid_to_guid(unsigned char *buf) +{ + unsigned char c; + + c = buf[0]; + buf[0] = buf[3]; + buf[3] = c; + c = buf[1]; + buf[1] = buf[2]; + buf[2] = c; + + c = buf[4]; + buf[4] = buf[5]; + buf[5] = c; + + c = buf[6]; + buf[6] = buf[7]; + buf[7] = c; +} + +static int uuid_guid_parse(char *uuidstr, unsigned char *uuid) +{ + int ret; + + ret = uuid_parse(uuidstr, uuid); + if (ret < 0) + return ret; + + if (__use_guid) + convert_uuid_to_guid(uuid); + + return ret; +} + +static int +fwu_parse_fill_image_uuid(struct fwu_mdata_object *mobj, + size_t idx, char *uuids) +{ + struct fwu_image_entry *image = fwu_get_image(mobj, idx); + struct fwu_image_bank_info *bank; + char *p = uuids, *uuid; + int i; + + if (!image) + return -ENOENT; + + /* Image location UUID */ + uuid = strsep(&p, ","); + if (!uuid) + return -EINVAL; + + if (strcmp(uuid, "0") && + uuid_guid_parse(uuid, (unsigned char *)&image->location_uuid) < 0) + return -EINVAL; + + /* Image type UUID */ + uuid = strsep(&p, ","); + if (!uuid) + return -EINVAL; + + if (uuid_guid_parse(uuid, (unsigned char *)&image->image_type_uuid) < 0) + return -EINVAL; + + /* Fill bank image-UUID */ + for (i = 0; i < mobj->banks; i++) { + bank = fwu_get_bank(mobj, idx, i); + if (!bank) + return -ENOENT; + bank->accepted = 1; + uuid = strsep(&p, ","); + if (!uuid) + return -EINVAL; + + if (strcmp(uuid, "0") && + uuid_guid_parse(uuid, (unsigned char *)&bank->image_uuid) < 0) + return -EINVAL; + } + return 0; +} + +/* Caller must ensure that @uuids[] has @mobj->images entries. */ +static int fwu_parse_fill_uuids(struct fwu_mdata_object *mobj, char *uuids[]) +{ + struct fwu_mdata *mdata = mobj->mdata; + int i, ret; + + mdata->version = FWU_MDATA_VERSION; + mdata->active_index = active_bank; + mdata->previous_active_index = previous_bank; + + for (i = 0; i < mobj->images; i++) { + ret = fwu_parse_fill_image_uuid(mobj, i, uuids[i]); + if (ret < 0) + return ret; + } + + mdata->crc32 = crc32(0, (const unsigned char *)&mdata->version, + mobj->size - sizeof(uint32_t)); + + return 0; +} + +static int +fwu_make_mdata(size_t images, size_t banks, char *uuids[], char *output) +{ + struct fwu_mdata_object *mobj; + FILE *file; + int ret; + + mobj = fwu_alloc_mdata(images, banks); + if (!mobj) + return -ENOMEM; + + ret = fwu_parse_fill_uuids(mobj, uuids); + if (ret < 0) + goto done_make; + + file = fopen(output, "w"); + if (!file) { + ret = -errno; + goto done_make; + } + + ret = fwrite(mobj->mdata, mobj->size, 1, file); + if (ret != mobj->size) + ret = -errno; + else + ret = 0; + + fclose(file); + +done_make: + free(mobj->mdata); + free(mobj); + + return ret; +} + +int main(int argc, char *argv[]) +{ + unsigned long banks = 0, images = 0; + int c, ret; + + /* Explicitly initialize defaults */ + active_bank = 0; + __use_guid = false; + previous_bank = INT_MAX; + + do { + c = getopt_long(argc, argv, opts_short, options, NULL); + switch (c) { + case 'h': + print_usage(); + return 0; + case 'b': + banks = strtoul(optarg, NULL, 0); + break; + case 'i': + images = strtoul(optarg, NULL, 0); + break; + case 'g': + __use_guid = true; + break; + case 'p': + previous_bank = strtoul(optarg, NULL, 0); + break; + case 'a': + active_bank = strtoul(optarg, NULL, 0); + break; + } + } while (c != -1); + + if (!banks || !images) { + fprintf(stderr, "Error: The number of banks and images must not be 0.\n"); + return -EINVAL; + } + + /* This command takes UUIDs * images and output file. */ + if (optind + images + 1 != argc) { + fprintf(stderr, "Error: UUID list or output file is not specified or too much.\n"); + print_usage(); + return -ERANGE; + } + + if (previous_bank == INT_MAX) { + /* set to the earlier bank in round-robin scheme */ + previous_bank = active_bank > 0 ? active_bank - 1 : banks - 1; + } + + ret = fwu_make_mdata(images, banks, argv + optind, argv[argc - 1]); + if (ret < 0) + fprintf(stderr, "Error: Failed to parse and write image: %s\n", + strerror(-ret)); + + return ret; +} diff --git a/tools/relocate-rela.c b/tools/relocate-rela.c index fe8cd6b..f230ec5 100644 --- a/tools/relocate-rela.c +++ b/tools/relocate-rela.c @@ -521,7 +521,7 @@ static int rela_elf32(char **argv, FILE *f) uint32_t pos = rela_start + sizeof(Elf32_Rela) * i; uint32_t addr, pos_dyn; - debug("\nPossition:\t%d/0x%x\n", i, pos); + debug("\nPosition:\t%d/0x%x\n", i, pos); if (fseek(f, pos, SEEK_SET) < 0) { fprintf(stderr, "%s: %s: seek to %" PRIx32 |