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| author | Jonas Karlman <jonas@kwiboo.se> | 2024-05-01 19:23:50 +0000 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2024-05-07 15:56:10 +0800 |
| commit | 94e2844c8cb38a7b35d028aa404d8c14372900cc (patch) | |
| tree | 42ea5495329276af63dc0424d134f84025338360 | |
| parent | 7c35f6d4819b5d00dba540ff27d6ac3cb8941ac6 (diff) | |
| download | u-boot-94e2844c8cb38a7b35d028aa404d8c14372900cc.zip u-boot-94e2844c8cb38a7b35d028aa404d8c14372900cc.tar.gz u-boot-94e2844c8cb38a7b35d028aa404d8c14372900cc.tar.bz2 | |
clk: rockchip: rk3328: Add SCLK_USB3OTG_REF support
The SCLK_USB3OTG_REF clocks is used as reference clock for USB3 block.
Add simple support to get rate of SCLK_USB3OTG_REF clocks to fix
reference clock period configuration.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3328.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 87075ec..314b903 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -706,6 +706,9 @@ static ulong rk3328_clk_get_rate(struct clk *clk) case PCLK_HDMIPHY: rate = rk3328_hdmiphy_get_clk(priv->cru); break; + case SCLK_USB3OTG_REF: + rate = OSC_HZ; + break; default: return -ENOENT; } @@ -780,6 +783,7 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case PCLK_DDR: case ACLK_GMAC: case PCLK_GMAC: + case SCLK_USB3OTG_REF: case SCLK_USB3OTG_SUSPEND: case USB480M: return 0; |