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| author | Christophe Leroy <christophe.leroy@csgroup.eu> | 2023-05-04 10:20:35 +0200 |
|---|---|---|
| committer | Christophe Leroy <christophe.leroy@csgroup.eu> | 2023-05-04 12:40:47 +0200 |
| commit | bebb8dfabc3af9eeca4283000571a7400cb88c71 (patch) | |
| tree | 4c413546004d4f9987ce292d63ff3846f0e02857 | |
| parent | fdd243d81bcf5e7fdc8cc7b5060c0c6ed60c5c81 (diff) | |
| download | u-boot-bebb8dfabc3af9eeca4283000571a7400cb88c71.zip u-boot-bebb8dfabc3af9eeca4283000571a7400cb88c71.tar.gz u-boot-bebb8dfabc3af9eeca4283000571a7400cb88c71.tar.bz2 | |
powerpc: mpc8xx: Reorganise init RAM
Using SMC relocation microcode patch or USB-SOF microcode patch
will disable DPRAM memory from 0x2000 to 0x2400 and from 0x2f00
to 0x3000.
At the time being, init RAM is setup to use 0x2800-0x2e00, but
the stack pointer goes beyond 0x2800 and even beyond 0x2400.
For the time being we are not going to use any microcode patch
that uses memory about 0x3000, so reorganise setup to use:
- 0x2800 - 0x2e00 for init malloc and global data and CPM buffers
- 0x3000 - 0x3c00 for init stack
For more details about CPM dual port ram, see
commit b1d62424cb ("powerpc: mpc8xx: redistribute data in CPM dpram")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
| -rw-r--r-- | arch/powerpc/cpu/mpc8xx/start.S | 8 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/cpm_8xx.h | 16 | ||||
| -rw-r--r-- | include/configs/cmpc885.h | 1 | ||||
| -rw-r--r-- | include/configs/mcr3000.h | 1 |
4 files changed, 15 insertions, 11 deletions
diff --git a/arch/powerpc/cpu/mpc8xx/start.S b/arch/powerpc/cpu/mpc8xx/start.S index 0aa73fc..7842951 100644 --- a/arch/powerpc/cpu/mpc8xx/start.S +++ b/arch/powerpc/cpu/mpc8xx/start.S @@ -141,14 +141,16 @@ in_flash: mtspr DER, r2 /* set up the stack on top of internal DPRAM */ - lis r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@h - ori r3, r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@l + lis r3, CFG_SYS_INIT_SP@h + ori r3, r3, CFG_SYS_INIT_SP@l stw r0, -4(r3) stw r0, -8(r3) addi r1, r3, -8 + lis r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@h + ori r3, r3, (CFG_SYS_INIT_RAM_ADDR + CFG_SYS_INIT_RAM_SIZE)@l + bl board_init_f_alloc_reserve - addi r1, r3, -8 /* Zeroise the CPM dpram */ lis r4, CONFIG_SYS_IMMR@h diff --git a/arch/powerpc/include/asm/cpm_8xx.h b/arch/powerpc/include/asm/cpm_8xx.h index 09c24ef..77ffcce 100644 --- a/arch/powerpc/include/asm/cpm_8xx.h +++ b/arch/powerpc/include/asm/cpm_8xx.h @@ -51,14 +51,14 @@ /* * DPRAM defines and allocation functions */ -#define CPM_SERIAL_BASE 0x1800 -#define CPM_I2C_BASE 0x1820 -#define CPM_SPI_BASE 0x1840 -#define CPM_FEC_BASE 0x1860 -#define CPM_SERIAL2_BASE 0x18e0 -#define CPM_SCC_BASE 0x1900 -#define CPM_POST_BASE 0x1980 -#define CPM_WLKBD_BASE 0x1a00 +#define CPM_SERIAL_BASE 0x0800 +#define CPM_I2C_BASE 0x0820 +#define CPM_SPI_BASE 0x0840 +#define CPM_FEC_BASE 0x0860 +#define CPM_SERIAL2_BASE 0x08E0 +#define CPM_SCC_BASE 0x0900 +#define CPM_POST_BASE 0x0980 +#define CPM_WLKBD_BASE 0x0a00 #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */ diff --git a/include/configs/cmpc885.h b/include/configs/cmpc885.h index b76230e..545365e 100644 --- a/include/configs/cmpc885.h +++ b/include/configs/cmpc885.h @@ -9,6 +9,7 @@ /* Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) #define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) +#define CFG_SYS_INIT_SP (CONFIG_SYS_IMMR + 0x3c00) /* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */ #define CFG_SYS_SDRAM_BASE 0x00000000 diff --git a/include/configs/mcr3000.h b/include/configs/mcr3000.h index 6b16b05..a07761f 100644 --- a/include/configs/mcr3000.h +++ b/include/configs/mcr3000.h @@ -14,6 +14,7 @@ /* Definitions for initial stack pointer and data area (in DPRAM) */ #define CFG_SYS_INIT_RAM_ADDR (CONFIG_SYS_IMMR + 0x2800) #define CFG_SYS_INIT_RAM_SIZE (0x2e00 - 0x2800) +#define CFG_SYS_INIT_SP (CONFIG_SYS_IMMR + 0x3c00) /* RAM configuration (note that CFG_SYS_SDRAM_BASE must be zero) */ #define CFG_SYS_SDRAM_BASE 0x00000000 |