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| author | Michael Walle <michael@walle.cc> | 2020-11-18 17:45:59 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-12-04 16:09:06 -0500 |
| commit | 8084e918bca8fa2ecf226a5eac5ea064d669b301 (patch) | |
| tree | 7dcfafae0ab9380e3fb3bdf343e9bb9524ba1c80 | |
| parent | 7b866825cd354a358eff8f62207701771e0511bd (diff) | |
| download | u-boot-8084e918bca8fa2ecf226a5eac5ea064d669b301.zip u-boot-8084e918bca8fa2ecf226a5eac5ea064d669b301.tar.gz u-boot-8084e918bca8fa2ecf226a5eac5ea064d669b301.tar.bz2 | |
armv8: layerscape: don't initialize GIC in SPL
The BL31 expects the GIC to be uninitialized. Thus, if we are loading
the BL31 by the SPL we must not initialize it. If u-boot is loaded by
the SPL directly, it will initialize the GIC again (in the same
lowlevel_init()).
This was tested on a custom board with SPL loading the BL31 and jumping
to u-boot as BL33 as well as loading u-boot directly by the SPL. In case
the ATF BL1/BL2 is used, this patch won't change anything, because no
SPL is used at all.
Signed-off-by: Michael Walle <michael@walle.cc>
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index a519f6e..d880373 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -192,6 +192,7 @@ ENTRY(lowlevel_init) #endif /* Initialize GIC Secure Bank Status */ +#if !defined(CONFIG_SPL_BUILD) #if defined(CONFIG_GICV2) || defined(CONFIG_GICV3) branch_if_slave x0, 1f bl get_gic_offset @@ -205,6 +206,7 @@ ENTRY(lowlevel_init) bl gic_init_secure_percpu #endif #endif +#endif 100: branch_if_master x0, x1, 2f |