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author | Simon Glass <sjg@chromium.org> | 2020-11-04 09:57:21 -0700 |
---|---|---|
committer | Bin Meng <bmeng.cn@gmail.com> | 2020-11-05 14:58:45 +0800 |
commit | 726310166b3585ee8a0936f88e7e1c12c3180013 (patch) | |
tree | 108dca40c66ac9013944cb1ae4c773c59d23b2d9 | |
parent | dc0791d4154614cf4f32e295f88ec1e7d5a227a1 (diff) | |
download | u-boot-726310166b3585ee8a0936f88e7e1c12c3180013.zip u-boot-726310166b3585ee8a0936f88e7e1c12c3180013.tar.gz u-boot-726310166b3585ee8a0936f88e7e1c12c3180013.tar.bz2 |
x86: coral: Drop the duplicate PCIe settings
These settings are included twice. The second lot are correct, so drop the
others.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reported-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
-rw-r--r-- | arch/x86/dts/chromebook_coral.dts | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/x86/dts/chromebook_coral.dts b/arch/x86/dts/chromebook_coral.dts index 893a59b..8801b58 100644 --- a/arch/x86/dts/chromebook_coral.dts +++ b/arch/x86/dts/chromebook_coral.dts @@ -718,8 +718,6 @@ fsps,ish-enable = <0>; fsps,enable-sata = <0>; - fsps,pcie-root-port-en = [00 00 00 00 00 01]; - fsps,pcie-rp-hot-plug = [00 00 00 00 00 01]; fsps,i2c6-enable = <I2CX_ENABLE_DISABLED>; fsps,i2c7-enable = <I2CX_ENABLE_DISABLED>; fsps,hsuart3-enable = <HSUARTX_ENABLE_DISABLED>; |