Merge branch '2021-08-05-drop-almost-all-pre-dm_pci-code'

- Remove the majority of our pre-DM_PCI PCI code as DM_PCI is true in
  almost all cases now.

71 files changed, 16 insertions, 3183 deletions

diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
index 0cf7302..15507a7 100644
--- a/.azure-pipelines.yml
+++ b/.azure-pipelines.yml
@@ -413,11 +413,11 @@ jobs:
         non_fsl_ppc:
           BUILDMAN: "powerpc -x freescale"
         mpc85xx_freescale:
-          BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t4qds -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x b4860qds -x bsc91*"
+          BUILDMAN: "mpc85xx&freescale -x t208xrdb -x t102* -x p1_p2_rdb_pc -x p1010rdb -x corenet_ds -x bsc91*"
         t208xrdb_corenet_ds:
           BUILDMAN: "t208xrdb corenet_ds"
         fsl_ppc:
-          BUILDMAN: "t4qds b4860qds mpc83xx&freescale"
+          BUILDMAN: "mpc83xx&freescale"
         t102x:
           BUILDMAN: "t102*"
         p1_p2_rdb_pc:
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index 423b715..8eb05c8 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -283,10 +283,6 @@ u32 get_ahb_clk(void)
 
 void arch_preboot_os(void)
 {
-#if defined(CONFIG_PCIE_IMX) && !CONFIG_IS_ENABLED(DM_PCI)
-	imx_pcie_remove();
-#endif
-
 #if defined(CONFIG_IMX_AHCI)
 	struct udevice *dev;
 	int rc;
diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c
index fa687d8..5357aa5 100644
--- a/arch/arm/mach-mvebu/arm64-common.c
+++ b/arch/arm/mach-mvebu/arm64-common.c
@@ -104,10 +104,9 @@ int arch_early_init_r(void)
 	/* Cause the SATA device to do its early init */
 	uclass_first_device(UCLASS_AHCI, &dev);
 
-#ifdef CONFIG_DM_PCI
 	/* Trigger PCIe devices detection */
-	pci_init();
-#endif
+	if (IS_ENABLED(CONFIG_PCI))
+		pci_init();
 
 	return 0;
 }
diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h b/arch/nds32/include/asm/arch-ag102/ag102.h
index d1f4b02..3255db6 100644
--- a/arch/nds32/include/asm/arch-ag102/ag102.h
+++ b/arch/nds32/include/asm/arch-ag102/ag102.h
@@ -11,8 +11,6 @@
  * Hardware register bases
  */
 
-/* PCI Controller */
-#define CONFIG_FTPCI100_BASE		0x90000000
 /* LPC Controller */
 #define CONFIG_LPC_IO_BASE		0x90100000
 /* LPC Controller */
diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c
index 507ab34..65ef049 100644
--- a/arch/powerpc/cpu/mpc83xx/pci.c
+++ b/arch/powerpc/cpu/mpc83xx/pci.c
@@ -27,166 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
 static struct pci_controller pci_hose[MAX_BUSES];
 static int pci_num_buses;
 
-#if !defined(CONFIG_DM_PCI)
-static void pci_init_bus(int bus, struct pci_region *reg)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile pot83xx_t *pot = immr->ios.pot;
-	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[bus];
-	struct pci_controller *hose = &pci_hose[bus];
-	u32 dev;
-	u16 reg16;
-	int i;
-
-	if (bus == 1)
-		pot += 3;
-
-	/* Setup outbound translation windows */
-	for (i = 0; i < 3; i++, reg++, pot++) {
-		if (reg->size == 0)
-			break;
-
-		hose->regions[i] = *reg;
-		hose->region_count++;
-
-		pot->potar = reg->bus_start >> 12;
-		pot->pobar = reg->phys_start >> 12;
-		pot->pocmr = ~(reg->size - 1) >> 12;
-
-		if (reg->flags & PCI_REGION_IO)
-			pot->pocmr |= POCMR_IO;
-#ifdef CONFIG_83XX_PCI_STREAMING
-		else if (reg->flags & PCI_REGION_PREFETCH)
-			pot->pocmr |= POCMR_SE;
-#endif
-
-		if (bus == 1)
-			pot->pocmr |= POCMR_DST;
-
-		pot->pocmr |= POCMR_EN;
-	}
-
-	/* Point inbound translation at RAM */
-	pci_ctrl->pitar1 = 0;
-	pci_ctrl->pibar1 = 0;
-	pci_ctrl->piebar1 = 0;
-	pci_ctrl->piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			   PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size - 1));
-
-	i = hose->region_count++;
-	hose->regions[i].bus_start = 0;
-	hose->regions[i].phys_start = 0;
-	hose->regions[i].size = gd->ram_size;
-	hose->regions[i].flags = PCI_REGION_MEM | PCI_REGION_SYS_MEMORY;
-
-	hose->first_busno = pci_last_busno() + 1;
-	hose->last_busno = 0xff;
-
-	pci_setup_indirect(hose, CONFIG_SYS_IMMR + 0x8300 + bus * 0x80,
-				 CONFIG_SYS_IMMR + 0x8304 + bus * 0x80);
-
-	pci_register_hose(hose);
-
-	/*
-	 * Write to Command register
-	 */
-	reg16 = 0xff;
-	dev = PCI_BDF(hose->first_busno, 0, 0);
-	pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
-	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
-	/*
-	 * Clear non-reserved bits in status register.
-	 */
-	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
-	pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
-	pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
-
-#ifdef CONFIG_PCI_SCAN_SHOW
-	printf("PCI:   Bus Dev VenId DevId Class Int\n");
-#endif
-#ifndef CONFIG_PCISLAVE
-	/*
-	 * Hose scan.
-	 */
-	hose->last_busno = pci_hose_scan(hose);
-#endif
-}
-
-/*
- * The caller must have already set OCCR, and the PCI_LAW BARs
- * must have been set to cover all of the requested regions.
- *
- * If fewer than three regions are requested, then the region
- * list is terminated with a region of size 0.
- */
-void mpc83xx_pci_init(int num_buses, struct pci_region **reg)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	int i;
-
-	if (num_buses > MAX_BUSES) {
-		printf("%d PCI buses requested, %d supported\n",
-		       num_buses, MAX_BUSES);
-
-		num_buses = MAX_BUSES;
-	}
-
-	pci_num_buses = num_buses;
-
-	/*
-	 * Release PCI RST Output signal.
-	 * Power on to RST high must be at least 100 ms as per PCI spec.
-	 * On warm boots only 1 ms is required, but we play it safe.
-	 */
-	udelay(100000);
-
-	for (i = 0; i < num_buses; i++)
-		immr->pci_ctrl[i].gcr = 1;
-
-	/*
-	 * RST high to first config access must be at least 2^25 cycles
-	 * as per PCI spec.  This could be cut in half if we know we're
-	 * running at 66MHz.  This could be insufficiently long if we're
-	 * running the PCI bus at significantly less than 33MHz.
-	 */
-	udelay(1020000);
-
-	for (i = 0; i < num_buses; i++)
-		pci_init_bus(i, reg[i]);
-}
-
-#ifdef CONFIG_PCISLAVE
-
-#define PCI_FUNCTION_CONFIG	0x44
-#define PCI_FUNCTION_CFG_LOCK	0x20
-
-/*
- * Unlock the configuration bit so that the host system can begin booting
- *
- * This should be used after you have:
- * 1) Called mpc83xx_pci_init()
- * 2) Set up your inbound translation windows to the appropriate size
- */
-void mpc83xx_pcislave_unlock(int bus)
-{
-	struct pci_controller *hose = &pci_hose[bus];
-	u32 dev;
-	u16 reg16;
-
-	/* Unlock configuration lock in PCI function configuration register */
-	dev = PCI_BDF(hose->first_busno, 0, 0);
-	pci_hose_read_config_word (hose, dev, PCI_FUNCTION_CONFIG, &reg16);
-	reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
-	pci_hose_write_config_word (hose, dev, PCI_FUNCTION_CONFIG, reg16);
-
-	/* The configuration bit is now unlocked, so we can scan the bus */
-	hose->last_busno = pci_hose_scan(hose);
-}
-#endif
-#endif /* CONFIG_DM_PCI */
-
 #if defined(CONFIG_OF_LIBFDT)
 void ft_pci_setup(void *blob, struct bd_info *bd)
 {
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 993e487..15248a4 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -33,7 +33,6 @@ obj-$(CONFIG_CPM2)	+= ether_fcc.o
 obj-$(CONFIG_OF_LIBFDT) += fdt.o
 obj-$(CONFIG_FSL_CORENET) += liodn.o
 obj-$(CONFIG_MP)	+= mp.o
-obj-$(CONFIG_PCI)	+= pci.o
 obj-$(CONFIG_SYS_DPAA_QBMAN) += portals.o
 
 # various SoC specific assignments
diff --git a/arch/powerpc/cpu/mpc85xx/pci.c b/arch/powerpc/cpu/mpc85xx/pci.c
deleted file mode 100644
index b7835c0..0000000
--- a/arch/powerpc/cpu/mpc85xx/pci.c
+++ /dev/null
@@ -1,191 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2004 Freescale Semiconductor.
- * Copyright (C) 2003 Motorola Inc.
- * Xianghua Xiao (x.xiao@motorola.com)
- */
-
-/*
- * PCI Configuration space access support for MPC85xx PCI Bridge
- */
-#include <common.h>
-#include <asm/bitops.h>
-#include <asm/cpm_85xx.h>
-#include <pci.h>
-
-#if !defined(CONFIG_FSL_PCI_INIT) && !defined(CONFIG_DM_PCI)
-
-#ifndef CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_BASE
-#endif
-
-#ifndef CONFIG_SYS_PCI1_IO_BUS
-#define CONFIG_SYS_PCI1_IO_BUS CONFIG_SYS_PCI1_IO_BASE
-#endif
-
-#ifndef CONFIG_SYS_PCI2_MEM_BUS
-#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI2_MEM_BASE
-#endif
-
-#ifndef CONFIG_SYS_PCI2_IO_BUS
-#define CONFIG_SYS_PCI2_IO_BUS CONFIG_SYS_PCI2_IO_BASE
-#endif
-
-static struct pci_controller *pci_hose;
-
-void
-pci_mpc85xx_init(struct pci_controller *board_hose)
-{
-	u16 reg16;
-	u32 dev;
-
-	volatile ccsr_pcix_t *pcix = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
-#ifdef CONFIG_MPC85XX_PCI2
-	volatile ccsr_pcix_t *pcix2 = (void *)(CONFIG_SYS_MPC85xx_PCIX2_ADDR);
-#endif
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct pci_controller * hose;
-
-	pci_hose = board_hose;
-
-	hose = &pci_hose[0];
-
-	hose->first_busno = 0;
-	hose->last_busno = 0xff;
-
-	pci_setup_indirect(hose,
-			   (CONFIG_SYS_IMMR+0x8000),
-			   (CONFIG_SYS_IMMR+0x8004));
-
-	/*
-	 * Hose scan.
-	 */
-	dev = PCI_BDF(hose->first_busno, 0, 0);
-	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
-	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
-	/*
-	 * Clear non-reserved bits in status register.
-	 */
-	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
-
-	if (!(gur->pordevsr & MPC85xx_PORDEVSR_PCI1)) {
-		/* PCI-X init */
-		if (CONFIG_SYS_CLK_FREQ < 66000000)
-			printf("PCI-X will only work at 66 MHz\n");
-
-		reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
-			| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
-		pci_hose_write_config_word(hose, dev, PCIX_COMMAND, reg16);
-	}
-
-	pcix->potar1   = (CONFIG_SYS_PCI1_MEM_BUS >> 12) & 0x000fffff;
-	pcix->potear1  = 0x00000000;
-	pcix->powbar1  = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & 0x000fffff;
-	pcix->powbear1 = 0x00000000;
-	pcix->powar1 = (POWAR_EN | POWAR_MEM_READ |
-			POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI1_MEM_SIZE) - 1));
-
-	pcix->potar2  = (CONFIG_SYS_PCI1_IO_BUS >> 12) & 0x000fffff;
-	pcix->potear2  = 0x00000000;
-	pcix->powbar2  = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & 0x000fffff;
-	pcix->powbear2 = 0x00000000;
-	pcix->powar2 = (POWAR_EN | POWAR_IO_READ |
-			POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI1_IO_SIZE) - 1));
-
-	pcix->pitar1 = 0x00000000;
-	pcix->piwbar1 = 0x00000000;
-	pcix->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
-			PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
-
-	pcix->powar3 = 0;
-	pcix->powar4 = 0;
-	pcix->piwar2 = 0;
-	pcix->piwar3 = 0;
-
-	pci_set_region(hose->regions + 0,
-		       CONFIG_SYS_PCI1_MEM_BUS,
-		       CONFIG_SYS_PCI1_MEM_PHYS,
-		       CONFIG_SYS_PCI1_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	pci_set_region(hose->regions + 1,
-		       CONFIG_SYS_PCI1_IO_BUS,
-		       CONFIG_SYS_PCI1_IO_PHYS,
-		       CONFIG_SYS_PCI1_IO_SIZE,
-		       PCI_REGION_IO);
-
-	hose->region_count = 2;
-
-	pci_register_hose(hose);
-
-	hose->last_busno = pci_hose_scan(hose);
-
-#ifdef CONFIG_MPC85XX_PCI2
-	hose = &pci_hose[1];
-
-	hose->first_busno = pci_hose[0].last_busno + 1;
-	hose->last_busno = 0xff;
-
-	pci_setup_indirect(hose,
-			   (CONFIG_SYS_IMMR+0x9000),
-			   (CONFIG_SYS_IMMR+0x9004));
-
-	dev = PCI_BDF(hose->first_busno, 0, 0);
-	pci_hose_read_config_word (hose, dev, PCI_COMMAND, &reg16);
-	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-	pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
-
-	/*
-	 * Clear non-reserved bits in status register.
-	 */
-	pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
-
-	pcix2->potar1   = (CONFIG_SYS_PCI2_MEM_BUS >> 12) & 0x000fffff;
-	pcix2->potear1  = 0x00000000;
-	pcix2->powbar1  = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & 0x000fffff;
-	pcix2->powbear1 = 0x00000000;
-	pcix2->powar1 = (POWAR_EN | POWAR_MEM_READ |
-			POWAR_MEM_WRITE | (__ilog2(CONFIG_SYS_PCI2_MEM_SIZE) - 1));
-
-	pcix2->potar2  = (CONFIG_SYS_PCI2_IO_BUS >> 12) & 0x000fffff;
-	pcix2->potear2  = 0x00000000;
-	pcix2->powbar2  = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & 0x000fffff;
-	pcix2->powbear2 = 0x00000000;
-	pcix2->powar2 = (POWAR_EN | POWAR_IO_READ |
-			POWAR_IO_WRITE | (__ilog2(CONFIG_SYS_PCI2_IO_SIZE) - 1));
-
-	pcix2->pitar1 = 0x00000000;
-	pcix2->piwbar1 = 0x00000000;
-	pcix2->piwar1 = (PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
-			PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP | PIWAR_MEM_2G);
-
-	pcix2->powar3 = 0;
-	pcix2->powar4 = 0;
-	pcix2->piwar2 = 0;
-	pcix2->piwar3 = 0;
-
-	pci_set_region(hose->regions + 0,
-		       CONFIG_SYS_PCI2_MEM_BUS,
-		       CONFIG_SYS_PCI2_MEM_PHYS,
-		       CONFIG_SYS_PCI2_MEM_SIZE,
-		       PCI_REGION_MEM);
-
-	pci_set_region(hose->regions + 1,
-		       CONFIG_SYS_PCI2_IO_BUS,
-		       CONFIG_SYS_PCI2_IO_PHYS,
-		       CONFIG_SYS_PCI2_IO_SIZE,
-		       PCI_REGION_IO);
-
-	hose->region_count = 2;
-
-	/*
-	 * Hose scan.
-	 */
-	pci_register_hose(hose);
-
-	hose->last_busno = pci_hose_scan(hose);
-#endif
-}
-#endif /* !CONFIG_FSL_PCI_INIT */
diff --git a/board/cavium/thunderx/thunderx.c b/board/cavium/thunderx/thunderx.c
index a7dc5c6..a8f8c78 100644
--- a/board/cavium/thunderx/thunderx.c
+++ b/board/cavium/thunderx/thunderx.c
@@ -123,10 +123,3 @@ int board_eth_init(struct bd_info *bis)
 
 	return rc;
 }
-
-#ifdef CONFIG_PCI
-void pci_init_board(void)
-{
-	printf("DEBUG: PCI Init TODO *****\n");
-}
-#endif
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 116c1e7..3a17168 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -63,7 +63,6 @@ obj-$(CONFIG_TARGET_P3041DS)		+= ics307_clk.o
 obj-$(CONFIG_TARGET_P4080DS)		+= ics307_clk.o
 obj-$(CONFIG_TARGET_P5040DS)		+= ics307_clk.o
 obj-$(CONFIG_VSC_CROSSBAR)    += vsc3316_3308.o
-obj-$(CONFIG_IDT8T49N222A)	+= idt8t49n222a_serdes_clk.o
 obj-$(CONFIG_ZM7300)		+= zm7300.o
 obj-$(CONFIG_POWER_PFUZE100)	+= pfuze.o
 obj-$(CONFIG_DM_PMIC_PFUZE100)	+= pfuze.o
diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c
index be97a28..dc2d628 100644
--- a/board/freescale/common/cds_pci_ft.c
+++ b/board/freescale/common/cds_pci_ft.c
@@ -9,68 +9,9 @@
 #include "cadmus.h"
 
 #if defined(CONFIG_OF_BOARD_SETUP)
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
-static void cds_pci_fixup(void *blob)
-{
-	int node;
-	const char *path;
-	int len, slot, i;
-	u32 *map = NULL, *piccells = NULL;
-	int off, cells;
-
-	node = fdt_path_offset(blob, "/aliases");
-	if (node >= 0) {
-		path = fdt_getprop(blob, node, "pci0", NULL);
-		if (path) {
-			node = fdt_path_offset(blob, path);
-			if (node >= 0) {
-				map = fdt_getprop_w(blob, node, "interrupt-map", &len);
-			}
-			/* Each item in "interrupt-map" property is translated with
-			 * following cells:
-			 * PCI #address-cells, PCI #interrupt-cells,
-			 * PIC address, PIC #address-cells, PIC #interrupt-cells.
-			 */
-			cells = fdt_getprop_u32_default(blob, path, "#address-cells", 1);
-			cells += fdt_getprop_u32_default(blob, path, "#interrupt-cells", 1);
-			off = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*(map+cells)));
-			if (off <= 0)
-				return;
-			cells += 1;
-			piccells = (u32 *)fdt_getprop(blob, off, "#address-cells", NULL);
-			if (piccells == NULL)
-				return;
-			cells += *piccells;
-			piccells = (u32 *)fdt_getprop(blob, off, "#interrupt-cells", NULL);
-			if (piccells == NULL)
-				return;
-			cells += *piccells;
-		}
-	}
-
-	if (map) {
-		len /= sizeof(u32);
-
-		slot = get_pci_slot();
-
-		for (i=0;i<len;i+=cells) {
-			/* We rotate the interrupt pins so that the mapping
-			 * changes depending on the slot the carrier card is in.
-			 */
-			map[3] = ((map[3] + slot - 2) % 4) + 1;
-			map+=cells;
-		}
-	}
-}
-#endif
-
 int ft_board_setup(void *blob, struct bd_info *bd)
 {
 	ft_cpu_setup(blob, bd);
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
-	ft_pci_setup(blob, bd);
-	cds_pci_fixup(blob);
-#endif
 
 	return 0;
 }
diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.c b/board/freescale/common/idt8t49n222a_serdes_clk.c
deleted file mode 100644
index bb3cdac..0000000
--- a/board/freescale/common/idt8t49n222a_serdes_clk.c
+++ /dev/null
@@ -1,208 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Author: Shaveta Leekha <shaveta@freescale.com>
- */
-
-#include "idt8t49n222a_serdes_clk.h"
-#include <log.h>
-#include <linux/delay.h>
-
-#define DEVICE_ID_REG		0x00
-
-static int check_pll_status(u8 idt_addr)
-{
-	u8 val = 0;
-	int ret;
-
-	ret = i2c_read(idt_addr, 0x17, 1, &val, 1);
-	if (ret < 0) {
-		printf("IDT:0x%x could not read status register from device.\n",
-			idt_addr);
-		return ret;
-	}
-
-	if (val & 0x04) {
-		debug("idt8t49n222a PLL is LOCKED: %x\n", val);
-	} else {
-		printf("idt8t49n222a PLL is not LOCKED: %x\n", val);
-		return -1;
-	}
-
-	return 0;
-}
-
-int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
-			enum serdes_refclk refclk1,
-			enum serdes_refclk refclk2, u8 feedback)
-{
-	u8 dev_id = 0;
-	int i, ret;
-
-	debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n",
-		idt_addr);
-
-	ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);
-	if (ret < 0) {
-		debug("IDT:0x%x could not read DEV_ID from device.\n",
-			idt_addr);
-		return ret;
-	}
-
-	if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) {
-		debug("IDT: device at address 0x%x is not idt8t49n222a.\n",
-			idt_addr);
-	}
-
-	if (serdes_num != 1 && serdes_num != 2) {
-		debug("serdes_num should be 1 for SerDes1 and"
-			" 2 for SerDes2.\n");
-		return -1;
-	}
-
-	if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88)
-		|| (refclk1 != SERDES_REFCLK_122_88
-			&& refclk2 == SERDES_REFCLK_122_88)) {
-		debug("Only one refclk at 122.88MHz is not supported."
-			" Please set both refclk1 & refclk2 to 122.88MHz"
-			" or both not to 122.88MHz.\n");
-		return -1;
-	}
-
-	if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88
-					&& refclk1 != SERDES_REFCLK_125
-					&& refclk1 != SERDES_REFCLK_156_25) {
-		debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"
-			" or 156.25MHz.\n");
-		return -1;
-	}
-
-	if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88
-					&& refclk2 != SERDES_REFCLK_125
-					&& refclk2 != SERDES_REFCLK_156_25) {
-		debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"
-			" or 156.25MHz.\n");
-		return -1;
-	}
-
-	if (feedback != 0 && feedback != 1) {
-		debug("valid values for feedback are 0(default) or 1.\n");
-		return -1;
-	}
-
-	/* Configuring IDT for output refclks as
-	 * Refclk1 = 122.88MHz  Refclk2 = 122.88MHz
-	 */
-	if (refclk1 == SERDES_REFCLK_122_88 &&
-			refclk2 == SERDES_REFCLK_122_88) {
-		printf("Setting refclk1:122.88 and refclk2:122.88\n");
-		for (i = 0; i < NUM_IDT_REGS; i++)
-			i2c_reg_write(idt_addr, idt_conf_122_88[i][0],
-						idt_conf_122_88[i][1]);
-
-		if (feedback) {
-			for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++)
-				i2c_reg_write(idt_addr,
-					idt_conf_122_88_feedback[i][0],
-					idt_conf_122_88_feedback[i][1]);
-		}
-	}
-
-	if (refclk1 != SERDES_REFCLK_122_88 &&
-			refclk2 != SERDES_REFCLK_122_88) {
-		for (i = 0; i < NUM_IDT_REGS; i++)
-			i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0],
-						idt_conf_not_122_88[i][1]);
-	}
-
-	/* Configuring IDT for output refclks as
-	 * Refclk1 = 100MHz  Refclk2 = 125MHz
-	 */
-	if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) {
-		printf("Setting refclk1:100 and refclk2:125\n");
-		i2c_reg_write(idt_addr, 0x11, 0x10);
-	}
-
-	/* Configuring IDT for output refclks as
-	 * Refclk1 = 125MHz  Refclk2 = 125MHz
-	 */
-	if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) {
-		printf("Setting refclk1:125 and refclk2:125\n");
-		i2c_reg_write(idt_addr, 0x10, 0x10);
-		i2c_reg_write(idt_addr, 0x11, 0x10);
-	}
-
-	/* Configuring IDT for output refclks as
-	 * Refclk1 = 125MHz  Refclk2 = 100MHz
-	 */
-	if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) {
-		printf("Setting refclk1:125 and refclk2:100\n");
-		i2c_reg_write(idt_addr, 0x10, 0x10);
-	}
-
-	/* Configuring IDT for output refclks as
-	 * Refclk1 = 156.25MHz  Refclk2 = 156.25MHz
-	 */
-	if (refclk1 == SERDES_REFCLK_156_25 &&
-			refclk2 == SERDES_REFCLK_156_25) {
-		printf("Setting refclk1:156.25 and refclk2:156.25\n");
-		for (i = 0; i < NUM_IDT_REGS_156_25; i++)
-			i2c_reg_write(idt_addr, idt_conf_156_25[i][0],
-						idt_conf_156_25[i][1]);
-	}
-
-	/* Configuring IDT for output refclks as
-	 * Refclk1 = 100MHz  Refclk2 = 156.25MHz
-	 */
-	if (refclk1 == SERDES_REFCLK_100 &&
-			refclk2 == SERDES_REFCLK_156_25) {
-		printf("Setting refclk1:100 and refclk2:156.25\n");
-		for (i = 0; i < NUM_IDT_REGS_156_25; i++)
-			i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0],
-						idt_conf_100_156_25[i][1]);
-	}
-
-	/* Configuring IDT for output refclks as
-	 * Refclk1 = 125MHz  Refclk2 = 156.25MHz
-	 */
-	if (refclk1 == SERDES_REFCLK_125 &&
-			refclk2 == SERDES_REFCLK_156_25) {
-		printf("Setting refclk1:125 and refclk2:156.25\n");
-		for (i = 0; i < NUM_IDT_REGS_156_25; i++)
-			i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0],
-						idt_conf_125_156_25[i][1]);
-	}
-
-	/* Configuring IDT for output refclks as
-	 * Refclk1 = 156.25MHz  Refclk2 = 100MHz
-	 */
-	if (refclk1 == SERDES_REFCLK_156_25 &&
-			refclk2 == SERDES_REFCLK_100) {
-		printf("Setting refclk1:156.25 and refclk2:100\n");
-		for (i = 0; i < NUM_IDT_REGS_156_25; i++)
-			i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0],
-						idt_conf_156_25_100[i][1]);
-	}
-
-	/* Configuring IDT for output refclks as
-	 * Refclk1 = 156.25MHz  Refclk2 = 125MHz
-	 */
-	if (refclk1 == SERDES_REFCLK_156_25 &&
-			refclk2 == SERDES_REFCLK_125) {
-		printf("Setting refclk1:156.25 and refclk2:125\n");
-		for (i = 0; i < NUM_IDT_REGS_156_25; i++)
-			i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0],
-						idt_conf_156_25_125[i][1]);
-	}
-
-	/* waiting for maximum of 1 second if PLL doesn'r get locked
-	 * initially. then check the status again.
-	 */
-	if (check_pll_status(idt_addr)) {
-		mdelay(1000);
-		if (check_pll_status(idt_addr))
-			return -1;
-	}
-
-	return 0;
-}
diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.h b/board/freescale/common/idt8t49n222a_serdes_clk.h
deleted file mode 100644
index b1528e3..0000000
--- a/board/freescale/common/idt8t49n222a_serdes_clk.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- * Author: Shaveta Leekha <shaveta@freescale.com>
- */
-
-#ifndef __IDT8T49N222A_SERDES_CLK_H_
-#define __IDT8T49N222A_SERDES_CLK_H_	1
-
-#include <common.h>
-#include <i2c.h>
-#include "qixis.h"
-#include "../b4860qds/b4860qds_qixis.h"
-#include <errno.h>
-
-#define NUM_IDT_REGS		23
-#define NUM_IDT_REGS_FEEDBACK	12
-#define NUM_IDT_REGS_156_25	11
-
-/* CLK */
-enum serdes_refclk {
-	SERDES_REFCLK_100,	/* refclk 100Mhz */
-	SERDES_REFCLK_122_88,	/* refclk 122.88Mhz */
-	SERDES_REFCLK_125,	/* refclk 125Mhz */
-	SERDES_REFCLK_156_25,	/* refclk 156.25Mhz */
-	SERDES_REFCLK_NONE = -1,
-};
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
- */
-static const u8 idt_conf_122_88[23][2] = { {0x00, 0x3C}, {0x01, 0x00},
-		{0x02, 0x9F}, {0x03, 0x00}, {0x04, 0x0B}, {0x05, 0x00},
-		{0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
-		{0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
-		{0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x12}, {0x11, 0x12},
-		{0x12, 0xB9}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
-		{0x16, 0xA0} };
-
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 not equal to 122.88MHz Refclk2 not equal to 122.88MHz
- */
-static const u8 idt_conf_not_122_88[23][2] = { {0x00, 0x00}, {0x01, 0x00},
-		{0x02, 0x00}, {0x03, 0x00}, {0x04, 0x0A}, {0x05, 0x00},
-		{0x06, 0x00}, {0x07, 0x00}, {0x08, 0x7D}, {0x09, 0x00},
-		{0x0A, 0x08}, {0x0B, 0x00}, {0x0C, 0xDC}, {0x0D, 0x00},
-		{0x0E, 0x00}, {0x0F, 0x00}, {0x10, 0x14}, {0x11, 0x14},
-		{0x12, 0x35}, {0x13, 0xBC}, {0x14, 0x40}, {0x15, 0x08},
-		{0x16, 0xA0} };
-
-/* Reconfiguration values for some of IDT registers for
- * Output Refclks:
- * Refclk1 = 122.88MHz Refclk2 = 122.88MHz
- * and with feedback as 1
- */
-static const u8 idt_conf_122_88_feedback[12][2] = { {0x00, 0x50}, {0x02, 0xD7},
-		{0x04, 0x89}, {0x06, 0xC3}, {0x08, 0xC0}, {0x0A, 0x07},
-		{0x0C, 0x80}, {0x10, 0x10}, {0x11, 0x10}, {0x12, 0x1B},
-		{0x14, 0x00}, {0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 156.25MHz Refclk2 : 156.25MHz
- */
-static const u8 idt_conf_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
-		{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
-		{0x10, 0x10}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
-		{0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 100MHz Refclk2 : 156.25MHz
- */
-static const u8 idt_conf_100_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
-		{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
-		{0x10, 0x19}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
-		{0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 125MHz Refclk2 : 156.25MHz
- */
-static const u8 idt_conf_125_156_25[11][2] = { {0x04, 0x19}, {0x06, 0x03},
-		{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
-		{0x10, 0x14}, {0x11, 0x10}, {0x12, 0xB5}, {0x13, 0x3C},
-		{0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 156.25MHz Refclk2 : 100MHz
- */
-static const u8 idt_conf_156_25_100[11][2] = { {0x04, 0x19}, {0x06, 0x03},
-		{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
-		{0x10, 0x10}, {0x11, 0x19}, {0x12, 0xB5}, {0x13, 0x3C},
-		{0x15, 0xE8} };
-
-/* configuration values for IDT registers for Output Refclks:
- * Refclk1 : 156.25MHz Refclk2 : 125MHz
- */
-static const u8 idt_conf_156_25_125[11][2] = { {0x04, 0x19}, {0x06, 0x03},
-		{0x08, 0xC0}, {0x0A, 0x07}, {0x0C, 0xA1}, {0x0E, 0x20},
-		{0x10, 0x10}, {0x11, 0x14}, {0x12, 0xB5}, {0x13, 0x3C},
-		{0x15, 0xE8} };
-
-int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
-			enum serdes_refclk refclk1,
-			enum serdes_refclk refclk2, u8 feedback);
-
-#endif	/*__IDT8T49N222A_SERDES_CLK_H_ */
diff --git a/board/freescale/common/p_corenet/Makefile b/board/freescale/common/p_corenet/Makefile
index 29c9d54..ce15601 100644
--- a/board/freescale/common/p_corenet/Makefile
+++ b/board/freescale/common/p_corenet/Makefile
@@ -4,5 +4,4 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 obj-y			+= law.o
-obj-$(CONFIG_PCI)	+= pci.o
 obj-y			+= tlb.o
diff --git a/board/freescale/common/p_corenet/pci.c b/board/freescale/common/p_corenet/pci.c
deleted file mode 100644
index 6363348..0000000
--- a/board/freescale/common/p_corenet/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2011 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index 3ddbe71..8c76c46 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -115,77 +115,4 @@ void pib_init(void)
 	i2c_set_bus_num(orig_i2c_bus);
 }
 
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-#ifndef CONFIG_MPC83XX_PCI2
-	struct pci_region *reg[] = { pci1_regions };
-#else
-	struct pci_region *reg[] = { pci1_regions, pci2_regions };
-#endif
-
-	/* initialize the PCA9555PW IO expander on the PIB board */
-	pib_init();
-
-	/* Enable all 8 PCI_CLK_OUTPUTS */
-	clk->occr = 0xff000000;
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	udelay(2000);
-
-#ifndef CONFIG_MPC83XX_PCI2
-	mpc83xx_pci_init(1, reg);
-#else
-	mpc83xx_pci_init(2, reg);
-#endif
-}
-
-#else
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
-	struct pci_region *reg[] = { pci1_regions };
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
-
-	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
-
-	mpc83xx_pci_init(1, reg);
-
-	/* Configure PCI Inbound Translation Windows (3 1MB windows) */
-	pci_ctrl->pitar0 = 0x0;
-	pci_ctrl->pibar0 = 0x0;
-	pci_ctrl->piwar0 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			   PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	pci_ctrl->pitar1  = 0x0;
-	pci_ctrl->pibar1  = 0x0;
-	pci_ctrl->piebar1 = 0x0;
-	pci_ctrl->piwar1  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	pci_ctrl->pitar2  = 0x0;
-	pci_ctrl->pibar2  = 0x0;
-	pci_ctrl->piebar2 = 0x0;
-	pci_ctrl->piwar2  = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
-			    PIWAR_WTT_SNOOP | PIWAR_IWS_1M;
-
-	/* Unlock the configuration bit */
-	mpc83xx_pcislave_unlock(0);
-	printf("PCI:   Agent mode enabled\n");
-}
 #endif /* CONFIG_PCISLAVE */
diff --git a/board/freescale/mpc837xerdb/Makefile b/board/freescale/mpc837xerdb/Makefile
index c683b01..4661e4c 100644
--- a/board/freescale/mpc837xerdb/Makefile
+++ b/board/freescale/mpc837xerdb/Makefile
@@ -4,4 +4,3 @@
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 
 obj-y += mpc837xerdb.o
-obj-$(CONFIG_PCI) += pci.o
diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c
deleted file mode 100644
index dccf8c5..0000000
--- a/board/freescale/mpc837xerdb/pci.c
+++ /dev/null
@@ -1,109 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <init.h>
-#include <mpc83xx.h>
-#include <pci.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-static struct pci_region pci_regions[] = {
-	{
-		bus_start: CONFIG_SYS_PCI_MEM_BASE,
-		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
-		size: CONFIG_SYS_PCI_MEM_SIZE,
-		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
-		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
-		size: CONFIG_SYS_PCI_MMIO_SIZE,
-		flags: PCI_REGION_MEM
-	},
-	{
-		bus_start: CONFIG_SYS_PCI_IO_BASE,
-		phys_start: CONFIG_SYS_PCI_IO_PHYS,
-		size: CONFIG_SYS_PCI_IO_SIZE,
-		flags: PCI_REGION_IO
-	}
-};
-
-static struct pci_region pcie_regions_0[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
-		.size = CONFIG_SYS_PCIE1_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-static struct pci_region pcie_regions_1[] = {
-	{
-		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
-		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
-		.flags = PCI_REGION_MEM,
-	},
-	{
-		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
-		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
-		.size = CONFIG_SYS_PCIE2_IO_SIZE,
-		.flags = PCI_REGION_IO,
-	},
-};
-
-void pci_init_board(void)
-{
-	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
-	volatile sysconf83xx_t *sysconf = &immr->sysconf;
-	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
-	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
-	volatile law83xx_t *pcie_law = sysconf->pcielaw;
-	struct pci_region *reg[] = { pci_regions };
-	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
-	u32 spridr = in_be32(&immr->sysconf.spridr);
-
-	/* Enable all 5 PCI_CLK_OUTPUTS */
-	clk->occr |= 0xf8000000;
-	udelay(2000);
-
-	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
-	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
-	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
-	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
-	mpc83xx_pci_init(1, reg);
-
-	/* There is no PEX in MPC8379 parts. */
-	if (PARTID_NO_E(spridr) == SPR_8379)
-		return;
-
-	/* Configure the clock for PCIE controller */
-	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
-				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
-
-	/* Deassert the resets in the control register */
-	out_be32(&sysconf->pecr1, 0xE0008000);
-	out_be32(&sysconf->pecr2, 0xE0008000);
-	udelay(2000);
-
-	/* Configure PCI Express Local Access Windows */
-	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
-	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
-
-	mpc83xx_pcie_init(2, pcie_reg);
-}
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index a1a9742b..cfb5b0b 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -168,113 +168,6 @@ void lbc_sdram_init(void)
 #endif	/* enable SDRAM init */
 }
 
-#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI)
-/* For some reason the Tundra PCI bridge shows up on itself as a
- * different device.  Work around that by refusing to configure it.
- */
-void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
-
-static struct pci_config_table pci_mpc85xxcds_config_table[] = {
-	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
-	{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
-	{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
-		mpc85xx_config_via_usbide, {0,0,0}},
-	{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
-		mpc85xx_config_via_usb, {0,0,0}},
-	{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
-		mpc85xx_config_via_usb2, {0,0,0}},
-	{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
-		mpc85xx_config_via_power, {0,0,0}},
-	{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
-		mpc85xx_config_via_ac97, {0,0,0}},
-	{},
-};
-
-static struct pci_controller pci1_hose;
-#endif	/* CONFIG_PCI */
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	struct fsl_pci_info pci_info;
-	u32 devdisr, pordevsr, io_sel;
-	u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
-	int first_free_busno = 0;
-	char buf[32];
-
-	devdisr = in_be32(&gur->devdisr);
-	pordevsr = in_be32(&gur->pordevsr);
-	porpllsr = in_be32(&gur->porpllsr);
-	io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
-
-	debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
-
-#ifdef CONFIG_PCI1
-	pci_speed = get_clock_freq ();	/* PCI PSPEED in [4:5] */
-	pci_32 = pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32;	/* PORDEVSR[15] */
-	pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
-	pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
-
-	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
-			(pci_32) ? 32 : 64,
-			strmhz(buf, pci_speed),
-			pci_clk_sel ? "sync" : "async",
-			pci_agent ? "agent" : "host",
-			pci_arb ? "arbiter" : "external-arbiter",
-			pci_info.regs);
-
-		pci1_hose.config_table = pci_mpc85xxcds_config_table;
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-
-#ifdef CONFIG_PCIX_CHECK
-		if (!(pordevsr & MPC85xx_PORDEVSR_PCI1)) {
-			/* PCI-X init */
-			if (CONFIG_SYS_CLK_FREQ < 66000000)
-				printf("PCI-X will only work at 66 MHz\n");
-
-			reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
-				| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
-			pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
-		}
-#endif
-	} else {
-		printf("PCI1: disabled\n");
-	}
-
-	puts("\n");
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
-#endif
-
-#ifdef CONFIG_PCI2
-{
-	uint pci2_clk_sel = porpllsr & 0x4000;	/* PORPLLSR[17] */
-	uint pci_dual = get_pci_dual ();	/* PCI DUAL in CM_PCI[3] */
-	if (pci_dual) {
-		printf("PCI2: 32 bit, 66 MHz, %s\n",
-			pci2_clk_sel ? "sync" : "async");
-	} else {
-		printf("PCI2: disabled\n");
-	}
-}
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI2); /* disable */
-#endif /* CONFIG_PCI2 */
-
-	fsl_pcie_init_board(first_free_busno);
-}
-#endif
-
 void configure_rgmii(void)
 {
 	unsigned short temp;
@@ -354,10 +247,3 @@ int board_eth_init(struct bd_info *bis)
 
 	return pci_eth_init(bis);
 }
-
-#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI)
-void ft_pci_setup(void *blob, struct bd_info *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c
index 9043633..84fc891 100644
--- a/board/freescale/p1010rdb/p1010rdb.c
+++ b/board/freescale/p1010rdb/p1010rdb.c
@@ -129,13 +129,6 @@ int board_early_init_r(void)
 	return 0;
 }
 
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif /* ifdef CONFIG_PCI */
-
 int config_board_mux(int ctrl_type)
 {
 	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -617,10 +610,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	base = env_get_bootm_low();
 	size = env_get_bootm_size();
 
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
-	FT_FSL_PCI_SETUP;
-#endif
-
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
 #if defined(CONFIG_HAS_FSL_DR_USB)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
index cf4d9c1..19ece12 100644
--- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
+++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c
@@ -239,13 +239,6 @@ int checkboard(void)
 	return 0;
 }
 
-#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-#endif
-
 int board_early_init_r(void)
 {
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
@@ -363,10 +356,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 
-#if !defined(CONFIG_DM_PCI)
-	FT_FSL_PCI_SETUP;
-#endif
-
 #ifdef CONFIG_QE
 	do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
 			sizeof("okay"), 0);
diff --git a/board/freescale/t102xrdb/Makefile b/board/freescale/t102xrdb/Makefile
index ddeb44f..e597486 100644
--- a/board/freescale/t102xrdb/Makefile
+++ b/board/freescale/t102xrdb/Makefile
@@ -10,7 +10,6 @@ else
 obj-y   += t102xrdb.o
 obj-$(CONFIG_TARGET_T1024RDB)   += cpld.o
 obj-y   += eth_t102xrdb.o
-obj-$(CONFIG_PCI)       += pci.o
 endif
 obj-y   += ddr.o
 obj-y   += law.o
diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c
deleted file mode 100644
index 45ab922..0000000
--- a/board/freescale/t102xrdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t104xrdb/Makefile b/board/freescale/t104xrdb/Makefile
index 31abbd9..d67e941 100644
--- a/board/freescale/t104xrdb/Makefile
+++ b/board/freescale/t104xrdb/Makefile
@@ -8,7 +8,6 @@ else
 obj-y	+= t104xrdb.o
 obj-y	+= cpld.o
 obj-y	+= eth.o
-obj-$(CONFIG_PCI)	+= pci.o
 obj-$(CONFIG_FSL_DIU_FB)+= diu.o
 endif
 obj-y	+= ddr.o
diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c
deleted file mode 100644
index 1fd2402..0000000
--- a/board/freescale/t104xrdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t208xqds/Makefile b/board/freescale/t208xqds/Makefile
index 55b1e73..de86130 100644
--- a/board/freescale/t208xqds/Makefile
+++ b/board/freescale/t208xqds/Makefile
@@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD
 obj-y += spl.o
 else
 obj-$(CONFIG_TARGET_T2080QDS) += t208xqds.o eth_t208xqds.o
-obj-$(CONFIG_PCI)      += pci.o
 endif
 
 obj-y   += ddr.o
diff --git a/board/freescale/t208xqds/pci.c b/board/freescale/t208xqds/pci.c
deleted file mode 100644
index a03b11c..0000000
--- a/board/freescale/t208xqds/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2013 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t208xrdb/Makefile b/board/freescale/t208xrdb/Makefile
index 25ea66a..7af3cd0 100644
--- a/board/freescale/t208xrdb/Makefile
+++ b/board/freescale/t208xrdb/Makefile
@@ -8,7 +8,6 @@ ifdef CONFIG_SPL_BUILD
 obj-y	+= spl.o
 else
 obj-$(CONFIG_TARGET_T2080RDB) += t208xrdb.o eth_t208xrdb.o cpld.o
-obj-$(CONFIG_PCI)      += pci.o
 endif
 
 obj-y   += ddr.o
diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c
deleted file mode 100644
index 45ab922..0000000
--- a/board/freescale/t208xrdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2007-2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/freescale/t4rdb/Makefile b/board/freescale/t4rdb/Makefile
index f1fd623..3106848 100644
--- a/board/freescale/t4rdb/Makefile
+++ b/board/freescale/t4rdb/Makefile
@@ -10,7 +10,6 @@ else
 obj-$(CONFIG_TARGET_T4240RDB)	+= t4240rdb.o
 obj-y			+= cpld.o
 obj-y			+= eth.o
-obj-$(CONFIG_PCI)	+= pci.o
 endif
 
 obj-y	+= ddr.o
diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c
deleted file mode 100644
index c2bc051..0000000
--- a/board/freescale/t4rdb/pci.c
+++ /dev/null
@@ -1,25 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- */
-
-#include <common.h>
-#include <command.h>
-#include <init.h>
-#include <pci.h>
-#include <asm/fsl_pci.h>
-#include <linux/libfdt.h>
-#include <fdt_support.h>
-#include <asm/fsl_serdes.h>
-
-#if !defined(CONFIG_DM_PCI)
-void pci_init_board(void)
-{
-	fsl_pcie_init_board(0);
-}
-
-void pci_of_setup(void *blob, struct bd_info *bd)
-{
-	FT_FSL_PCI_SETUP;
-}
-#endif
diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c
index 9af1f92..d2e2e4a 100644
--- a/board/imgtec/malta/malta.c
+++ b/board/imgtec/malta/malta.c
@@ -196,7 +196,6 @@ int board_fix_fdt(void *rw_fdt_blob)
 }
 #endif
 
-#if IS_ENABLED(CONFIG_DM_PCI)
 int board_early_init_r(void)
 {
 	struct udevice *dev;
@@ -243,69 +242,3 @@ int board_early_init_r(void)
 
 	return 0;
 }
-#else
-void pci_init_board(void)
-{
-	pci_dev_t bdf;
-	u32 val32;
-	u8 val8;
-
-	switch (malta_sys_con()) {
-	case SYSCON_GT64120:
-		gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
-				 0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
-				 0x10000000, 0x10000000, 128 * 1024 * 1024,
-				 0x00000000, 0x00000000, 0x20000);
-		break;
-
-	default:
-	case SYSCON_MSC01:
-		msc01_pci_init((void *)CKSEG1ADDR(MALTA_MSC01_PCI_BASE),
-			       0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
-			       MALTA_MSC01_PCIMEM_MAP,
-			       CKSEG1ADDR(MALTA_MSC01_PCIMEM_BASE),
-			       MALTA_MSC01_PCIMEM_SIZE, MALTA_MSC01_PCIIO_MAP,
-			       0x00000000, MALTA_MSC01_PCIIO_SIZE);
-		break;
-	}
-
-	bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
-			      PCI_DEVICE_ID_INTEL_82371AB_0, 0);
-	if (bdf == -1)
-		panic("Failed to find PIIX4 PCI bridge\n");
-
-	/* setup PCI interrupt routing */
-	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCA, 10);
-	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCB, 10);
-	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCC, 11);
-	pci_write_config_byte(bdf, PCI_CFG_PIIX4_PIRQRCD, 11);
-
-	/* mux SERIRQ onto SERIRQ pin */
-	pci_read_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, &val32);
-	val32 |= PCI_CFG_PIIX4_GENCFG_SERIRQ;
-	pci_write_config_dword(bdf, PCI_CFG_PIIX4_GENCFG, val32);
-
-	/* enable SERIRQ - Linux currently depends upon this */
-	pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8);
-	val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT;
-	pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8);
-
-	bdf = pci_find_device(PCI_VENDOR_ID_INTEL,
-			      PCI_DEVICE_ID_INTEL_82371AB, 0);
-	if (bdf == -1)
-		panic("Failed to find PIIX4 IDE controller\n");
-
-	/* enable bus master & IO access */
-	val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
-	pci_write_config_dword(bdf, PCI_COMMAND, val32);
-
-	/* set latency */
-	pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40);
-
-	/* enable IDE/ATA */
-	pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI,
-			       PCI_CFG_PIIX4_IDETIM_IDE);
-	pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC,
-			       PCI_CFG_PIIX4_IDETIM_IDE);
-}
-#endif
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 3444af6..3ba2fbb 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -53,7 +53,7 @@ int checkboard (void)
 	}
 	putc('\n');
 
-#if defined(CONFIG_PCI) || defined(CONFIG_DM_PCI)
+#if defined(CONFIG_PCI)
 	/* Check the PCI_clk sel bit */
 	if (in_be32(&gur->porpllsr) & (1<<15)) {
 		src = "SYSCLK";
@@ -130,9 +130,7 @@ int misc_init_r (void)
 			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 	}
 
-#if defined(CONFIG_DM_PCI)
 	pci_init();
-#endif
 
 	return 0;
 }
diff --git a/board/xes/common/fsl_8xxx_pci.c b/board/xes/common/fsl_8xxx_pci.c
index 157aa32..c1fce7d 100644
--- a/board/xes/common/fsl_8xxx_pci.c
+++ b/board/xes/common/fsl_8xxx_pci.c
@@ -14,56 +14,6 @@
 #include <linux/libfdt.h>
 #include <fdt_support.h>
 
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif
-
-void pci_init_board(void)
-{
-	int first_free_busno = 0;
-
-#ifdef CONFIG_PCI1
-	int pcie_ep;
-	struct fsl_pci_info pci_info;
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	u32 devdisr = in_be32(&gur->devdisr);
-	uint pci_spd_norm = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_SPD;
-	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
-	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
-	uint pcix = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1;
-	uint freq = CONFIG_SYS_CLK_FREQ / 1000 / 1000;
-
-	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
-			pci_32 ? 32 : 64,
-			pcix ? "PCIX" : "PCI",
-			pci_spd_norm ? ">=" : "<=",
-			pcix ? freq * 2 : freq,
-			pcie_ep ? "agent" : "host",
-			pci_arb ? "arbiter" : "external-arbiter");
-
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-	} else {
-		printf("PCI1: disabled\n");
-	}
-#elif defined CONFIG_ARCH_MPC8548
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	/* PCI1 not present on MPC8572 */
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
-#endif
-
-	fsl_pcie_init_board(first_free_busno);
-}
-
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_pci_setup(void *blob, struct bd_info *bd)
 {
diff --git a/cmd/pci.c b/cmd/pci.c
index 22de942..af75a6c 100644
--- a/cmd/pci.c
+++ b/cmd/pci.c
@@ -47,7 +47,6 @@ static int pci_field_width(enum pci_size_t size)
 	return pci_byte_size(size) * 2;
 }
 
-#ifdef CONFIG_DM_PCI
 static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
 {
 	for (; regs->name; regs++) {
@@ -59,40 +58,7 @@ static void pci_show_regs(struct udevice *dev, struct pci_reg_info *regs)
 		       pci_field_width(regs->size), val);
 	}
 }
-#else
-static unsigned long pci_read_config(pci_dev_t dev, int offset,
-				     enum pci_size_t size)
-{
-	u32 val32;
-	u16 val16;
-	u8 val8;
 
-	switch (size) {
-	case PCI_SIZE_8:
-		pci_read_config_byte(dev, offset, &val8);
-		return val8;
-	case PCI_SIZE_16:
-		pci_read_config_word(dev, offset, &val16);
-		return val16;
-	case PCI_SIZE_32:
-	default:
-		pci_read_config_dword(dev, offset, &val32);
-		return val32;
-	}
-}
-
-static void pci_show_regs(pci_dev_t dev, struct pci_reg_info *regs)
-{
-	for (; regs->name; regs++) {
-		printf("  %s =%*s%#.*lx\n", regs->name,
-		       (int)(28 - strlen(regs->name)), "",
-		       pci_field_width(regs->size),
-		       pci_read_config(dev, regs->offset, regs->size));
-	}
-}
-#endif
-
-#ifdef CONFIG_DM_PCI
 int pci_bar_show(struct udevice *dev)
 {
 	u8 header_type;
@@ -162,7 +128,6 @@ int pci_bar_show(struct udevice *dev)
 
 	return 0;
 }
-#endif
 
 static struct pci_reg_info regs_start[] = {
 	{ "vendor ID", PCI_SIZE_16, PCI_VENDOR_ID },
@@ -258,23 +223,12 @@ static struct pci_reg_info regs_cardbus[] = {
  *
  * @dev: Bus+Device+Function number
  */
-#ifdef CONFIG_DM_PCI
 void pci_header_show(struct udevice *dev)
-#else
-void pci_header_show(pci_dev_t dev)
-#endif
 {
-#ifdef CONFIG_DM_PCI
 	unsigned long class, header_type;
 
 	dm_pci_read_config(dev, PCI_CLASS_CODE, &class, PCI_SIZE_8);
 	dm_pci_read_config(dev, PCI_HEADER_TYPE, &header_type, PCI_SIZE_8);
-#else
-	u8 class, header_type;
-
-	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
-	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
-#endif
 	pci_show_regs(dev, regs_start);
 	printf("  class code =                  0x%.2x (%s)\n", (int)class,
 	       pci_class_str(class));
@@ -307,7 +261,6 @@ void pciinfo_header(int busnum, bool short_listing)
 	}
 }
 
-#ifdef CONFIG_DM_PCI
 /**
  * pci_header_show_brief() - Show the short-form PCI device header
  *
@@ -355,102 +308,6 @@ static void pciinfo(struct udevice *bus, bool short_listing)
 	}
 }
 
-#else
-
-/**
- * pci_header_show_brief() - Show the short-form PCI device header
- *
- * Reads and prints the header of the specified PCI device in short form.
- *
- * @dev: Bus+Device+Function number
- */
-void pci_header_show_brief(pci_dev_t dev)
-{
-	u16 vendor, device;
-	u8 class, subclass;
-
-	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
-	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
-	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
-	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
-
-	printf("0x%.4x     0x%.4x     %-23s 0x%.2x\n",
-	       vendor, device,
-	       pci_class_str(class), subclass);
-}
-
-/**
- * pciinfo() - Show a list of devices on the PCI bus
- *
- * Show information about devices on PCI bus. Depending on @short_pci_listing
- * the output will be more or less exhaustive.
- *
- * @bus_num: The number of the bus to be scanned
- * @short_pci_listing: true to use short form, showing only a brief header
- * for each device
- */
-void pciinfo(int bus_num, int short_pci_listing)
-{
-	struct pci_controller *hose = pci_bus_to_hose(bus_num);
-	int device;
-	int function;
-	unsigned char header_type;
-	unsigned short vendor_id;
-	pci_dev_t dev;
-	int ret;
-
-	if (!hose)
-		return;
-
-	pciinfo_header(bus_num, short_pci_listing);
-
-	for (device = 0; device < PCI_MAX_PCI_DEVICES; device++) {
-		header_type = 0;
-		vendor_id = 0;
-		for (function = 0; function < PCI_MAX_PCI_FUNCTIONS;
-		     function++) {
-			/*
-			 * If this is not a multi-function device, we skip
-			 * the rest.
-			 */
-			if (function && !(header_type & 0x80))
-				break;
-
-			dev = PCI_BDF(bus_num, device, function);
-
-			if (pci_skip_dev(hose, dev))
-				continue;
-
-			ret = pci_read_config_word(dev, PCI_VENDOR_ID,
-						   &vendor_id);
-			if (ret)
-				goto error;
-			if ((vendor_id == 0xFFFF) || (vendor_id == 0x0000))
-				continue;
-
-			if (!function) {
-				pci_read_config_byte(dev, PCI_HEADER_TYPE,
-						     &header_type);
-			}
-
-			if (short_pci_listing) {
-				printf("%02x.%02x.%02x   ", bus_num, device,
-				       function);
-				pci_header_show_brief(dev);
-			} else {
-				printf("\nFound PCI device %02x.%02x.%02x:\n",
-				       bus_num, device, function);
-				pci_header_show(dev);
-			}
-		}
-	}
-
-	return;
-error:
-	printf("Cannot read bus configuration: %d\n", ret);
-}
-#endif
-
 /**
  * get_pci_dev() - Convert the "bus.device.function" identifier into a number
  *
@@ -482,13 +339,8 @@ static pci_dev_t get_pci_dev(char *name)
 	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
 }
 
-#ifdef CONFIG_DM_PCI
 static int pci_cfg_display(struct udevice *dev, ulong addr,
 			   enum pci_size_t size, ulong length)
-#else
-static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
-			   ulong length)
-#endif
 {
 #define DISP_LINE_LEN	16
 	ulong i, nbytes, linebytes;
@@ -509,11 +361,7 @@ static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
 		for (i = 0; i < linebytes; i += byte_size) {
 			unsigned long val;
 
-#ifdef CONFIG_DM_PCI
 			dm_pci_read_config(dev, addr, &val, size);
-#else
-			val = pci_read_config(bdf, addr, size);
-#endif
 			printf(" %0*lx", pci_field_width(size), val);
 			addr += byte_size;
 		}
@@ -528,31 +376,8 @@ static int pci_cfg_display(pci_dev_t bdf, ulong addr, enum pci_size_t size,
 	return (rc);
 }
 
-#ifndef CONFIG_DM_PCI
-static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
-{
-	if (size == 4) {
-		pci_write_config_dword(bdf, addr, value);
-	}
-	else if (size == 2) {
-		ushort val = value & 0xffff;
-		pci_write_config_word(bdf, addr, val);
-	}
-	else {
-		u_char val = value & 0xff;
-		pci_write_config_byte(bdf, addr, val);
-	}
-	return 0;
-}
-#endif
-
-#ifdef CONFIG_DM_PCI
 static int pci_cfg_modify(struct udevice *dev, ulong addr, ulong size,
 			  ulong value, int incrflag)
-#else
-static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
-			  int incrflag)
-#endif
 {
 	ulong	i;
 	int	nbytes;
@@ -563,11 +388,7 @@ static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
 	 */
 	do {
 		printf("%08lx:", addr);
-#ifdef CONFIG_DM_PCI
 		dm_pci_read_config(dev, addr, &val, size);
-#else
-		val = pci_read_config(bdf, addr, size);
-#endif
 		printf(" %0*lx", pci_field_width(size), val);
 
 		nbytes = cli_readline(" ? ");
@@ -594,11 +415,7 @@ static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
 				/* good enough to not time out
 				 */
 				bootretry_reset_cmd_timeout();
-#ifdef CONFIG_DM_PCI
 				dm_pci_write_config(dev, addr, i, size);
-#else
-				pci_cfg_write(bdf, addr, size, i);
-#endif
 				if (incrflag)
 					addr += size;
 			}
@@ -608,7 +425,6 @@ static int pci_cfg_modify(pci_dev_t bdf, ulong addr, ulong size, ulong value,
 	return 0;
 }
 
-#ifdef CONFIG_DM_PCI
 static const struct pci_flag_info {
 	uint flag;
 	const char *name;
@@ -647,7 +463,6 @@ static void pci_show_regions(struct udevice *bus)
 		printf("\n");
 	}
 }
-#endif
 
 /* PCI Configuration Space access commands
  *
@@ -661,11 +476,7 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 {
 	ulong addr = 0, value = 0, cmd_size = 0;
 	enum pci_size_t size = PCI_SIZE_32;
-#ifdef CONFIG_DM_PCI
 	struct udevice *dev, *bus;
-#else
-	pci_dev_t dev;
-#endif
 	int busnum = 0;
 	pci_dev_t bdf = 0;
 	char cmd = 's';
@@ -687,19 +498,15 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 		if (argc > 4)
 			value = hextoul(argv[4], NULL);
 	case 'h':		/* header */
-#ifdef CONFIG_DM_PCI
 	case 'b':		/* bars */
-#endif
 		if (argc < 3)
 			goto usage;
 		if ((bdf = get_pci_dev(argv[2])) == -1)
 			return 1;
 		break;
-#if defined(CONFIG_DM_PCI)
 	case 'e':
 		pci_init();
 		return 0;
-#endif
 	case 'r': /* no break */
 	default:		/* scan bus */
 		value = 1; /* short listing */
@@ -711,7 +518,6 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 			if (argc > 1)
 				busnum = hextoul(argv[1], NULL);
 		}
-#ifdef CONFIG_DM_PCI
 		ret = uclass_get_device_by_seq(UCLASS_PCI, busnum, &bus);
 		if (ret) {
 			printf("No such bus\n");
@@ -721,21 +527,14 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 			pci_show_regions(bus);
 		else
 			pciinfo(bus, value);
-#else
-		pciinfo(busnum, value);
-#endif
 		return 0;
 	}
 
-#ifdef CONFIG_DM_PCI
 	ret = dm_pci_bus_find_bdf(bdf, &dev);
 	if (ret) {
 		printf("No such device\n");
 		return CMD_RET_FAILURE;
 	}
-#else
-	dev = bdf;
-#endif
 
 	switch (argv[1][0]) {
 	case 'h':		/* header */
@@ -756,17 +555,10 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 	case 'w':		/* write */
 		if (argc < 5)
 			goto usage;
-#ifdef CONFIG_DM_PCI
 		ret = dm_pci_write_config(dev, addr, value, size);
-#else
-		ret = pci_cfg_write(dev, addr, size, value);
-#endif
 		break;
-#ifdef CONFIG_DM_PCI
-
 	case 'b':		/* bars */
 		return pci_bar_show(dev);
-#endif
 	default:
 		ret = CMD_RET_USAGE;
 		break;
@@ -783,18 +575,14 @@ static int do_pci(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
 static char pci_help_text[] =
 	"[bus] [long]\n"
 	"    - short or long list of PCI devices on bus 'bus'\n"
-#if defined(CONFIG_DM_PCI)
 	"pci enum\n"
 	"    - Enumerate PCI buses\n"
-#endif
 	"pci header b.d.f\n"
 	"    - show header of PCI device 'bus.device.function'\n"
-#ifdef CONFIG_DM_PCI
 	"pci bar b.d.f\n"
 	"    - show BARs base and size for device b.d.f'\n"
 	"pci regions\n"
 	"    - show PCI regions\n"
-#endif
 	"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
 	"    - display PCI configuration space (CFG)\n"
 	"pci next[.b, .w, .l] b.d.f address\n"
diff --git a/doc/board/freescale/b4860qds.rst b/doc/board/freescale/b4860qds.rst
deleted file mode 100644
index de14d85..0000000
--- a/doc/board/freescale/b4860qds.rst
+++ /dev/null
@@ -1,453 +0,0 @@
-.. SPDX-License-Identifier: GPL-2.0+
-
-B4860QDS
-========
-
-The B4860QDS is a Freescale reference board that hosts the B4860 SoC
-(and variants).
-
-B4860 Overview
---------------
-The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
-StarCore and Power Architecture® cores. It targets the broadband wireless
-infrastructure and builds upon the proven success of the existing multicore
-DSPs and Power CPUs. It is designed to bolster the rapidly changing and
-expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
-
-The B4860 is a highly-integrated StarCore and Power Architecture processor that
-contains:
-
-* Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
-  clusters-each core runs up to 1.2 GHz, with an architecture highly optimized
-  for wireless base station applications
-* Four dual-thread e6500 Power Architecture processors organized in one
-  cluster-each core runs up to 1.8 GHz
-* Two DDR3/3L controllers for high-speed, industry-standard memory interface
-  each runs at up to 1866.67 MHz
-* MAPLE-B3 hardware acceleration-for forward error correction schemes including
-  Turbo or Viterbi decoding, Turbo encoding and rate matching, MIMO MMSE
-  equalization scheme, matrix operations, CRC insertion and check, DFT/iDFT and
-  FFT/iFFT calculations, PUSCH/PDSCH acceleration, and UMTS chip rate
-  acceleration
-* CoreNet fabric that fully supports coherency using MESI protocol between the
-  e6500 cores, SC3900 FVP cores, memories and external interfaces.
-  CoreNet fabric interconnect runs at 667 MHz and supports coherent and
-  non-coherent out of order transactions with prioritization and bandwidth
-  allocation amongst CoreNet endpoints.
-* Data Path Acceleration Architecture, which includes the following:
-
-     * Frame Manager (FMan), which supports in-line packet parsing and general
-       classification to enable policing and QoS-based packet distribution
-     * Queue Manager (QMan) and Buffer Manager (BMan), which allow offloading
-       of queue management, task management, load distribution, flow ordering,
-       buffer management, and allocation tasks from the cores
-     * Security engine (SEC 5.3)-crypto-acceleration for protocols such as
-       IPsec, SSL, and 802.16
-     * RapidIO manager (RMAN) - Support SRIO types 8, 9, 10, and 11 (inbound
-       and outbound). Supports types 5, 6 (outbound only)
-
-* Large internal cache memory with snooping and stashing capabilities for
-  bandwidth saving and high utilization of processor elements. The 9856-Kbyte
-  internal memory space includes the following:
-
-     * 32 Kbyte L1 ICache per e6500/SC3900 core
-     * 32 Kbyte L1 DCache per e6500/SC3900 core
-     * 2048 Kbyte unified L2 cache for each SC3900 FVP cluster
-     * 2048 Kbyte unified L2 cache for the e6500 cluster
-     * Two 512 Kbyte shared L3 CoreNet platform caches (CPC)
-
-* Sixteen 10-GHz SerDes lanes serving:
-
-     * Two Serial RapidIO interfaces
-     * Each supports up to 4 lanes and a total of up to 8 lanes
-
-* Up to 8-lanes Common Public Radio Interface (CPRI) controller for
-  glue-less antenna connection
-* Two 10-Gbit Ethernet controllers (10GEC)
-* Six 1G/2.5-Gbit Ethernet controllers for network communications
-* PCI Express controller
-* Debug (Aurora)
-* Two OCeaN DMAs
-* Various system peripherals
-* 182 32-bit timers
-
-B4860QDS Overview
------------------
-- DDRC1: Ten separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
-  ECC, 4 GB of memory in two ranks of 2 GB.
-- DDRC2: Five separate DDR3 parts of 16-bit to support 72-bit (ECC) at 1866MT/s,
-  ECC, 2 GB of memory. Single rank.
-- SerDes 1 multiplexing: Two Vitesse (transmit and receive path) cross-point
-  16x16 switch VSC3316
-- SerDes 2 multiplexing: Two Vitesse (transmit and receive path) cross-point
-  8x8 switch VSC3308
-- USB 2.0 ULPI PHY USB3315 by SMSC supports USB port in host mode.
-  B4860 UART port is available over USB-to-UART translator USB2SER or over
-  RS232 flat cable.
-- A Vitesse dual SGMII phy VSC8662 links the B4860 SGMII lines to 2xRJ-45
-  copper connectors for Stand-alone mode and to the 1000Base-X over AMC
-  MicroTCA connector ports 0 and 2 for AMC mode.
-- The B4860 configuration may be loaded from nine bits coded reset configuration
-  reset source. The RCW source is set by appropriate DIP-switches.
-- 16-bit NOR Flash / PROMJet
-- QIXIS 8-bit NOR Flash Emulator
-- 8-bit NAND Flash
-- 24-bit SPI Flash
-- Long address I2C EEPROM
-- Available debug interfaces are:
-
-     - On-board eCWTAP controller with ETH and USB I/F
-     - JTAG/COP 16-pin header for any external TAP controller
-     - External JTAG source over AMC to support B2B configuration
-     - 70-pin Aurora debug connector
-
-- QIXIS (FPGA) logic:
-     - 2 KB internal memory space including
-
-- IDT840NT4 clock synthesizer provides B4860 essential clocks : SYSCLK,
-  DDRCLK1,2 and RTCCLK.
-- Two 8T49N222A SerDes ref clock devices support two SerDes port clock
-  frequency - total four refclk, including CPRI clock scheme.
-
-
-B4420 Personality
------------------
-
-B4420 is a reduced personality of B4860 with less core/clusters(both SC3900
-and e6500), less DDR controllers, less serdes lanes, less SGMII interfaces
-and reduced target frequencies.
-
-Key differences between B4860 and B4420
----------------------------------------
-
-B4420 has:
-
-1. Less e6500 cores: 1 cluster with 2 e6500 cores
-2. Less SC3900 cores/clusters: 1 cluster with 2 SC3900 cores per cluster
-3. Single DDRC
-4. 2X 4 lane serdes
-5. 3 SGMII interfaces
-6. no sRIO
-7. no 10G
-
-B4860QDS Default Settings
--------------------------
-
-Switch Settings
-^^^^^^^^^^^^^^^
-
-.. code-block:: none
-
-   SW1	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]
-   SW2	ON	ON	ON	ON	ON	ON	OFF	OFF
-   SW3	OFF	OFF	OFF	ON	OFF	OFF	ON	OFF
-   SW5	OFF	OFF	OFF	OFF	OFF	OFF	ON	ON
-
-Note:
-
-- PCIe slots modes: All the PCIe devices work as Root Complex.
-- Boot location: NOR flash.
-
-SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
-66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
-
-NAND boot::
-
-	SW1 [1.1] = 0
-	SW2 [1.1] = 1
-	SW3 [1:4] = 0001
-
-NOR boot::
-
-	SW1 [1.1] = 1
-	SW2 [1.1] = 0
-	SW3 [1:4] = 1000
-
-B4420QDS Default Settings
--------------------------
-
-Switch Settings
-^^^^^^^^^^^^^^^
-
-.. code-block:: none
-
-   SW1	OFF[0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]	OFF [0]
-   SW2	ON	OFF	ON	OFF	ON	ON	OFF	OFF
-   SW3	OFF	OFF	OFF	ON	OFF	OFF	ON	OFF
-   SW5	OFF	OFF	OFF	OFF	OFF	OFF	ON	ON
-
-Note:
-
-- PCIe slots modes: All the PCIe devices work as Root Complex.
-- Boot location: NOR flash.
-
-SysClk/Core(e6500)/CCB/DDR/FMan/DDRCLK/StarCore/CPRI-Maple/eTVPE-Maple/ULB-Maple
-66MHz/1.6GHz/667MHz/1.6GHz data rate/667MHz/133MHz/1200MHz/500MHz/800MHz/667MHz
-
-NAND boot::
-
-	SW1 [1.1] = 0
-	SW2 [1.1] = 1
-	SW3 [1:4] = 0001
-
-NOR boot::
-
-	SW1 [1.1] = 1
-	SW2 [1.1] = 0
-	SW3 [1:4] = 1000
-
-Memory map on B4860QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-=============   =============   =============== =======
-Start Address	End Address	Description	Size
-=============   =============   =============== =======
-0xF_FFDF_1000 	0xF_FFFF_FFFF	Free		2 MB
-0xF_FFDF_0000 	0xF_FFDF_0FFF	IFC - FPGA 	4 KB
-0xF_FF81_0000 	0xF_FFDE_FFFF	Free		5 MB
-0xF_FF80_0000	0xF_FF80_FFFF	IFC NAND Flash	64 KB
-0xF_FF00_0000	0xF_FF7F_FFFF	Free		8 MB
-0xF_FE00_0000 	0xF_FEFF_FFFF	CCSRBAR		16 MB
-0xF_F801_0000 	0xF_FDFF_FFFF	Free		95 MB
-0xF_F800_0000	0xF_F800_FFFF	PCIe I/O Space 	64 KB
-0xF_F600_0000 	0xF_F7FF_FFFF	QMAN s/w portal	32 MB
-0xF_F400_0000 	0xF_F5FF_FFFF	BMAN s/w portal	32 MB
-0xF_F000_0000 	0xF_F3FF_FFFF	Free		64 MB
-0xF_E800_0000 	0xF_EFFF_FFFF	IFC  NOR Flash 	128 MB
-0xF_E000_0000	0xF_E7FF_FFFF	Promjet		128 MB
-0xF_A0C0_0000 	0xF_DFFF_FFFF	Free		1012 MB
-0xF_A000_0000 	0xF_A0BF_FFFF	MAPLE0/1/2	12 MB
-0xF_0040_0000 	0xF_9FFF_FFFF	Free		12 GB
-0xF_0000_0000 	0xF_01FF_FFFF	DCSR		32 MB
-0xC_4000_0000 	0xE_FFFF_FFFF	Free		11 GB
-0xC_3000_0000 	0xC_3FFF_FFFF	sRIO-2 I/O 	256 MB
-0xC_2000_0000 	0xC_2FFF_FFFF	sRIO-1 I/O  	256 MB
-0xC_0000_0000	0xC_1FFF_FFFF	PCIe Mem Space 	512 MB
-0x1_0000_0000 	0xB_FFFF_FFFF	Free		44 GB
-0x0_8000_0000 	0x0_FFFF_FFFF	DDRC1		2 GB
-0x0_0000_0000 	0x0_7FFF_FFFF	DDRC2	  	2 GB
-=============   =============   =============== =======
-
-Memory map on B4420QDS
-----------------------
-The addresses in brackets are physical addresses.
-
-=============   =============   =============== =======
-Start Address	End Address	Description	Size
-=============   =============   =============== =======
-0xF_FFDF_1000 	0xF_FFFF_FFFF	Free		2 MB
-0xF_FFDF_0000 	0xF_FFDF_0FFF	IFC - FPGA 	4 KB
-0xF_FF81_0000 	0xF_FFDE_FFFF	Free		5 MB
-0xF_FF80_0000	0xF_FF80_FFFF	IFC NAND Flash	64 KB
-0xF_FF00_0000	0xF_FF7F_FFFF	Free		8 MB
-0xF_FE00_0000 	0xF_FEFF_FFFF	CCSRBAR		16 MB
-0xF_F801_0000 	0xF_FDFF_FFFF	Free		95 MB
-0xF_F800_0000	0xF_F800_FFFF	PCIe I/O Space 	64 KB
-0xF_F600_0000 	0xF_F7FF_FFFF	QMAN s/w portal	32 MB
-0xF_F400_0000 	0xF_F5FF_FFFF	BMAN s/w portal	32 MB
-0xF_F000_0000 	0xF_F3FF_FFFF	Free		64 MB
-0xF_E800_0000 	0xF_EFFF_FFFF	IFC  NOR Flash 	128 MB
-0xF_E000_0000	0xF_E7FF_FFFF	Promjet		128 MB
-0xF_A0C0_0000 	0xF_DFFF_FFFF	Free		1012 MB
-0xF_A000_0000 	0xF_A0BF_FFFF	MAPLE0/1/2	12 MB
-0xF_0040_0000 	0xF_9FFF_FFFF	Free		12 GB
-0xF_0000_0000 	0xF_01FF_FFFF	DCSR		32 MB
-0xC_4000_0000 	0xE_FFFF_FFFF	Free		11 GB
-0xC_3000_0000 	0xC_3FFF_FFFF	sRIO-2 I/O 	256 MB
-0xC_2000_0000 	0xC_2FFF_FFFF	sRIO-1 I/O  	256 MB
-0xC_0000_0000	0xC_1FFF_FFFF	PCIe Mem Space 	512 MB
-0x1_0000_0000 	0xB_FFFF_FFFF	Free		44 GB
-0x0_0000_0000 	0x0_FFFF_FFFF	DDRC1		4 GB
-=============   =============   =============== =======
-
-NOR Flash memory Map on B4860 and B4420QDS
-------------------------------------------
-
-=============   =============   ==============================  =========
- Start		 End		Definition			Size
-=============   =============   ==============================  =========
-0xEFF40000	0xEFFFFFFF	U-Boot (current bank)		768KB
-0xEFF20000	0xEFF3FFFF	U-Boot env (current bank)	128KB
-0xEFF00000	0xEFF1FFFF	FMAN Ucode (current bank)	128KB
-0xEF300000	0xEFEFFFFF	rootfs (alternate bank)		12MB
-0xEE800000	0xEE8FFFFF	device tree (alternate bank)	1MB
-0xEE020000	0xEE6FFFFF	Linux.uImage (alternate bank)	6MB+896KB
-0xEE000000	0xEE01FFFF	RCW (alternate bank)		128KB
-0xEDF40000	0xEDFFFFFF	U-Boot (alternate bank)		768KB
-0xEDF20000	0xEDF3FFFF	U-Boot env (alternate bank)	128KB
-0xEDF00000	0xEDF1FFFF	FMAN ucode (alternate bank)	128KB
-0xED300000	0xEDEFFFFF	rootfs (current bank)		12MB
-0xEC800000	0xEC8FFFFF	device tree (current bank)	1MB
-0xEC020000	0xEC6FFFFF	Linux.uImage (current bank)	6MB+896KB
-0xEC000000	0xEC01FFFF	RCW (current bank)		128KB
-=============   =============   ==============================  =========
-
-Various Software configurations/environment variables/commands
---------------------------------------------------------------
-The below commands apply to both B4860QDS and B4420QDS.
-
-U-Boot environment variable hwconfig
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-The default hwconfig is:
-
-.. code-block:: none
-
-   hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;usb1:dr_mode=host,phy_type=ulpi
-
-Note: For USB gadget set "dr_mode=peripheral"
-
-FMAN Ucode versions
-^^^^^^^^^^^^^^^^^^^
-
-fsl_fman_ucode_B4860_106_3_6.bin
-
-Switching to alternate bank
-^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Commands for switching to alternate bank.
-
-1. To change from vbank0 to vbank2
-
-.. code-block:: none
-
-   => qixis_reset altbank (it will boot using vbank2)
-
-2. To change from vbank2 to vbank0
-
-.. code-block:: none
-
-   => qixis reset (it will boot using vbank0)
-
-To change personality of board
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-For changing personality from B4860 to B4420
-
-1. Boot from vbank0
-2. Flash vbank2 with b4420 rcw and U-Boot
-3. Give following commands to uboot prompt
-
-.. code-block:: none
-
-   => mw.b ffdf0040 0x30;
-   => mw.b ffdf0010 0x00;
-   => mw.b ffdf0062 0x02;
-   => mw.b ffdf0050 0x02;
-   => mw.b ffdf0010 0x30;
-   => reset
-
-Note:
-
-- Power off cycle will lead to default switch settings.
-- 0xffdf0000 is the address of the QIXIS FPGA.
-
-Switching between NOR and NAND boot(RCW src changed from NOR <-> NAND)
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-To change from NOR to NAND boot give following command on uboot prompt
-
-.. code-block:: none
-
-   => mw.b ffdf0040 0x30
-   => mw.b ffdf0010 0x00
-   => mw.b 0xffdf0050 0x08
-   => mw.b 0xffdf0060 0x82
-   => mw.b ffdf0061 0x00
-   => mw.b ffdf0010 0x30
-   => reset
-
-To change from NAND to NOR boot give following command on uboot prompt:
-
-.. code-block:: none
-
-   => mw.b ffdf0040 0x30
-   => mw.b ffdf0010 0x00
-   => mw.b 0xffdf0050 0x00(for vbank0) or (mw.b 0xffdf0050 0x02 for vbank2)
-   => mw.b 0xffdf0060 0x12
-   => mw.b ffdf0061 0x01
-   => mw.b ffdf0010 0x30
-   => reset
-
-Note:
-
-- Power off cycle will lead to default switch settings.
-- 0xffdf0000 is the address of the QIXIS FPGA.
-
-Ethernet interfaces for B4860QDS
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Serdes protocosl tested:
-* 0x2a, 0x8d (serdes1, serdes2) [DEFAULT]
-* 0x2a, 0xb2 (serdes1, serdes2)
-
-When using [DEFAULT] RCW, which including 2 * 1G SGMII on board and 2 * 1G
-SGMII on SGMII riser card.
-
-Under U-Boot these network interfaces are recognized as::
-
-   FM1@DTSEC3, FM1@DTSEC4, FM1@DTSEC5 and FM1@DTSEC6.
-
-On Linux the interfaces are renamed as::
-
-   eth2 -> fm1-gb2
-   eth3 -> fm1-gb3
-   eth4 -> fm1-gb4
-   eth5 -> fm1-gb5
-
-RCW and Ethernet interfaces for B4420QDS
-^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
-
-Serdes protocosl tested:
-* 0x18, 0x9e (serdes1, serdes2)
-
-Under U-Boot these network interfaces are recognized as::
-
-   FM1@DTSEC3, FM1@DTSEC4 and  e1000#0.
-
-On Linux the interfaces are renamed as::
-
-   eth2 -> fm1-gb2
-   eth3 -> fm1-gb3
-
-NAND boot with 2 Stage boot loader
-----------------------------------
-PBL initialise the internal SRAM and copy SPL(160KB) in SRAM.
-SPL further initialise DDR using SPD and environment variables and copy
-U-Boot(768 KB) from flash to DDR.
-Finally SPL transer control to U-Boot for futher booting.
-
-SPL has following features:
- - Executes within 256K
- - No relocation required
-
-Run time view of SPL framework during  boot:
-
-+----------------------------------------------+
-|Area        | Address                         |
-+----------------------------------------------+
-|Secure boot | 0xFFFC0000 (32KB)               |
-|headers     |                                 |
-+----------------------------------------------+
-|GD, BD      | 0xFFFC8000 (4KB)                |
-+----------------------------------------------+
-|ENV         | 0xFFFC9000 (8KB)                |
-+----------------------------------------------+
-|HEAP        | 0xFFFCB000 (30KB)               |
-+----------------------------------------------+
-|STACK       | 0xFFFD8000 (22KB)               |
-+----------------------------------------------+
-|U-Boot SPL  | 0xFFFD8000 (160KB)              |
-+----------------------------------------------+
-
-NAND Flash memory Map on B4860 and B4420QDS
--------------------------------------------
-
-=============   =============   =============================   =====
-Start		End		Definition			Size
-=============   =============   =============================   =====
-0x000000	0x0FFFFF	U-Boot                          1MB
-0x140000	0x15FFFF	U-Boot env                      128KB
-0x1A0000	0x1BFFFF	FMAN Ucode                      128KB
-=============   =============   =============================   =====
diff --git a/doc/board/freescale/index.rst b/doc/board/freescale/index.rst
index 313cf40..bddc6c6 100644
--- a/doc/board/freescale/index.rst
+++ b/doc/board/freescale/index.rst
@@ -6,7 +6,6 @@ Freescale
 .. toctree::
    :maxdepth: 2
 
-   b4860qds
    imx8mm_evk
    imx8mn_evk
    imx8mp_evk
diff --git a/doc/develop/driver-model/migration.rst b/doc/develop/driver-model/migration.rst
index 8d0bb76..8bb8601 100644
--- a/doc/develop/driver-model/migration.rst
+++ b/doc/develop/driver-model/migration.rst
@@ -75,15 +75,6 @@ Partially converted::
 * Status: In progress
 * Deadline: 2019.07
 
-CONFIG_DM_PCI
--------------
-Deadline: 2019.07
-
-The PCI subsystem has supported driver model since mid 2015. Maintainers should
-submit patches switching over to using CONFIG_DM_PCI and other base driver
-model options in time for inclusion in the 2019.07 release.
-
-
 CONFIG_DM_VIDEO
 ---------------
 Deadline: 2019.07
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index 7e4e97d..dda712f 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -27,11 +27,7 @@
 
 #include "sata_sil.h"
 
-#ifdef CONFIG_DM_PCI
 #define virt_to_bus(devno, v)	dm_pci_virt_to_mem(devno, (void *) (v))
-#else
-#define virt_to_bus(devno, v)	pci_virt_to_mem(devno, (void *) (v))
-#endif
 
 /* just compatible ahci_ops */
 struct sil_ops {
@@ -616,11 +612,7 @@ static int sil_init_sata(struct udevice *uc_dev, int dev)
 #else
 	priv->sil_sata_desc[dev] = sata;
 	priv->port_num = dev;
-#ifdef CONFIG_DM_PCI
 	sata->devno = uc_dev->parent;
-#else
-	sata->devno = sata_info.devno;
-#endif	/* CONFIG_DM_PCI */
 #endif
 	sata->id = dev;
 	sata->port = port;
diff --git a/drivers/ata/sata_sil.h b/drivers/ata/sata_sil.h
index a300c0c..bea4322 100644
--- a/drivers/ata/sata_sil.h
+++ b/drivers/ata/sata_sil.h
@@ -21,11 +21,7 @@ struct sil_sata {
 	u16		pio;
 	u16		mwdma;
 	u16		udma;
-#ifdef CONFIG_DM_PCI
 	struct udevice	*devno;
-#else
-	pci_dev_t	devno;
-#endif
 	int		wcache;
 	int		flush;
 	int		flush_ext;
diff --git a/drivers/bios_emulator/atibios.c b/drivers/bios_emulator/atibios.c
index 6c7cc24..9547470 100644
--- a/drivers/bios_emulator/atibios.c
+++ b/drivers/bios_emulator/atibios.c
@@ -230,19 +230,12 @@ This function executes the BIOS POST code on the controller. We assume that
 at this stage the controller has its I/O and memory space enabled and
 that all other controllers are in a disabled state.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 static void PCI_doBIOSPOST(struct udevice *pcidev, BE_VGAInfo *vga_info,
 			   int vesa_mode, struct vbe_mode_info *mode_info)
-#else
-static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
-			   int vesa_mode, struct vbe_mode_info *mode_info)
-#endif
 {
 	RMREGS regs;
 	RMSREGS sregs;
-#ifdef CONFIG_DM_PCI
 	pci_dev_t bdf;
-#endif
 
 	/* Determine the value to store in AX for BIOS POST. Per the PCI specs,
 	 AH must contain the bus and AL must contain the devfn, encoded as
@@ -250,14 +243,9 @@ static void PCI_doBIOSPOST(pci_dev_t pcidev, BE_VGAInfo *vga_info,
 	 */
 	memset(&regs, 0, sizeof(regs));
 	memset(&sregs, 0, sizeof(sregs));
-#ifdef CONFIG_DM_PCI
 	bdf = dm_pci_get_bdf(pcidev);
 	regs.x.ax = (int)PCI_BUS(bdf) << 8 |
 			(int)PCI_DEV(bdf) << 3 | (int)PCI_FUNC(bdf);
-#else
-	regs.x.ax = ((int)PCI_BUS(pcidev) << 8) |
-	    ((int)PCI_DEV(pcidev) << 3) | (int)PCI_FUNC(pcidev);
-#endif
 	/*Setup the X86 emulator for the VGA BIOS*/
 	BE_setVGA(vga_info);
 
@@ -300,28 +288,15 @@ NOTE: This function leaves the original memory aperture disabled by leaving
       it programmed to all 1's. It must be restored to the correct value
       later.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 static u32 PCI_findBIOSAddr(struct udevice *pcidev, int *bar)
-#else
-static u32 PCI_findBIOSAddr(pci_dev_t pcidev, int *bar)
-#endif
 {
 	u32 base, size;
 
 	for (*bar = 0x10; *bar <= 0x14; (*bar) += 4) {
-#ifdef CONFIG_DM_PCI
 		dm_pci_read_config32(pcidev, *bar, &base);
-#else
-		pci_read_config_dword(pcidev, *bar, &base);
-#endif
 		if (!(base & 0x1)) {
-#ifdef CONFIG_DM_PCI
 			dm_pci_write_config32(pcidev, *bar, 0xFFFFFFFF);
 			dm_pci_read_config32(pcidev, *bar, &size);
-#else
-			pci_write_config_dword(pcidev, *bar, 0xFFFFFFFF);
-			pci_read_config_dword(pcidev, *bar, &size);
-#endif
 			size = ~(size & ~0xFF) + 1;
 			if (size >= MAX_BIOSLEN)
 				return base & ~0xFF;
@@ -344,19 +319,11 @@ necessary).
 Anyway to fix this we change all I/O mapped base registers and
 chop off the top bits.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 static void PCI_fixupIObase(struct udevice *pcidev, int reg, u32 *base)
-#else
-static void PCI_fixupIObase(pci_dev_t pcidev, int reg, u32 * base)
-#endif
 {
 	if ((*base & 0x1) && (*base > 0xFFFE)) {
 		*base &= 0xFFFF;
-#ifdef CONFIG_DM_PCI
 		dm_pci_write_config32(pcidev, reg, *base);
-#else
-		pci_write_config_dword(pcidev, reg, *base);
-#endif
 
 	}
 }
@@ -371,30 +338,18 @@ Pointers to the mapped BIOS image
 REMARKS:
 Maps a pointer to the BIOS image on the graphics card on the PCI bus.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 void *PCI_mapBIOSImage(struct udevice *pcidev)
-#else
-void *PCI_mapBIOSImage(pci_dev_t pcidev)
-#endif
 {
 	u32 BIOSImageBus;
 	int BIOSImageBAR;
 	u8 *BIOSImage;
 
 	/*Save PCI BAR registers that might get changed*/
-#ifdef CONFIG_DM_PCI
 	dm_pci_read_config32(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
 	dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
 	dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
 	dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
 	dm_pci_read_config32(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
-#else
-	pci_read_config_dword(pcidev, PCI_ROM_ADDRESS, &saveROMBaseAddress);
-	pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_0, &saveBaseAddress10);
-	pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_1, &saveBaseAddress14);
-	pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_2, &saveBaseAddress18);
-	pci_read_config_dword(pcidev, PCI_BASE_ADDRESS_4, &saveBaseAddress20);
-#endif
 
 	/*Fix up I/O base registers to less than 64K */
 	if(saveBaseAddress14 != 0)
@@ -413,21 +368,12 @@ void *PCI_mapBIOSImage(pci_dev_t pcidev)
 		return NULL;
 	}
 
-#ifdef CONFIG_DM_PCI
 	BIOSImage = dm_pci_bus_to_virt(pcidev, BIOSImageBus,
 				       PCI_REGION_MEM, 0, MAP_NOCACHE);
 
 	/*Change the PCI BAR registers to map it onto the bus.*/
 	dm_pci_write_config32(pcidev, BIOSImageBAR, 0);
 	dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
-#else
-	BIOSImage = pci_bus_to_virt(pcidev, BIOSImageBus,
-				    PCI_REGION_MEM, 0, MAP_NOCACHE);
-
-	/*Change the PCI BAR registers to map it onto the bus.*/
-	pci_write_config_dword(pcidev, BIOSImageBAR, 0);
-	pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, BIOSImageBus | 0x1);
-#endif
 	udelay(1);
 
 	/*Check that the BIOS image is valid. If not fail, or return the
@@ -447,7 +393,6 @@ pcidev	- PCI device info for the video card on the bus
 REMARKS:
 Unmaps the BIOS image for the device and restores framebuffer mappings
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 void PCI_unmapBIOSImage(struct udevice *pcidev, void *BIOSImage)
 {
 	dm_pci_write_config32(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
@@ -456,16 +401,6 @@ void PCI_unmapBIOSImage(struct udevice *pcidev, void *BIOSImage)
 	dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
 	dm_pci_write_config32(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
 }
-#else
-void PCI_unmapBIOSImage(pci_dev_t pcidev, void *BIOSImage)
-{
-	pci_write_config_dword(pcidev, PCI_ROM_ADDRESS, saveROMBaseAddress);
-	pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_0, saveBaseAddress10);
-	pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_1, saveBaseAddress14);
-	pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_2, saveBaseAddress18);
-	pci_write_config_dword(pcidev, PCI_BASE_ADDRESS_4, saveBaseAddress20);
-}
-#endif
 
 /****************************************************************************
 PARAMETERS:
@@ -479,22 +414,14 @@ REMARKS:
 Loads and POST's the display controllers BIOS, directly from the BIOS
 image we can extract over the PCI bus.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 static int PCI_postController(struct udevice *pcidev, uchar *bios_rom,
 			      int bios_len, BE_VGAInfo *vga_info,
 			      int vesa_mode, struct vbe_mode_info *mode_info)
-#else
-static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
-			      BE_VGAInfo *vga_info, int vesa_mode,
-			      struct vbe_mode_info *mode_info)
-#endif
 {
 	u32 bios_image_len;
 	uchar *mapped_bios;
 	uchar *copy_of_bios;
-#ifdef CONFIG_DM_PCI
 	pci_dev_t bdf;
-#endif
 
 	if (bios_rom) {
 		copy_of_bios = bios_rom;
@@ -522,16 +449,10 @@ static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
 	}
 
 	/*Save information in vga_info structure*/
-#ifdef CONFIG_DM_PCI
 	bdf = dm_pci_get_bdf(pcidev);
 	vga_info->function = PCI_FUNC(bdf);
 	vga_info->device = PCI_DEV(bdf);
 	vga_info->bus = PCI_BUS(bdf);
-#else
-	vga_info->function = PCI_FUNC(pcidev);
-	vga_info->device = PCI_DEV(pcidev);
-	vga_info->bus = PCI_BUS(pcidev);
-#endif
 	vga_info->pcidev = pcidev;
 	vga_info->BIOSImage = copy_of_bios;
 	vga_info->BIOSImageLen = bios_image_len;
@@ -549,22 +470,13 @@ static int PCI_postController(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
 	return true;
 }
 
-#ifdef CONFIG_DM_PCI
 int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **vga_infop)
-#else
-int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **vga_infop)
-#endif
 {
 	BE_VGAInfo *VGAInfo;
-#ifdef CONFIG_DM_PCI
 	pci_dev_t bdf = dm_pci_get_bdf(pcidev);
 
 	printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
 	       PCI_BUS(bdf), PCI_FUNC(bdf), PCI_DEV(bdf));
-#else
-	printf("videoboot: Booting PCI video card bus %d, function %d, device %d\n",
-	       PCI_BUS(pcidev), PCI_FUNC(pcidev), PCI_DEV(pcidev));
-#endif
 	/*Initialise the x86 BIOS emulator*/
 	if ((VGAInfo = malloc(sizeof(*VGAInfo))) == NULL) {
 		printf("videoboot: Out of memory!\n");
@@ -582,15 +494,9 @@ void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void))
 	X86EMU_setupIntrFunc(intnum, (X86EMU_intrFuncs)int_func);
 }
 
-#ifdef CONFIG_DM_PCI
 int biosemu_run(struct udevice *pcidev, uchar *bios_rom, int bios_len,
 		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
 		struct vbe_mode_info *mode_info)
-#else
-int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
-		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
-		struct vbe_mode_info *mode_info)
-#endif
 {
 	/*Post all the display controller BIOS'es*/
 	if (!PCI_postController(pcidev, bios_rom, bios_len, vga_info,
@@ -623,12 +529,8 @@ REMARKS:
 Boots the PCI/AGP video card on the bus using the Video ROM BIOS image
 and the X86 BIOS emulator module.
 ****************************************************************************/
-#ifdef CONFIG_DM_PCI
 int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
 		      int clean_up)
-#else
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up)
-#endif
 {
 	BE_VGAInfo *VGAInfo;
 	int ret;
diff --git a/drivers/bios_emulator/bios.c b/drivers/bios_emulator/bios.c
index 77c7f94..9596a1f 100644
--- a/drivers/bios_emulator/bios.c
+++ b/drivers/bios_emulator/bios.c
@@ -185,21 +185,12 @@ static void X86API int1A(int unused)
 	case 0xB103:		/* Find PCI class code */
 		M.x86.R_AH = DEVICE_NOT_FOUND;
 #ifdef __KERNEL__
-#ifdef CONFIG_DM_PCI
 		dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG,
 				    &interface);
 		dm_pci_read_config8(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE,
 				    &subclass);
 		dm_pci_read_config8(_BE_env.vgaInfo.pcidev,
 				    PCI_CLASS_DEVICE + 1, &baseclass);
-#else
-		pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_PROG,
-				     &interface);
-		pci_read_config_byte(_BE_env.vgaInfo.pcidev, PCI_CLASS_DEVICE,
-				     &subclass);
-		pci_read_config_byte(_BE_env.vgaInfo.pcidev,
-				     PCI_CLASS_DEVICE + 1, &baseclass);
-#endif
 		if (M.x86.R_CL == interface && M.x86.R_CH == subclass
 		    && (u8) (M.x86.R_ECX >> 16) == baseclass) {
 #else
@@ -218,13 +209,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_read_config8(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
 					    &M.x86.R_CL);
-# else
-			pci_read_config_byte(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
-					     &M.x86.R_CL);
-# endif
 #else
 			M.x86.R_CL =
 			    (u8) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_BYTE,
@@ -238,13 +224,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_read_config16(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
 					     &M.x86.R_CX);
-# else
-			pci_read_config_word(_BE_env.vgaInfo.pcidev, M.x86.R_DI,
-					     &M.x86.R_CX);
-# endif
 #else
 			M.x86.R_CX =
 			    (u16) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_WORD,
@@ -258,13 +239,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_read_config32(_BE_env.vgaInfo.pcidev,
 					     M.x86.R_DI, &M.x86.R_ECX);
-# else
-			pci_read_config_dword(_BE_env.vgaInfo.pcidev,
-					      M.x86.R_DI, &M.x86.R_ECX);
-# endif
 #else
 			M.x86.R_ECX =
 			    (u32) PCI_accessReg(M.x86.R_DI, 0, PCI_READ_DWORD,
@@ -278,13 +254,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_write_config8(_BE_env.vgaInfo.pcidev,
 					     M.x86.R_DI, M.x86.R_CL);
-# else
-			pci_write_config_byte(_BE_env.vgaInfo.pcidev,
-					      M.x86.R_DI, M.x86.R_CL);
-# endif
 #else
 			PCI_accessReg(M.x86.R_DI, M.x86.R_CL, PCI_WRITE_BYTE,
 				      _BE_env.vgaInfo.pciInfo);
@@ -297,13 +268,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
 					      M.x86.R_DI, M.x86.R_CX);
-# else
-			pci_write_config_word(_BE_env.vgaInfo.pcidev,
-					      M.x86.R_DI, M.x86.R_CX);
-# endif
 #else
 			PCI_accessReg(M.x86.R_DI, M.x86.R_CX, PCI_WRITE_WORD,
 				      _BE_env.vgaInfo.pciInfo);
@@ -316,13 +282,8 @@ static void X86API int1A(int unused)
 		if (M.x86.R_BX == pciSlot) {
 			M.x86.R_AH = SUCCESSFUL;
 #ifdef __KERNEL__
-# ifdef CONFIG_DM_PCI
 			dm_pci_write_config32(_BE_env.vgaInfo.pcidev,
 					      M.x86.R_DI, M.x86.R_ECX);
-# else
-			pci_write_config_dword(_BE_env.vgaInfo.pcidev,
-					       M.x86.R_DI, M.x86.R_ECX);
-# endif
 #else
 			PCI_accessReg(M.x86.R_DI, M.x86.R_ECX, PCI_WRITE_DWORD,
 				      _BE_env.vgaInfo.pciInfo);
diff --git a/drivers/core/fdtaddr.c b/drivers/core/fdtaddr.c
index b9874c7..4ffbd6b 100644
--- a/drivers/core/fdtaddr.c
+++ b/drivers/core/fdtaddr.c
@@ -200,8 +200,7 @@ fdt_addr_t devfdt_get_addr_pci(const struct udevice *dev)
 	ulong addr;
 
 	addr = devfdt_get_addr(dev);
-	if (CONFIG_IS_ENABLED(PCI) && IS_ENABLED(CONFIG_DM_PCI) &&
-	    addr == FDT_ADDR_T_NONE) {
+	if (CONFIG_IS_ENABLED(PCI) && addr == FDT_ADDR_T_NONE) {
 		struct fdt_pci_addr pci_addr;
 		u32 bar;
 		int ret;
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 83d7a4e..bdfdec9 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -19,7 +19,6 @@ obj-$(CONFIG_PCI_GT64120) += pci_gt64120.o
 obj-$(CONFIG_PCI_MPC85XX) += pci_mpc85xx.o
 obj-$(CONFIG_PCI_MSC01) += pci_msc01.o
 obj-$(CONFIG_PCIE_IMX) += pcie_imx.o
-obj-$(CONFIG_FTPCI100) += pci_ftpci100.o
 obj-$(CONFIG_PCI_MVEBU) += pci_mvebu.o
 obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
 obj-$(CONFIG_PCI_RCAR_GEN3) += pci-rcar-gen3.o
diff --git a/drivers/pci/pci_common.c b/drivers/pci/pci_common.c
index 5231b69..02a71da 100644
--- a/drivers/pci/pci_common.c
+++ b/drivers/pci/pci_common.c
@@ -99,7 +99,7 @@ __weak int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
 	return 0;
 }
 
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
+#if defined(CONFIG_DM_PCI_COMPAT)
 /* Get a virtual address associated with a BAR region */
 void *pci_map_bar(pci_dev_t pdev, int bar, int flags)
 {
@@ -361,4 +361,4 @@ pci_dev_t pci_find_class(uint find_class, int index)
 
 	return -ENODEV;
 }
-#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
+#endif /* CONFIG_DM_PCI_COMPAT */
diff --git a/drivers/pci/pci_ftpci100.c b/drivers/pci/pci_ftpci100.c
deleted file mode 100644
index 32fac87..0000000
--- a/drivers/pci/pci_ftpci100.c
+++ /dev/null
@@ -1,319 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
- *
- * Copyright (C) 2011 Andes Technology Corporation
- * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
- * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
- */
-#include <common.h>
-#include <init.h>
-#include <log.h>
-#include <malloc.h>
-#include <pci.h>
-
-#include <faraday/ftpci100.h>
-
-#include <asm/io.h>
-#include <asm/types.h> /* u32, u16.... used by pci.h */
-
-struct ftpci100_data {
-	unsigned int reg_base;
-	unsigned int io_base;
-	unsigned int mem_base;
-	unsigned int mmio_base;
-	unsigned int ndevs;
-};
-
-static struct pci_config devs[FTPCI100_MAX_FUNCTIONS];
-static struct pci_controller local_hose;
-
-static void setup_pci_bar(unsigned int bus, unsigned int dev, unsigned func,
-		unsigned char header, struct ftpci100_data *priv)
-{
-	struct pci_controller *hose = (struct pci_controller *)&local_hose;
-	unsigned int i, tmp32, bar_no, iovsmem = 1;
-	pci_dev_t dev_nu;
-
-	/* A device is present, add an entry to the array */
-	devs[priv->ndevs].bus = bus;
-	devs[priv->ndevs].dev = dev;
-	devs[priv->ndevs].func = func;
-
-	dev_nu = PCI_BDF(bus, dev, func);
-
-	if ((header & 0x7f) == 0x01)
-		/* PCI-PCI Bridge */
-		bar_no = 2;
-	else
-		bar_no = 6;
-
-	/* Allocate address spaces by configuring BARs */
-	for (i = 0; i < bar_no; i++) {
-		pci_hose_write_config_dword(hose, dev_nu,
-					PCI_BASE_ADDRESS_0 + i * 4, 0xffffffff);
-		pci_hose_read_config_dword(hose, dev_nu,
-					PCI_BASE_ADDRESS_0 + i * 4, &tmp32);
-
-		if (tmp32 == 0x0)
-			continue;
-
-		/* IO space */
-		if (tmp32 & 0x1) {
-			iovsmem = 0;
-			unsigned int size_mask = ~(tmp32 & 0xfffffffc);
-
-			if (priv->io_base & size_mask)
-				priv->io_base = (priv->io_base & ~size_mask) + \
-						 size_mask + 1;
-
-			devs[priv->ndevs].bar[i].addr = priv->io_base;
-			devs[priv->ndevs].bar[i].size = size_mask + 1;
-
-			pci_hose_write_config_dword(hose, dev_nu,
-					PCI_BASE_ADDRESS_0 + i * 4,
-					priv->io_base);
-
-			debug("Allocated IO address 0x%X-" \
-				"0x%X for Bus %d, Device %d, Function %d\n",
-				priv->io_base,
-				priv->io_base + size_mask, bus, dev, func);
-
-			priv->io_base += size_mask + 1;
-		} else {
-			/* Memory space */
-			unsigned int is_64bit = ((tmp32 & 0x6) == 0x4);
-			unsigned int is_pref = tmp32 & 0x8;
-			unsigned int size_mask = ~(tmp32 & 0xfffffff0);
-			unsigned int alloc_base;
-			unsigned int *addr_mem_base;
-
-			if (is_pref)
-				addr_mem_base = &priv->mem_base;
-			else
-				addr_mem_base = &priv->mmio_base;
-
-			alloc_base = *addr_mem_base;
-
-			if (alloc_base & size_mask)
-				alloc_base = (alloc_base & ~size_mask) \
-						+ size_mask + 1;
-
-			pci_hose_write_config_dword(hose, dev_nu,
-					PCI_BASE_ADDRESS_0 + i * 4, alloc_base);
-
-			debug("Allocated %s address 0x%X-" \
-				"0x%X for Bus %d, Device %d, Function %d\n",
-				is_pref ? "MEM" : "MMIO", alloc_base,
-				alloc_base + size_mask, bus, dev, func);
-
-			devs[priv->ndevs].bar[i].addr = alloc_base;
-			devs[priv->ndevs].bar[i].size = size_mask + 1;
-
-			debug("BAR address  BAR size\n");
-			debug("%010x  %08d\n",
-				devs[priv->ndevs].bar[0].addr,
-				devs[priv->ndevs].bar[0].size);
-
-			alloc_base += size_mask + 1;
-			*addr_mem_base = alloc_base;
-
-			if (is_64bit) {
-				i++;
-				pci_hose_write_config_dword(hose, dev_nu,
-					PCI_BASE_ADDRESS_0 + i * 4, 0x0);
-			}
-		}
-	}
-
-	/* Enable Bus Master, Memory Space, and IO Space */
-	pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
-	pci_hose_write_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, 0x08);
-	pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
-
-	pci_hose_read_config_dword(hose, dev_nu, PCI_COMMAND, &tmp32);
-
-	tmp32 &= 0xffff;
-
-	if (iovsmem == 0)
-		tmp32 |= 0x5;
-	else
-		tmp32 |= 0x6;
-
-	pci_hose_write_config_dword(hose, dev_nu, PCI_COMMAND, tmp32);
-}
-
-static void pci_bus_scan(struct ftpci100_data *priv)
-{
-	struct pci_controller *hose = (struct pci_controller *)&local_hose;
-	unsigned int bus, dev, func;
-	pci_dev_t dev_nu;
-	unsigned int data32;
-	unsigned int tmp;
-	unsigned char header;
-	unsigned char int_pin;
-	unsigned int niobars;
-	unsigned int nmbars;
-
-	priv->ndevs = 1;
-
-	nmbars = 0;
-	niobars = 0;
-
-	for (bus = 0; bus < MAX_BUS_NUM; bus++)
-		for (dev = 0; dev < MAX_DEV_NUM; dev++)
-			for (func = 0; func < MAX_FUN_NUM; func++) {
-				dev_nu = PCI_BDF(bus, dev, func);
-				pci_hose_read_config_dword(hose, dev_nu,
-							PCI_VENDOR_ID, &data32);
-
-				/*
-				 * some broken boards return 0 or ~0,
-				 * if a slot is empty.
-				 */
-				if (data32 == 0xffffffff ||
-					data32 == 0x00000000 ||
-					data32 == 0x0000ffff ||
-					data32 == 0xffff0000)
-					continue;
-
-				pci_hose_read_config_dword(hose, dev_nu,
-							PCI_HEADER_TYPE, &tmp);
-				header = (unsigned char)tmp;
-				setup_pci_bar(bus, dev, func, header, priv);
-
-				devs[priv->ndevs].v_id = (u16)(data32 & \
-								0x0000ffff);
-
-				devs[priv->ndevs].d_id = (u16)((data32 & \
-							0xffff0000) >> 16);
-
-				/* Figure out what INTX# line the card uses */
-				pci_hose_read_config_byte(hose, dev_nu,
-						PCI_INTERRUPT_PIN, &int_pin);
-
-				/* assign the appropriate irq line */
-				if (int_pin > PCI_IRQ_LINES) {
-					printf("more irq lines than expect\n");
-				} else if (int_pin != 0) {
-					/* This device uses an interrupt line */
-					devs[priv->ndevs].pin = int_pin;
-				}
-
-				pci_hose_read_config_dword(hose, dev_nu,
-						PCI_CLASS_DEVICE, &data32);
-
-				debug("%06d  %03d  %03d  " \
-					"%04d  %08x  %08x  " \
-					"%03d  %08x  %06d  %08x\n",
-					priv->ndevs, devs[priv->ndevs].bus,
-					devs[priv->ndevs].dev,
-					devs[priv->ndevs].func,
-					devs[priv->ndevs].d_id,
-					devs[priv->ndevs].v_id,
-					devs[priv->ndevs].pin,
-					devs[priv->ndevs].bar[0].addr,
-					devs[priv->ndevs].bar[0].size,
-					data32 >> 8);
-
-				priv->ndevs++;
-			}
-}
-
-static void ftpci_preinit(struct ftpci100_data *priv)
-{
-	struct ftpci100_ahbc *ftpci100;
-	struct pci_controller *hose = (struct pci_controller *)&local_hose;
-	u32 pci_config_addr;
-	u32 pci_config_data;
-
-	priv->reg_base = CONFIG_FTPCI100_BASE;
-	priv->io_base = CONFIG_FTPCI100_BASE + CONFIG_FTPCI100_IO_SIZE;
-	priv->mmio_base = CONFIG_FTPCI100_MEM_BASE;
-	priv->mem_base = CONFIG_FTPCI100_MEM_BASE + CONFIG_FTPCI100_MEM_SIZE;
-
-	ftpci100 = (struct ftpci100_ahbc *)priv->reg_base;
-
-	pci_config_addr = (u32) &ftpci100->conf;
-	pci_config_data = (u32) &ftpci100->data;
-
-	/* print device name */
-	printf("FTPCI100\n");
-
-	/* dump basic configuration */
-	debug("%s: Config addr is %08X, data port is %08X\n",
-		__func__, pci_config_addr, pci_config_data);
-
-	/* PCI memory space */
-	pci_set_region(hose->regions + 0,
-		CONFIG_PCI_MEM_BUS,
-		CONFIG_PCI_MEM_PHYS,
-		CONFIG_PCI_MEM_SIZE,
-		PCI_REGION_MEM);
-	hose->region_count++;
-
-	/* PCI IO space */
-	pci_set_region(hose->regions + 1,
-		CONFIG_PCI_IO_BUS,
-		CONFIG_PCI_IO_PHYS,
-		CONFIG_PCI_IO_SIZE,
-		PCI_REGION_IO);
-	hose->region_count++;
-
-#if defined(CONFIG_PCI_SYS_BUS)
-	/* PCI System Memory space */
-	pci_set_region(hose->regions + 2,
-		CONFIG_PCI_SYS_BUS,
-		CONFIG_PCI_SYS_PHYS,
-		CONFIG_PCI_SYS_SIZE,
-		PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-	hose->region_count++;
-#endif
-
-	/* setup indirect read/write function */
-	pci_setup_indirect(hose, pci_config_addr, pci_config_data);
-
-	/* register hose */
-	pci_register_hose(hose);
-}
-
-void pci_ftpci_init(void)
-{
-	struct ftpci100_data *priv = NULL;
-	struct pci_controller *hose = (struct pci_controller *)&local_hose;
-	pci_dev_t bridge_num;
-
-	struct pci_device_id bridge_ids[] = {
-		{FTPCI100_BRIDGE_VENDORID, FTPCI100_BRIDGE_DEVICEID},
-		{0, 0}
-	};
-
-	priv = malloc(sizeof(struct ftpci100_data));
-
-	if (!priv) {
-		printf("%s(): failed to malloc priv\n", __func__);
-		return;
-	}
-
-	memset(priv, 0, sizeof(struct ftpci100_data));
-
-	ftpci_preinit(priv);
-
-	debug("Device  bus  dev  func  deviceID  vendorID  pin  address" \
-		"   size    class\n");
-
-	pci_bus_scan(priv);
-
-	/*
-	 * Setup the PCI Bridge Window to 1GB,
-	 * it will cause USB OHCI Host controller Unrecoverable Error
-	 * if it is not set.
-	 */
-	bridge_num = pci_find_devices(bridge_ids, 0);
-	if (bridge_num == -1) {
-		printf("PCI Bridge not found\n");
-		return;
-	}
-	pci_hose_write_config_dword(hose, bridge_num, PCI_MEM_BASE_SIZE1,
-					FTPCI100_BASE_ADR_SIZE(1024));
-}
diff --git a/drivers/pci/pci_gt64120.c b/drivers/pci/pci_gt64120.c
index e57fedf..153c65b 100644
--- a/drivers/pci/pci_gt64120.c
+++ b/drivers/pci/pci_gt64120.c
@@ -114,69 +114,6 @@ static int gt_config_access(struct gt64120_pci_controller *gt,
 	return 0;
 }
 
-#if !IS_ENABLED(CONFIG_DM_PCI)
-static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
-				int where, u32 *value)
-{
-	struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
-
-	*value = 0xffffffff;
-	return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
-}
-
-static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
-				 int where, u32 value)
-{
-	struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
-	u32 data = value;
-
-	return gt_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
-}
-
-void gt64120_pci_init(void *regs, unsigned long sys_bus, unsigned long sys_phys,
-		     unsigned long sys_size, unsigned long mem_bus,
-		     unsigned long mem_phys, unsigned long mem_size,
-		     unsigned long io_bus, unsigned long io_phys,
-		     unsigned long io_size)
-{
-	static struct gt64120_pci_controller global_gt;
-	struct gt64120_pci_controller *gt;
-	struct pci_controller *hose;
-
-	gt = &global_gt;
-	gt->regs = regs;
-
-	hose = &gt->hose;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0;
-
-	/* System memory space */
-	pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	/* PCI memory space */
-	pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
-		       PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
-		       PCI_REGION_IO);
-
-	hose->region_count = 3;
-
-	pci_set_ops(hose,
-		    pci_hose_read_config_byte_via_dword,
-		    pci_hose_read_config_word_via_dword,
-		    gt_read_config_dword,
-		    pci_hose_write_config_byte_via_dword,
-		    pci_hose_write_config_word_via_dword,
-		    gt_write_config_dword);
-
-	pci_register_hose(hose);
-	hose->last_busno = pci_hose_scan(hose);
-}
-#else
 static int gt64120_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
 				   uint where, ulong *val,
 				   enum pci_size_t size)
@@ -246,4 +183,3 @@ U_BOOT_DRIVER(gt64120_pci) = {
 	.probe		= gt64120_pci_probe,
 	.priv_auto	= sizeof(struct gt64120_pci_controller),
 };
-#endif
diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c
index c17da47..2f1b688 100644
--- a/drivers/pci/pci_msc01.c
+++ b/drivers/pci/pci_msc01.c
@@ -62,69 +62,6 @@ static int msc01_config_access(struct msc01_pci_controller *msc01,
 	return 0;
 }
 
-#if !IS_ENABLED(CONFIG_DM_PCI)
-static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
-				   int where, u32 *value)
-{
-	struct msc01_pci_controller *msc01 = hose_to_msc01(hose);
-
-	*value = 0xffffffff;
-	return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value);
-}
-
-static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
-				    int where, u32 value)
-{
-	struct msc01_pci_controller *gt = hose_to_msc01(hose);
-	u32 data = value;
-
-	return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
-}
-
-void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys,
-		    unsigned long sys_size, unsigned long mem_bus,
-		    unsigned long mem_phys, unsigned long mem_size,
-		    unsigned long io_bus, unsigned long io_phys,
-		    unsigned long io_size)
-{
-	static struct msc01_pci_controller global_msc01;
-	struct msc01_pci_controller *msc01;
-	struct pci_controller *hose;
-
-	msc01 = &global_msc01;
-	msc01->base = base;
-
-	hose = &msc01->hose;
-
-	hose->first_busno = 0;
-	hose->last_busno = 0;
-
-	/* System memory space */
-	pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
-		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	/* PCI memory space */
-	pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
-		       PCI_REGION_MEM);
-
-	/* PCI I/O space */
-	pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
-		       PCI_REGION_IO);
-
-	hose->region_count = 3;
-
-	pci_set_ops(hose,
-		    pci_hose_read_config_byte_via_dword,
-		    pci_hose_read_config_word_via_dword,
-		    msc01_read_config_dword,
-		    pci_hose_write_config_byte_via_dword,
-		    pci_hose_write_config_word_via_dword,
-		    msc01_write_config_dword);
-
-	pci_register_hose(hose);
-	hose->last_busno = pci_hose_scan(hose);
-}
-#else
 static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
 				 uint where, ulong *val, enum pci_size_t size)
 {
@@ -192,4 +129,3 @@ U_BOOT_DRIVER(msc01_pci) = {
 	.probe		= msc01_pci_probe,
 	.priv_auto	= sizeof(struct msc01_pci_controller),
 };
-#endif
diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index 7b46fdb..756166f 100644
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -681,86 +681,6 @@ static int imx_pcie_link_up(struct imx_pcie_priv *priv)
 	return 0;
 }
 
-#if !CONFIG_IS_ENABLED(DM_PCI)
-static struct imx_pcie_priv imx_pcie_priv = {
-	.dbi_base	= (void __iomem *)MX6_DBI_ADDR,
-	.cfg_base	= (void __iomem *)MX6_ROOT_ADDR,
-};
-
-static struct imx_pcie_priv *priv = &imx_pcie_priv;
-
-static int imx_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
-				int where, u32 *val)
-{
-	struct imx_pcie_priv *priv = hose->priv_data;
-
-	return imx_pcie_read_cfg(priv, d, where, val);
-}
-
-static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
-				 int where, u32 val)
-{
-	struct imx_pcie_priv *priv = hose->priv_data;
-
-	return imx_pcie_write_cfg(priv, d, where, val);
-}
-
-void imx_pcie_init(void)
-{
-	/* Static instance of the controller. */
-	static struct pci_controller	pcc;
-	struct pci_controller		*hose = &pcc;
-	int ret;
-
-	memset(&pcc, 0, sizeof(pcc));
-
-	hose->priv_data = priv;
-
-	/* PCI I/O space */
-	pci_set_region(&hose->regions[0],
-		       MX6_IO_ADDR, MX6_IO_ADDR,
-		       MX6_IO_SIZE, PCI_REGION_IO);
-
-	/* PCI memory space */
-	pci_set_region(&hose->regions[1],
-		       MX6_MEM_ADDR, MX6_MEM_ADDR,
-		       MX6_MEM_SIZE, PCI_REGION_MEM);
-
-	/* System memory space */
-	pci_set_region(&hose->regions[2],
-		       MMDC0_ARB_BASE_ADDR, MMDC0_ARB_BASE_ADDR,
-		       0xefffffff, PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
-	hose->region_count = 3;
-
-	pci_set_ops(hose,
-		    pci_hose_read_config_byte_via_dword,
-		    pci_hose_read_config_word_via_dword,
-		    imx_pcie_read_config,
-		    pci_hose_write_config_byte_via_dword,
-		    pci_hose_write_config_word_via_dword,
-		    imx_pcie_write_config);
-
-	/* Start the controller. */
-	ret = imx_pcie_link_up(priv);
-
-	if (!ret) {
-		pci_register_hose(hose);
-		hose->last_busno = pci_hose_scan(hose);
-	}
-}
-
-void imx_pcie_remove(void)
-{
-	imx6_pcie_assert_core_reset(priv, true);
-}
-
-/* Probe function. */
-void pci_init_board(void)
-{
-	imx_pcie_init();
-}
-#else
 static int imx_pcie_dm_read_config(const struct udevice *dev, pci_dev_t bdf,
 				   uint offset, ulong *value,
 				   enum pci_size_t size)
@@ -852,4 +772,3 @@ U_BOOT_DRIVER(imx_pcie) = {
 	.priv_auto	= sizeof(struct imx_pcie_priv),
 	.flags			= DM_FLAG_OS_PREPARE,
 };
-#endif
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index ce69750..d93d241 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -284,7 +284,6 @@ void scsi_init(void)
 	 */
 	for (i = 0; i < ARRAY_SIZE(scsi_device_list); i++) {
 		/* get PCI Device ID */
-#ifdef CONFIG_DM_PCI
 		struct udevice *dev;
 		int ret;
 
@@ -294,11 +293,6 @@ void scsi_init(void)
 			busdevfunc = dm_pci_get_bdf(dev);
 			break;
 		}
-#else
-		busdevfunc = pci_find_device(scsi_device_list[i].vendor,
-					     scsi_device_list[i].device,
-					     0);
-#endif
 		if (busdevfunc != -1)
 			break;
 	}
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index c62d8fe..fedf0db 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -54,7 +54,7 @@
 
 #if defined(CONFIG_CPU_ARM920T) || \
 	defined(CONFIG_PCI_OHCI) || \
-	defined(CONFIG_DM_PCI) || \
+	defined(CONFIG_PCI) || \
 	defined(CONFIG_SYS_OHCI_USE_NPS)
 # define OHCI_USE_NPS		/* force NoPowerSwitching mode */
 #endif
diff --git a/include/bios_emul.h b/include/bios_emul.h
index 158e0f2..72410dc 100644
--- a/include/bios_emul.h
+++ b/include/bios_emul.h
@@ -30,11 +30,7 @@ typedef struct {
 	int bus;
 	u32 VendorID;
 	u32 DeviceID;
-#ifdef CONFIG_DM_PCI
 	struct udevice *pcidev;
-#else
-	pci_dev_t pcidev;
-#endif
 	void *BIOSImage;
 	u32 BIOSImageLen;
 	u8 LowMem[1536];
@@ -42,12 +38,8 @@ typedef struct {
 
 struct vbe_mode_info;
 
-#ifdef CONFIG_DM_PCI
 int BootVideoCardBIOS(struct udevice *pcidev, BE_VGAInfo **pVGAInfo,
 		      int clean_up);
-#else
-int BootVideoCardBIOS(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo, int clean_up);
-#endif
 
 /* Run a BIOS ROM natively (only supported on x86 machines) */
 void bios_run_on_x86(struct udevice *dev, unsigned long addr, int vesa_mode,
@@ -65,18 +57,10 @@ void bios_set_interrupt_handler(int intnum, int (*int_handler_func)(void));
 
 void biosemu_set_interrupt_handler(int intnum, int (*int_func)(void));
 
-#ifdef CONFIG_DM_PCI
 int biosemu_setup(struct udevice *pcidev, BE_VGAInfo **pVGAInfo);
 
 int biosemu_run(struct udevice *dev, uchar *bios_rom, int bios_len,
 		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
 		struct vbe_mode_info *mode_info);
-#else
-int biosemu_setup(pci_dev_t pcidev, BE_VGAInfo **pVGAInfo);
-
-int biosemu_run(pci_dev_t pcidev, uchar *bios_rom, int bios_len,
-		BE_VGAInfo *vga_info, int clean_up, int vesa_mode,
-		struct vbe_mode_info *mode_info);
-#endif
 
 #endif
diff --git a/include/config_distro_bootcmd.h b/include/config_distro_bootcmd.h
index e70423f..750e9e0 100644
--- a/include/config_distro_bootcmd.h
+++ b/include/config_distro_bootcmd.h
@@ -265,7 +265,7 @@
 	BOOT_TARGET_DEVICES_references_IDE_without_CONFIG_IDE
 #endif
 
-#if defined(CONFIG_DM_PCI)
+#if defined(CONFIG_PCI)
 #define BOOTENV_RUN_PCI_ENUM "run boot_pci_enum; "
 #define BOOTENV_SHARED_PCI \
 	"boot_pci_enum=pci enum\0"
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 4dad6a5..d6ae419 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -228,7 +228,6 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/MPC8349EMDS_SDRAM.h b/include/configs/MPC8349EMDS_SDRAM.h
index f7c13d4..8ebca99 100644
--- a/include/configs/MPC8349EMDS_SDRAM.h
+++ b/include/configs/MPC8349EMDS_SDRAM.h
@@ -283,7 +283,6 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957  /* Freescale */
 
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h
index e16a593..0a136b4 100644
--- a/include/configs/MPC837XERDB.h
+++ b/include/configs/MPC837XERDB.h
@@ -258,7 +258,6 @@
 #define CONFIG_PCI_INDIRECT_BRIDGE
 
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
 #endif	/* CONFIG_PCI */
 
 /*
diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h
index d843ba1..ac9afa1 100644
--- a/include/configs/MPC8540ADS.h
+++ b/include/configs/MPC8540ADS.h
@@ -241,7 +241,6 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 32e1925..d3e5da0 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -370,23 +370,7 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 #if defined(CONFIG_PCI)
-
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT		1	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE	1
-#define CONFIG_SYS_PCIE1_NAME		"Slot"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xa0000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00100000	/*   1M */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-
 #endif	/* CONFIG_PCI */
 
 #if defined(CONFIG_TSEC_ENET)
diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h
index 464e7c7..02aeb6f 100644
--- a/include/configs/MPC8560ADS.h
+++ b/include/configs/MPC8560ADS.h
@@ -238,7 +238,6 @@
 #endif
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h
index f5209e1..b7e44d1 100644
--- a/include/configs/P1010RDB.h
+++ b/include/configs/P1010RDB.h
@@ -150,34 +150,6 @@
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
 #endif
 
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
-#define CONFIG_SYS_PCIE1_NAME		"mini PCIe Slot"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-#if defined(CONFIG_TARGET_P1010RDB_PA)
-#define CONFIG_SYS_PCIE2_NAME		"PCIe Slot"
-#elif defined(CONFIG_TARGET_P1010RDB_PB)
-#define CONFIG_SYS_PCIE2_NAME		"mini PCIe Slot"
-#endif
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif
 
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index b5b1594..4ef0613 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -417,23 +417,6 @@ unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
 #ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index 1b4720d..1873044 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -487,23 +487,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #endif
 
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h
index 57a0bf5..fb215bb 100644
--- a/include/configs/T104xRDB.h
+++ b/include/configs/T104xRDB.h
@@ -537,26 +537,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #endif
 
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index b8d1693..f61b40f 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -486,26 +486,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 
 #ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif
 
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index a04a49d..63cc5af 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -435,26 +435,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 
 #ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000 /* 256M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x10000000	/* 256M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif
 
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h
index aa185be..57a39fa 100644
--- a/include/configs/T4240RDB.h
+++ b/include/configs/T4240RDB.h
@@ -196,27 +196,6 @@
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 
 #ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 924093e6..c877f3c 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -430,27 +430,6 @@
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 
 #ifdef CONFIG_PCI
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */
 
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index ba5b649..54c82b4 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -529,30 +529,6 @@
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xffc00000
 #endif
 
-#if !defined(CONFIG_DM_PCI)
-#define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_SYS_PCIE2_NAME		"PCIe SLOT"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xc0000000
-#else
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
-#endif
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-
-#define CONFIG_SYS_PCIE1_NAME		"mini PCIe SLOT"
-#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#else
-#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
-#endif
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-#endif
-
 #define CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif /* CONFIG_PCI */
 
diff --git a/include/configs/t4qds.h b/include/configs/t4qds.h
deleted file mode 100644
index b62ddc7..0000000
--- a/include/configs/t4qds.h
+++ /dev/null
@@ -1,240 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2011-2012 Freescale Semiconductor, Inc.
- */
-
-/*
- * Corenet DS style board configuration file
- */
-#ifndef __T4QDS_H
-#define __T4QDS_H
-
-/* High Level Configuration Options */
-#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
-
-#ifndef CONFIG_RESET_VECTOR_ADDRESS
-#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
-#endif
-
-#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
-#define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
-#define CONFIG_PCIE1			/* PCIE controller 1 */
-#define CONFIG_PCIE2			/* PCIE controller 2 */
-#define CONFIG_PCIE3			/* PCIE controller 3 */
-#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
-#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
-
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-#define CONFIG_SRIO2			/* SRIO port 2 */
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_SYS_CACHE_STASHING
-#define CONFIG_BTB			/* toggle branch predition */
-#ifdef CONFIG_DDR_ECC
-#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
-#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
-#endif
-
-#define CONFIG_ENABLE_36BIT_PHYS
-
-/*
- *  Config the L3 Cache as L3 SRAM
- */
-#define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
-#define CONFIG_SYS_L3_SIZE		(512 << 10)
-#define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
-#define SPL_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
-#define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
-#define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)
-
-#define CONFIG_SYS_DCSRBAR		0xf0000000
-#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
-
-/*
- * DDR Setup
- */
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-
-#define CONFIG_DIMM_SLOTS_PER_CTLR	2
-#define CONFIG_CHIP_SELECTS_PER_CTRL	4
-
-#define CONFIG_DDR_SPD
-
-/*
- * IFC Definitions
- */
-#define CONFIG_SYS_FLASH_BASE	0xe0000000
-#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
-
-#ifdef CONFIG_SPL_BUILD
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
-#else
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
-#endif
-
-#define CONFIG_HWCONFIG
-
-/* define to use L1 as initial stack */
-#define CONFIG_L1_INIT_RAM
-#define CONFIG_SYS_INIT_RAM_LOCK
-#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
-/* The assembler doesn't like typecast */
-#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
-	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
-	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
-#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-					GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
-#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
-
-/* Serial Port - controlled on board with jumper J8
- * open - index 2
- * shorted - index 1
- */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
-#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
-#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
-
-/* I2C */
-#define CONFIG_SYS_I2C_LEGACY
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
-#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100
-
-/*
- * RapidIO
- */
-#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
-
-#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
-#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
-#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
-
-/*
- * General PCI
- * Memory space is mapped 1-1, but I/O space must start from 0.
- */
-
-/* controller 1, direct to uli, tgtid 3, Base address 20000 */
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
-#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 2, Slot 2, tgtid 2, Base address 201000 */
-#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
-#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
-#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
-#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
-#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 3, Slot 1, tgtid 1, Base address 202000 */
-#define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
-#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
-#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
-#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
-#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */
-
-/* controller 4, Base address 203000 */
-#define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
-#define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
-#define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
-#define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */
-
-#ifdef CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-
-#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
-#endif	/* CONFIG_PCI */
-
-/* SATA */
-#ifdef CONFIG_FSL_SATA_V2
-#define CONFIG_SYS_SATA_MAX_DEVICE	2
-#define CONFIG_SATA1
-#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
-#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
-#define CONFIG_SATA2
-#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
-#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA
-
-#define CONFIG_LBA48
-#endif
-
-#ifdef CONFIG_FMAN_ENET
-#define CONFIG_ETHPRIME		"FM1@DTSEC1"
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_LOADS_ECHO		/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 64 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
-#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
-
-#ifdef CONFIG_CMD_KGDB
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
-#endif
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ROOTPATH		"/opt/nfsroot"
-#define CONFIG_BOOTFILE		"uImage"
-#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
-
-/* default location for tftp and bootm */
-#define CONFIG_LOADADDR		1000000
-
-#define CONFIG_HVBOOT				\
- "setenv bootargs config-addr=0x60000000; "	\
- "bootm 0x01000000 - 0x00f00000"
-
-#endif	/* __CONFIG_H */
diff --git a/include/init.h b/include/init.h
index fd51d7f..c781789 100644
--- a/include/init.h
+++ b/include/init.h
@@ -297,9 +297,6 @@ int board_late_init(void);
 int board_postclk_init(void); /* after clocks/timebase, before env/serial */
 int board_early_init_r(void);
 
-/* TODO(sjg@chromium.org): Drop this when DM_PCI migration is completed */
-void pci_init_board(void);
-
 /**
  * arch_initr_trap() - Init traps
  *
diff --git a/include/pci.h b/include/pci.h
index 258c8f8..4d77113 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -836,11 +836,6 @@ int pci_last_busno(void);
 extern void pci_mpc85xx_init (struct pci_controller *hose);
 #endif
 
-#ifdef CONFIG_PCIE_IMX
-extern void imx_pcie_remove(void);
-#endif
-
-#if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
 /**
  * pci_write_bar32() - Write the address of a BAR including control bits
  *
@@ -848,6 +843,8 @@ extern void imx_pcie_remove(void);
  * with devices which require hard-coded addresses, not part of the normal
  * PCI enumeration process.
  *
+ * This is only available if CONFIG_DM_PCI_COMPAT is enabled
+ *
  * @hose:	PCI hose to use
  * @dev:	PCI device to update
  * @barnum:	BAR number (0-5)
@@ -859,6 +856,8 @@ void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
 /**
  * pci_read_bar32() - read the address of a bar
  *
+ * This is only available if CONFIG_DM_PCI_COMPAT is enabled
+ *
  * @hose:	PCI hose to use
  * @dev:	PCI device to inspect
  * @barnum:	BAR number (0-5)
@@ -869,6 +868,8 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
 /**
  * pci_hose_find_devices() - Find devices by vendor/device ID
  *
+ * This is only available if CONFIG_DM_PCI_COMPAT is enabled
+ *
  * @hose:	PCI hose to search
  * @busnum:	Bus number to search
  * @ids:	PCI vendor/device IDs to look for, terminated by 0, 0 record
@@ -879,7 +880,6 @@ u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
  */
 pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
 				struct pci_device_id *ids, int *indexp);
-#endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
 
 /* Access sizes for PCI reads and writes */
 enum pci_size_t {
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index a6507ed..dc78060 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -505,10 +505,6 @@ CONFIG_FTINTC010_BASE
 CONFIG_FTLCDC100_BASE
 CONFIG_FTMAC100_BASE
 CONFIG_FTMAC110_BASE
-CONFIG_FTPCI100_BASE
-CONFIG_FTPCI100_IO_SIZE
-CONFIG_FTPCI100_MEM_BASE
-CONFIG_FTPCI100_MEM_SIZE
 CONFIG_FTPMU010
 CONFIG_FTPMU010_BASE
 CONFIG_FTPMU010_POWER
@@ -2936,7 +2932,6 @@ CONFIG_SYS_PCI_NR_INBOUND_WIN
 CONFIG_SYS_PCI_SLV_MEM_BUS
 CONFIG_SYS_PCI_SLV_MEM_LOCAL
 CONFIG_SYS_PCI_SLV_MEM_SIZE
-CONFIG_SYS_PCI_SUBSYS_VENDORID
 CONFIG_SYS_PCI_SYS_MEM_BUS
 CONFIG_SYS_PCI_SYS_MEM_PHYS
 CONFIG_SYS_PCI_SYS_MEM_SIZE