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| author | Dai Okamura <okamura.dai@socionext.com> | 2022-12-09 20:33:47 +0900 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-01-02 14:10:23 -0500 |
| commit | ef75d482aa9d75d41305e5dddcbc8632f528e6f5 (patch) | |
| tree | 4a55c5ed12d9e012ec2f91955a9066259bd85062 | |
| parent | 1e91a0ea326f2005d34921c4bc37a35eeccad368 (diff) | |
| download | u-boot-ef75d482aa9d75d41305e5dddcbc8632f528e6f5.zip u-boot-ef75d482aa9d75d41305e5dddcbc8632f528e6f5.tar.gz u-boot-ef75d482aa9d75d41305e5dddcbc8632f528e6f5.tar.bz2 | |
pinctrl: uniphier: add ethernet TX pin data for PXs3
PXs3 Ref boards need to change the strength of ethernet ports
for stability, like LD20's one.
This adds the table data and fixes the boot issue on PXs3 Ref board.
Fixes: 0852033309 ("ARM: uniphier: sync with Linux 5.8-rc4")
Signed-off-by: Dai Okamura <okamura.dai@socionext.com>
| -rw-r--r-- | drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c index 1fc7bdb..8a8f126 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs3.c @@ -1,7 +1,8 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright (C) 2017 Socionext Inc. + * Copyright (C) 2017-2021 Socionext Inc. * Author: Masahiro Yamada <yamada.masahiro@socionext.com> + * Author: Dai Okamura <dai.okamura@socionext.com> */ #include <common.h> @@ -10,6 +11,21 @@ #include "pinctrl-uniphier.h" +static const struct uniphier_pinctrl_pin uniphier_pxs3_pins[] = { + UNIPHIER_PINCTRL_PIN(62, "RGMII0_TXCLK", 28, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(63, "RGMII0_TXD0", 29, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(64, "RGMII0_TXD1", 30, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(65, "RGMII0_TXD2", 31, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(66, "RGMII0_TXD3", 32, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(67, "RGMII0_TXCTL", 33, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(78, "RGMII1_TXCLK", 44, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(79, "RGMII1_TXD0", 45, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(80, "RGMII1_TXD1", 46, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(81, "RGMII1_TXD2", 47, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(82, "RGMII1_TXD3", 48, UNIPHIER_PIN_DRV_2BIT), + UNIPHIER_PINCTRL_PIN(83, "RGMII1_TXCTL", 49, UNIPHIER_PIN_DRV_2BIT), +}; + static const unsigned emmc_pins[] = {31, 32, 33, 34, 35, 36, 37, 38}; static const int emmc_muxvals[] = {0, 0, 0, 0, 0, 0, 0, 0}; static const unsigned emmc_dat8_pins[] = {39, 40, 41, 42}; @@ -121,6 +137,8 @@ static const char * const uniphier_pxs3_functions[] = { }; static struct uniphier_pinctrl_socdata uniphier_pxs3_pinctrl_socdata = { + .pins = uniphier_pxs3_pins, + .pins_count = ARRAY_SIZE(uniphier_pxs3_pins), .groups = uniphier_pxs3_groups, .groups_count = ARRAY_SIZE(uniphier_pxs3_groups), .functions = uniphier_pxs3_functions, |