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| author | Samuel Holland <samuel@sholland.org> | 2021-10-20 23:01:29 -0500 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2022-04-04 23:24:16 +0100 |
| commit | 923d89316ae6e48a4ce5abd4324c74aae38dddde (patch) | |
| tree | 7343892004d3639f03bf129e4ede22dd6c2a8983 | |
| parent | aadf3d53830c9ce0787ed6d9c711141d17f9ad29 (diff) | |
| download | u-boot-923d89316ae6e48a4ce5abd4324c74aae38dddde.zip u-boot-923d89316ae6e48a4ce5abd4324c74aae38dddde.tar.gz u-boot-923d89316ae6e48a4ce5abd4324c74aae38dddde.tar.bz2 | |
i2c: sun6i_p2wi: Only do non-DM pin setup for non-DM I2C
When the DM_I2C driver is loaded, the pin setup is done automatically
from the device tree by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| -rw-r--r-- | drivers/i2c/sun6i_p2wi.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/i2c/sun6i_p2wi.c b/drivers/i2c/sun6i_p2wi.c index c9e1b3f..73b808b 100644 --- a/drivers/i2c/sun6i_p2wi.c +++ b/drivers/i2c/sun6i_p2wi.c @@ -102,12 +102,6 @@ static int sun6i_p2wi_change_to_p2wi_mode(struct sunxi_p2wi_reg *base, static void sun6i_p2wi_init(struct sunxi_p2wi_reg *base) { - /* Enable p2wi and PIO clk, and de-assert their resets */ - prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); - - sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK); - sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA); - /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */ writel(P2WI_CTRL_RESET, &base->ctrl); sdelay(0x100); @@ -142,6 +136,12 @@ void p2wi_init(void) { struct sunxi_p2wi_reg *base = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE; + /* Enable p2wi and PIO clk, and de-assert their resets */ + prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI); + + sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK); + sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA); + sun6i_p2wi_init(base); } #endif |