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| author | Samuel Holland <samuel@sholland.org> | 2021-08-28 13:22:41 -0500 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2022-04-04 23:24:16 +0100 |
| commit | 12bd00aafc5a0848d21dbc096b6481d62bba976c (patch) | |
| tree | 837719e9a570e27e01b170a0e690d27ac2f63752 | |
| parent | fcdbbd68d389e9696e707706917b72c21f9f946b (diff) | |
| download | u-boot-12bd00aafc5a0848d21dbc096b6481d62bba976c.zip u-boot-12bd00aafc5a0848d21dbc096b6481d62bba976c.tar.gz u-boot-12bd00aafc5a0848d21dbc096b6481d62bba976c.tar.bz2 | |
net: sunxi_emac: Remove non-DM pin setup
This is now handled automatically by the pinctrl driver.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| -rw-r--r-- | arch/arm/include/asm/arch-sunxi/gpio.h | 1 | ||||
| -rw-r--r-- | drivers/net/sunxi_emac.c | 7 |
2 files changed, 1 insertions, 7 deletions
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h index 773711b..e93c9e8 100644 --- a/arch/arm/include/asm/arch-sunxi/gpio.h +++ b/arch/arm/include/asm/arch-sunxi/gpio.h @@ -135,7 +135,6 @@ enum sunxi_gpio_number { #define SUNXI_GPIO_OUTPUT 1 #define SUNXI_GPIO_DISABLE 7 -#define SUNXI_GPA_EMAC 2 #define SUN6I_GPA_GMAC 2 #define SUN7I_GPA_GMAC 5 #define SUN8I_H3_GPA_UART0 2 diff --git a/drivers/net/sunxi_emac.c b/drivers/net/sunxi_emac.c index 17ad88e..d15b0ad 100644 --- a/drivers/net/sunxi_emac.c +++ b/drivers/net/sunxi_emac.c @@ -17,7 +17,6 @@ #include <net.h> #include <asm/io.h> #include <asm/arch/clock.h> -#include <asm/arch/gpio.h> /* EMAC register */ struct emac_regs { @@ -511,15 +510,11 @@ static int sunxi_emac_board_setup(struct udevice *dev, struct sunxi_sramc_regs *sram = (struct sunxi_sramc_regs *)SUNXI_SRAMC_BASE; struct emac_regs *regs = priv->regs; - int pin, ret; + int ret; /* Map SRAM to EMAC */ setbits_le32(&sram->ctrl1, 0x5 << 2); - /* Configure pin mux settings for MII Ethernet */ - for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) - sunxi_gpio_set_cfgpin(pin, SUNXI_GPA_EMAC); - /* Set up clock gating */ ret = clk_enable(&priv->clk); if (ret) { |