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| author | Tom Rini <trini@konsulko.com> | 2022-02-26 10:21:13 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-02-26 10:21:13 -0500 |
| commit | 7228ef94824c6442546431582dad0e3794264501 (patch) | |
| tree | 005dad53f4b7a98da42b05a111e379537cf76f5c | |
| parent | c6ae38b38967a5c33d729c20e508a03ba3e0e3f6 (diff) | |
| parent | 4ce849f535ba185288c27e30091d71446e32a47a (diff) | |
| download | u-boot-7228ef94824c6442546431582dad0e3794264501.zip u-boot-7228ef94824c6442546431582dad0e3794264501.tar.gz u-boot-7228ef94824c6442546431582dad0e3794264501.tar.bz2 | |
Merge https://source.denx.de/u-boot/custodians/u-boot-sh
- rzg2_beacon updates
| -rw-r--r-- | configs/rzg2_beacon_defconfig | 2 | ||||
| -rw-r--r-- | drivers/net/ravb.c | 34 |
2 files changed, 32 insertions, 4 deletions
diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig index e6a0d68..91b3fa2 100644 --- a/configs/rzg2_beacon_defconfig +++ b/configs/rzg2_beacon_defconfig @@ -62,7 +62,7 @@ CONFIG_DM_MTD=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_BITBANGMII=y -CONFIG_PHY_REALTEK=y +CONFIG_PHY_ATHEROS=y CONFIG_DM_ETH=y CONFIG_RENESAS_RAVB=y CONFIG_DM_REGULATOR=y diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 1d1118c..4078d33 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -52,6 +52,7 @@ #define CSR_OPS 0x0000000F #define CSR_OPS_CONFIG BIT(1) +#define APSR_RDM BIT(13) #define APSR_TDM BIT(14) #define TCCR_TSRQ0 BIT(0) @@ -376,6 +377,9 @@ static int ravb_dmac_init(struct udevice *dev) struct ravb_priv *eth = dev_get_priv(dev); struct eth_pdata *pdata = dev_get_plat(dev); int ret = 0; + int mode = 0; + unsigned int delay; + bool explicit_delay = false; /* Set CONFIG mode */ ret = ravb_reset(dev); @@ -402,9 +406,33 @@ static int ravb_dmac_init(struct udevice *dev) (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995)) return 0; - if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) || - (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)) - writel(APSR_TDM, eth->iobase + RAVB_REG_APSR); + if (!dev_read_u32(dev, "rx-internal-delay-ps", &delay)) { + /* Valid values are 0 and 1800, according to DT bindings */ + if (delay) { + mode |= APSR_RDM; + explicit_delay = true; + } + } + + if (!dev_read_u32(dev, "tx-internal-delay-ps", &delay)) { + /* Valid values are 0 and 2000, according to DT bindings */ + if (delay) { + mode |= APSR_TDM; + explicit_delay = true; + } + } + + if (!explicit_delay) { + if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || + pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID) + mode |= APSR_RDM; + + if (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID || + pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID) + mode |= APSR_TDM; + } + + writel(mode, eth->iobase + RAVB_REG_APSR); return 0; } |