Merge tag 'xilinx-for-v2023.01-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.01-rc3

microblaze:
- Enable 32 bit addressing mode for SPIs

zynq:
- Minor DT fixes (PL clock enabling)

zynqmp:
- Disable watchdog by default
- Remove unused xlnx,eeprom chosen support
- Add missing symlink for vck190 SC revB
- Use mdio bus with ethernet-phy-id description

versal:
- Add mini qspi/ospi configuration

versal-net:
- Add soc driver
- Fix Kconfig entry for SOC
- Fix loading address location for MINI configuration
- Disable LMB for mini configuration

net:
- Fix ethernet-phy-id usage in the code

pinctrl:
- Revert high impedance/output enable support

timer:
- Fix timer relocation for Microblaze
- Fix timer wrap in 32bit Xilinx timer driver

31 files changed, 468 insertions, 74 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index 97b2f69..bc9081b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -664,6 +664,7 @@ M:	Michal Simek <michal.simek@amd.com>
 S:	Maintained
 T:	git https://source.denx.de/u-boot/custodians/u-boot-microblaze.git
 F:	arch/arm/mach-versal-net/
+F:	drivers/soc/soc_xilinx_versal_net.c
 N:	(?<!uni)versal-net
 
 ARM VERSAL
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7866e8f..f95ed71 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1230,7 +1230,7 @@ config ARCH_VERSAL
 	imply ENV_VARS_UBOOT_RUNTIME_CONFIG
 
 config ARCH_VERSAL_NET
-	bool "Support Xilinx Keystone Platform"
+	bool "Support Xilinx Versal NET Platform"
 	select ARM64
 	select CLK
 	select DM
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e89598a..43951a7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -383,6 +383,8 @@ dtb-$(CONFIG_ARCH_VERSAL) += \
 	versal-mini.dtb \
 	versal-mini-emmc0.dtb \
 	versal-mini-emmc1.dtb \
+	versal-mini-ospi-single.dtb \
+	versal-mini-qspi-single.dtb \
 	xilinx-versal-virt.dtb
 dtb-$(CONFIG_ARCH_VERSAL_NET) += \
 	versal-net-mini.dtb \
diff --git a/arch/arm/dts/versal-mini-ospi-single.dts b/arch/arm/dts/versal-mini-ospi-single.dts
new file mode 100644
index 0000000..23f6e47
--- /dev/null
+++ b/arch/arm/dts/versal-mini-ospi-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI single DTS
+ *
+ * Copyright (C) 2018-2020 Xilinx, Inc.
+ */
+
+#include "versal-mini-ospi.dtsi"
+
+/ {
+	model = "Xilinx Versal MINI OSPI SINGLE";
+};
+
+&flash0 {
+	spi-rx-bus-width = <8>;
+};
diff --git a/arch/arm/dts/versal-mini-ospi.dtsi b/arch/arm/dts/versal-mini-ospi.dtsi
new file mode 100644
index 0000000..a4b76e2
--- /dev/null
+++ b/arch/arm/dts/versal-mini-ospi.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal Mini OSPI Configuration
+ *
+ * (C) Copyright 2018-2019, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "xlnx,versal";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Xilinx Versal MINI OSPI";
+
+	clk125: clk125 {
+		compatible = "fixed-clock";
+		#clock-cells = <0x0>;
+		clock-frequency = <125000000>;
+	};
+
+	dcc: dcc {
+		compatible = "arm,dcc";
+		status = "okay";
+		u-boot,dm-pre-reloc;
+	};
+
+	amba: amba {
+		u-boot,dm-pre-reloc;
+		compatible = "simple-bus";
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+
+		ospi: spi@f1010000 {
+			compatible = "cadence,qspi", "cdns,qspi-nor";
+			status = "okay";
+			reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
+			clock-names = "ref_clk", "pclk";
+			clocks = <&clk125 &clk125>;
+			bus-num = <2>;
+			num-cs = <1>;
+			cdns,fifo-depth = <256>;
+			cdns,fifo-width = <4>;
+			cdns,is-dma = <1>;
+			cdns,trigger-address = <0xc0000000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			flash0: flash@0 {
+				compatible = "n25q512a", "micron,m25p80",
+					     "jedec,spi-nor";
+				reg = <0x0>;
+				spi-tx-bus-width = <8>;
+				spi-rx-bus-width = <8>;
+				spi-max-frequency = <20000000>;
+			};
+		};
+	};
+
+	aliases {
+		serial0 = &dcc;
+		spi0 = &ospi;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200";
+	};
+
+	memory@fffc0000 {
+		device_type = "memory";
+		reg = <0x0 0xfffc0000 0x0 0x40000>;
+	};
+};
diff --git a/arch/arm/dts/versal-mini-qspi-single.dts b/arch/arm/dts/versal-mini-qspi-single.dts
new file mode 100644
index 0000000..ee518d5
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi-single.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal QSPI single DTS
+ *
+ * Copyright (C) 2018-2019 Xilinx, Inc.
+ */
+
+#include "versal-mini-qspi.dtsi"
+
+/ {
+	model = "Xilinx Versal MINI QSPI SINGLE";
+};
+
+&flash0 {
+	spi-rx-bus-width = <4>;
+};
diff --git a/arch/arm/dts/versal-mini-qspi.dtsi b/arch/arm/dts/versal-mini-qspi.dtsi
new file mode 100644
index 0000000..71d0ba5
--- /dev/null
+++ b/arch/arm/dts/versal-mini-qspi.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal Mini QSPI Configuration
+ *
+ * (C) Copyright 2018-2019, Xilinx, Inc.
+ *
+ * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+
+/dts-v1/;
+
+/ {
+	compatible = "xlnx,versal";
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "Xilinx Versal MINI QSPI";
+
+	clk150: clk150 {
+		compatible = "fixed-clock";
+		#clock-cells = <0x0>;
+		clock-frequency = <150000000>;
+	};
+
+	dcc: dcc {
+		compatible = "arm,dcc";
+		status = "okay";
+		u-boot,dm-pre-reloc;
+	};
+
+	amba: amba {
+		u-boot,dm-pre-reloc;
+		compatible = "simple-bus";
+		#address-cells = <0x2>;
+		#size-cells = <0x2>;
+		ranges;
+
+		qspi: spi@f1030000 {
+			compatible = "xlnx,versal-qspi-1.0";
+			status = "okay";
+			clock-names = "ref_clk", "pclk";
+			num-cs = <0x1>;
+			reg = <0x0 0xf1030000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&clk150 &clk150>;
+
+			flash0: flash@0 {
+				compatible = "n25q512a", "micron,m25p80",
+					     "jedec,spi-nor";
+				reg = <0x0>;
+				spi-tx-bus-width = <4>;
+				spi-rx-bus-width = <4>;
+				spi-max-frequency = <20000000>;
+			};
+		};
+	};
+
+	aliases {
+		serial0 = &dcc;
+		spi0 = &qspi;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200";
+	};
+
+	memory@fffc0000 {
+		device_type = "memory";
+		reg = <0x0 0xfffc0000 0x0 0x40000>;
+	};
+};
diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index edc147d..f72ef52 100644
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -340,7 +340,7 @@
 				u-boot,dm-pre-reloc;
 				#clock-cells = <1>;
 				compatible = "xlnx,ps7-clkc";
-				fclk-enable = <0>;
+				fclk-enable = <0xf>;
 				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
 						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
 						"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts
index 3e13767..4858b4d 100644
--- a/arch/arm/dts/zynqmp-zcu106-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu106-revA.dts
@@ -200,12 +200,19 @@
 	phy-mode = "rgmii-id";
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gem3_default>;
-	phy0: ethernet-phy@c {
-		reg = <0xc>;
-		ti,rx-internal-delay = <0x8>;
-		ti,tx-internal-delay = <0xa>;
-		ti,fifo-depth = <0x1>;
-		ti,dp83867-rxctrl-strap-quirk;
+	mdio: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		phy0: ethernet-phy@c {
+			#phy-cells = <1>;
+			reg = <0xc>;
+			compatible = "ethernet-phy-id2000.a231";
+			ti,rx-internal-delay = <0x8>;
+			ti,tx-internal-delay = <0xa>;
+			ti,fifo-depth = <0x1>;
+			ti,dp83867-rxctrl-strap-quirk;
+			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;
+		};
 	};
 };
 
diff --git a/arch/arm/mach-versal-net/cpu.c b/arch/arm/mach-versal-net/cpu.c
index 4c9b154..a82741e 100644
--- a/arch/arm/mach-versal-net/cpu.c
+++ b/arch/arm/mach-versal-net/cpu.c
@@ -15,6 +15,7 @@
 #include <asm/arch/hardware.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/cache.h>
+#include <dm/platdata.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -87,3 +88,7 @@ u64 get_page_table_size(void)
 {
 	return 0x14000;
 }
+
+U_BOOT_DRVINFO(soc_xilinx_versal_net) = {
+	.name = "soc_xilinx_versal_net",
+};
diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h
index 1dc16d4..268ec50 100644
--- a/arch/arm/mach-zynq/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynq/include/mach/sys_proto.h
@@ -17,6 +17,4 @@ extern int zynq_slcr_get_mio_pin_status(const char *periph);
 extern void zynq_ddrc_init(void);
 extern unsigned int zynq_get_silicon_version(void);
 
-int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
-
 #endif /* _SYS_PROTO_H_ */
diff --git a/arch/arm/mach-zynqmp/include/mach/sys_proto.h b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
index 9fffb4e..c6733ed 100644
--- a/arch/arm/mach-zynqmp/include/mach/sys_proto.h
+++ b/arch/arm/mach-zynqmp/include/mach/sys_proto.h
@@ -46,7 +46,6 @@ enum {
 	TCM_SPLIT,
 };
 
-int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
 unsigned int zynqmp_get_silicon_version(void);
 
 int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
diff --git a/board/xilinx/common/board.c b/board/xilinx/common/board.c
index 99fdbac..59d87f2 100644
--- a/board/xilinx/common/board.c
+++ b/board/xilinx/common/board.c
@@ -54,34 +54,6 @@ struct efi_capsule_update_info update_info = {
 u8 num_image_type_guids = ARRAY_SIZE(fw_images);
 #endif /* EFI_HAVE_CAPSULE_SUPPORT */
 
-#if defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
-int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
-{
-	int ret = -EINVAL;
-	struct udevice *dev;
-	ofnode eeprom;
-
-	eeprom = ofnode_get_chosen_node("xlnx,eeprom");
-	if (!ofnode_valid(eeprom))
-		return -ENODEV;
-
-	debug("%s: Path to EEPROM %s\n", __func__,
-	      ofnode_read_chosen_string("xlnx,eeprom"));
-
-	ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
-	if (ret)
-		return ret;
-
-	ret = dm_i2c_read(dev, CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET, ethaddr, 6);
-	if (ret)
-		debug("%s: I2C EEPROM MAC address read failed\n", __func__);
-	else
-		debug("%s: I2C EEPROM MAC %pM\n", __func__, ethaddr);
-
-	return ret;
-}
-#endif
-
 #define EEPROM_HEADER_MAGIC		0xdaaddeed
 #define EEPROM_HDR_MANUFACTURER_LEN	16
 #define EEPROM_HDR_NAME_LEN		16
diff --git a/board/xilinx/zynqmp/zynqmp-e-a2197-00-revB b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revB
new file mode 120000
index 0000000..15ccce3
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-e-a2197-00-revB
@@ -0,0 +1 @@
+zynqmp-e-a2197-00-revA
\ No newline at end of file
diff --git a/configs/microblaze-generic_defconfig b/configs/microblaze-generic_defconfig
index 1a23dc5..f1b9cb4 100644
--- a/configs/microblaze-generic_defconfig
+++ b/configs/microblaze-generic_defconfig
@@ -71,6 +71,7 @@ CONFIG_FLASH_CFI_MTD=y
 CONFIG_SYS_FLASH_PROTECTION=y
 CONFIG_SYS_FLASH_CFI=y
 CONFIG_SYS_MAX_FLASH_SECT=2048
+CONFIG_SPI_FLASH_BAR=y
 CONFIG_SPI_FLASH_ISSI=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
diff --git a/configs/xilinx_versal_mini_ospi_defconfig b/configs/xilinx_versal_mini_ospi_defconfig
new file mode 100644
index 0000000..2c4e210
--- /dev/null
+++ b/configs/xilinx_versal_mini_ospi_defconfig
@@ -0,0 +1,72 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi"
+CONFIG_COUNTER_FREQUENCY=100000000
+CONFIG_ARCH_VERSAL=y
+CONFIG_TEXT_BASE=0xFFFC0000
+CONFIG_SYS_MALLOC_LEN=0x2000
+CONFIG_SYS_MALLOC_F_LEN=0x500
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x80
+# CONFIG_DM_GPIO is not set
+CONFIG_DEFAULT_DEVICE_TREE="versal-mini-ospi-single"
+CONFIG_SYS_PROMPT="Versal> "
+CONFIG_SYS_MEM_RSVD_FOR_MMU=y
+CONFIG_VERSAL_NO_DDR=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE0000
+# CONFIG_EXPERT is not set
+# CONFIG_AUTOBOOT is not set
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_BOARD_LATE_INIT is not set
+# CONFIG_CMDLINE_EDITING is not set
+# CONFIG_AUTO_COMPLETE is not set
+# CONFIG_SYS_LONGHELP is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_NET is not set
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=30000000
+CONFIG_SPI_FLASH_SOFT_RESET=y
+CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MT35XU=y
+CONFIG_ARM_DCC=y
+CONFIG_SOC_XILINX_VERSAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_CADENCE_QSPI=y
+CONFIG_HAS_CQSPI_REF_CLK=y
+CONFIG_CQSPI_REF_CLK=200000000
+CONFIG_CADENCE_OSPI_VERSAL=y
+# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_mini_qspi_defconfig b/configs/xilinx_versal_mini_qspi_defconfig
new file mode 100644
index 0000000..0062f6a
--- /dev/null
+++ b/configs/xilinx_versal_mini_qspi_defconfig
@@ -0,0 +1,75 @@
+CONFIG_ARM=y
+CONFIG_SYS_CONFIG_NAME="xilinx_versal_mini_qspi"
+CONFIG_COUNTER_FREQUENCY=100000000
+CONFIG_ARCH_VERSAL=y
+CONFIG_TEXT_BASE=0xFFFC0000
+CONFIG_SYS_MALLOC_LEN=0x2000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_ENV_SIZE=0x80
+CONFIG_DEFAULT_DEVICE_TREE="versal-mini-qspi-single"
+CONFIG_SYS_PROMPT="Versal> "
+CONFIG_SYS_MEM_RSVD_FOR_MMU=y
+CONFIG_VERSAL_NO_DDR=y
+# CONFIG_PSCI_RESET is not set
+CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xFFFE0000
+# CONFIG_EXPERT is not set
+# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set
+# CONFIG_AUTOBOOT is not set
+CONFIG_LOGLEVEL=0
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+# CONFIG_BOARD_LATE_INIT is not set
+# CONFIG_CMDLINE_EDITING is not set
+# CONFIG_AUTO_COMPLETE is not set
+# CONFIG_SYS_LONGHELP is not set
+# CONFIG_SYS_XTRACE is not set
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_BOOTD is not set
+# CONFIG_CMD_BOOTM is not set
+# CONFIG_CMD_BOOTI is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_FDT is not set
+# CONFIG_CMD_GO is not set
+# CONFIG_CMD_RUN is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_SAVEENV is not set
+# CONFIG_CMD_ENV_EXISTS is not set
+# CONFIG_CMD_CRC32 is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+# CONFIG_CMD_ECHO is not set
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
+# CONFIG_NET is not set
+# CONFIG_DM_WARN is not set
+# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_GPIO is not set
+# CONFIG_I2C is not set
+# CONFIG_INPUT is not set
+# CONFIG_MMC is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SF_DEFAULT_SPEED=30000000
+# CONFIG_SPI_FLASH_SMART_HWCAPS is not set
+# CONFIG_SPI_FLASH_UNLOCK_ALL is not set
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+# CONFIG_POWER is not set
+CONFIG_ARM_DCC=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_mini_defconfig b/configs/xilinx_versal_net_mini_defconfig
index e3aa45c..c5fa431 100644
--- a/configs/xilinx_versal_net_mini_defconfig
+++ b/configs/xilinx_versal_net_mini_defconfig
@@ -13,7 +13,7 @@ CONFIG_DEFAULT_DEVICE_TREE="versal-net-mini"
 CONFIG_SYS_PROMPT="Versal NET> "
 CONFIG_SYS_MEM_RSVD_FOR_MMU=y
 # CONFIG_PSCI_RESET is not set
-CONFIG_SYS_LOAD_ADDR=0x8000000
+CONFIG_SYS_LOAD_ADDR=0xBBF00000
 CONFIG_SYS_MEMTEST_START=0x00000000
 CONFIG_SYS_MEMTEST_END=0x00001000
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
@@ -70,3 +70,4 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ARM_DCC=y
 CONFIG_PL01X_SERIAL=y
 # CONFIG_GZIP is not set
+# CONFIG_LMB is not set
diff --git a/configs/xilinx_versal_net_virt_defconfig b/configs/xilinx_versal_net_virt_defconfig
index 8a53490..431a8de 100644
--- a/configs/xilinx_versal_net_virt_defconfig
+++ b/configs/xilinx_versal_net_virt_defconfig
@@ -108,6 +108,8 @@ CONFIG_RESET_ZYNQMP=y
 CONFIG_ARM_DCC=y
 CONFIG_PL01X_SERIAL=y
 CONFIG_XILINX_UARTLITE=y
+CONFIG_SOC_DEVICE=y
+CONFIG_SOC_XILINX_VERSAL_NET=y
 CONFIG_SPI=y
 CONFIG_DM_SPI=y
 CONFIG_CADENCE_QSPI=y
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig
index ea11127..9696e41 100644
--- a/configs/xilinx_zynqmp_virt_defconfig
+++ b/configs/xilinx_zynqmp_virt_defconfig
@@ -81,7 +81,6 @@ CONFIG_CMD_SF_TEST=y
 CONFIG_CMD_SPI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_USB_MASS_STORAGE=y
-CONFIG_CMD_WDT=y
 CONFIG_BOOTP_MAY_FAIL=y
 CONFIG_BOOTP_BOOTFILESIZE=y
 CONFIG_CMD_TFTPPUT=y
@@ -229,7 +228,6 @@ CONFIG_SPLASH_SCREEN=y
 CONFIG_BMP_16BPP=y
 CONFIG_BMP_24BPP=y
 CONFIG_BMP_32BPP=y
-CONFIG_WDT=y
 CONFIG_PANIC_HANG=y
 CONFIG_TPM=y
 CONFIG_SPL_GZIP=y
diff --git a/drivers/core/ofnode.c b/drivers/core/ofnode.c
index 14bbfe7..4d56b1a 100644
--- a/drivers/core/ofnode.c
+++ b/drivers/core/ofnode.c
@@ -1197,12 +1197,12 @@ int ofnode_read_eth_phy_id(ofnode node, u16 *vendor, u16 *device)
 	while (list < end) {
 		len = strlen(list);
 
-		if (len >= strlen("ethernet-phy-idVVVV,DDDD")) {
+		if (len >= strlen("ethernet-phy-idVVVV.DDDD")) {
 			char *s = strstr(list, "ethernet-phy-id");
 
 			/*
 			 * check if the string is something like
-			 * ethernet-phy-idVVVV,DDDD
+			 * ethernet-phy-idVVVV.DDDD
 			 */
 			if (s && s[19] == '.') {
 				s += strlen("ethernet-phy-id");
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 3f4357e..507b19b 100644
--- a/drivers/net/zynq_gem.c
+++ b/drivers/net/zynq_gem.c
@@ -662,21 +662,6 @@ static void zynq_gem_halt(struct udevice *dev)
 						ZYNQ_GEM_NWCTRL_TXEN_MASK, 0);
 }
 
-__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
-{
-	return -ENOSYS;
-}
-
-static int zynq_gem_read_rom_mac(struct udevice *dev)
-{
-	struct eth_pdata *pdata = dev_get_plat(dev);
-
-	if (!pdata)
-		return -ENOSYS;
-
-	return zynq_board_read_rom_ethaddr(pdata->enetaddr);
-}
-
 static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr,
 				int devad, int reg)
 {
@@ -884,7 +869,6 @@ static const struct eth_ops zynq_gem_ops = {
 	.free_pkt		= zynq_gem_free_pkt,
 	.stop			= zynq_gem_halt,
 	.write_hwaddr		= zynq_gem_setup_mac,
-	.read_rom_hwaddr	= zynq_gem_read_rom_mac,
 };
 
 static int zynq_gem_of_to_plat(struct udevice *dev)
diff --git a/drivers/pinctrl/pinctrl-zynqmp.c b/drivers/pinctrl/pinctrl-zynqmp.c
index 52d428f..7c5a02d 100644
--- a/drivers/pinctrl/pinctrl-zynqmp.c
+++ b/drivers/pinctrl/pinctrl-zynqmp.c
@@ -467,10 +467,6 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin,
 				 pin);
 		break;
 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
-		param = PM_PINCTRL_CONFIG_TRI_STATE;
-		arg = PM_PINCTRL_TRI_STATE_ENABLE;
-		ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
-		break;
 	case PIN_CONFIG_LOW_POWER_MODE:
 		/*
 		 * This cases are mentioned in dts but configurable
@@ -479,11 +475,6 @@ static int zynqmp_pinconf_set(struct udevice *dev, unsigned int pin,
 		 */
 		ret = 0;
 		break;
-	case PIN_CONFIG_OUTPUT_ENABLE:
-		param = PM_PINCTRL_CONFIG_TRI_STATE;
-		arg = PM_PINCTRL_TRI_STATE_DISABLE;
-		ret = zynqmp_pm_pinctrl_set_config(pin, param, arg);
-		break;
 	default:
 		dev_warn(dev, "unsupported configuration parameter '%u'\n",
 			 param);
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index 292dc41..acf555b 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -32,6 +32,14 @@ config SOC_XILINX_VERSAL
 	  This allows other drivers to verify the SoC familiy & revision using
 	  matching SoC attributes.
 
+config SOC_XILINX_VERSAL_NET
+	bool "Enable SoC Device ID driver for Xilinx Versal NET"
+	depends on SOC_DEVICE && ARCH_VERSAL_NET
+	help
+	  Enable this option to select SoC device id driver for Xilinx Versal NET.
+	  This allows other drivers to verify the SoC familiy & revision using
+	  matching SoC attributes.
+
 source "drivers/soc/ti/Kconfig"
 
 endmenu
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 031fa76..8438565 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SOC_DEVICE_TI_K3) += soc_ti_k3.o
 obj-$(CONFIG_SANDBOX) += soc_sandbox.o
 obj-$(CONFIG_SOC_XILINX_ZYNQMP) += soc_xilinx_zynqmp.o
 obj-$(CONFIG_SOC_XILINX_VERSAL) += soc_xilinx_versal.o
+obj-$(CONFIG_SOC_XILINX_VERSAL_NET) += soc_xilinx_versal_net.o
diff --git a/drivers/soc/soc_xilinx_versal_net.c b/drivers/soc/soc_xilinx_versal_net.c
new file mode 100644
index 0000000..146d068
--- /dev/null
+++ b/drivers/soc/soc_xilinx_versal_net.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Versal NET SOC driver
+ *
+ * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <soc.h>
+#include <zynqmp_firmware.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+#include <linux/bitfield.h>
+
+/*
+ * v1 -> 0x10 - ES1
+ * v2 -> 0x20 - Production
+ */
+static const char versal_family[] = "Versal NET";
+
+struct soc_xilinx_versal_net_priv {
+	const char *family;
+	char revision;
+};
+
+static int soc_xilinx_versal_net_get_family(struct udevice *dev, char *buf, int size)
+{
+	struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev);
+
+	return snprintf(buf, size, "%s", priv->family);
+}
+
+static int soc_xilinx_versal_net_get_revision(struct udevice *dev, char *buf, int size)
+{
+	struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev);
+
+	return snprintf(buf, size, "v%d", priv->revision);
+}
+
+static const struct soc_ops soc_xilinx_versal_net_ops = {
+	.get_family = soc_xilinx_versal_net_get_family,
+	.get_revision = soc_xilinx_versal_net_get_revision,
+};
+
+static int soc_xilinx_versal_net_probe(struct udevice *dev)
+{
+	struct soc_xilinx_versal_net_priv *priv = dev_get_priv(dev);
+	u32 ret_payload[PAYLOAD_ARG_CNT];
+	int ret;
+
+	priv->family = versal_family;
+
+	if (IS_ENABLED(CONFIG_ZYNQMP_FIRMWARE)) {
+		ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0,
+					ret_payload);
+		if (ret)
+			return ret;
+	} else {
+		ret_payload[2] = readl(PMC_TAP_VERSION);
+		if (!ret_payload[2])
+			return -EINVAL;
+	}
+
+	priv->revision = FIELD_GET(PS_VERSION_MASK, ret_payload[2]);
+
+	return 0;
+}
+
+U_BOOT_DRIVER(soc_xilinx_versal_net) = {
+	.name		= "soc_xilinx_versal_net",
+	.id		= UCLASS_SOC,
+	.ops		= &soc_xilinx_versal_net_ops,
+	.probe		= soc_xilinx_versal_net_probe,
+	.priv_auto	= sizeof(struct soc_xilinx_versal_net_priv),
+	.flags		= DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index a9547a8..e0d5e6b 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -182,11 +182,11 @@ int cadence_qspi_versal_flash_reset(struct udevice *dev)
 
 	/* set direction as output */
 	writel((readl(BOOT_MODE_DIR) | BIT(FLASH_RESET_GPIO)),
-	       BOOT_MODE_POR_0);
+	       BOOT_MODE_DIR);
 
 	/* Data output enable */
 	writel((readl(BOOT_MODE_OUT) | BIT(FLASH_RESET_GPIO)),
-	       BOOT_MODE_POR_1);
+	       BOOT_MODE_OUT);
 
 	/* IOU SLCR write enable */
 	writel(0, WPROT_PMC_MIO);
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 49facc4..48eff77 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -104,7 +104,8 @@
 #define TAP_DLY_BYPASS_LQSPI_RX_VALUE	0x1
 #define TAP_DLY_BYPASS_LQSPI_RX_SHIFT	2
 #define GQSPI_DATA_DLY_ADJ_OFST		0x000001F8
-#define IOU_TAPDLY_BYPASS_OFST !IS_ENABLED(CONFIG_ARCH_VERSAL) ? \
+#define IOU_TAPDLY_BYPASS_OFST !(IS_ENABLED(CONFIG_ARCH_VERSAL) || \
+				 IS_ENABLED(CONFIG_ARCH_VERSAL_NET)) ? \
 				0xFF180390 : 0xF103003C
 #define GQSPI_LPBK_DLY_ADJ_LPBK_MASK	0x00000020
 #define GQSPI_FREQ_37_5MHZ		37500000
diff --git a/drivers/timer/timer-uclass.c b/drivers/timer/timer-uclass.c
index cbc3647..bb71979 100644
--- a/drivers/timer/timer-uclass.c
+++ b/drivers/timer/timer-uclass.c
@@ -18,6 +18,7 @@
 #include <init.h>
 #include <timer.h>
 #include <linux/err.h>
+#include <relocate.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -32,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int notrace timer_get_count(struct udevice *dev, u64 *count)
 {
-	const struct timer_ops *ops = device_get_ops(dev);
+	struct timer_ops *ops = timer_get_ops(dev);
 
 	if (!ops->get_count)
 		return -ENOSYS;
@@ -50,6 +51,19 @@ unsigned long notrace timer_get_rate(struct udevice *dev)
 
 static int timer_pre_probe(struct udevice *dev)
 {
+	if (IS_ENABLED(CONFIG_NEEDS_MANUAL_RELOC) &&
+	    (gd->flags & GD_FLG_RELOC)) {
+		struct timer_ops *ops = timer_get_ops(dev);
+		static int reloc_done;
+
+		if (!reloc_done) {
+			if (ops->get_count)
+				MANUAL_RELOC(ops->get_count);
+
+			reloc_done++;
+		}
+	}
+
 	if (CONFIG_IS_ENABLED(OF_REAL)) {
 		struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
 		struct clk timer_clk;
diff --git a/drivers/timer/xilinx-timer.c b/drivers/timer/xilinx-timer.c
index 75b4473..172fd9f 100644
--- a/drivers/timer/xilinx-timer.c
+++ b/drivers/timer/xilinx-timer.c
@@ -40,7 +40,7 @@ static u64 xilinx_timer_get_count(struct udevice *dev)
 
 	regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value);
 
-	return value;
+	return timer_conv_64(value);
 }
 
 static int xilinx_timer_probe(struct udevice *dev)
diff --git a/include/timer.h b/include/timer.h
index a044cb0..d33a26e 100644
--- a/include/timer.h
+++ b/include/timer.h
@@ -6,6 +6,8 @@
 #ifndef _TIMER_H_
 #define _TIMER_H_
 
+#define timer_get_ops(dev)	((struct timer_ops *)(dev)->driver->ops)
+
 /**
  * dm_timer_init() - initialize a timer for time keeping. On success
  * initializes gd->timer so that lib/timer can use it for future