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| author | Tom Rini <trini@konsulko.com> | 2022-07-31 21:08:28 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-08-12 16:10:49 -0400 |
| commit | 4143a237947576b581eed1eaf88c207df80d418e (patch) | |
| tree | 3e8c198fc6f9d0906928377de928170df1786d2b | |
| parent | 1de46d91dddfd60107c665530aed6ac25f55960e (diff) | |
| download | u-boot-4143a237947576b581eed1eaf88c207df80d418e.zip u-boot-4143a237947576b581eed1eaf88c207df80d418e.tar.gz u-boot-4143a237947576b581eed1eaf88c207df80d418e.tar.bz2 | |
Convert CONFIG_SYS_FSL_PCIE_COMPAT to Kconfig
This converts the following to Kconfig:
CONFIG_SYS_FSL_PCIE_COMPAT
To do this, introduce a choice and option for each of the strings used
and set CONFIG_SYS_FSL_PCIE_COMPAT based on that.
Signed-off-by: Tom Rini <trini@konsulko.com>
| -rw-r--r-- | README | 5 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/Kconfig | 37 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/config_mpc85xx.h | 12 |
3 files changed, 37 insertions, 17 deletions
@@ -300,11 +300,6 @@ The following options need to be configured: system clock. On most PQ3 devices this is 8, on newer QorIQ devices it can be 16 or 32. The ratio varies from SoC to Soc. - CONFIG_SYS_FSL_PCIE_COMPAT - - Defines the string to utilize when trying to match PCIe device - tree nodes for the given platform. - CONFIG_SYS_FSL_ERRATUM_A004510 Enables a workaround for erratum A004510. If set, diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 18ef718..d01e69b 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -259,6 +259,7 @@ config ARCH_B4420 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -289,6 +290,7 @@ config ARCH_B4860 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -326,6 +328,7 @@ config ARCH_BSC9132 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB @@ -434,6 +437,7 @@ config ARCH_P1010 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC_E500_USE_DEBUG_TLB @@ -515,6 +519,7 @@ config ARCH_P1023 select FSL_PCIE_RESET select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC @@ -602,6 +607,7 @@ config ARCH_P2041 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS1 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC @@ -631,6 +637,7 @@ config ARCH_P3041 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS1 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select FSL_ELBC @@ -664,6 +671,7 @@ config ARCH_P4080 select SYS_FSL_ERRATUM_I2C_A004447 select SYS_FSL_ERRATUM_NMG_CPU_A011 select SYS_FSL_ERRATUM_SRIO_A004034 + select SYS_FSL_PCIE_COMPAT_P4080_PCIE select SYS_P4080_ERRATUM_CPU22 select SYS_P4080_ERRATUM_PCIE_A003 select SYS_P4080_ERRATUM_SERDES8 @@ -700,6 +708,7 @@ config ARCH_P5040 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS1 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -730,6 +739,7 @@ config ARCH_T1024 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC @@ -757,6 +767,7 @@ config ARCH_T1040 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC @@ -783,6 +794,7 @@ config ARCH_T1042 select SYS_FSL_HAS_DDR4 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_5 select FSL_IFC @@ -811,6 +823,7 @@ config ARCH_T2080 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -843,6 +856,7 @@ config ARCH_T4240 select SYS_FSL_HAS_DDR3 select SYS_FSL_HAS_SEC select SYS_FSL_QORIQ_CHASSIS2 + select SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 select SYS_FSL_SEC_BE select SYS_FSL_SEC_COMPAT_4 select SYS_PPC64 @@ -1310,6 +1324,29 @@ config SYS_FSL_CPC config SYS_CACHE_STASHING bool "Enable cache stashing" +config SYS_FSL_PCIE_COMPAT_P4080_PCIE + bool + +config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 + bool + +config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 + bool + +config SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 + bool + +config SYS_FSL_PCIE_COMPAT + string + depends on FSL_CORENET + default "fsl,p4080-pcie" if SYS_FSL_PCIE_COMPAT_P4080_PCIE + default "fsl,qoriq-pcie-v2.2" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v22 + default "fsl,qoriq-pcie-v2.4" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v24 + default "fsl,qoriq-pcie-v3.0" if SYS_FSL_PCIE_COMPAT_QORIQ_PCIE_v30 + help + Defines the string to utilize when trying to match PCIe device tree + nodes for the given platform. + config SYS_MPC85XX_NO_RESETVEC bool "Discard resetvec section and move bootpg section up" depends on MPC85xx diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 0d31e70..f972bee 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -27,7 +27,6 @@ #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_FSL_USB1_PHY_ENABLE @@ -50,7 +49,6 @@ #define CONFIG_SYS_QMAN_NUM_PORTALS 3 #define CONFIG_SYS_BMAN_NUM_PORTALS 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x10000 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" /* P1024 is lower end variant of P1020 */ #elif defined(CONFIG_ARCH_P1024) @@ -76,7 +74,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -91,7 +88,6 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 32 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -108,7 +104,6 @@ #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie" #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -124,7 +119,6 @@ #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #define CONFIG_SYS_FSL_USB2_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY @@ -139,7 +133,6 @@ #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 3 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2" #elif defined(CONFIG_ARCH_T4240) #define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */ @@ -166,7 +159,6 @@ #define CONFIG_SYS_FM2_CLK 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 #define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 #define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 @@ -183,7 +175,6 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB1_PHY_ENABLE #ifdef CONFIG_ARCH_B4860 @@ -217,7 +208,6 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE @@ -240,7 +230,6 @@ #define CONFIG_SYS_FM_MURAM_SIZE 0x30000 #define CONFIG_SYS_FSL_SINGLE_SOURCE_CLK #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE @@ -268,7 +257,6 @@ #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 #define CONFIG_SYS_FSL_TBCLK_DIV 16 -#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0" #define CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |