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| author | Andre Przywara <andre.przywara@arm.com> | 2022-05-09 17:08:49 +0100 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-06-03 11:15:24 -0400 |
| commit | 2b641211c51d5357eacadf571d2ee70da16749e1 (patch) | |
| tree | ba2b6952e28fc595bdba9eaaa6e8fdafe9bf3def | |
| parent | 7704b7fd673a603805f5ddd8807f69d4bc3b9188 (diff) | |
| download | u-boot-2b641211c51d5357eacadf571d2ee70da16749e1.zip u-boot-2b641211c51d5357eacadf571d2ee70da16749e1.tar.gz u-boot-2b641211c51d5357eacadf571d2ee70da16749e1.tar.bz2 | |
armv8: Fix TCR 64-bit writes
The AArch64 TCR_ELx register is a 64-bit register, and many newer
architecture features use bits in the upper half. So far U-Boot was
igorant of those bits, trying to leave them alone.
However, in an effort to set bit 31 to 1, it failed doing so, because
the compiler sign-extended "1 << 31", so that all bits[63:31] got set.
Older ARMv8.0 cores don't define anything dangerous up there, but newer
architecture revisions do, and setting all those bits will end badly:
=================
$ qemu-system-aarch64 -cpu max ....
U-Boot 2022.07-rc1 (May 09 2022 - 15:21:00 +0100)
DRAM: 1.5 GiB
================= (hangs here)
Defining TCR_ELx_RSVD to "1U << 31" avoids the sign-extension, so all
upper bits stay at a safe 0 value. This means no more surprises when
U-Boot runs on a more capable CPU core.
Reported-by: Balaji Anandapadmanaban <Balaji.Anandapadmanaban@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tested-by: Peter Collingbourne <pcc@google.com>
Reviewed-by: Peter Collingbourne <pcc@google.com>
| -rw-r--r-- | arch/arm/include/asm/armv8/mmu.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index fc97c55..c36b2cf 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -99,9 +99,9 @@ #define TCR_TG0_16K (2 << 14) #define TCR_EPD1_DISABLE (1 << 23) -#define TCR_EL1_RSVD (1 << 31) -#define TCR_EL2_RSVD (1 << 31 | 1 << 23) -#define TCR_EL3_RSVD (1 << 31 | 1 << 23) +#define TCR_EL1_RSVD (1U << 31) +#define TCR_EL2_RSVD (1U << 31 | 1 << 23) +#define TCR_EL3_RSVD (1U << 31 | 1 << 23) #ifndef __ASSEMBLY__ static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) |