diff options
| author | Tom Rini <trini@konsulko.com> | 2024-03-02 14:30:25 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-03-02 14:30:25 -0500 |
| commit | eac52e4be4e234d563d6911737ee7ccdc0ada1f1 (patch) | |
| tree | 9fc71e478d84ea5be40f1a0196a5507ee31246e4 | |
| parent | 574aac1c8c59522c286bec4cdfb07c22bc3c124d (diff) | |
| parent | 7b1a24765deae9c202012fa9280e884b70f358f1 (diff) | |
| download | u-boot-WIP/02Mar2024.zip u-boot-WIP/02Mar2024.tar.gz u-boot-WIP/02Mar2024.tar.bz2 | |
Merge patch series "ARM: renesas: Rename R-Mobile to Renesas"WIP/02Mar2024
Marek Vasut <marek.vasut+renesas@mailbox.org> says:
Rename R-Mobile to Renesas all over the place because the chips are
made by Renesas, while only a subset of them is from the R-Mobile line.
147 files changed, 439 insertions, 4355 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 0b08ca1..cd9b2d4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -497,7 +497,7 @@ M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> M: Marek Vasut <marek.vasut+renesas@mailbox.org> S: Maintained T: git https://source.denx.de/u-boot/custodians/u-boot-sh.git -F: arch/arm/mach-rmobile/ +F: arch/arm/mach-renesas/ F: drivers/clk/renesas/ F: drivers/gpio/gpio-rcar.c F: drivers/i2c/rcar_* @@ -1266,7 +1266,7 @@ spl/u-boot-spl.srec: spl/u-boot-spl FORCE $(call if_changed,objcopy) %.scif: %.srec - $(Q)$(MAKE) $(build)=arch/arm/mach-rmobile $@ + $(Q)$(MAKE) $(build)=arch/arm/mach-renesas $@ OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec) \ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fde85dc..01d6556 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1071,7 +1071,7 @@ config ARCH_QEMU imply USB_KEYBOARD imply CMD_USB -config ARCH_RMOBILE +config ARCH_RENESAS bool "Renesas ARM SoCs" select DM select DM_SERIAL @@ -2269,7 +2269,7 @@ source "arch/arm/mach-orion5x/Kconfig" source "arch/arm/mach-owl/Kconfig" -source "arch/arm/mach-rmobile/Kconfig" +source "arch/arm/mach-renesas/Kconfig" source "arch/arm/mach-meson/Kconfig" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 5ebe061..a4266a3 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -75,7 +75,7 @@ machine-$(CONFIG_ARCH_NPCM) += npcm machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 machine-$(CONFIG_ARCH_ORION5X) += orion5x machine-$(CONFIG_ARCH_OWL) += owl -machine-$(CONFIG_ARCH_RMOBILE) += rmobile +machine-$(CONFIG_ARCH_RENESAS) += renesas machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-renesas/Kconfig index 38ede6e..2ac8676 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-renesas/Kconfig @@ -1,4 +1,4 @@ -if ARCH_RMOBILE +if ARCH_RENESAS # Renesas ARM SoCs R-Car Gen3/Gen4 (64bit) config RCAR_64 @@ -89,12 +89,12 @@ config RZG2L endchoice config SYS_SOC - default "rmobile" if ARCH_RMOBILE + default "renesas" if ARCH_RENESAS -source "arch/arm/mach-rmobile/Kconfig.32" -source "arch/arm/mach-rmobile/Kconfig.64" -source "arch/arm/mach-rmobile/Kconfig.rza1" -source "arch/arm/mach-rmobile/Kconfig.rzn1" -source "arch/arm/mach-rmobile/Kconfig.rzg2l" +source "arch/arm/mach-renesas/Kconfig.32" +source "arch/arm/mach-renesas/Kconfig.64" +source "arch/arm/mach-renesas/Kconfig.rza1" +source "arch/arm/mach-renesas/Kconfig.rzn1" +source "arch/arm/mach-renesas/Kconfig.rzg2l" endif diff --git a/arch/arm/mach-rmobile/Kconfig.32 b/arch/arm/mach-renesas/Kconfig.32 index 1ac31c2..693a5ab 100644 --- a/arch/arm/mach-rmobile/Kconfig.32 +++ b/arch/arm/mach-renesas/Kconfig.32 @@ -1,6 +1,6 @@ if RCAR_32 -config ARCH_RMOBILE_BOARD_STRING +config ARCH_RENESAS_BOARD_STRING string "Renesas RCar Gen2 board name" default "Board" @@ -10,9 +10,6 @@ config RCAR_GEN2 select PHY_RCAR_GEN2 select TMU_TIMER -config R8A7740 - bool "Renesas SoC R8A7740" - config R8A7790 bool "Renesas SoC R8A7790" select RCAR_GEN2 @@ -125,7 +122,7 @@ endchoice config TMU_TIMER bool -config RMOBILE_EXTRAM_BOOT +config RENESAS_EXTRAM_BOOT bool "Enable boot from RAM" depends on TARGET_ALT || TARGET_BLANCHE || TARGET_KOELSCH || TARGET_LAGER || TARGET_PORTER || TARGET_SILK || TARGET_STOUT diff --git a/arch/arm/mach-rmobile/Kconfig.64 b/arch/arm/mach-renesas/Kconfig.64 index 57ed1d6..b5067d0 100644 --- a/arch/arm/mach-rmobile/Kconfig.64 +++ b/arch/arm/mach-renesas/Kconfig.64 @@ -6,7 +6,7 @@ config SYS_MALLOC_F_LEN config OF_LIBFDT_OVERLAY default y if RCAR_64 -source "arch/arm/mach-rmobile/Kconfig.rcar3" -source "arch/arm/mach-rmobile/Kconfig.rcar4" +source "arch/arm/mach-renesas/Kconfig.rcar3" +source "arch/arm/mach-renesas/Kconfig.rcar4" endif diff --git a/arch/arm/mach-rmobile/Kconfig.rcar3 b/arch/arm/mach-renesas/Kconfig.rcar3 index ad35d10..ad35d10 100644 --- a/arch/arm/mach-rmobile/Kconfig.rcar3 +++ b/arch/arm/mach-renesas/Kconfig.rcar3 diff --git a/arch/arm/mach-rmobile/Kconfig.rcar4 b/arch/arm/mach-renesas/Kconfig.rcar4 index e80dce1..e80dce1 100644 --- a/arch/arm/mach-rmobile/Kconfig.rcar4 +++ b/arch/arm/mach-renesas/Kconfig.rcar4 diff --git a/arch/arm/mach-rmobile/Kconfig.rza1 b/arch/arm/mach-renesas/Kconfig.rza1 index e88f9a2..e88f9a2 100644 --- a/arch/arm/mach-rmobile/Kconfig.rza1 +++ b/arch/arm/mach-renesas/Kconfig.rza1 diff --git a/arch/arm/mach-rmobile/Kconfig.rzg2l b/arch/arm/mach-renesas/Kconfig.rzg2l index dc30bdf..dc30bdf 100644 --- a/arch/arm/mach-rmobile/Kconfig.rzg2l +++ b/arch/arm/mach-renesas/Kconfig.rzg2l diff --git a/arch/arm/mach-rmobile/Kconfig.rzn1 b/arch/arm/mach-renesas/Kconfig.rzn1 index 73138d6..73138d6 100644 --- a/arch/arm/mach-rmobile/Kconfig.rzn1 +++ b/arch/arm/mach-renesas/Kconfig.rzn1 diff --git a/arch/arm/mach-rmobile/Makefile b/arch/arm/mach-renesas/Makefile index ff8b0c7..71e12e0 100644 --- a/arch/arm/mach-rmobile/Makefile +++ b/arch/arm/mach-renesas/Makefile @@ -8,7 +8,6 @@ obj-y += emac.o obj-$(CONFIG_DISPLAY_BOARDINFO) += board.o obj-$(CONFIG_TMU_TIMER) += ../../sh/lib/time.o -obj-$(CONFIG_R8A7740) += lowlevel_init.o cpu_info-r8a7740.o pfc-r8a7740.o obj-$(CONFIG_RCAR_GEN2) += lowlevel_init_ca15.o cpu_info-rcar.o obj-$(CONFIG_RCAR_64) += lowlevel_init_gen3.o obj-$(CONFIG_RCAR_GEN3) += cpu_info-rcar.o memmap-gen3.o diff --git a/arch/arm/mach-rmobile/board.c b/arch/arm/mach-renesas/board.c index 79c7e02..f061e41 100644 --- a/arch/arm/mach-rmobile/board.c +++ b/arch/arm/mach-renesas/board.c @@ -7,10 +7,10 @@ #include <init.h> #include <asm/io.h> -#ifdef CONFIG_ARCH_RMOBILE_BOARD_STRING +#ifdef CONFIG_ARCH_RENESAS_BOARD_STRING int checkboard(void) { - printf("Board: %s\n", CONFIG_ARCH_RMOBILE_BOARD_STRING); + printf("Board: %s\n", CONFIG_ARCH_RENESAS_BOARD_STRING); return 0; } #endif diff --git a/arch/arm/mach-rmobile/cpu_info-rcar.c b/arch/arm/mach-renesas/cpu_info-rcar.c index b9d8b5e..74140fd 100644 --- a/arch/arm/mach-rmobile/cpu_info-rcar.c +++ b/arch/arm/mach-renesas/cpu_info-rcar.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 /* - * arch/arm/cpu/armv7/rmobile/cpu_info-rcar.c + * arch/arm/mach-renesas/cpu_info-rcar.c * * Copyright (C) 2013,2014 Renesas Electronics Corporation */ @@ -13,7 +13,7 @@ #define R8A7796_REV_1_3 0x5211 #define R8A77995_REV_1_1 0x5810 -static u32 rmobile_get_prr(void) +static u32 renesas_get_prr(void) { if (IS_ENABLED(CONFIG_RCAR_64)) return readl(0xFFF00044); @@ -21,14 +21,14 @@ static u32 rmobile_get_prr(void) return readl(0xFF000044); } -u32 rmobile_get_cpu_type(void) +u32 renesas_get_cpu_type(void) { - return (rmobile_get_prr() & 0x00007F00) >> 8; + return (renesas_get_prr() & 0x00007F00) >> 8; } -u32 rmobile_get_cpu_rev_integer(void) +u32 renesas_get_cpu_rev_integer(void) { - const u32 prr = rmobile_get_prr(); + const u32 prr = renesas_get_prr(); const u32 rev = prr & PRR_MASK; if (rev == R8A7796_REV_1_1 || rev == R8A7796_REV_1_3 || @@ -38,9 +38,9 @@ u32 rmobile_get_cpu_rev_integer(void) return ((prr & 0x000000F0) >> 4) + 1; } -u32 rmobile_get_cpu_rev_fraction(void) +u32 renesas_get_cpu_rev_fraction(void) { - const u32 prr = rmobile_get_prr(); + const u32 prr = renesas_get_prr(); const u32 rev = prr & PRR_MASK; if (rev == R8A7796_REV_1_1 || rev == R8A77995_REV_1_1) diff --git a/arch/arm/mach-rmobile/cpu_info-rzg.c b/arch/arm/mach-renesas/cpu_info-rzg.c index 4ade4bc..4ade4bc 100644 --- a/arch/arm/mach-rmobile/cpu_info-rzg.c +++ b/arch/arm/mach-renesas/cpu_info-rzg.c diff --git a/arch/arm/mach-rmobile/cpu_info-rzg2l.c b/arch/arm/mach-renesas/cpu_info-rzg2l.c index bd3146f..ab95ce7 100644 --- a/arch/arm/mach-rmobile/cpu_info-rzg2l.c +++ b/arch/arm/mach-renesas/cpu_info-rzg2l.c @@ -4,7 +4,7 @@ * */ -#include <mach/rmobile.h> +#include <mach/renesas.h> #include <asm/io.h> #include <linux/libfdt.h> @@ -21,7 +21,7 @@ struct tfa_info { }; static const struct tfa_info tfa_info[] = { - { "renesas,r9a07g044l2", "R9A07G044L", RMOBILE_CPU_TYPE_R9A07G044L }, + { "renesas,r9a07g044l2", "R9A07G044L", RENESAS_CPU_TYPE_R9A07G044L }, }; static const struct tfa_info invalid_tfa_info = { NULL, "(invalid)", 0 }; @@ -47,17 +47,17 @@ const u8 *rzg_get_cpu_name(void) return get_tfa_info()->cpu_name; } -u32 rmobile_get_cpu_type(void) +u32 renesas_get_cpu_type(void) { return get_tfa_info()->cpu_type; } -u32 rmobile_get_cpu_rev_integer(void) +u32 renesas_get_cpu_rev_integer(void) { return (readl(SYSC_LSI_DEVID) >> 28) + 1; } -u32 rmobile_get_cpu_rev_fraction(void) +u32 renesas_get_cpu_rev_fraction(void) { return 0; } diff --git a/arch/arm/mach-renesas/cpu_info.c b/arch/arm/mach-renesas/cpu_info.c new file mode 100644 index 0000000..2f9a437 --- /dev/null +++ b/arch/arm/mach-renesas/cpu_info.c @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * (C) Copyright 2012-2021 Renesas Solutions Corp. + */ + +#include <cpu_func.h> +#include <asm/cache.h> +#include <init.h> +#include <asm/io.h> +#include <env.h> +#include <linux/ctype.h> + +#ifdef CONFIG_ARCH_CPU_INIT +int arch_cpu_init(void) +{ + icache_enable(); + return 0; +} +#endif + +/* R-Car Gen3 and Gen4 D-cache is enabled in memmap-gen3.c */ +#ifndef CONFIG_RCAR_64 +#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) +void enable_caches(void) +{ + dcache_enable(); +} +#endif +#endif + +#ifdef CONFIG_DISPLAY_CPUINFO +#if !defined(CONFIG_RZA1) && !defined(CONFIG_RZN1) +__weak const u8 *rzg_get_cpu_name(void) +{ + return 0; +} + +__weak u32 renesas_get_cpu_type(void) +{ + return 0x0; +} + +__weak u32 renesas_get_cpu_rev_integer(void) +{ + return 0; +} + +__weak u32 renesas_get_cpu_rev_fraction(void) +{ + return 0; +} + +/* CPU information table */ +static const struct { + u16 cpu_type; + u8 cpu_name[10]; +} renesas_cpuinfo[] = { + { RENESAS_CPU_TYPE_R8A7790, "R8A7790" }, + { RENESAS_CPU_TYPE_R8A7791, "R8A7791" }, + { RENESAS_CPU_TYPE_R8A7792, "R8A7792" }, + { RENESAS_CPU_TYPE_R8A7793, "R8A7793" }, + { RENESAS_CPU_TYPE_R8A7794, "R8A7794" }, + { RENESAS_CPU_TYPE_R8A7795, "R8A7795" }, + { RENESAS_CPU_TYPE_R8A7796, "R8A7796" }, + { RENESAS_CPU_TYPE_R8A77965, "R8A77965" }, + { RENESAS_CPU_TYPE_R8A77970, "R8A77970" }, + { RENESAS_CPU_TYPE_R8A77980, "R8A77980" }, + { RENESAS_CPU_TYPE_R8A77990, "R8A77990" }, + { RENESAS_CPU_TYPE_R8A77995, "R8A77995" }, + { RENESAS_CPU_TYPE_R8A779A0, "R8A779A0" }, + { RENESAS_CPU_TYPE_R8A779F0, "R8A779F0" }, + { RENESAS_CPU_TYPE_R8A779G0, "R8A779G0" }, + { RENESAS_CPU_TYPE_R8A779H0, "R8A779H0" }, + { 0x0, "CPU" }, +}; + +static int renesas_cpuinfo_idx(void) +{ + u32 cpu_type = renesas_get_cpu_type(); + int i; + + for (i = 0; i < ARRAY_SIZE(renesas_cpuinfo) - 1; i++) + if (renesas_cpuinfo[i].cpu_type == cpu_type) + return i; + + /* Unknown "CPU" entry */ + return ARRAY_SIZE(renesas_cpuinfo) - 1; +} + +static const u8 *get_cpu_name(int idx) +{ + const u8 *cpu_name = rzg_get_cpu_name(); + + return cpu_name ? cpu_name : renesas_cpuinfo[idx].cpu_name; +} + +#ifdef CONFIG_ARCH_MISC_INIT +int arch_misc_init(void) +{ + int i, idx = renesas_cpuinfo_idx(); + const u8 *cpu_name = get_cpu_name(idx); + char cpu[10] = { 0 }; + + for (i = 0; i < sizeof(cpu); i++) + cpu[i] = tolower(cpu_name[i]); + + env_set("platform", cpu); + + return 0; +} +#endif + +int print_cpuinfo(void) +{ + int i = renesas_cpuinfo_idx(); + + if (renesas_cpuinfo[i].cpu_type == RENESAS_CPU_TYPE_R8A7796 && + renesas_get_cpu_rev_integer() == 1 && + renesas_get_cpu_rev_fraction() == 1) { + printf("CPU: Renesas Electronics %s rev 1.1/1.2\n", get_cpu_name(i)); + return 0; + } + + printf("CPU: Renesas Electronics %s rev %d.%d\n", + get_cpu_name(i), renesas_get_cpu_rev_integer(), + renesas_get_cpu_rev_fraction()); + + return 0; +} +#elif defined(CONFIG_RZA1) +int print_cpuinfo(void) +{ + printf("CPU: Renesas Electronics RZ/A1\n"); + return 0; +} +#else /* CONFIG_RZN1 */ +int print_cpuinfo(void) +{ + printf("CPU: Renesas Electronics RZ/N1\n"); + return 0; +} +#endif +#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/mach-rmobile/emac.c b/arch/arm/mach-renesas/emac.c index 9565162..03bca88 100644 --- a/arch/arm/mach-rmobile/emac.c +++ b/arch/arm/mach-renesas/emac.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * RMOBILE EtherMAC initialization. + * Renesas EtherMAC initialization. * * Copyright (C) 2012 Renesas Solutions Corp. * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> diff --git a/arch/arm/mach-rmobile/include/mach/boot0.h b/arch/arm/mach-renesas/include/mach/boot0.h index 1d8c3ee..1d8c3ee 100644 --- a/arch/arm/mach-rmobile/include/mach/boot0.h +++ b/arch/arm/mach-renesas/include/mach/boot0.h diff --git a/arch/arm/mach-renesas/include/mach/gpio.h b/arch/arm/mach-renesas/include/mach/gpio.h new file mode 100644 index 0000000..efdde0a --- /dev/null +++ b/arch/arm/mach-renesas/include/mach/gpio.h @@ -0,0 +1,4 @@ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-rmobile/include/mach/irqs.h b/arch/arm/mach-renesas/include/mach/irqs.h index dcb714f..dcb714f 100644 --- a/arch/arm/mach-rmobile/include/mach/irqs.h +++ b/arch/arm/mach-renesas/include/mach/irqs.h diff --git a/arch/arm/mach-rmobile/include/mach/r8a7790.h b/arch/arm/mach-renesas/include/mach/r8a7790.h index 485ea7e..61101df 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-renesas/include/mach/r8a7790.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/include/asm/arch-rmobile/r8a7790.h + * arch/arm/include/asm/arch-renesas/r8a7790.h * * Copyright (C) 2013,2014 Renesas Electronics Corporation */ @@ -28,6 +28,6 @@ #define R8A7790_CUT_ES2X 2 #define IS_R8A7790_ES2() \ - (rmobile_get_cpu_rev_integer() == R8A7790_CUT_ES2X) + (renesas_get_cpu_rev_integer() == R8A7790_CUT_ES2X) #endif /* __ASM_ARCH_R8A7790_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7791.h b/arch/arm/mach-renesas/include/mach/r8a7791.h index 2006ad58..40524d7 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7791.h +++ b/arch/arm/mach-renesas/include/mach/r8a7791.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/include/asm/arch-rmobile/r8a7791.h + * arch/arm/include/asm/arch-renesas/r8a7791.h * * Copyright (C) 2013,2014 Renesas Electronics Corporation */ @@ -65,6 +65,6 @@ #define R8A7791_CUT_ES2X 2 #define IS_R8A7791_ES2() \ - (rmobile_get_cpu_rev_integer() == R8A7791_CUT_ES2X) + (renesas_get_cpu_rev_integer() == R8A7791_CUT_ES2X) #endif /* __ASM_ARCH_R8A7791_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7792.h b/arch/arm/mach-renesas/include/mach/r8a7792.h index cc1b00d..51c0d63 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7792.h +++ b/arch/arm/mach-renesas/include/mach/r8a7792.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/include/asm/arch-rmobile/r8a7792.h + * arch/arm/include/asm/arch-renesas/r8a7792.h * * Copyright (C) 2016 Renesas Electronics Corporation */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7793.h b/arch/arm/mach-renesas/include/mach/r8a7793.h index 02f4286..f15f823 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7793.h +++ b/arch/arm/mach-renesas/include/mach/r8a7793.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/include/asm/arch-rmobile/r8a7793.h + * arch/arm/include/asm/arch-renesas/r8a7793.h * * Copyright (C) 2014 Renesas Electronics Corporation */ @@ -71,6 +71,6 @@ #define R8A7793_CUT_ES2X 2 #define IS_R8A7793_ES2() \ - (rmobile_get_cpu_rev_integer() == R8A7793_CUT_ES2X) + (renesas_get_cpu_rev_integer() == R8A7793_CUT_ES2X) #endif /* __ASM_ARCH_R8A7793_H */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7794.h b/arch/arm/mach-renesas/include/mach/r8a7794.h index a2a949d..592625e 100644 --- a/arch/arm/mach-rmobile/include/mach/r8a7794.h +++ b/arch/arm/mach-renesas/include/mach/r8a7794.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/include/asm/arch-rmobile/r8a7794.h + * arch/arm/include/asm/arch-renesas/r8a7794.h * * Copyright (C) 2014 Renesas Electronics Corporation */ @@ -28,6 +28,6 @@ #define R8A7794_CUT_ES2 2 #define IS_R8A7794_ES2() \ - (rmobile_get_cpu_rev_integer() == R8A7794_CUT_ES2) + (renesas_get_cpu_rev_integer() == R8A7794_CUT_ES2) #endif /* __ASM_ARCH_R8A7794_H */ diff --git a/arch/arm/mach-rmobile/include/mach/rcar-base.h b/arch/arm/mach-renesas/include/mach/rcar-base.h index e422e91..4c2ee81 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-base.h +++ b/arch/arm/mach-renesas/include/mach/rcar-base.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/include/asm/arch-rmobile/rcar-base.h + * arch/arm/include/asm/arch-renesas/rcar-base.h * * Copyright (C) 2013,2014 Renesas Electronics Corporation */ diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h index ca12742..5e2e9ec 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h +++ b/arch/arm/mach-renesas/include/mach/rcar-gen3-base.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * ./arch/arm/mach-rmobile/include/mach/rcar-gen3-base.h + * ./arch/arm/mach-renesas/include/mach/rcar-gen3-base.h * * Copyright (C) 2015 Renesas Electronics Corporation */ diff --git a/arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h b/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h index ac57698..f34473d 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h +++ b/arch/arm/mach-renesas/include/mach/rcar-gen4-base.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * ./arch/arm/mach-rmobile/include/mach/rcar-gen4-base.h + * ./arch/arm/mach-renesas/include/mach/rcar-gen4-base.h * * Copyright (C) 2021 Renesas Electronics Corp. */ diff --git a/arch/arm/mach-rmobile/include/mach/rcar-mstp.h b/arch/arm/mach-renesas/include/mach/rcar-mstp.h index d241652..7ca362e 100644 --- a/arch/arm/mach-rmobile/include/mach/rcar-mstp.h +++ b/arch/arm/mach-renesas/include/mach/rcar-mstp.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/include/asm/arch-rmobile/rcar-mstp.h + * arch/arm/include/asm/arch-renesas/rcar-mstp.h * * Copyright (C) 2013, 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> * Copyright (C) 2013, 2014 Renesas Electronics Corporation diff --git a/arch/arm/mach-renesas/include/mach/renesas.h b/arch/arm/mach-renesas/include/mach/renesas.h new file mode 100644 index 0000000..c69c764 --- /dev/null +++ b/arch/arm/mach-renesas/include/mach/renesas.h @@ -0,0 +1,56 @@ +#ifndef __ASM_ARCH_RENESAS_H +#define __ASM_ARCH_RENESAS_H + +#if defined(CONFIG_ARCH_RENESAS) +#if defined(CONFIG_R8A7790) +#include <asm/arch/r8a7790.h> +#elif defined(CONFIG_R8A7791) +#include <asm/arch/r8a7791.h> +#elif defined(CONFIG_R8A7792) +#include <asm/arch/r8a7792.h> +#elif defined(CONFIG_R8A7793) +#include <asm/arch/r8a7793.h> +#elif defined(CONFIG_R8A7794) +#include <asm/arch/r8a7794.h> +#elif defined(CONFIG_RCAR_GEN3) +#include <asm/arch/rcar-gen3-base.h> +#elif defined(CONFIG_RCAR_GEN4) +#include <asm/arch/rcar-gen4-base.h> +#elif defined(CONFIG_R7S72100) +#elif defined(CONFIG_RZG2L) +#include <asm/arch/rzg2l.h> +#else +#error "SOC Name not defined" +#endif +#endif /* CONFIG_ARCH_RENESAS */ + +/* PRR CPU IDs */ +#define RENESAS_CPU_TYPE_R8A7740 0x40 +#define RENESAS_CPU_TYPE_R8A7790 0x45 +#define RENESAS_CPU_TYPE_R8A7791 0x47 +#define RENESAS_CPU_TYPE_R8A7792 0x4A +#define RENESAS_CPU_TYPE_R8A7793 0x4B +#define RENESAS_CPU_TYPE_R8A7794 0x4C +#define RENESAS_CPU_TYPE_R8A7795 0x4F +#define RENESAS_CPU_TYPE_R8A7796 0x52 +#define RENESAS_CPU_TYPE_R8A77965 0x55 +#define RENESAS_CPU_TYPE_R8A77970 0x54 +#define RENESAS_CPU_TYPE_R8A77980 0x56 +#define RENESAS_CPU_TYPE_R8A77990 0x57 +#define RENESAS_CPU_TYPE_R8A77995 0x58 +#define RENESAS_CPU_TYPE_R8A779A0 0x59 +#define RENESAS_CPU_TYPE_R8A779F0 0x5A +#define RENESAS_CPU_TYPE_R8A779G0 0x5C +#define RENESAS_CPU_TYPE_R8A779H0 0x5D +#define RENESAS_CPU_TYPE_R9A07G044L 0x9A070440 + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +const u8 *rzg_get_cpu_name(void); +u32 renesas_get_cpu_type(void); +u32 renesas_get_cpu_rev_integer(void); +u32 renesas_get_cpu_rev_fraction(void); +#endif /* __ASSEMBLY__ */ + +#endif /* __ASM_ARCH_RENESAS_H */ diff --git a/arch/arm/mach-rmobile/include/mach/rzg2l.h b/arch/arm/mach-renesas/include/mach/rzg2l.h index 057df5c..057df5c 100644 --- a/arch/arm/mach-rmobile/include/mach/rzg2l.h +++ b/arch/arm/mach-renesas/include/mach/rzg2l.h diff --git a/arch/arm/mach-rmobile/include/mach/sys_proto.h b/arch/arm/mach-renesas/include/mach/sys_proto.h index ec8036a..ec8036a 100644 --- a/arch/arm/mach-rmobile/include/mach/sys_proto.h +++ b/arch/arm/mach-renesas/include/mach/sys_proto.h diff --git a/arch/arm/mach-rmobile/lowlevel_init_ca15.S b/arch/arm/mach-renesas/lowlevel_init_ca15.S index a52b761..059cd73 100644 --- a/arch/arm/mach-rmobile/lowlevel_init_ca15.S +++ b/arch/arm/mach-renesas/lowlevel_init_ca15.S @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S + * arch/arm/mach-renesas/lowlevel_init_ca15.S * This file is lager low level initialize. * * Copyright (C) 2013, 2014 Renesas Electronics Corporation diff --git a/arch/arm/mach-rmobile/lowlevel_init_gen3.S b/arch/arm/mach-renesas/lowlevel_init_gen3.S index 0d77800..0d77800 100644 --- a/arch/arm/mach-rmobile/lowlevel_init_gen3.S +++ b/arch/arm/mach-renesas/lowlevel_init_gen3.S diff --git a/arch/arm/mach-rmobile/memmap-gen3.c b/arch/arm/mach-renesas/memmap-gen3.c index 4dff9e0..4dff9e0 100644 --- a/arch/arm/mach-rmobile/memmap-gen3.c +++ b/arch/arm/mach-renesas/memmap-gen3.c diff --git a/arch/arm/mach-rmobile/memmap-rzg2l.c b/arch/arm/mach-renesas/memmap-rzg2l.c index 9934a77..9934a77 100644 --- a/arch/arm/mach-rmobile/memmap-rzg2l.c +++ b/arch/arm/mach-renesas/memmap-rzg2l.c diff --git a/arch/arm/mach-rmobile/psci-r8a779a0.c b/arch/arm/mach-renesas/psci-r8a779a0.c index b6c49e7..b6c49e7 100644 --- a/arch/arm/mach-rmobile/psci-r8a779a0.c +++ b/arch/arm/mach-renesas/psci-r8a779a0.c diff --git a/arch/arm/mach-rmobile/cpu_info-r8a7740.c b/arch/arm/mach-rmobile/cpu_info-r8a7740.c deleted file mode 100644 index 5a94235..0000000 --- a/arch/arm/mach-rmobile/cpu_info-r8a7740.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * (C) Copyright 2012 Renesas Solutions Corp. - */ - -#include <asm/io.h> - -u32 rmobile_get_cpu_type(void) -{ - u32 id; - u32 type; - struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE; - - id = readl(hpb->cccr); - type = (id >> 8) & 0xFF; - - return type; -} - -u32 rmobile_get_cpu_rev(void) -{ - u32 id; - u32 rev; - struct r8a7740_hpb *hpb = (struct r8a7740_hpb *)HPB_BASE; - - id = readl(hpb->cccr); - rev = (id >> 4) & 0xF; - - return rev; -} diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c deleted file mode 100644 index 3d5d5ba..0000000 --- a/arch/arm/mach-rmobile/cpu_info.c +++ /dev/null @@ -1,151 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * (C) Copyright 2012-2021 Renesas Solutions Corp. - */ - -#include <cpu_func.h> -#include <asm/cache.h> -#include <init.h> -#include <asm/io.h> -#include <env.h> -#include <linux/ctype.h> - -#ifdef CONFIG_ARCH_CPU_INIT -int arch_cpu_init(void) -{ - icache_enable(); - return 0; -} -#endif - -/* R-Car Gen3 and Gen4 D-cache is enabled in memmap-gen3.c */ -#ifndef CONFIG_RCAR_64 -#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) -void enable_caches(void) -{ - dcache_enable(); -} -#endif -#endif - -#ifdef CONFIG_DISPLAY_CPUINFO -#if !defined(CONFIG_RZA1) && !defined(CONFIG_RZN1) -__weak const u8 *rzg_get_cpu_name(void) -{ - return 0; -} - -static u32 __rmobile_get_cpu_type(void) -{ - return 0x0; -} -u32 rmobile_get_cpu_type(void) - __attribute__((weak, alias("__rmobile_get_cpu_type"))); - -static u32 __rmobile_get_cpu_rev_integer(void) -{ - return 0; -} -u32 rmobile_get_cpu_rev_integer(void) - __attribute__((weak, alias("__rmobile_get_cpu_rev_integer"))); - -static u32 __rmobile_get_cpu_rev_fraction(void) -{ - return 0; -} -u32 rmobile_get_cpu_rev_fraction(void) - __attribute__((weak, alias("__rmobile_get_cpu_rev_fraction"))); - -/* CPU information table */ -static const struct { - u16 cpu_type; - u8 cpu_name[10]; -} rmobile_cpuinfo[] = { - { RMOBILE_CPU_TYPE_R8A7740, "R8A7740" }, - { RMOBILE_CPU_TYPE_R8A7790, "R8A7790" }, - { RMOBILE_CPU_TYPE_R8A7791, "R8A7791" }, - { RMOBILE_CPU_TYPE_R8A7792, "R8A7792" }, - { RMOBILE_CPU_TYPE_R8A7793, "R8A7793" }, - { RMOBILE_CPU_TYPE_R8A7794, "R8A7794" }, - { RMOBILE_CPU_TYPE_R8A7795, "R8A7795" }, - { RMOBILE_CPU_TYPE_R8A7796, "R8A7796" }, - { RMOBILE_CPU_TYPE_R8A77965, "R8A77965" }, - { RMOBILE_CPU_TYPE_R8A77970, "R8A77970" }, - { RMOBILE_CPU_TYPE_R8A77980, "R8A77980" }, - { RMOBILE_CPU_TYPE_R8A77990, "R8A77990" }, - { RMOBILE_CPU_TYPE_R8A77995, "R8A77995" }, - { RMOBILE_CPU_TYPE_R8A779A0, "R8A779A0" }, - { RMOBILE_CPU_TYPE_R8A779F0, "R8A779F0" }, - { RMOBILE_CPU_TYPE_R8A779G0, "R8A779G0" }, - { RMOBILE_CPU_TYPE_R8A779H0, "R8A779H0" }, - { 0x0, "CPU" }, -}; - -static int rmobile_cpuinfo_idx(void) -{ - u32 cpu_type = rmobile_get_cpu_type(); - int i; - - for (i = 0; i < ARRAY_SIZE(rmobile_cpuinfo) - 1; i++) - if (rmobile_cpuinfo[i].cpu_type == cpu_type) - return i; - - /* Unknown "CPU" entry */ - return ARRAY_SIZE(rmobile_cpuinfo) - 1; -} - -static const u8 *get_cpu_name(int idx) -{ - const u8 *cpu_name = rzg_get_cpu_name(); - - return cpu_name ? cpu_name : rmobile_cpuinfo[idx].cpu_name; -} - -#ifdef CONFIG_ARCH_MISC_INIT -int arch_misc_init(void) -{ - int i, idx = rmobile_cpuinfo_idx(); - const u8 *cpu_name = get_cpu_name(idx); - char cpu[10] = { 0 }; - - for (i = 0; i < sizeof(cpu); i++) - cpu[i] = tolower(cpu_name[i]); - - env_set("platform", cpu); - - return 0; -} -#endif - -int print_cpuinfo(void) -{ - int i = rmobile_cpuinfo_idx(); - - if (rmobile_cpuinfo[i].cpu_type == RMOBILE_CPU_TYPE_R8A7796 && - rmobile_get_cpu_rev_integer() == 1 && - rmobile_get_cpu_rev_fraction() == 1) { - printf("CPU: Renesas Electronics %s rev 1.1/1.2\n", get_cpu_name(i)); - return 0; - } - - printf("CPU: Renesas Electronics %s rev %d.%d\n", - get_cpu_name(i), rmobile_get_cpu_rev_integer(), - rmobile_get_cpu_rev_fraction()); - - return 0; -} -#elif defined(CONFIG_RZA1) -int print_cpuinfo(void) -{ - printf("CPU: Renesas Electronics RZ/A1\n"); - return 0; -} -#else /* CONFIG_RZN1 */ -int print_cpuinfo(void) -{ - printf("CPU: Renesas Electronics RZ/N1\n"); - return 0; -} -#endif -#endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/mach-rmobile/include/mach/gpio.h b/arch/arm/mach-rmobile/include/mach/gpio.h deleted file mode 100644 index 150aa46..0000000 --- a/arch/arm/mach-rmobile/include/mach/gpio.h +++ /dev/null @@ -1,9 +0,0 @@ -#ifndef __ASM_ARCH_GPIO_H -#define __ASM_ARCH_GPIO_H - -#if defined(CONFIG_R8A7740) -#include "r8a7740-gpio.h" -void r8a7740_pinmux_init(void); -#endif - -#endif /* __ASM_ARCH_GPIO_H */ diff --git a/arch/arm/mach-rmobile/include/mach/mmc.h b/arch/arm/mach-rmobile/include/mach/mmc.h deleted file mode 100644 index 7a0e6f0..0000000 --- a/arch/arm/mach-rmobile/include/mach/mmc.h +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Renesas SuperH MMCIF driver. - * - * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> - * Copyright (C) 2014 Renesas Electronics Corporation - */ -#ifndef _RMOBILE_MMC_H_ -#define _RMOBILE_MMC_H_ - -int mmcif_mmc_init(void); - -#endif /* _RMOBILE_MMC_H_ */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7740-gpio.h b/arch/arm/mach-rmobile/include/mach/r8a7740-gpio.h deleted file mode 100644 index 125b3b4..0000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7740-gpio.h +++ /dev/null @@ -1,572 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - */ - -#ifndef __ASM_R8A7740_H__ -#define __ASM_R8A7740_H__ - -/* - * MD_CKx pin - */ -#define MD_CK2 (1 << 2) -#define MD_CK1 (1 << 1) -#define MD_CK0 (1 << 0) - -/* - * Pin Function Controller: - * GPIO_FN_xx - GPIO used to select pin function - * GPIO_PORTxx - GPIO mapped to real I/O pin on CPU - */ -enum { - /* PORT */ - GPIO_PORT0, GPIO_PORT1, GPIO_PORT2, GPIO_PORT3, GPIO_PORT4, - GPIO_PORT5, GPIO_PORT6, GPIO_PORT7, GPIO_PORT8, GPIO_PORT9, - - GPIO_PORT10, GPIO_PORT11, GPIO_PORT12, GPIO_PORT13, GPIO_PORT14, - GPIO_PORT15, GPIO_PORT16, GPIO_PORT17, GPIO_PORT18, GPIO_PORT19, - - GPIO_PORT20, GPIO_PORT21, GPIO_PORT22, GPIO_PORT23, GPIO_PORT24, - GPIO_PORT25, GPIO_PORT26, GPIO_PORT27, GPIO_PORT28, GPIO_PORT29, - - GPIO_PORT30, GPIO_PORT31, GPIO_PORT32, GPIO_PORT33, GPIO_PORT34, - GPIO_PORT35, GPIO_PORT36, GPIO_PORT37, GPIO_PORT38, GPIO_PORT39, - - GPIO_PORT40, GPIO_PORT41, GPIO_PORT42, GPIO_PORT43, GPIO_PORT44, - GPIO_PORT45, GPIO_PORT46, GPIO_PORT47, GPIO_PORT48, GPIO_PORT49, - - GPIO_PORT50, GPIO_PORT51, GPIO_PORT52, GPIO_PORT53, GPIO_PORT54, - GPIO_PORT55, GPIO_PORT56, GPIO_PORT57, GPIO_PORT58, GPIO_PORT59, - - GPIO_PORT60, GPIO_PORT61, GPIO_PORT62, GPIO_PORT63, GPIO_PORT64, - GPIO_PORT65, GPIO_PORT66, GPIO_PORT67, GPIO_PORT68, GPIO_PORT69, - - GPIO_PORT70, GPIO_PORT71, GPIO_PORT72, GPIO_PORT73, GPIO_PORT74, - GPIO_PORT75, GPIO_PORT76, GPIO_PORT77, GPIO_PORT78, GPIO_PORT79, - - GPIO_PORT80, GPIO_PORT81, GPIO_PORT82, GPIO_PORT83, GPIO_PORT84, - GPIO_PORT85, GPIO_PORT86, GPIO_PORT87, GPIO_PORT88, GPIO_PORT89, - - GPIO_PORT90, GPIO_PORT91, GPIO_PORT92, GPIO_PORT93, GPIO_PORT94, - GPIO_PORT95, GPIO_PORT96, GPIO_PORT97, GPIO_PORT98, GPIO_PORT99, - - GPIO_PORT100, GPIO_PORT101, GPIO_PORT102, GPIO_PORT103, GPIO_PORT104, - GPIO_PORT105, GPIO_PORT106, GPIO_PORT107, GPIO_PORT108, GPIO_PORT109, - - GPIO_PORT110, GPIO_PORT111, GPIO_PORT112, GPIO_PORT113, GPIO_PORT114, - GPIO_PORT115, GPIO_PORT116, GPIO_PORT117, GPIO_PORT118, GPIO_PORT119, - - GPIO_PORT120, GPIO_PORT121, GPIO_PORT122, GPIO_PORT123, GPIO_PORT124, - GPIO_PORT125, GPIO_PORT126, GPIO_PORT127, GPIO_PORT128, GPIO_PORT129, - - GPIO_PORT130, GPIO_PORT131, GPIO_PORT132, GPIO_PORT133, GPIO_PORT134, - GPIO_PORT135, GPIO_PORT136, GPIO_PORT137, GPIO_PORT138, GPIO_PORT139, - - GPIO_PORT140, GPIO_PORT141, GPIO_PORT142, GPIO_PORT143, GPIO_PORT144, - GPIO_PORT145, GPIO_PORT146, GPIO_PORT147, GPIO_PORT148, GPIO_PORT149, - - GPIO_PORT150, GPIO_PORT151, GPIO_PORT152, GPIO_PORT153, GPIO_PORT154, - GPIO_PORT155, GPIO_PORT156, GPIO_PORT157, GPIO_PORT158, GPIO_PORT159, - - GPIO_PORT160, GPIO_PORT161, GPIO_PORT162, GPIO_PORT163, GPIO_PORT164, - GPIO_PORT165, GPIO_PORT166, GPIO_PORT167, GPIO_PORT168, GPIO_PORT169, - - GPIO_PORT170, GPIO_PORT171, GPIO_PORT172, GPIO_PORT173, GPIO_PORT174, - GPIO_PORT175, GPIO_PORT176, GPIO_PORT177, GPIO_PORT178, GPIO_PORT179, - - GPIO_PORT180, GPIO_PORT181, GPIO_PORT182, GPIO_PORT183, GPIO_PORT184, - GPIO_PORT185, GPIO_PORT186, GPIO_PORT187, GPIO_PORT188, GPIO_PORT189, - - GPIO_PORT190, GPIO_PORT191, GPIO_PORT192, GPIO_PORT193, GPIO_PORT194, - GPIO_PORT195, GPIO_PORT196, GPIO_PORT197, GPIO_PORT198, GPIO_PORT199, - - GPIO_PORT200, GPIO_PORT201, GPIO_PORT202, GPIO_PORT203, GPIO_PORT204, - GPIO_PORT205, GPIO_PORT206, GPIO_PORT207, GPIO_PORT208, GPIO_PORT209, - - GPIO_PORT210, GPIO_PORT211, - - /* IRQ */ - GPIO_FN_IRQ0_PORT2, GPIO_FN_IRQ0_PORT13, - GPIO_FN_IRQ1, - GPIO_FN_IRQ2_PORT11, GPIO_FN_IRQ2_PORT12, - GPIO_FN_IRQ3_PORT10, GPIO_FN_IRQ3_PORT14, - GPIO_FN_IRQ4_PORT15, GPIO_FN_IRQ4_PORT172, - GPIO_FN_IRQ5_PORT0, GPIO_FN_IRQ5_PORT1, - GPIO_FN_IRQ6_PORT121, GPIO_FN_IRQ6_PORT173, - GPIO_FN_IRQ7_PORT120, GPIO_FN_IRQ7_PORT209, - GPIO_FN_IRQ8, - GPIO_FN_IRQ9_PORT118, GPIO_FN_IRQ9_PORT210, - GPIO_FN_IRQ10, - GPIO_FN_IRQ11, - GPIO_FN_IRQ12_PORT42, GPIO_FN_IRQ12_PORT97, - GPIO_FN_IRQ13_PORT64, GPIO_FN_IRQ13_PORT98, - GPIO_FN_IRQ14_PORT63, GPIO_FN_IRQ14_PORT99, - GPIO_FN_IRQ15_PORT62, GPIO_FN_IRQ15_PORT100, - GPIO_FN_IRQ16_PORT68, GPIO_FN_IRQ16_PORT211, - GPIO_FN_IRQ17, - GPIO_FN_IRQ18, - GPIO_FN_IRQ19, - GPIO_FN_IRQ20, - GPIO_FN_IRQ21, - GPIO_FN_IRQ22, - GPIO_FN_IRQ23, - GPIO_FN_IRQ24, - GPIO_FN_IRQ25, - GPIO_FN_IRQ26_PORT58, GPIO_FN_IRQ26_PORT81, - GPIO_FN_IRQ27_PORT57, GPIO_FN_IRQ27_PORT168, - GPIO_FN_IRQ28_PORT56, GPIO_FN_IRQ28_PORT169, - GPIO_FN_IRQ29_PORT50, GPIO_FN_IRQ29_PORT170, - GPIO_FN_IRQ30_PORT49, GPIO_FN_IRQ30_PORT171, - GPIO_FN_IRQ31_PORT41, GPIO_FN_IRQ31_PORT167, - - /* Function */ - - /* DBGT */ - GPIO_FN_DBGMDT2, GPIO_FN_DBGMDT1, GPIO_FN_DBGMDT0, - GPIO_FN_DBGMD10, GPIO_FN_DBGMD11, GPIO_FN_DBGMD20, - GPIO_FN_DBGMD21, - - /* FSI */ - GPIO_FN_FSIAISLD_PORT0, /* FSIAISLD Port 0/5 */ - GPIO_FN_FSIAISLD_PORT5, - GPIO_FN_FSIASPDIF_PORT9, /* FSIASPDIF Port 9/18 */ - GPIO_FN_FSIASPDIF_PORT18, - GPIO_FN_FSIAOSLD1, GPIO_FN_FSIAOSLD2, - GPIO_FN_FSIAOLR, GPIO_FN_FSIAOBT, - GPIO_FN_FSIAOSLD, GPIO_FN_FSIAOMC, - GPIO_FN_FSIACK, GPIO_FN_FSIAILR, - GPIO_FN_FSIAIBT, - - /* FMSI */ - GPIO_FN_FMSISLD_PORT1, /* FMSISLD Port 1/6 */ - GPIO_FN_FMSISLD_PORT6, - GPIO_FN_FMSIILR, GPIO_FN_FMSIIBT, - GPIO_FN_FMSIOLR, GPIO_FN_FMSIOBT, - GPIO_FN_FMSICK, GPIO_FN_FMSOILR, - GPIO_FN_FMSOIBT, GPIO_FN_FMSOOLR, - GPIO_FN_FMSOOBT, GPIO_FN_FMSOSLD, - GPIO_FN_FMSOCK, - - /* SCIFA0 */ - GPIO_FN_SCIFA0_SCK, GPIO_FN_SCIFA0_CTS, - GPIO_FN_SCIFA0_RTS, GPIO_FN_SCIFA0_RXD, - GPIO_FN_SCIFA0_TXD, - - /* SCIFA1 */ - GPIO_FN_SCIFA1_CTS, GPIO_FN_SCIFA1_SCK, - GPIO_FN_SCIFA1_RXD, GPIO_FN_SCIFA1_TXD, - GPIO_FN_SCIFA1_RTS, - - /* SCIFA2 */ - GPIO_FN_SCIFA2_SCK_PORT22, /* SCIFA2_SCK Port 22/199 */ - GPIO_FN_SCIFA2_SCK_PORT199, - GPIO_FN_SCIFA2_RXD, GPIO_FN_SCIFA2_TXD, - GPIO_FN_SCIFA2_CTS, GPIO_FN_SCIFA2_RTS, - - /* SCIFA3 */ - GPIO_FN_SCIFA3_RTS_PORT105, /* MSEL5CR_8_0 */ - GPIO_FN_SCIFA3_SCK_PORT116, - GPIO_FN_SCIFA3_CTS_PORT117, - GPIO_FN_SCIFA3_RXD_PORT174, - GPIO_FN_SCIFA3_TXD_PORT175, - - GPIO_FN_SCIFA3_RTS_PORT161, /* MSEL5CR_8_1 */ - GPIO_FN_SCIFA3_SCK_PORT158, - GPIO_FN_SCIFA3_CTS_PORT162, - GPIO_FN_SCIFA3_RXD_PORT159, - GPIO_FN_SCIFA3_TXD_PORT160, - - /* SCIFA4 */ - GPIO_FN_SCIFA4_RXD_PORT12, /* MSEL5CR[12:11] = 00 */ - GPIO_FN_SCIFA4_TXD_PORT13, - - GPIO_FN_SCIFA4_RXD_PORT204, /* MSEL5CR[12:11] = 01 */ - GPIO_FN_SCIFA4_TXD_PORT203, - - GPIO_FN_SCIFA4_RXD_PORT94, /* MSEL5CR[12:11] = 10 */ - GPIO_FN_SCIFA4_TXD_PORT93, - - GPIO_FN_SCIFA4_SCK_PORT21, /* SCIFA4_SCK Port 21/205 */ - GPIO_FN_SCIFA4_SCK_PORT205, - - /* SCIFA5 */ - GPIO_FN_SCIFA5_TXD_PORT20, /* MSEL5CR[15:14] = 00 */ - GPIO_FN_SCIFA5_RXD_PORT10, - - GPIO_FN_SCIFA5_RXD_PORT207, /* MSEL5CR[15:14] = 01 */ - GPIO_FN_SCIFA5_TXD_PORT208, - - GPIO_FN_SCIFA5_TXD_PORT91, /* MSEL5CR[15:14] = 10 */ - GPIO_FN_SCIFA5_RXD_PORT92, - - GPIO_FN_SCIFA5_SCK_PORT23, /* SCIFA5_SCK Port 23/206 */ - GPIO_FN_SCIFA5_SCK_PORT206, - - /* SCIFA6 */ - GPIO_FN_SCIFA6_SCK, GPIO_FN_SCIFA6_RXD, GPIO_FN_SCIFA6_TXD, - - /* SCIFA7 */ - GPIO_FN_SCIFA7_TXD, GPIO_FN_SCIFA7_RXD, - - /* SCIFAB */ - GPIO_FN_SCIFB_SCK_PORT190, /* MSEL5CR_17_0 */ - GPIO_FN_SCIFB_RXD_PORT191, - GPIO_FN_SCIFB_TXD_PORT192, - GPIO_FN_SCIFB_RTS_PORT186, - GPIO_FN_SCIFB_CTS_PORT187, - - GPIO_FN_SCIFB_SCK_PORT2, /* MSEL5CR_17_1 */ - GPIO_FN_SCIFB_RXD_PORT3, - GPIO_FN_SCIFB_TXD_PORT4, - GPIO_FN_SCIFB_RTS_PORT172, - GPIO_FN_SCIFB_CTS_PORT173, - - /* LCD0 */ - GPIO_FN_LCDC0_SELECT, - GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2, - GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5, - GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8, - GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11, - GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14, - GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17, - GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC, - - GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */ - GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */ - - GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */ - GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */ - - GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162, - GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158, - GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159, - GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */ - - GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4, - GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2, - GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1, - GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */ - - /* LCD1 */ - GPIO_FN_LCDC1_SELECT, - GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2, - GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5, - GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8, - GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11, - GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14, - GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17, - GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20, - GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23, - GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC, - GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC, - - GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */ - GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */ - - GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */ - GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */ - - /* RSPI */ - GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, - GPIO_FN_RSPI_SSL2_A, GPIO_FN_RSPI_SSL3_A, - GPIO_FN_RSPI_MOSI_A, GPIO_FN_RSPI_MISO_A, - GPIO_FN_RSPI_CK_A, - - /* VIO CKO */ - GPIO_FN_VIO_CKO1, - GPIO_FN_VIO_CKO2, - GPIO_FN_VIO_CKO_1, - GPIO_FN_VIO_CKO, - - /* VIO0 */ - GPIO_FN_VIO0_D0, GPIO_FN_VIO0_D1, GPIO_FN_VIO0_D2, - GPIO_FN_VIO0_D3, GPIO_FN_VIO0_D4, GPIO_FN_VIO0_D5, - GPIO_FN_VIO0_D6, GPIO_FN_VIO0_D7, GPIO_FN_VIO0_D8, - GPIO_FN_VIO0_D9, GPIO_FN_VIO0_D10, GPIO_FN_VIO0_D11, - GPIO_FN_VIO0_D12, GPIO_FN_VIO0_VD, GPIO_FN_VIO0_HD, - GPIO_FN_VIO0_CLK, GPIO_FN_VIO0_FIELD, - - GPIO_FN_VIO0_D13_PORT26, /* MSEL5CR_27_0 */ - GPIO_FN_VIO0_D14_PORT25, - GPIO_FN_VIO0_D15_PORT24, - - GPIO_FN_VIO0_D13_PORT22, /* MSEL5CR_27_1 */ - GPIO_FN_VIO0_D14_PORT95, - GPIO_FN_VIO0_D15_PORT96, - - /* VIO1 */ - GPIO_FN_VIO1_D0, GPIO_FN_VIO1_D1, GPIO_FN_VIO1_D2, - GPIO_FN_VIO1_D3, GPIO_FN_VIO1_D4, GPIO_FN_VIO1_D5, - GPIO_FN_VIO1_D6, GPIO_FN_VIO1_D7, GPIO_FN_VIO1_VD, - GPIO_FN_VIO1_HD, GPIO_FN_VIO1_CLK, GPIO_FN_VIO1_FIELD, - - /* TPU0 */ - GPIO_FN_TPU0TO0, GPIO_FN_TPU0TO1, - GPIO_FN_TPU0TO3, - GPIO_FN_TPU0TO2_PORT66, /* TPU0TO2 Port 66/202 */ - GPIO_FN_TPU0TO2_PORT202, - - /* SSP1 0 */ - GPIO_FN_STP0_IPD0, GPIO_FN_STP0_IPD1, GPIO_FN_STP0_IPD2, - GPIO_FN_STP0_IPD3, GPIO_FN_STP0_IPD4, GPIO_FN_STP0_IPD5, - GPIO_FN_STP0_IPD6, GPIO_FN_STP0_IPD7, GPIO_FN_STP0_IPEN, - GPIO_FN_STP0_IPCLK, GPIO_FN_STP0_IPSYNC, - - /* SSP1 1 */ - GPIO_FN_STP1_IPD1, GPIO_FN_STP1_IPD2, GPIO_FN_STP1_IPD3, - GPIO_FN_STP1_IPD4, GPIO_FN_STP1_IPD5, GPIO_FN_STP1_IPD6, - GPIO_FN_STP1_IPD7, GPIO_FN_STP1_IPCLK, GPIO_FN_STP1_IPSYNC, - - GPIO_FN_STP1_IPD0_PORT186, /* MSEL5CR_23_0 */ - GPIO_FN_STP1_IPEN_PORT187, - - GPIO_FN_STP1_IPD0_PORT194, /* MSEL5CR_23_1 */ - GPIO_FN_STP1_IPEN_PORT193, - - /* SIM */ - GPIO_FN_SIM_RST, GPIO_FN_SIM_CLK, - GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ - GPIO_FN_SIM_D_PORT199, - - /* SDHI0 */ - GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2, - GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP, - GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK, - - /* SDHI1 */ - GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2, - GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP, - GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK, - - /* SDHI2 */ - GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2, - GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD, - - GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */ - GPIO_FN_SDHI2_WP_PORT25, - - GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */ - GPIO_FN_SDHI2_CD_PORT202, - - /* MSIOF2 */ - GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, - GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, - GPIO_FN_MSIOF2_MCK1, GPIO_FN_MSIOF2_MCK0, GPIO_FN_MSIOF2_RSYNC, - GPIO_FN_MSIOF2_RSCK, - - /* KEYSC */ - GPIO_FN_KEYIN4, GPIO_FN_KEYIN5, - GPIO_FN_KEYIN6, GPIO_FN_KEYIN7, - GPIO_FN_KEYOUT0, GPIO_FN_KEYOUT1, GPIO_FN_KEYOUT2, - GPIO_FN_KEYOUT3, GPIO_FN_KEYOUT4, GPIO_FN_KEYOUT5, - GPIO_FN_KEYOUT6, GPIO_FN_KEYOUT7, - - GPIO_FN_KEYIN0_PORT43, /* MSEL4CR_18_0 */ - GPIO_FN_KEYIN1_PORT44, - GPIO_FN_KEYIN2_PORT45, - GPIO_FN_KEYIN3_PORT46, - - GPIO_FN_KEYIN0_PORT58, /* MSEL4CR_18_1 */ - GPIO_FN_KEYIN1_PORT57, - GPIO_FN_KEYIN2_PORT56, - GPIO_FN_KEYIN3_PORT55, - - /* VOU */ - GPIO_FN_DV_D0, GPIO_FN_DV_D1, GPIO_FN_DV_D2, GPIO_FN_DV_D3, - GPIO_FN_DV_D4, GPIO_FN_DV_D5, GPIO_FN_DV_D6, GPIO_FN_DV_D7, - GPIO_FN_DV_D8, GPIO_FN_DV_D9, GPIO_FN_DV_D10, GPIO_FN_DV_D11, - GPIO_FN_DV_D12, GPIO_FN_DV_D13, GPIO_FN_DV_D14, GPIO_FN_DV_D15, - GPIO_FN_DV_CLK, - GPIO_FN_DV_VSYNC, - GPIO_FN_DV_HSYNC, - - /* MEMC */ - GPIO_FN_MEMC_AD0, GPIO_FN_MEMC_AD1, GPIO_FN_MEMC_AD2, - GPIO_FN_MEMC_AD3, GPIO_FN_MEMC_AD4, GPIO_FN_MEMC_AD5, - GPIO_FN_MEMC_AD6, GPIO_FN_MEMC_AD7, GPIO_FN_MEMC_AD8, - GPIO_FN_MEMC_AD9, GPIO_FN_MEMC_AD10, GPIO_FN_MEMC_AD11, - GPIO_FN_MEMC_AD12, GPIO_FN_MEMC_AD13, GPIO_FN_MEMC_AD14, - GPIO_FN_MEMC_AD15, GPIO_FN_MEMC_CS0, GPIO_FN_MEMC_INT, - GPIO_FN_MEMC_NWE, GPIO_FN_MEMC_NOE, - - GPIO_FN_MEMC_CS1, /* MSEL4CR_6_0 */ - GPIO_FN_MEMC_ADV, - GPIO_FN_MEMC_WAIT, - GPIO_FN_MEMC_BUSCLK, - - GPIO_FN_MEMC_A1, /* MSEL4CR_6_1 */ - GPIO_FN_MEMC_DREQ0, - GPIO_FN_MEMC_DREQ1, - GPIO_FN_MEMC_A0, - - /* MMC */ - GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69, - GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71, - GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73, - GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75, - GPIO_FN_MMC0_CLK_PORT66, - GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */ - - GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148, - GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146, - GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144, - GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142, - GPIO_FN_MMC1_CLK_PORT103, - GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */ - - /* MSIOF0 */ - GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, - GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, - GPIO_FN_MSIOF0_MCK0, GPIO_FN_MSIOF0_MCK1, - GPIO_FN_MSIOF0_RSYNC, GPIO_FN_MSIOF0_RSCK, - GPIO_FN_MSIOF0_TSCK, GPIO_FN_MSIOF0_TSYNC, - - /* MSIOF1 */ - GPIO_FN_MSIOF1_RSCK, GPIO_FN_MSIOF1_RSYNC, - GPIO_FN_MSIOF1_MCK0, GPIO_FN_MSIOF1_MCK1, - - GPIO_FN_MSIOF1_SS2_PORT116, GPIO_FN_MSIOF1_SS1_PORT117, - GPIO_FN_MSIOF1_RXD_PORT118, GPIO_FN_MSIOF1_TXD_PORT119, - GPIO_FN_MSIOF1_TSYNC_PORT120, - GPIO_FN_MSIOF1_TSCK_PORT121, /* MSEL4CR_10_0 */ - - GPIO_FN_MSIOF1_SS1_PORT67, GPIO_FN_MSIOF1_TSCK_PORT72, - GPIO_FN_MSIOF1_TSYNC_PORT73, GPIO_FN_MSIOF1_TXD_PORT74, - GPIO_FN_MSIOF1_RXD_PORT75, - GPIO_FN_MSIOF1_SS2_PORT202, /* MSEL4CR_10_1 */ - - /* GPIO */ - GPIO_FN_GPO0, GPIO_FN_GPI0, - GPIO_FN_GPO1, GPIO_FN_GPI1, - - /* USB0 */ - GPIO_FN_USB0_OCI, GPIO_FN_USB0_PPON, GPIO_FN_VBUS, - - /* USB1 */ - GPIO_FN_USB1_OCI, GPIO_FN_USB1_PPON, - - /* BBIF1 */ - GPIO_FN_BBIF1_RXD, GPIO_FN_BBIF1_TXD, GPIO_FN_BBIF1_TSYNC, - GPIO_FN_BBIF1_TSCK, GPIO_FN_BBIF1_RSCK, GPIO_FN_BBIF1_RSYNC, - GPIO_FN_BBIF1_FLOW, GPIO_FN_BBIF1_RX_FLOW_N, - - /* BBIF2 */ - GPIO_FN_BBIF2_TXD2_PORT5, /* MSEL5CR_0_0 */ - GPIO_FN_BBIF2_RXD2_PORT60, - GPIO_FN_BBIF2_TSYNC2_PORT6, - GPIO_FN_BBIF2_TSCK2_PORT59, - - GPIO_FN_BBIF2_RXD2_PORT90, /* MSEL5CR_0_1 */ - GPIO_FN_BBIF2_TXD2_PORT183, - GPIO_FN_BBIF2_TSCK2_PORT89, - GPIO_FN_BBIF2_TSYNC2_PORT184, - - /* BSC / FLCTL / PCMCIA */ - GPIO_FN_CS0, GPIO_FN_CS2, GPIO_FN_CS4, - GPIO_FN_CS5B, GPIO_FN_CS6A, - GPIO_FN_CS5A_PORT105, /* CS5A PORT 19/105 */ - GPIO_FN_CS5A_PORT19, - GPIO_FN_IOIS16, /* ? */ - - GPIO_FN_A0, GPIO_FN_A1, GPIO_FN_A2, GPIO_FN_A3, - GPIO_FN_A4_FOE, /* share with FLCTL */ - GPIO_FN_A5_FCDE, /* share with FLCTL */ - GPIO_FN_A6, GPIO_FN_A7, GPIO_FN_A8, GPIO_FN_A9, - GPIO_FN_A10, GPIO_FN_A11, GPIO_FN_A12, GPIO_FN_A13, - GPIO_FN_A14, GPIO_FN_A15, GPIO_FN_A16, GPIO_FN_A17, - GPIO_FN_A18, GPIO_FN_A19, GPIO_FN_A20, GPIO_FN_A21, - GPIO_FN_A22, GPIO_FN_A23, GPIO_FN_A24, GPIO_FN_A25, - GPIO_FN_A26, - - GPIO_FN_D0_NAF0, GPIO_FN_D1_NAF1, /* share with FLCTL */ - GPIO_FN_D2_NAF2, GPIO_FN_D3_NAF3, /* share with FLCTL */ - GPIO_FN_D4_NAF4, GPIO_FN_D5_NAF5, /* share with FLCTL */ - GPIO_FN_D6_NAF6, GPIO_FN_D7_NAF7, /* share with FLCTL */ - GPIO_FN_D8_NAF8, GPIO_FN_D9_NAF9, /* share with FLCTL */ - GPIO_FN_D10_NAF10, GPIO_FN_D11_NAF11, /* share with FLCTL */ - GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, /* share with FLCTL */ - GPIO_FN_D14_NAF14, GPIO_FN_D15_NAF15, /* share with FLCTL */ - - GPIO_FN_D16, GPIO_FN_D17, GPIO_FN_D18, GPIO_FN_D19, - GPIO_FN_D20, GPIO_FN_D21, GPIO_FN_D22, GPIO_FN_D23, - GPIO_FN_D24, GPIO_FN_D25, GPIO_FN_D26, GPIO_FN_D27, - GPIO_FN_D28, GPIO_FN_D29, GPIO_FN_D30, GPIO_FN_D31, - - GPIO_FN_WE0_FWE, /* share with FLCTL */ - GPIO_FN_WE1, - GPIO_FN_WE2_ICIORD, /* share with PCMCIA */ - GPIO_FN_WE3_ICIOWR, /* share with PCMCIA */ - GPIO_FN_CKO, GPIO_FN_BS, GPIO_FN_RDWR, - GPIO_FN_RD_FSC, /* share with FLCTL */ - GPIO_FN_WAIT_PORT177, /* WAIT Port 90/177 */ - GPIO_FN_WAIT_PORT90, - - GPIO_FN_FCE0, GPIO_FN_FCE1, GPIO_FN_FRB, /* FLCTL */ - - /* IRDA */ - GPIO_FN_IRDA_FIRSEL, GPIO_FN_IRDA_IN, GPIO_FN_IRDA_OUT, - - /* ATAPI */ - GPIO_FN_IDE_D0, GPIO_FN_IDE_D1, GPIO_FN_IDE_D2, - GPIO_FN_IDE_D3, GPIO_FN_IDE_D4, GPIO_FN_IDE_D5, - GPIO_FN_IDE_D6, GPIO_FN_IDE_D7, GPIO_FN_IDE_D8, - GPIO_FN_IDE_D9, GPIO_FN_IDE_D10, GPIO_FN_IDE_D11, - GPIO_FN_IDE_D12, GPIO_FN_IDE_D13, GPIO_FN_IDE_D14, - GPIO_FN_IDE_D15, GPIO_FN_IDE_A0, GPIO_FN_IDE_A1, - GPIO_FN_IDE_A2, GPIO_FN_IDE_CS0, GPIO_FN_IDE_CS1, - GPIO_FN_IDE_IOWR, GPIO_FN_IDE_IORD, GPIO_FN_IDE_IORDY, - GPIO_FN_IDE_INT, GPIO_FN_IDE_RST, GPIO_FN_IDE_DIRECTION, - GPIO_FN_IDE_EXBUF_ENB, GPIO_FN_IDE_IODACK, GPIO_FN_IDE_IODREQ, - - /* RMII */ - GPIO_FN_RMII_CRS_DV, GPIO_FN_RMII_RX_ER, GPIO_FN_RMII_RXD0, - GPIO_FN_RMII_RXD1, GPIO_FN_RMII_TX_EN, GPIO_FN_RMII_TXD0, - GPIO_FN_RMII_MDC, GPIO_FN_RMII_TXD1, GPIO_FN_RMII_MDIO, - GPIO_FN_RMII_REF50CK, /* for RMII */ - GPIO_FN_RMII_REF125CK, /* for GMII */ - - /* GEther */ - GPIO_FN_ET_TX_CLK, GPIO_FN_ET_TX_EN, GPIO_FN_ET_ETXD0, - GPIO_FN_ET_ETXD1, GPIO_FN_ET_ETXD2, GPIO_FN_ET_ETXD3, - GPIO_FN_ET_ETXD4, GPIO_FN_ET_ETXD5, /* for GEther */ - GPIO_FN_ET_ETXD6, GPIO_FN_ET_ETXD7, /* for GEther */ - GPIO_FN_ET_COL, GPIO_FN_ET_TX_ER, - GPIO_FN_ET_RX_CLK, GPIO_FN_ET_RX_DV, - GPIO_FN_ET_ERXD0, GPIO_FN_ET_ERXD1, - GPIO_FN_ET_ERXD2, GPIO_FN_ET_ERXD3, - GPIO_FN_ET_ERXD4, GPIO_FN_ET_ERXD5, /* for GEther */ - GPIO_FN_ET_ERXD6, GPIO_FN_ET_ERXD7, /* for GEther */ - GPIO_FN_ET_RX_ER, GPIO_FN_ET_CRS, - GPIO_FN_ET_MDC, GPIO_FN_ET_MDIO, - GPIO_FN_ET_LINK, GPIO_FN_ET_PHY_INT, - GPIO_FN_ET_WOL, GPIO_FN_ET_GTX_CLK, - - /* DMA0 */ - GPIO_FN_DREQ0, GPIO_FN_DACK0, - - /* DMA1 */ - GPIO_FN_DREQ1, GPIO_FN_DACK1, - - /* SYSC */ - GPIO_FN_RESETOUTS, - GPIO_FN_RESETP_PULLUP, - GPIO_FN_RESETP_PLAIN, - - /* SDENC */ - GPIO_FN_SDENC_CPG, - GPIO_FN_SDENC_DV_CLKI, - - /* IRREM */ - GPIO_FN_IROUT, - - /* DEBUG */ - GPIO_FN_EDEBGREQ_PULLDOWN, - GPIO_FN_EDEBGREQ_PULLUP, - - GPIO_FN_TRACEAUD_FROM_VIO, - GPIO_FN_TRACEAUD_FROM_LCDC0, - GPIO_FN_TRACEAUD_FROM_MEMC, -}; - -#endif /* __ASM_R8A7740_H__ */ diff --git a/arch/arm/mach-rmobile/include/mach/r8a7740.h b/arch/arm/mach-rmobile/include/mach/r8a7740.h deleted file mode 100644 index f1fcfe1..0000000 --- a/arch/arm/mach-rmobile/include/mach/r8a7740.h +++ /dev/null @@ -1,274 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#ifndef __ASM_ARCH_R8A7740_H -#define __ASM_ARCH_R8A7740_H - -/* - * R8A7740 I/O Addresses - */ - -#define MERAM_BASE 0xE5580000 -#define DDRP_BASE 0xC12A0000 -#define HPB_BASE 0xE6000000 -#define RWDT0_BASE 0xE6020000 -#define RWDT1_BASE 0xE6030000 -#define GPIO_BASE 0xE6050000 -#define CMT1_BASE 0xE6138000 -#define CPG_BASE 0xE6150000 -#define SYSC_BASE 0xE6180000 -#define SDHI0_BASE 0xE6850000 -#define SDHI1_BASE 0xE6860000 -#define MMCIF_BASE 0xE6BD0000 -#define SCIF5_BASE 0xE6CB0000 -#define SCIF6_BASE 0xE6CC0000 -#define DBSC_BASE 0xFE400000 -#define BSC_BASE 0xFEC10000 -#define I2C0_BASE 0xFFF20000 -#define I2C1_BASE 0xE6C20000 -#define TMU_BASE 0xFFF80000 - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -/* RWDT */ -struct r8a7740_rwdt { - u16 rwtcnt0; /* 0x00 */ - u16 dummy0; /* 0x02 */ - u16 rwtcsra0; /* 0x04 */ - u16 dummy1; /* 0x06 */ - u16 rwtcsrb0; /* 0x08 */ - u16 dummy2; /* 0x0A */ -}; - -/* HPB Semaphore Control Registers */ -struct r8a7740_hpb { - u32 hpbctrl0; - u32 hpbctrl1; - u32 hpbctrl2; - u32 cccr; - u32 dummy0; /* 0x20 */ - u32 hpbctrl4; - u32 hpbctrl5; -}; - -/* CPG */ -struct r8a7740_cpg { - u32 frqcra; - u32 frqcrb; - u32 vclkcr1; - u32 vclkcr2; - u32 fmsickcr; - u32 fmsockcr; - u32 fsiackcr; - u32 dummy0; /* 0x1c */ - u32 rtstbcr; - u32 systbcr; - u32 pllc01cr; - u32 pllc2cr; - u32 mstpsr0; - u32 dummy1; /* 0x34 */ - u32 mstpsr1; - u32 mstpsr5; - u32 mstpsr2; - u32 dummy2; /* 0x44 */ - u32 mstpsr3; - u32 mstpsr4; - u32 dummy3; /* 0x50 */ - u32 astat; - u32 dummy4[4]; /* 0x58 .. 0x64 */ - u32 ztrckcr; - u32 dummy5[5]; /* 0x6c .. 0x7c */ - u32 subckcr; - u32 spuckcr; - u32 vouckcr; - u32 usbckcr; - u32 dummy6[3]; /* 0x90 .. 0x98 */ - u32 stprckcr; - u32 srcr0; - u32 dummy7; /* 0xa4 */ - u32 srcr1; - u32 dummy8; /* 0xac */ - u32 srcr2; - u32 dummy9; /* 0xb4 */ - u32 srcr3; - u32 srcr4; - u32 dummy10; /* 0xc0 */ - u32 srcr5; - u32 pllc01stpcr; - u32 dummy11[5]; /* 0xcc .. 0xdc */ - u32 frqcrc; - u32 frqcrd; - u32 dummy12[10]; /* 0xe8 .. 0x10c */ - u32 rmstpcr0; - u32 rmstpcr1; - u32 rmstpcr2; - u32 rmstpcr3; - u32 rmstpcr4; - u32 rmstpcr5; - u32 dummy13[2]; /* 0x128 .. 0x12c */ - u32 smstpcr0; - u32 smstpcr1; - u32 smstpcr2; - u32 smstpcr3; - u32 smstpcr4; - u32 smstpcr5; -}; - -/* BSC */ -struct r8a7740_bsc { - u32 cmncr; - u32 cs0bcr; - u32 cs2bcr; - u32 dummy0; /* 0x0c */ - u32 cs4bcr; - u32 cs5abcr; - u32 cs5bbcr; - u32 cs6abcr; - u32 dummy1; /* 0x20 */ - u32 cs0wcr; - u32 cs2wcr; - u32 dummy2; /* 0x2c */ - u32 cs4wcr; - u32 cs5awcr; - u32 cs5bwcr; - u32 cs6awcr; - u32 dummy3[5]; /* 0x40 .. 0x50 */ - u32 rbwtcnt; - u32 busycr; - u32 dummy4[5]; /* 0x5c .. 0x6c */ - u32 bromtimcr; - u32 dummy5[7]; /* 0x74 .. 0x8c */ - u32 bptcr00; - u32 bptcr01; - u32 bptcr02; - u32 bptcr03; - u32 bptcr04; - u32 bptcr05; - u32 bptcr06; - u32 bptcr07; - u32 bptcr08; - u32 bptcr09; - u32 bptcr10; - u32 bptcr11; - u32 bptcr12; - u32 bptcr13; - u32 bptcr14; - u32 bptcr15; - u32 bptcr16; - u32 bptcr17; - u32 bptcr18; - u32 bptcr19; - u32 bptcr20; - u32 bptcr21; - u32 bptcr22; - u32 bptcr23; - u32 bptcr24; - u32 bptcr25; - u32 bptcr26; - u32 bptcr27; - u32 bptcr28; - u32 bptcr29; - u32 bptcr30; - u32 bptcr31; - u32 bswcr; - u32 dummy6[68]; /* 0x114 .. 0x220 */ - u32 cs0wcr2; - u32 cs2wcr2; - u32 dummy7; /* 0x22c */ - u32 cs4wcr2; -}; - -#define CS0WCR2 0xFEC10224 -#define CS2WCR2 0xFEC10228 -#define CS4WCR2 0xFEC10230 - -/* DDRP */ -struct r8a7740_ddrp { - u32 funcctrl; - u32 dllctrl; - u32 zqcalctrl; - u32 zqodtctrl; - u32 rdctrl; - u32 rdtmg; - u32 fifoinit; - u32 outctrl; - u32 dummy0[50]; /* 0x20 .. 0xe4 */ - u32 dqcalofs1; - u32 dqcalofs2; - u32 dummy1[2]; /* 0xf0 .. 0xf4 */ - u32 dqcalexp; -}; - -#define DDRPNCNT 0xE605803C -#define DDRVREFCNT 0xE61500EC - -/* DBSC */ -struct r8a7740_dbsc { - u32 dummy0; - u32 dbsvcr; - u32 dbstate0; - u32 dbstate1; - u32 dbacen; - u32 dbrfen; - u32 dbcmd; - u32 dbwait; - u32 dbkind; - u32 dbconf0; - u32 dummy1[2]; /* 0x28 .. 0x2c */ - u32 dbphytype; - u32 dummy2[3]; /* 0x34 .. 0x3c */ - u32 dbtr0; - u32 dbtr1; - u32 dbtr2; - u32 dummy3; /* 0x4c */ - u32 dbtr3; - u32 dbtr4; - u32 dbtr5; - u32 dbtr6; - u32 dbtr7; - u32 dbtr8; - u32 dbtr9; - u32 dbtr10; - u32 dbtr11; - u32 dbtr12; - u32 dbtr13; - u32 dbtr14; - u32 dbtr15; - u32 dbtr16; - u32 dbtr17; - u32 dbtr18; - u32 dbtr19; - u32 dummy4[7]; /* 0x94 .. 0xac */ - u32 dbbl; - u32 dummy5[3]; /* 0xb4 .. 0xbc */ - u32 dbadj0; - u32 dbadj1; - u32 dbadj2; - u32 dummy6[5]; /* 0xcc .. 0xdc */ - u32 dbrfcnf0; - u32 dbrfcnf1; - u32 dbrfcnf2; - u32 dbrfcnf3; - u32 dummy7; /* 0xf0 */ - u32 dbcalcnf; - u32 dbcaltr; - u32 dummy8; /* 0xfc */; - u32 dbrnk0; - u32 dummy9[31]; /* 0x104 .. 0x17C */ - u32 dbpdncnf; - u32 dummy10[7]; /* 0x184 .. 0x19C */ - u32 dbmrrdr; - u32 dummy11[39]; /* 0x1A4 .. 0x23C */ - u32 dbdfistat; - u32 dbdficnt; - u32 dummy12[46]; /* 0x248 .. 0x2FC */ - u32 dbbs0cnt0; - u32 dbbs0cnt1; -}; - -#endif - -#endif /* __ASM_ARCH_R8A7740_H */ diff --git a/arch/arm/mach-rmobile/include/mach/rmobile.h b/arch/arm/mach-rmobile/include/mach/rmobile.h deleted file mode 100644 index f021621..0000000 --- a/arch/arm/mach-rmobile/include/mach/rmobile.h +++ /dev/null @@ -1,58 +0,0 @@ -#ifndef __ASM_ARCH_RMOBILE_H -#define __ASM_ARCH_RMOBILE_H - -#if defined(CONFIG_ARCH_RMOBILE) -#if defined(CONFIG_R8A7740) -#include <asm/arch/r8a7740.h> -#elif defined(CONFIG_R8A7790) -#include <asm/arch/r8a7790.h> -#elif defined(CONFIG_R8A7791) -#include <asm/arch/r8a7791.h> -#elif defined(CONFIG_R8A7792) -#include <asm/arch/r8a7792.h> -#elif defined(CONFIG_R8A7793) -#include <asm/arch/r8a7793.h> -#elif defined(CONFIG_R8A7794) -#include <asm/arch/r8a7794.h> -#elif defined(CONFIG_RCAR_GEN3) -#include <asm/arch/rcar-gen3-base.h> -#elif defined(CONFIG_RCAR_GEN4) -#include <asm/arch/rcar-gen4-base.h> -#elif defined(CONFIG_R7S72100) -#elif defined(CONFIG_RZG2L) -#include <asm/arch/rzg2l.h> -#else -#error "SOC Name not defined" -#endif -#endif /* CONFIG_ARCH_RMOBILE */ - -/* PRR CPU IDs */ -#define RMOBILE_CPU_TYPE_R8A7740 0x40 -#define RMOBILE_CPU_TYPE_R8A7790 0x45 -#define RMOBILE_CPU_TYPE_R8A7791 0x47 -#define RMOBILE_CPU_TYPE_R8A7792 0x4A -#define RMOBILE_CPU_TYPE_R8A7793 0x4B -#define RMOBILE_CPU_TYPE_R8A7794 0x4C -#define RMOBILE_CPU_TYPE_R8A7795 0x4F -#define RMOBILE_CPU_TYPE_R8A7796 0x52 -#define RMOBILE_CPU_TYPE_R8A77965 0x55 -#define RMOBILE_CPU_TYPE_R8A77970 0x54 -#define RMOBILE_CPU_TYPE_R8A77980 0x56 -#define RMOBILE_CPU_TYPE_R8A77990 0x57 -#define RMOBILE_CPU_TYPE_R8A77995 0x58 -#define RMOBILE_CPU_TYPE_R8A779A0 0x59 -#define RMOBILE_CPU_TYPE_R8A779F0 0x5A -#define RMOBILE_CPU_TYPE_R8A779G0 0x5C -#define RMOBILE_CPU_TYPE_R8A779H0 0x5D -#define RMOBILE_CPU_TYPE_R9A07G044L 0x9A070440 - -#ifndef __ASSEMBLY__ -#include <asm/types.h> - -const u8 *rzg_get_cpu_name(void); -u32 rmobile_get_cpu_type(void); -u32 rmobile_get_cpu_rev_integer(void); -u32 rmobile_get_cpu_rev_fraction(void); -#endif /* __ASSEMBLY__ */ - -#endif /* __ASM_ARCH_RMOBILE_H */ diff --git a/arch/arm/mach-rmobile/include/mach/sh_sdhi.h b/arch/arm/mach-rmobile/include/mach/sh_sdhi.h deleted file mode 100644 index 7741718..0000000 --- a/arch/arm/mach-rmobile/include/mach/sh_sdhi.h +++ /dev/null @@ -1,170 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * drivers/mmc/sh-sdhi.h - * - * SD/MMC driver for Renesas rmobile ARM SoCs - * - * Copyright (C) 2013-2017 Renesas Electronics Corporation - * Copyright (C) 2008-2009 Renesas Solutions Corp. - */ - -#ifndef _SH_SDHI_H -#define _SH_SDHI_H - -#include <linux/bitops.h> -#define SDHI_CMD (0x0000 >> 1) -#define SDHI_PORTSEL (0x0004 >> 1) -#define SDHI_ARG0 (0x0008 >> 1) -#define SDHI_ARG1 (0x000C >> 1) -#define SDHI_STOP (0x0010 >> 1) -#define SDHI_SECCNT (0x0014 >> 1) -#define SDHI_RSP00 (0x0018 >> 1) -#define SDHI_RSP01 (0x001C >> 1) -#define SDHI_RSP02 (0x0020 >> 1) -#define SDHI_RSP03 (0x0024 >> 1) -#define SDHI_RSP04 (0x0028 >> 1) -#define SDHI_RSP05 (0x002C >> 1) -#define SDHI_RSP06 (0x0030 >> 1) -#define SDHI_RSP07 (0x0034 >> 1) -#define SDHI_INFO1 (0x0038 >> 1) -#define SDHI_INFO2 (0x003C >> 1) -#define SDHI_INFO1_MASK (0x0040 >> 1) -#define SDHI_INFO2_MASK (0x0044 >> 1) -#define SDHI_CLK_CTRL (0x0048 >> 1) -#define SDHI_SIZE (0x004C >> 1) -#define SDHI_OPTION (0x0050 >> 1) -#define SDHI_ERR_STS1 (0x0058 >> 1) -#define SDHI_ERR_STS2 (0x005C >> 1) -#define SDHI_BUF0 (0x0060 >> 1) -#define SDHI_SDIO_MODE (0x0068 >> 1) -#define SDHI_SDIO_INFO1 (0x006C >> 1) -#define SDHI_SDIO_INFO1_MASK (0x0070 >> 1) -#define SDHI_CC_EXT_MODE (0x01B0 >> 1) -#define SDHI_SOFT_RST (0x01C0 >> 1) -#define SDHI_VERSION (0x01C4 >> 1) -#define SDHI_HOST_MODE (0x01C8 >> 1) -#define SDHI_SDIF_MODE (0x01CC >> 1) -#define SDHI_EXT_SWAP (0x01E0 >> 1) -#define SDHI_SD_DMACR (0x0324 >> 1) - -/* SDHI CMD VALUE */ -#define CMD_MASK 0x0000ffff - -/* SDHI_PORTSEL */ -#define USE_1PORT (1 << 8) /* 1 port */ - -/* SDHI_ARG */ -#define ARG0_MASK 0x0000ffff -#define ARG1_MASK 0x0000ffff - -/* SDHI_STOP */ -#define STOP_SEC_ENABLE (1 << 8) - -/* SDHI_INFO1 */ -#define INFO1_RESP_END (1 << 0) -#define INFO1_ACCESS_END (1 << 2) -#define INFO1_CARD_RE (1 << 3) -#define INFO1_CARD_IN (1 << 4) -#define INFO1_ISD0CD (1 << 5) -#define INFO1_WRITE_PRO (1 << 7) -#define INFO1_DATA3_CARD_RE (1 << 8) -#define INFO1_DATA3_CARD_IN (1 << 9) -#define INFO1_DATA3 (1 << 10) - -/* SDHI_INFO2 */ -#define INFO2_CMD_ERROR (1 << 0) -#define INFO2_CRC_ERROR (1 << 1) -#define INFO2_END_ERROR (1 << 2) -#define INFO2_TIMEOUT (1 << 3) -#define INFO2_BUF_ILL_WRITE (1 << 4) -#define INFO2_BUF_ILL_READ (1 << 5) -#define INFO2_RESP_TIMEOUT (1 << 6) -#define INFO2_SDDAT0 (1 << 7) -#define INFO2_BRE_ENABLE (1 << 8) -#define INFO2_BWE_ENABLE (1 << 9) -#define INFO2_CBUSY (1 << 14) -#define INFO2_ILA (1 << 15) -#define INFO2_ALL_ERR (0x807f) - -/* SDHI_INFO1_MASK */ -#define INFO1M_RESP_END (1 << 0) -#define INFO1M_ACCESS_END (1 << 2) -#define INFO1M_CARD_RE (1 << 3) -#define INFO1M_CARD_IN (1 << 4) -#define INFO1M_DATA3_CARD_RE (1 << 8) -#define INFO1M_DATA3_CARD_IN (1 << 9) -#define INFO1M_ALL (0xffff) -#define INFO1M_SET (INFO1M_RESP_END | \ - INFO1M_ACCESS_END | \ - INFO1M_DATA3_CARD_RE | \ - INFO1M_DATA3_CARD_IN) - -/* SDHI_INFO2_MASK */ -#define INFO2M_CMD_ERROR (1 << 0) -#define INFO2M_CRC_ERROR (1 << 1) -#define INFO2M_END_ERROR (1 << 2) -#define INFO2M_TIMEOUT (1 << 3) -#define INFO2M_BUF_ILL_WRITE (1 << 4) -#define INFO2M_BUF_ILL_READ (1 << 5) -#define INFO2M_RESP_TIMEOUT (1 << 6) -#define INFO2M_BRE_ENABLE (1 << 8) -#define INFO2M_BWE_ENABLE (1 << 9) -#define INFO2M_ILA (1 << 15) -#define INFO2M_ALL (0xffff) -#define INFO2M_ALL_ERR (0x807f) - -/* SDHI_CLK_CTRL */ -#define CLK_ENABLE (1 << 8) - -/* SDHI_OPTION */ -#define OPT_BUS_WIDTH_M (5 << 13) /* 101b (15-13bit) */ -#define OPT_BUS_WIDTH_1 (4 << 13) /* bus width = 1 bit */ -#define OPT_BUS_WIDTH_4 (0 << 13) /* bus width = 4 bit */ -#define OPT_BUS_WIDTH_8 (1 << 13) /* bus width = 8 bit */ - -/* SDHI_ERR_STS1 */ -#define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \ - (1 << 8) | (1 << 5)) -#define ERR_STS1_CMD_ERROR ((1 << 4) | (1 << 3) | (1 << 2) | \ - (1 << 1) | (1 << 0)) - -/* SDHI_ERR_STS2 */ -#define ERR_STS2_RES_TIMEOUT (1 << 0) -#define ERR_STS2_RES_STOP_TIMEOUT ((1 << 0) | (1 << 1)) -#define ERR_STS2_SYS_ERROR ((1 << 6) | (1 << 5) | (1 << 4) | \ - (1 << 3) | (1 << 2) | (1 << 1) | \ - (1 << 0)) - -/* SDHI_SDIO_MODE */ -#define SDIO_MODE_ON (1 << 0) -#define SDIO_MODE_OFF (0 << 0) - -/* SDHI_SDIO_INFO1 */ -#define SDIO_INFO1_IOIRQ (1 << 0) -#define SDIO_INFO1_EXPUB52 (1 << 14) -#define SDIO_INFO1_EXWT (1 << 15) - -/* SDHI_SDIO_INFO1_MASK */ -#define SDIO_INFO1M_CLEAR ((1 << 1) | (1 << 2)) -#define SDIO_INFO1M_ON ((1 << 15) | (1 << 14) | (1 << 2) | \ - (1 << 1) | (1 << 0)) - -/* SDHI_EXT_SWAP */ -#define SET_SWAP ((1 << 6) | (1 << 7)) /* SWAP */ - -/* SDHI_SOFT_RST */ -#define SOFT_RST_ON (0 << 0) -#define SOFT_RST_OFF (1 << 0) - -#define CLKDEV_SD_DATA 25000000 /* 25 MHz */ -#define CLKDEV_HS_DATA 50000000 /* 50 MHz */ -#define CLKDEV_MMC_DATA 20000000 /* 20MHz */ -#define CLKDEV_INIT 400000 /* 100 - 400 KHz */ - -/* For quirk */ -#define SH_SDHI_QUIRK_16BIT_BUF BIT(0) -#define SH_SDHI_QUIRK_64BIT_BUF BIT(1) - -int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks); - -#endif /* _SH_SDHI_H */ diff --git a/arch/arm/mach-rmobile/lowlevel_init.S b/arch/arm/mach-rmobile/lowlevel_init.S deleted file mode 100644 index 212e955..0000000 --- a/arch/arm/mach-rmobile/lowlevel_init.S +++ /dev/null @@ -1,72 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com> - * Copyright (C) 2012 Renesas Solutions Corp. - */ - -#include <config.h> -#include <linux/linkage.h> -#include <system-constants.h> - -ENTRY(lowlevel_init) - ldr r0, =MERAM_BASE - mov r1, #0x0 - str r1, [r0] - - mrc p15, 0, r0, c0, c0, 5 - ands r0, r0, #0xF - beq lowlevel_init__ - b wait_interrupt - - .pool - .align 4 - -wait_interrupt: -#ifdef ICCICR - ldr r1, =ICCICR - mov r2, #0x0 - str r2, [r1] - mov r2, #0xF0 - adds r1, r1, #4 /* ICCPMR */ - str r2, [r1] - ldr r1, =ICCICR - mov r2, #0x1 - str r2, [r1] -#endif - -wait_loop: - .long 0xE320F003 /* wfi */ - - ldr r2, [r1, #0xC] - str r2, [r1, #0x10] - - ldr r0, =MERAM_BASE - ldr r2, [r0] - cmp r2, #0 - movne pc, r2 - - b wait_loop - -wait_loop_end: - .pool - .align 4 - -lowlevel_init__: - - mov r0, #0x200000 - -loop0: - subs r0, r0, #1 - bne loop0 - - ldr sp, MERAM_STACK - b s_init - - .pool - .align 4 - -ENDPROC(lowlevel_init) - .ltorg - -MERAM_STACK: - .word LOW_LEVEL_MERAM_STACK diff --git a/arch/arm/mach-rmobile/pfc-r8a7740.c b/arch/arm/mach-rmobile/pfc-r8a7740.c deleted file mode 100644 index 4f48476..0000000 --- a/arch/arm/mach-rmobile/pfc-r8a7740.c +++ /dev/null @@ -1,2612 +0,0 @@ -/* - * R8A7740 processor support - * - * Copyright (C) 2011 Renesas Solutions Corp. - * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the - * License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <sh_pfc.h> -#include <asm/gpio.h> -#include <asm/arch/irqs.h> - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \ - PORT_10(fn, pfx##10, sfx), PORT_90(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##20, sfx), \ - PORT_1(fn, pfx##210, sfx), PORT_1(fn, pfx##211, sfx) - -enum { - PINMUX_RESERVED = 0, - - /* PORT0_DATA -> PORT211_DATA */ - PINMUX_DATA_BEGIN, - PORT_ALL(DATA), - PINMUX_DATA_END, - - /* PORT0_IN -> PORT211_IN */ - PINMUX_INPUT_BEGIN, - PORT_ALL(IN), - PINMUX_INPUT_END, - - /* PORT0_IN_PU -> PORT211_IN_PU */ - PINMUX_INPUT_PULLUP_BEGIN, - PORT_ALL(IN_PU), - PINMUX_INPUT_PULLUP_END, - - /* PORT0_IN_PD -> PORT211_IN_PD */ - PINMUX_INPUT_PULLDOWN_BEGIN, - PORT_ALL(IN_PD), - PINMUX_INPUT_PULLDOWN_END, - - /* PORT0_OUT -> PORT211_OUT */ - PINMUX_OUTPUT_BEGIN, - PORT_ALL(OUT), - PINMUX_OUTPUT_END, - - PINMUX_FUNCTION_BEGIN, - PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */ - PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */ - PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */ - PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */ - PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */ - PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */ - PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */ - PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */ - PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */ - PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */ - - MSEL1CR_31_0, MSEL1CR_31_1, - MSEL1CR_30_0, MSEL1CR_30_1, - MSEL1CR_29_0, MSEL1CR_29_1, - MSEL1CR_28_0, MSEL1CR_28_1, - MSEL1CR_27_0, MSEL1CR_27_1, - MSEL1CR_26_0, MSEL1CR_26_1, - MSEL1CR_16_0, MSEL1CR_16_1, - MSEL1CR_15_0, MSEL1CR_15_1, - MSEL1CR_14_0, MSEL1CR_14_1, - MSEL1CR_13_0, MSEL1CR_13_1, - MSEL1CR_12_0, MSEL1CR_12_1, - MSEL1CR_9_0, MSEL1CR_9_1, - MSEL1CR_7_0, MSEL1CR_7_1, - MSEL1CR_6_0, MSEL1CR_6_1, - MSEL1CR_5_0, MSEL1CR_5_1, - MSEL1CR_4_0, MSEL1CR_4_1, - MSEL1CR_3_0, MSEL1CR_3_1, - MSEL1CR_2_0, MSEL1CR_2_1, - MSEL1CR_0_0, MSEL1CR_0_1, - - MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */ - MSEL3CR_6_0, MSEL3CR_6_1, - - MSEL4CR_19_0, MSEL4CR_19_1, - MSEL4CR_18_0, MSEL4CR_18_1, - MSEL4CR_15_0, MSEL4CR_15_1, - MSEL4CR_10_0, MSEL4CR_10_1, - MSEL4CR_6_0, MSEL4CR_6_1, - MSEL4CR_4_0, MSEL4CR_4_1, - MSEL4CR_1_0, MSEL4CR_1_1, - - MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */ - MSEL5CR_30_0, MSEL5CR_30_1, - MSEL5CR_29_0, MSEL5CR_29_1, - MSEL5CR_27_0, MSEL5CR_27_1, - MSEL5CR_25_0, MSEL5CR_25_1, - MSEL5CR_23_0, MSEL5CR_23_1, - MSEL5CR_21_0, MSEL5CR_21_1, - MSEL5CR_19_0, MSEL5CR_19_1, - MSEL5CR_17_0, MSEL5CR_17_1, - MSEL5CR_15_0, MSEL5CR_15_1, - MSEL5CR_14_0, MSEL5CR_14_1, - MSEL5CR_13_0, MSEL5CR_13_1, - MSEL5CR_12_0, MSEL5CR_12_1, - MSEL5CR_11_0, MSEL5CR_11_1, - MSEL5CR_10_0, MSEL5CR_10_1, - MSEL5CR_8_0, MSEL5CR_8_1, - MSEL5CR_7_0, MSEL5CR_7_1, - MSEL5CR_6_0, MSEL5CR_6_1, - MSEL5CR_5_0, MSEL5CR_5_1, - MSEL5CR_4_0, MSEL5CR_4_1, - MSEL5CR_3_0, MSEL5CR_3_1, - MSEL5CR_2_0, MSEL5CR_2_1, - MSEL5CR_0_0, MSEL5CR_0_1, - PINMUX_FUNCTION_END, - - PINMUX_MARK_BEGIN, - - /* IRQ */ - IRQ0_PORT2_MARK, IRQ0_PORT13_MARK, - IRQ1_MARK, - IRQ2_PORT11_MARK, IRQ2_PORT12_MARK, - IRQ3_PORT10_MARK, IRQ3_PORT14_MARK, - IRQ4_PORT15_MARK, IRQ4_PORT172_MARK, - IRQ5_PORT0_MARK, IRQ5_PORT1_MARK, - IRQ6_PORT121_MARK, IRQ6_PORT173_MARK, - IRQ7_PORT120_MARK, IRQ7_PORT209_MARK, - IRQ8_MARK, - IRQ9_PORT118_MARK, IRQ9_PORT210_MARK, - IRQ10_MARK, - IRQ11_MARK, - IRQ12_PORT42_MARK, IRQ12_PORT97_MARK, - IRQ13_PORT64_MARK, IRQ13_PORT98_MARK, - IRQ14_PORT63_MARK, IRQ14_PORT99_MARK, - IRQ15_PORT62_MARK, IRQ15_PORT100_MARK, - IRQ16_PORT68_MARK, IRQ16_PORT211_MARK, - IRQ17_MARK, - IRQ18_MARK, - IRQ19_MARK, - IRQ20_MARK, - IRQ21_MARK, - IRQ22_MARK, - IRQ23_MARK, - IRQ24_MARK, - IRQ25_MARK, - IRQ26_PORT58_MARK, IRQ26_PORT81_MARK, - IRQ27_PORT57_MARK, IRQ27_PORT168_MARK, - IRQ28_PORT56_MARK, IRQ28_PORT169_MARK, - IRQ29_PORT50_MARK, IRQ29_PORT170_MARK, - IRQ30_PORT49_MARK, IRQ30_PORT171_MARK, - IRQ31_PORT41_MARK, IRQ31_PORT167_MARK, - - /* Function */ - - /* DBGT */ - DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK, - DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK, - DBGMD21_MARK, - - /* FSI */ - FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */ - FSIAISLD_PORT5_MARK, - FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */ - FSIASPDIF_PORT18_MARK, - FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK, - FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK, - FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK, - - /* FMSI */ - FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */ - FMSISLD_PORT6_MARK, - FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK, - FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK, - FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK, - - /* SCIFA0 */ - SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK, - SCIFA0_RXD_MARK, SCIFA0_TXD_MARK, - - /* SCIFA1 */ - SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK, - SCIFA1_TXD_MARK, SCIFA1_RTS_MARK, - - /* SCIFA2 */ - SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */ - SCIFA2_SCK_PORT199_MARK, - SCIFA2_RXD_MARK, SCIFA2_TXD_MARK, - SCIFA2_CTS_MARK, SCIFA2_RTS_MARK, - - /* SCIFA3 */ - SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */ - SCIFA3_SCK_PORT116_MARK, - SCIFA3_CTS_PORT117_MARK, - SCIFA3_RXD_PORT174_MARK, - SCIFA3_TXD_PORT175_MARK, - - SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */ - SCIFA3_SCK_PORT158_MARK, - SCIFA3_CTS_PORT162_MARK, - SCIFA3_RXD_PORT159_MARK, - SCIFA3_TXD_PORT160_MARK, - - /* SCIFA4 */ - SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */ - SCIFA4_TXD_PORT13_MARK, - - SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */ - SCIFA4_TXD_PORT203_MARK, - - SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */ - SCIFA4_TXD_PORT93_MARK, - - SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */ - SCIFA4_SCK_PORT205_MARK, - - /* SCIFA5 */ - SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */ - SCIFA5_RXD_PORT10_MARK, - - SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */ - SCIFA5_TXD_PORT208_MARK, - - SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */ - SCIFA5_RXD_PORT92_MARK, - - SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */ - SCIFA5_SCK_PORT206_MARK, - - /* SCIFA6 */ - SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK, - - /* SCIFA7 */ - SCIFA7_TXD_MARK, SCIFA7_RXD_MARK, - - /* SCIFAB */ - SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */ - SCIFB_RXD_PORT191_MARK, - SCIFB_TXD_PORT192_MARK, - SCIFB_RTS_PORT186_MARK, - SCIFB_CTS_PORT187_MARK, - - SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */ - SCIFB_RXD_PORT3_MARK, - SCIFB_TXD_PORT4_MARK, - SCIFB_RTS_PORT172_MARK, - SCIFB_CTS_PORT173_MARK, - - /* LCD0 */ - LCDC0_SELECT_MARK, - - LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK, - LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK, - LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK, - LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK, - LCD0_D16_MARK, LCD0_D17_MARK, - LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK, - LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */ - LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */ - LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */ - LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */ - - LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */ - LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK, - LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK, - LCD0_LCLK_PORT165_MARK, - - LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */ - LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK, - LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK, - LCD0_LCLK_PORT102_MARK, - - /* LCD1 */ - LCDC1_SELECT_MARK, - - LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK, - LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK, - LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK, - LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK, - LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK, - LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK, - LCD1_DON_MARK, LCD1_VCPWC_MARK, - LCD1_LCLK_MARK, LCD1_VEPWC_MARK, - - LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */ - LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */ - LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */ - LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */ - - /* RSPI */ - RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK, - RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK, - RSPI_MISO_A_MARK, - - /* VIO CKO */ - VIO_CKO1_MARK, /* needs fixup */ - VIO_CKO2_MARK, - VIO_CKO_1_MARK, - VIO_CKO_MARK, - - /* VIO0 */ - VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK, - VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK, - VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK, - VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK, - VIO0_FIELD_MARK, - - VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */ - VIO0_D14_PORT25_MARK, - VIO0_D15_PORT24_MARK, - - VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */ - VIO0_D14_PORT95_MARK, - VIO0_D15_PORT96_MARK, - - /* VIO1 */ - VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK, - VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK, - VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK, - - /* TPU0 */ - TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK, - TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */ - TPU0TO2_PORT202_MARK, - - /* SSP1 0 */ - STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK, - STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK, - STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK, - - /* SSP1 1 */ - STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK, - STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK, - STP1_IPSYNC_MARK, - - STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */ - STP1_IPEN_PORT187_MARK, - - STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */ - STP1_IPEN_PORT193_MARK, - - /* SIM */ - SIM_RST_MARK, SIM_CLK_MARK, - SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */ - SIM_D_PORT199_MARK, - - /* SDHI0 */ - SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK, - SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK, - - /* SDHI1 */ - SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK, - SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK, - - /* SDHI2 */ - SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK, - SDHI2_CLK_MARK, SDHI2_CMD_MARK, - - SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */ - SDHI2_WP_PORT25_MARK, - - SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */ - SDHI2_CD_PORT202_MARK, - - /* MSIOF2 */ - MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK, - MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK, - MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK, - MSIOF2_RSCK_MARK, - - /* KEYSC */ - KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK, - KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, - KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK, - - KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */ - KEYIN1_PORT44_MARK, - KEYIN2_PORT45_MARK, - KEYIN3_PORT46_MARK, - - KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */ - KEYIN1_PORT57_MARK, - KEYIN2_PORT56_MARK, - KEYIN3_PORT55_MARK, - - /* VOU */ - DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK, - DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK, - DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK, - DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK, - DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK, - - /* MEMC */ - MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK, - MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK, - MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK, - MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK, - MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK, - - MEMC_CS1_MARK, /* MSEL4CR_6_0 */ - MEMC_ADV_MARK, - MEMC_WAIT_MARK, - MEMC_BUSCLK_MARK, - - MEMC_A1_MARK, /* MSEL4CR_6_1 */ - MEMC_DREQ0_MARK, - MEMC_DREQ1_MARK, - MEMC_A0_MARK, - - /* MMC */ - MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, - MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, - MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK, - MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */ - - MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, - MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, - MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK, - MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */ - - /* MSIOF0 */ - MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK, - MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK, - MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK, - MSIOF0_TSYNC_MARK, - - /* MSIOF1 */ - MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK, - MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK, - - MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK, - MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK, - MSIOF1_TSYNC_PORT120_MARK, - MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */ - - MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK, - MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK, - MSIOF1_RXD_PORT75_MARK, - MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */ - - /* GPIO */ - GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK, - - /* USB0 */ - USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK, - - /* USB1 */ - USB1_OCI_MARK, USB1_PPON_MARK, - - /* BBIF1 */ - BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK, - BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK, - BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK, - - /* BBIF2 */ - BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */ - BBIF2_RXD2_PORT60_MARK, - BBIF2_TSYNC2_PORT6_MARK, - BBIF2_TSCK2_PORT59_MARK, - - BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */ - BBIF2_TXD2_PORT183_MARK, - BBIF2_TSCK2_PORT89_MARK, - BBIF2_TSYNC2_PORT184_MARK, - - /* BSC / FLCTL / PCMCIA */ - CS0_MARK, CS2_MARK, CS4_MARK, - CS5B_MARK, CS6A_MARK, - CS5A_PORT105_MARK, /* CS5A PORT 19/105 */ - CS5A_PORT19_MARK, - IOIS16_MARK, /* ? */ - - A0_MARK, A1_MARK, A2_MARK, A3_MARK, - A4_FOE_MARK, /* share with FLCTL */ - A5_FCDE_MARK, /* share with FLCTL */ - A6_MARK, A7_MARK, A8_MARK, A9_MARK, - A10_MARK, A11_MARK, A12_MARK, A13_MARK, - A14_MARK, A15_MARK, A16_MARK, A17_MARK, - A18_MARK, A19_MARK, A20_MARK, A21_MARK, - A22_MARK, A23_MARK, A24_MARK, A25_MARK, - A26_MARK, - - D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */ - D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */ - D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */ - D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */ - D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */ - D15_NAF15_MARK, /* share with FLCTL */ - D16_MARK, D17_MARK, D18_MARK, D19_MARK, - D20_MARK, D21_MARK, D22_MARK, D23_MARK, - D24_MARK, D25_MARK, D26_MARK, D27_MARK, - D28_MARK, D29_MARK, D30_MARK, D31_MARK, - - WE0_FWE_MARK, /* share with FLCTL */ - WE1_MARK, - WE2_ICIORD_MARK, /* share with PCMCIA */ - WE3_ICIOWR_MARK, /* share with PCMCIA */ - CKO_MARK, BS_MARK, RDWR_MARK, - RD_FSC_MARK, /* share with FLCTL */ - WAIT_PORT177_MARK, /* WAIT Port 90/177 */ - WAIT_PORT90_MARK, - - FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */ - - /* IRDA */ - IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK, - - /* ATAPI */ - IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK, - IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK, - IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK, - IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK, - IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK, - IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK, - IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK, - IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK, - - /* RMII */ - RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK, - RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK, - RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK, - RMII_REF50CK_MARK, /* for RMII */ - RMII_REF125CK_MARK, /* for GMII */ - - /* GEther */ - ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK, - ET_ETXD2_MARK, ET_ETXD3_MARK, - ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */ - ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */ - ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK, - ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK, - ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */ - ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */ - ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK, - ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK, - - /* DMA0 */ - DREQ0_MARK, DACK0_MARK, - - /* DMA1 */ - DREQ1_MARK, DACK1_MARK, - - /* SYSC */ - RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK, - - /* IRREM */ - IROUT_MARK, - - /* SDENC */ - SDENC_CPG_MARK, SDENC_DV_CLKI_MARK, - - /* DEBUG */ - EDEBGREQ_PULLUP_MARK, /* for JTAG */ - EDEBGREQ_PULLDOWN_MARK, - - TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */ - TRACEAUD_FROM_LCDC0_MARK, - TRACEAUD_FROM_MEMC_MARK, - - PINMUX_MARK_END, -}; - -static unsigned short pinmux_data[] = { - /* specify valid pin states for each pin in GPIO mode */ - - /* I/O and Pull U/D */ - PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), - PORT_DATA_IO_PD(2), PORT_DATA_IO_PD(3), - PORT_DATA_IO_PD(4), PORT_DATA_IO_PD(5), - PORT_DATA_IO_PD(6), PORT_DATA_IO(7), - PORT_DATA_IO(8), PORT_DATA_IO(9), - - PORT_DATA_IO_PD(10), PORT_DATA_IO_PD(11), - PORT_DATA_IO_PD(12), PORT_DATA_IO_PU_PD(13), - PORT_DATA_IO_PD(14), PORT_DATA_IO_PD(15), - PORT_DATA_IO_PD(16), PORT_DATA_IO_PD(17), - PORT_DATA_IO(18), PORT_DATA_IO_PU(19), - - PORT_DATA_IO_PU_PD(20), PORT_DATA_IO_PD(21), - PORT_DATA_IO_PU_PD(22), PORT_DATA_IO(23), - PORT_DATA_IO_PU(24), PORT_DATA_IO_PU(25), - PORT_DATA_IO_PU(26), PORT_DATA_IO_PU(27), - PORT_DATA_IO_PU(28), PORT_DATA_IO_PU(29), - - PORT_DATA_IO_PU(30), PORT_DATA_IO_PD(31), - PORT_DATA_IO_PD(32), PORT_DATA_IO_PD(33), - PORT_DATA_IO_PD(34), PORT_DATA_IO_PU(35), - PORT_DATA_IO_PU(36), PORT_DATA_IO_PD(37), - PORT_DATA_IO_PU(38), PORT_DATA_IO_PD(39), - - PORT_DATA_IO_PU_PD(40), PORT_DATA_IO_PD(41), - PORT_DATA_IO_PD(42), PORT_DATA_IO_PU_PD(43), - PORT_DATA_IO_PU_PD(44), PORT_DATA_IO_PU_PD(45), - PORT_DATA_IO_PU_PD(46), PORT_DATA_IO_PU_PD(47), - PORT_DATA_IO_PU_PD(48), PORT_DATA_IO_PU_PD(49), - - PORT_DATA_IO_PU_PD(50), PORT_DATA_IO_PD(51), - PORT_DATA_IO_PD(52), PORT_DATA_IO_PD(53), - PORT_DATA_IO_PD(54), PORT_DATA_IO_PU_PD(55), - PORT_DATA_IO_PU_PD(56), PORT_DATA_IO_PU_PD(57), - PORT_DATA_IO_PU_PD(58), PORT_DATA_IO_PU_PD(59), - - PORT_DATA_IO_PU_PD(60), PORT_DATA_IO_PD(61), - PORT_DATA_IO_PD(62), PORT_DATA_IO_PD(63), - PORT_DATA_IO_PD(64), PORT_DATA_IO_PD(65), - PORT_DATA_IO_PU_PD(66), PORT_DATA_IO_PU_PD(67), - PORT_DATA_IO_PU_PD(68), PORT_DATA_IO_PU_PD(69), - - PORT_DATA_IO_PU_PD(70), PORT_DATA_IO_PU_PD(71), - PORT_DATA_IO_PU_PD(72), PORT_DATA_IO_PU_PD(73), - PORT_DATA_IO_PU_PD(74), PORT_DATA_IO_PU_PD(75), - PORT_DATA_IO_PU_PD(76), PORT_DATA_IO_PU_PD(77), - PORT_DATA_IO_PU_PD(78), PORT_DATA_IO_PU_PD(79), - - PORT_DATA_IO_PU_PD(80), PORT_DATA_IO_PU_PD(81), - PORT_DATA_IO(82), PORT_DATA_IO_PU_PD(83), - PORT_DATA_IO(84), PORT_DATA_IO_PD(85), - PORT_DATA_IO_PD(86), PORT_DATA_IO_PD(87), - PORT_DATA_IO_PD(88), PORT_DATA_IO_PD(89), - - PORT_DATA_IO_PD(90), PORT_DATA_IO_PU_PD(91), - PORT_DATA_IO_PU_PD(92), PORT_DATA_IO_PU_PD(93), - PORT_DATA_IO_PU_PD(94), PORT_DATA_IO_PU_PD(95), - PORT_DATA_IO_PU_PD(96), PORT_DATA_IO_PU_PD(97), - PORT_DATA_IO_PU_PD(98), PORT_DATA_IO_PU_PD(99), - - PORT_DATA_IO_PU_PD(100), PORT_DATA_IO(101), - PORT_DATA_IO_PU(102), PORT_DATA_IO_PU_PD(103), - PORT_DATA_IO_PU(104), PORT_DATA_IO_PU(105), - PORT_DATA_IO_PU_PD(106), PORT_DATA_IO(107), - PORT_DATA_IO(108), PORT_DATA_IO(109), - - PORT_DATA_IO(110), PORT_DATA_IO(111), - PORT_DATA_IO(112), PORT_DATA_IO(113), - PORT_DATA_IO_PU_PD(114), PORT_DATA_IO(115), - PORT_DATA_IO_PD(116), PORT_DATA_IO_PD(117), - PORT_DATA_IO_PD(118), PORT_DATA_IO_PD(119), - - PORT_DATA_IO_PD(120), PORT_DATA_IO_PD(121), - PORT_DATA_IO_PD(122), PORT_DATA_IO_PD(123), - PORT_DATA_IO_PD(124), PORT_DATA_IO(125), - PORT_DATA_IO(126), PORT_DATA_IO(127), - PORT_DATA_IO(128), PORT_DATA_IO(129), - - PORT_DATA_IO(130), PORT_DATA_IO(131), - PORT_DATA_IO(132), PORT_DATA_IO(133), - PORT_DATA_IO(134), PORT_DATA_IO(135), - PORT_DATA_IO(136), PORT_DATA_IO(137), - PORT_DATA_IO(138), PORT_DATA_IO(139), - - PORT_DATA_IO(140), PORT_DATA_IO(141), - PORT_DATA_IO_PU(142), PORT_DATA_IO_PU(143), - PORT_DATA_IO_PU(144), PORT_DATA_IO_PU(145), - PORT_DATA_IO_PU(146), PORT_DATA_IO_PU(147), - PORT_DATA_IO_PU(148), PORT_DATA_IO_PU(149), - - PORT_DATA_IO_PU(150), PORT_DATA_IO_PU(151), - PORT_DATA_IO_PU(152), PORT_DATA_IO_PU(153), - PORT_DATA_IO_PU(154), PORT_DATA_IO_PU(155), - PORT_DATA_IO_PU(156), PORT_DATA_IO_PU(157), - PORT_DATA_IO_PD(158), PORT_DATA_IO_PD(159), - - PORT_DATA_IO_PU_PD(160), PORT_DATA_IO_PD(161), - PORT_DATA_IO_PD(162), PORT_DATA_IO_PD(163), - PORT_DATA_IO_PD(164), PORT_DATA_IO_PD(165), - PORT_DATA_IO_PU(166), PORT_DATA_IO_PU(167), - PORT_DATA_IO_PU(168), PORT_DATA_IO_PU(169), - - PORT_DATA_IO_PU(170), PORT_DATA_IO_PU(171), - PORT_DATA_IO_PD(172), PORT_DATA_IO_PD(173), - PORT_DATA_IO_PD(174), PORT_DATA_IO_PD(175), - PORT_DATA_IO_PU(176), PORT_DATA_IO_PU_PD(177), - PORT_DATA_IO_PU(178), PORT_DATA_IO_PD(179), - - PORT_DATA_IO_PD(180), PORT_DATA_IO_PU(181), - PORT_DATA_IO_PU(182), PORT_DATA_IO(183), - PORT_DATA_IO_PD(184), PORT_DATA_IO_PD(185), - PORT_DATA_IO_PD(186), PORT_DATA_IO_PD(187), - PORT_DATA_IO_PD(188), PORT_DATA_IO_PD(189), - - PORT_DATA_IO_PD(190), PORT_DATA_IO_PD(191), - PORT_DATA_IO_PD(192), PORT_DATA_IO_PU_PD(193), - PORT_DATA_IO_PU_PD(194), PORT_DATA_IO_PD(195), - PORT_DATA_IO_PU_PD(196), PORT_DATA_IO_PD(197), - PORT_DATA_IO_PU_PD(198), PORT_DATA_IO_PU_PD(199), - - PORT_DATA_IO_PU_PD(200), PORT_DATA_IO_PU(201), - PORT_DATA_IO_PU_PD(202), PORT_DATA_IO(203), - PORT_DATA_IO_PU_PD(204), PORT_DATA_IO_PU_PD(205), - PORT_DATA_IO_PU_PD(206), PORT_DATA_IO_PU_PD(207), - PORT_DATA_IO_PU_PD(208), PORT_DATA_IO_PD(209), - - PORT_DATA_IO_PD(210), PORT_DATA_IO_PD(211), - - /* Port0 */ - PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1), - PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0), - PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3), - PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0), - PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6), - PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7), - PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0), - - /* Port1 */ - PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1), - PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0), - PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3), - PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0), - PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6), - PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7), - PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1), - - /* Port2 */ - PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1), - PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1), - PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0), - PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7), - PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1), - - /* Port3 */ - PINMUX_DATA(DBGMD21_MARK, PORT3_FN1), - PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1), - PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0), - PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7), - - /* Port4 */ - PINMUX_DATA(DBGMD20_MARK, PORT4_FN1), - PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1), - PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0), - PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7), - - /* Port5 */ - PINMUX_DATA(DBGMD11_MARK, PORT5_FN1), - PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0), - PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1), - PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6), - PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7), - - /* Port6 */ - PINMUX_DATA(DBGMD10_MARK, PORT6_FN1), - PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0), - PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1), - PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6), - PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7), - - /* Port7 */ - PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1), - - /* Port8 */ - PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1), - - /* Port9 */ - PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1), - PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0), - - /* Port10 */ - PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1), - PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, - MSEL5CR_15_0), - PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0), - - /* Port11 */ - PINMUX_DATA(FSIACK_MARK, PORT11_FN1), - PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0), - - /* Port12 */ - PINMUX_DATA(FSIAILR_MARK, PORT12_FN1), - PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, - MSEL5CR_11_0), - PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6), - PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7), - PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1), - - /* Port13 */ - PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1), - PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, - MSEL5CR_11_0), - PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7), - PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0), - - /* Port14 */ - PINMUX_DATA(FMSOILR_MARK, PORT14_FN1), - PINMUX_DATA(FMSIILR_MARK, PORT14_FN2), - PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3), - PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7), - PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1), - - /* Port15 */ - PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1), - PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2), - PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3), - PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7), - PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0), - - /* Port16 */ - PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1), - PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2), - - /* Port17 */ - PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1), - PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2), - - /* Port18 */ - PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1), - PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1), - - /* Port19 */ - PINMUX_DATA(FMSICK_MARK, PORT19_FN1), - PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1), - PINMUX_DATA(IRQ10_MARK, PORT19_FN0), - - /* Port20 */ - PINMUX_DATA(FMSOCK_MARK, PORT20_FN1), - PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, - MSEL5CR_14_0), - PINMUX_DATA(IRQ1_MARK, PORT20_FN0), - - /* Port21 */ - PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1), - PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0), - PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4), - PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5), - PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6), - PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7), - - /* Port22 */ - PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0), - PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0), - PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1), - - /* Port23 */ - PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1), - PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0), - PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4), - PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5), - PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6), - PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7), - - /* Port24 */ - PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0), - PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5), - PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6), - PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0), - - /* Port25 */ - PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0), - PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5), - PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6), - PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0), - - /* Port26 */ - PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0), - PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5), - PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6), - - /* Port27 - Port39 Function */ - PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1), - PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1), - PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1), - PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1), - PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1), - PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1), - PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1), - PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1), - PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1), - PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1), - PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1), - PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1), - PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1), - - /* Port38 IRQ */ - PINMUX_DATA(IRQ25_MARK, PORT38_FN0), - - /* Port40 */ - PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0), - PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6), - PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7), - - /* Port41 */ - PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1), - PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2), - PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1), - - /* Port42 */ - PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1), - PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2), - PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1), - - /* Port43 */ - PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1), - PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2), - PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0), - PINMUX_DATA(DV_D15_MARK, PORT43_FN6), - - /* Port44 */ - PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1), - PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2), - PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0), - PINMUX_DATA(DV_D14_MARK, PORT44_FN6), - - /* Port45 */ - PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1), - PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2), - PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0), - PINMUX_DATA(DV_D13_MARK, PORT45_FN6), - - /* Port46 */ - PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1), - PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0), - PINMUX_DATA(DV_D12_MARK, PORT46_FN6), - - /* Port47 */ - PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1), - PINMUX_DATA(KEYIN4_MARK, PORT47_FN3), - PINMUX_DATA(DV_D11_MARK, PORT47_FN6), - - /* Port48 */ - PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1), - PINMUX_DATA(KEYIN5_MARK, PORT48_FN3), - PINMUX_DATA(DV_D10_MARK, PORT48_FN6), - - /* Port49 */ - PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1), - PINMUX_DATA(KEYIN6_MARK, PORT49_FN3), - PINMUX_DATA(DV_D9_MARK, PORT49_FN6), - PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1), - - /* Port50 */ - PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1), - PINMUX_DATA(KEYIN7_MARK, PORT50_FN3), - PINMUX_DATA(DV_D8_MARK, PORT50_FN6), - PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1), - - /* Port51 */ - PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1), - PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3), - PINMUX_DATA(DV_D7_MARK, PORT51_FN6), - - /* Port52 */ - PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1), - PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3), - PINMUX_DATA(DV_D6_MARK, PORT52_FN6), - - /* Port53 */ - PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1), - PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3), - PINMUX_DATA(DV_D5_MARK, PORT53_FN6), - - /* Port54 */ - PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1), - PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3), - PINMUX_DATA(DV_D4_MARK, PORT54_FN6), - - /* Port55 */ - PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1), - PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3), - PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1), - PINMUX_DATA(DV_D3_MARK, PORT55_FN6), - - /* Port56 */ - PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1), - PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3), - PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1), - PINMUX_DATA(DV_D2_MARK, PORT56_FN6), - PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1), - - /* Port57 */ - PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1), - PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3), - PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1), - PINMUX_DATA(DV_D1_MARK, PORT57_FN6), - PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1), - - /* Port58 */ - PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1), - PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3), - PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1), - PINMUX_DATA(DV_D0_MARK, PORT58_FN6), - PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1), - - /* Port59 */ - PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1), - PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0), - PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6), - - /* Port60 */ - PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1), - PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0), - PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6), - - /* Port61 */ - PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1), - PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2), - - /* Port62 */ - PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1), - PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4), - PINMUX_DATA(DV_CLK_MARK, PORT62_FN6), - PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1), - - /* Port63 */ - PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1), - PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6), - PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1), - - /* Port64 */ - PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1), - PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4), - PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6), - PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1), - - /* Port65 */ - PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1), - PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2), - PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4), - - /* Port66 */ - PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1), - PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0), - PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0), - PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6), - - /* Port67 - Port73 Function1 */ - PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1), - PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1), - PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1), - PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1), - PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1), - PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1), - PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1), - - /* Port67 - Port73 Function2 */ - PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1), - PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2), - PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2), - PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2), - PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2), - PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1), - PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1), - - /* Port67 - Port73 Function4 */ - PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0), - PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0), - - /* Port67 - Port73 Function6 */ - PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6), - PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6), - PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6), - PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6), - PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6), - PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6), - PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6), - - /* Port67 - Port71 IRQ */ - PINMUX_DATA(IRQ20_MARK, PORT67_FN0), - PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0), - PINMUX_DATA(IRQ17_MARK, PORT69_FN0), - PINMUX_DATA(IRQ18_MARK, PORT70_FN0), - PINMUX_DATA(IRQ19_MARK, PORT71_FN0), - - /* Port74 */ - PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1), - PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1), - PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0), - PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6), - PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7), - - /* Port75 */ - PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1), - PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1), - PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0), - PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6), - PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7), - - /* Port76 - Port80 Function */ - PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1), - PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1), - PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1), - PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1), - PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1), - - /* Port81 */ - PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1), - PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0), - - /* Port82 - Port88 Function */ - PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1), - PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1), - PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1), - PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1), - PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1), - PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1), - PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1), - - /* Port89 */ - PINMUX_DATA(DREQ0_MARK, PORT89_FN1), - PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1), - PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6), - - /* Port90 */ - PINMUX_DATA(DACK0_MARK, PORT90_FN1), - PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1), - PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6), - PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1), - - /* Port91 */ - PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1), - PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2), - PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, - MSEL5CR_14_0), - PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7), - - /* Port92 */ - PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1), - PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2), - PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, - MSEL5CR_14_0), - PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6), - PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7), - - /* Port93 */ - PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1), - PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2), - PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, - MSEL5CR_11_0), - PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6), - PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7), - - /* Port94 */ - PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1), - PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2), - PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, - MSEL5CR_11_0), - PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6), - PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7), - - /* Port95 */ - PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0), - PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1), - - PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2), - PINMUX_DATA(SIM_RST_MARK, PORT95_FN4), - PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1), - PINMUX_DATA(IRQ22_MARK, PORT95_FN0), - - /* Port96 */ - PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0), - PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1), - - PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2), - PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4), - PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1), - PINMUX_DATA(IRQ23_MARK, PORT96_FN0), - - /* Port97 */ - PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1), - PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2), - PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6), - PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7), - PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0), - - /* Port98 */ - PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1), - PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2), - PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7), - PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0), - - /* Port99 */ - PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1), - PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2), - PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6), - PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7), - PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0), - - /* Port100 */ - PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1), - PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2), - PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7), - PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0), - - /* Port101 */ - PINMUX_DATA(FCE0_MARK, PORT101_FN1), - - /* Port102 */ - PINMUX_DATA(FRB_MARK, PORT102_FN1), - PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0), - - /* Port103 */ - PINMUX_DATA(CS5B_MARK, PORT103_FN1), - PINMUX_DATA(FCE1_MARK, PORT103_FN2), - PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1), - - /* Port104 */ - PINMUX_DATA(CS6A_MARK, PORT104_FN1), - PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1), - PINMUX_DATA(IRQ11_MARK, PORT104_FN0), - - /* Port105 */ - PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0), - PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0), - - /* Port106 */ - PINMUX_DATA(IOIS16_MARK, PORT106_FN1), - PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6), - - /* Port107 - Port115 Function */ - PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1), - PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1), - PINMUX_DATA(CS0_MARK, PORT109_FN1), - PINMUX_DATA(CS2_MARK, PORT110_FN1), - PINMUX_DATA(CS4_MARK, PORT111_FN1), - PINMUX_DATA(WE1_MARK, PORT112_FN1), - PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1), - PINMUX_DATA(RDWR_MARK, PORT114_FN1), - PINMUX_DATA(RD_FSC_MARK, PORT115_FN1), - - /* Port116 */ - PINMUX_DATA(A25_MARK, PORT116_FN1), - PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2), - PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0), - PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0), - PINMUX_DATA(GPO1_MARK, PORT116_FN5), - - /* Port117 */ - PINMUX_DATA(A24_MARK, PORT117_FN1), - PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2), - PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0), - PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0), - PINMUX_DATA(GPO0_MARK, PORT117_FN5), - - /* Port118 */ - PINMUX_DATA(A23_MARK, PORT118_FN1), - PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2), - PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0), - PINMUX_DATA(GPI1_MARK, PORT118_FN5), - PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0), - - /* Port119 */ - PINMUX_DATA(A22_MARK, PORT119_FN1), - PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2), - PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0), - PINMUX_DATA(GPI0_MARK, PORT119_FN5), - PINMUX_DATA(IRQ8_MARK, PORT119_FN0), - - /* Port120 */ - PINMUX_DATA(A21_MARK, PORT120_FN1), - PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2), - PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0), - PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_0), - - /* Port121 */ - PINMUX_DATA(A20_MARK, PORT121_FN1), - PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2), - PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0), - PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0), - - /* Port122 */ - PINMUX_DATA(A19_MARK, PORT122_FN1), - PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2), - - /* Port123 */ - PINMUX_DATA(A18_MARK, PORT123_FN1), - PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2), - - /* Port124 */ - PINMUX_DATA(A17_MARK, PORT124_FN1), - PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2), - - /* Port125 - Port141 Function */ - PINMUX_DATA(A16_MARK, PORT125_FN1), - PINMUX_DATA(A15_MARK, PORT126_FN1), - PINMUX_DATA(A14_MARK, PORT127_FN1), - PINMUX_DATA(A13_MARK, PORT128_FN1), - PINMUX_DATA(A12_MARK, PORT129_FN1), - PINMUX_DATA(A11_MARK, PORT130_FN1), - PINMUX_DATA(A10_MARK, PORT131_FN1), - PINMUX_DATA(A9_MARK, PORT132_FN1), - PINMUX_DATA(A8_MARK, PORT133_FN1), - PINMUX_DATA(A7_MARK, PORT134_FN1), - PINMUX_DATA(A6_MARK, PORT135_FN1), - PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1), - PINMUX_DATA(A4_FOE_MARK, PORT137_FN1), - PINMUX_DATA(A3_MARK, PORT138_FN1), - PINMUX_DATA(A2_MARK, PORT139_FN1), - PINMUX_DATA(A1_MARK, PORT140_FN1), - PINMUX_DATA(CKO_MARK, PORT141_FN1), - - /* Port142 - Port157 Function1 */ - PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1), - PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1), - PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1), - PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1), - PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1), - PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1), - PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1), - PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1), - PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1), - PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1), - PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1), - PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1), - PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1), - PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1), - PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1), - PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1), - - /* Port142 - Port149 Function3 */ - PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1), - PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1), - - /* Port158 */ - PINMUX_DATA(D31_MARK, PORT158_FN1), - PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1), - PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3), - PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1), - PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5), - PINMUX_DATA(IDE_D15_MARK, PORT158_FN6), - - /* Port159 */ - PINMUX_DATA(D30_MARK, PORT159_FN1), - PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1), - PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3), - PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1), - PINMUX_DATA(IDE_D14_MARK, PORT159_FN6), - - /* Port160 */ - PINMUX_DATA(D29_MARK, PORT160_FN1), - PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1), - PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1), - PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5), - PINMUX_DATA(IDE_D13_MARK, PORT160_FN6), - - /* Port161 */ - PINMUX_DATA(D28_MARK, PORT161_FN1), - PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1), - PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3), - PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1), - PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5), - PINMUX_DATA(IDE_D12_MARK, PORT161_FN6), - - /* Port162 */ - PINMUX_DATA(D27_MARK, PORT162_FN1), - PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1), - PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1), - PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5), - PINMUX_DATA(IDE_D11_MARK, PORT162_FN6), - - /* Port163 */ - PINMUX_DATA(D26_MARK, PORT163_FN1), - PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2), - PINMUX_DATA(ET_COL_MARK, PORT163_FN3), - PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1), - PINMUX_DATA(IROUT_MARK, PORT163_FN5), - PINMUX_DATA(IDE_D10_MARK, PORT163_FN6), - - /* Port164 */ - PINMUX_DATA(D25_MARK, PORT164_FN1), - PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2), - PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3), - PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4), - PINMUX_DATA(IDE_D9_MARK, PORT164_FN6), - - /* Port165 */ - PINMUX_DATA(D24_MARK, PORT165_FN1), - PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2), - PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1), - PINMUX_DATA(IDE_D8_MARK, PORT165_FN6), - - /* Port166 - Port171 Function1 */ - PINMUX_DATA(D21_MARK, PORT166_FN1), - PINMUX_DATA(D20_MARK, PORT167_FN1), - PINMUX_DATA(D19_MARK, PORT168_FN1), - PINMUX_DATA(D18_MARK, PORT169_FN1), - PINMUX_DATA(D17_MARK, PORT170_FN1), - PINMUX_DATA(D16_MARK, PORT171_FN1), - - /* Port166 - Port171 Function3 */ - PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3), - PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3), - PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3), - PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3), - PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3), - PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3), - - /* Port166 - Port171 Function6 */ - PINMUX_DATA(IDE_D5_MARK, PORT166_FN6), - PINMUX_DATA(IDE_D4_MARK, PORT167_FN6), - PINMUX_DATA(IDE_D3_MARK, PORT168_FN6), - PINMUX_DATA(IDE_D2_MARK, PORT169_FN6), - PINMUX_DATA(IDE_D1_MARK, PORT170_FN6), - PINMUX_DATA(IDE_D0_MARK, PORT171_FN6), - - /* Port167 - Port171 IRQ */ - PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0), - PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0), - PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0), - PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0), - PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0), - - /* Port172 */ - PINMUX_DATA(D23_MARK, PORT172_FN1), - PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1), - PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3), - PINMUX_DATA(IDE_D7_MARK, PORT172_FN6), - PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1), - - /* Port173 */ - PINMUX_DATA(D22_MARK, PORT173_FN1), - PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1), - PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3), - PINMUX_DATA(IDE_D6_MARK, PORT173_FN6), - PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1), - - /* Port174 */ - PINMUX_DATA(A26_MARK, PORT174_FN1), - PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2), - PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3), - PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0), - - /* Port175 */ - PINMUX_DATA(A0_MARK, PORT175_FN1), - PINMUX_DATA(BS_MARK, PORT175_FN2), - PINMUX_DATA(ET_WOL_MARK, PORT175_FN3), - PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0), - - /* Port176 */ - PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3), - - /* Port177 */ - PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0), - PINMUX_DATA(ET_LINK_MARK, PORT177_FN3), - PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6), - PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1), - - /* Port178 */ - PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1), - PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5), - PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6), - - /* Port179 */ - PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1), - PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5), - PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6), - - /* Port180 */ - PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1), - PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4), - PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5), - PINMUX_DATA(IDE_INT_MARK, PORT180_FN6), - PINMUX_DATA(IRQ24_MARK, PORT180_FN0), - - /* Port181 */ - PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1), - PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5), - PINMUX_DATA(IDE_RST_MARK, PORT181_FN6), - - /* Port182 */ - PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1), - PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5), - PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6), - - /* Port183 */ - PINMUX_DATA(DREQ1_MARK, PORT183_FN1), - PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1), - PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3), - - /* Port184 */ - PINMUX_DATA(DACK1_MARK, PORT184_FN1), - PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1), - PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3), - - /* Port185 - Port192 Function1 */ - PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1), - PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0), - PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0), - PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1), - PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0), - PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0), - PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0), - - /* Port185 - Port192 Function3 */ - PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3), - PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3), - PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3), - PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3), - PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3), - PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3), - PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3), - PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3), - - /* Port185 - Port192 Function6 */ - PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6), - PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0), - PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0), - PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6), - PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6), - PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6), - PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6), - PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6), - - /* Port193 */ - PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1), - PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3), - PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), - PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7), - - /* Port194 */ - PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1), - PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3), - PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), - PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7), - - /* Port195 */ - PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1), - PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3), - PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6), - PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7), - - /* Port196 */ - PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1), - PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3), - PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6), - PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7), - - /* Port197 */ - PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1), - PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5), - PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6), - PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7), - - /* Port198 */ - PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1), - PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5), - PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6), - PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7), - - /* Port199 */ - PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1), - PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1), - PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3), - PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1), - PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6), - PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7), - - /* Port200 */ - PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1), - PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2), - PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3), - PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6), - PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7), - - /* Port201 */ - PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0), - PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1), - - PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2), - PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3), - PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6), - PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7), - - /* Port202 */ - PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0), - PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1), - - PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1), - PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3), - PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1), - PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6), - PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1), - PINMUX_DATA(IRQ21_MARK, PORT202_FN0), - - /* Port203 - Port208 Function1 */ - PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1), - PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1), - PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1), - PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1), - PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1), - PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1), - - /* Port203 - Port208 Function3 */ - PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3), - PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3), - PINMUX_DATA(ET_CRS_MARK, PORT205_FN3), - PINMUX_DATA(ET_MDC_MARK, PORT206_FN3), - PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3), - PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3), - - /* Port203 - Port208 Function6 */ - PINMUX_DATA(IDE_A2_MARK, PORT203_FN6), - PINMUX_DATA(IDE_A1_MARK, PORT204_FN6), - PINMUX_DATA(IDE_A0_MARK, PORT205_FN6), - PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6), - PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6), - PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6), - - /* Port203 - Port208 Function7 */ - PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, - MSEL5CR_11_1), - PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, - MSEL5CR_11_1), - PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1), - PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1), - PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, - MSEL5CR_14_1), - PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, - MSEL5CR_14_1), - - /* Port209 */ - PINMUX_DATA(VBUS_MARK, PORT209_FN1), - PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_1), - - /* Port210 */ - PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1), - - /* Port211 */ - PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1), - - /* LCDC select */ - PINMUX_DATA(LCDC0_SELECT_MARK, MSEL3CR_6_0), - PINMUX_DATA(LCDC1_SELECT_MARK, MSEL3CR_6_1), - - /* SDENC */ - PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0), - PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1), - - /* SYSC */ - PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0), - PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1), - - /* DEBUG */ - PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0), - PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1), - - PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0), - PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1), - PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), -}; - -static struct pinmux_gpio pinmux_gpios[] = { - - /* PORT */ - GPIO_PORT_ALL(), - - /* IRQ */ - GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), - GPIO_FN(IRQ1), - GPIO_FN(IRQ2_PORT11), GPIO_FN(IRQ2_PORT12), - GPIO_FN(IRQ3_PORT10), GPIO_FN(IRQ3_PORT14), - GPIO_FN(IRQ4_PORT15), GPIO_FN(IRQ4_PORT172), - GPIO_FN(IRQ5_PORT0), GPIO_FN(IRQ5_PORT1), - GPIO_FN(IRQ6_PORT121), GPIO_FN(IRQ6_PORT173), - GPIO_FN(IRQ7_PORT120), GPIO_FN(IRQ7_PORT209), - GPIO_FN(IRQ8), - GPIO_FN(IRQ9_PORT118), GPIO_FN(IRQ9_PORT210), - GPIO_FN(IRQ10), - GPIO_FN(IRQ11), - GPIO_FN(IRQ12_PORT42), GPIO_FN(IRQ12_PORT97), - GPIO_FN(IRQ13_PORT64), GPIO_FN(IRQ13_PORT98), - GPIO_FN(IRQ14_PORT63), GPIO_FN(IRQ14_PORT99), - GPIO_FN(IRQ15_PORT62), GPIO_FN(IRQ15_PORT100), - GPIO_FN(IRQ16_PORT68), GPIO_FN(IRQ16_PORT211), - GPIO_FN(IRQ17), - GPIO_FN(IRQ18), - GPIO_FN(IRQ19), - GPIO_FN(IRQ20), - GPIO_FN(IRQ21), - GPIO_FN(IRQ22), - GPIO_FN(IRQ23), - GPIO_FN(IRQ24), - GPIO_FN(IRQ25), - GPIO_FN(IRQ26_PORT58), GPIO_FN(IRQ26_PORT81), - GPIO_FN(IRQ27_PORT57), GPIO_FN(IRQ27_PORT168), - GPIO_FN(IRQ28_PORT56), GPIO_FN(IRQ28_PORT169), - GPIO_FN(IRQ29_PORT50), GPIO_FN(IRQ29_PORT170), - GPIO_FN(IRQ30_PORT49), GPIO_FN(IRQ30_PORT171), - GPIO_FN(IRQ31_PORT41), GPIO_FN(IRQ31_PORT167), - - /* Function */ - - /* DBGT */ - GPIO_FN(DBGMDT2), GPIO_FN(DBGMDT1), GPIO_FN(DBGMDT0), - GPIO_FN(DBGMD10), GPIO_FN(DBGMD11), GPIO_FN(DBGMD20), - GPIO_FN(DBGMD21), - - /* FSI */ - GPIO_FN(FSIAISLD_PORT0), /* FSIAISLD Port 0/5 */ - GPIO_FN(FSIAISLD_PORT5), - GPIO_FN(FSIASPDIF_PORT9), /* FSIASPDIF Port 9/18 */ - GPIO_FN(FSIASPDIF_PORT18), - GPIO_FN(FSIAOSLD1), GPIO_FN(FSIAOSLD2), GPIO_FN(FSIAOLR), - GPIO_FN(FSIAOBT), GPIO_FN(FSIAOSLD), GPIO_FN(FSIAOMC), - GPIO_FN(FSIACK), GPIO_FN(FSIAILR), GPIO_FN(FSIAIBT), - - /* FMSI */ - GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */ - GPIO_FN(FMSISLD_PORT6), - GPIO_FN(FMSIILR), GPIO_FN(FMSIIBT), GPIO_FN(FMSIOLR), - GPIO_FN(FMSIOBT), GPIO_FN(FMSICK), GPIO_FN(FMSOILR), - GPIO_FN(FMSOIBT), GPIO_FN(FMSOOLR), GPIO_FN(FMSOOBT), - GPIO_FN(FMSOSLD), GPIO_FN(FMSOCK), - - /* SCIFA0 */ - GPIO_FN(SCIFA0_SCK), GPIO_FN(SCIFA0_CTS), GPIO_FN(SCIFA0_RTS), - GPIO_FN(SCIFA0_RXD), GPIO_FN(SCIFA0_TXD), - - /* SCIFA1 */ - GPIO_FN(SCIFA1_CTS), GPIO_FN(SCIFA1_SCK), - GPIO_FN(SCIFA1_RXD), GPIO_FN(SCIFA1_TXD), GPIO_FN(SCIFA1_RTS), - - /* SCIFA2 */ - GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */ - GPIO_FN(SCIFA2_SCK_PORT199), - GPIO_FN(SCIFA2_RXD), GPIO_FN(SCIFA2_TXD), - GPIO_FN(SCIFA2_CTS), GPIO_FN(SCIFA2_RTS), - - /* SCIFA3 */ - GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */ - GPIO_FN(SCIFA3_SCK_PORT116), - GPIO_FN(SCIFA3_CTS_PORT117), - GPIO_FN(SCIFA3_RXD_PORT174), - GPIO_FN(SCIFA3_TXD_PORT175), - - GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */ - GPIO_FN(SCIFA3_SCK_PORT158), - GPIO_FN(SCIFA3_CTS_PORT162), - GPIO_FN(SCIFA3_RXD_PORT159), - GPIO_FN(SCIFA3_TXD_PORT160), - - /* SCIFA4 */ - GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */ - GPIO_FN(SCIFA4_TXD_PORT13), - - GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */ - GPIO_FN(SCIFA4_TXD_PORT203), - - GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */ - GPIO_FN(SCIFA4_TXD_PORT93), - - GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */ - GPIO_FN(SCIFA4_SCK_PORT205), - - /* SCIFA5 */ - GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */ - GPIO_FN(SCIFA5_RXD_PORT10), - - GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */ - GPIO_FN(SCIFA5_TXD_PORT208), - - GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */ - GPIO_FN(SCIFA5_RXD_PORT92), - - GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */ - GPIO_FN(SCIFA5_SCK_PORT206), - - /* SCIFA6 */ - GPIO_FN(SCIFA6_SCK), GPIO_FN(SCIFA6_RXD), GPIO_FN(SCIFA6_TXD), - - /* SCIFA7 */ - GPIO_FN(SCIFA7_TXD), GPIO_FN(SCIFA7_RXD), - - /* SCIFAB */ - GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */ - GPIO_FN(SCIFB_RXD_PORT191), - GPIO_FN(SCIFB_TXD_PORT192), - GPIO_FN(SCIFB_RTS_PORT186), - GPIO_FN(SCIFB_CTS_PORT187), - - GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */ - GPIO_FN(SCIFB_RXD_PORT3), - GPIO_FN(SCIFB_TXD_PORT4), - GPIO_FN(SCIFB_RTS_PORT172), - GPIO_FN(SCIFB_CTS_PORT173), - - /* LCD0 */ - GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2), - GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5), - GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8), - GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11), - GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14), - GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17), - GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC), - GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN), - GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP), - GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD), - GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS), - - GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162), - GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158), - GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159), - GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */ - - GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4), - GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2), - GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1), - GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */ - - /* LCD1 */ - GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2), - GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5), - GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8), - GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11), - GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14), - GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17), - GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20), - GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23), - GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS), - GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON), - GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN), - GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP), - - /* RSPI */ - GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), - GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), - GPIO_FN(RSPI_MISO_A), - - /* VIO CKO */ - GPIO_FN(VIO_CKO1), - GPIO_FN(VIO_CKO2), - GPIO_FN(VIO_CKO_1), - GPIO_FN(VIO_CKO), - - /* VIO0 */ - GPIO_FN(VIO0_D0), GPIO_FN(VIO0_D1), GPIO_FN(VIO0_D2), - GPIO_FN(VIO0_D3), GPIO_FN(VIO0_D4), GPIO_FN(VIO0_D5), - GPIO_FN(VIO0_D6), GPIO_FN(VIO0_D7), GPIO_FN(VIO0_D8), - GPIO_FN(VIO0_D9), GPIO_FN(VIO0_D10), GPIO_FN(VIO0_D11), - GPIO_FN(VIO0_D12), GPIO_FN(VIO0_VD), GPIO_FN(VIO0_HD), - GPIO_FN(VIO0_CLK), GPIO_FN(VIO0_FIELD), - - GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */ - GPIO_FN(VIO0_D14_PORT25), - GPIO_FN(VIO0_D15_PORT24), - - GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */ - GPIO_FN(VIO0_D14_PORT95), - GPIO_FN(VIO0_D15_PORT96), - - /* VIO1 */ - GPIO_FN(VIO1_D0), GPIO_FN(VIO1_D1), GPIO_FN(VIO1_D2), - GPIO_FN(VIO1_D3), GPIO_FN(VIO1_D4), GPIO_FN(VIO1_D5), - GPIO_FN(VIO1_D6), GPIO_FN(VIO1_D7), GPIO_FN(VIO1_VD), - GPIO_FN(VIO1_HD), GPIO_FN(VIO1_CLK), GPIO_FN(VIO1_FIELD), - - /* TPU0 */ - GPIO_FN(TPU0TO0), GPIO_FN(TPU0TO1), GPIO_FN(TPU0TO3), - GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */ - GPIO_FN(TPU0TO2_PORT202), - - /* SSP1 0 */ - GPIO_FN(STP0_IPD0), GPIO_FN(STP0_IPD1), GPIO_FN(STP0_IPD2), - GPIO_FN(STP0_IPD3), GPIO_FN(STP0_IPD4), GPIO_FN(STP0_IPD5), - GPIO_FN(STP0_IPD6), GPIO_FN(STP0_IPD7), GPIO_FN(STP0_IPEN), - GPIO_FN(STP0_IPCLK), GPIO_FN(STP0_IPSYNC), - - /* SSP1 1 */ - GPIO_FN(STP1_IPD1), GPIO_FN(STP1_IPD2), GPIO_FN(STP1_IPD3), - GPIO_FN(STP1_IPD4), GPIO_FN(STP1_IPD5), GPIO_FN(STP1_IPD6), - GPIO_FN(STP1_IPD7), GPIO_FN(STP1_IPCLK), GPIO_FN(STP1_IPSYNC), - - GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */ - GPIO_FN(STP1_IPEN_PORT187), - - GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */ - GPIO_FN(STP1_IPEN_PORT193), - - /* SIM */ - GPIO_FN(SIM_RST), GPIO_FN(SIM_CLK), - GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ - GPIO_FN(SIM_D_PORT199), - - /* SDHI0 */ - GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2), - GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP), - GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK), - - /* SDHI1 */ - GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2), - GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP), - GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK), - - /* SDHI2 */ - GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2), - GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD), - - GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */ - GPIO_FN(SDHI2_WP_PORT25), - - GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */ - GPIO_FN(SDHI2_CD_PORT202), - - /* MSIOF2 */ - GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), - GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), - GPIO_FN(MSIOF2_MCK1), GPIO_FN(MSIOF2_MCK0), GPIO_FN(MSIOF2_RSYNC), - GPIO_FN(MSIOF2_RSCK), - - /* KEYSC */ - GPIO_FN(KEYIN4), GPIO_FN(KEYIN5), - GPIO_FN(KEYIN6), GPIO_FN(KEYIN7), - GPIO_FN(KEYOUT0), GPIO_FN(KEYOUT1), GPIO_FN(KEYOUT2), - GPIO_FN(KEYOUT3), GPIO_FN(KEYOUT4), GPIO_FN(KEYOUT5), - GPIO_FN(KEYOUT6), GPIO_FN(KEYOUT7), - - GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */ - GPIO_FN(KEYIN1_PORT44), - GPIO_FN(KEYIN2_PORT45), - GPIO_FN(KEYIN3_PORT46), - - GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */ - GPIO_FN(KEYIN1_PORT57), - GPIO_FN(KEYIN2_PORT56), - GPIO_FN(KEYIN3_PORT55), - - /* VOU */ - GPIO_FN(DV_D0), GPIO_FN(DV_D1), GPIO_FN(DV_D2), - GPIO_FN(DV_D3), GPIO_FN(DV_D4), GPIO_FN(DV_D5), - GPIO_FN(DV_D6), GPIO_FN(DV_D7), GPIO_FN(DV_D8), - GPIO_FN(DV_D9), GPIO_FN(DV_D10), GPIO_FN(DV_D11), - GPIO_FN(DV_D12), GPIO_FN(DV_D13), GPIO_FN(DV_D14), - GPIO_FN(DV_D15), GPIO_FN(DV_CLK), - GPIO_FN(DV_VSYNC), GPIO_FN(DV_HSYNC), - - /* MEMC */ - GPIO_FN(MEMC_AD0), GPIO_FN(MEMC_AD1), GPIO_FN(MEMC_AD2), - GPIO_FN(MEMC_AD3), GPIO_FN(MEMC_AD4), GPIO_FN(MEMC_AD5), - GPIO_FN(MEMC_AD6), GPIO_FN(MEMC_AD7), GPIO_FN(MEMC_AD8), - GPIO_FN(MEMC_AD9), GPIO_FN(MEMC_AD10), GPIO_FN(MEMC_AD11), - GPIO_FN(MEMC_AD12), GPIO_FN(MEMC_AD13), GPIO_FN(MEMC_AD14), - GPIO_FN(MEMC_AD15), GPIO_FN(MEMC_CS0), GPIO_FN(MEMC_INT), - GPIO_FN(MEMC_NWE), GPIO_FN(MEMC_NOE), GPIO_FN(MEMC_CS1), - GPIO_FN(MEMC_A1), GPIO_FN(MEMC_ADV), GPIO_FN(MEMC_DREQ0), - GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), - GPIO_FN(MEMC_A0), - - /* MMC */ - GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69), - GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71), - GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73), - GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75), - GPIO_FN(MMC0_CLK_PORT66), - GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */ - - GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148), - GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146), - GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144), - GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142), - GPIO_FN(MMC1_CLK_PORT103), - GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */ - - /* MSIOF0 */ - GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), - GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), - GPIO_FN(MSIOF0_RSYNC), GPIO_FN(MSIOF0_RSCK), GPIO_FN(MSIOF0_TSCK), - GPIO_FN(MSIOF0_TSYNC), - - /* MSIOF1 */ - GPIO_FN(MSIOF1_RSCK), GPIO_FN(MSIOF1_RSYNC), - GPIO_FN(MSIOF1_MCK0), GPIO_FN(MSIOF1_MCK1), - - GPIO_FN(MSIOF1_SS2_PORT116), GPIO_FN(MSIOF1_SS1_PORT117), - GPIO_FN(MSIOF1_RXD_PORT118), GPIO_FN(MSIOF1_TXD_PORT119), - GPIO_FN(MSIOF1_TSYNC_PORT120), - GPIO_FN(MSIOF1_TSCK_PORT121), /* MSEL4CR_10_0 */ - - GPIO_FN(MSIOF1_SS1_PORT67), GPIO_FN(MSIOF1_TSCK_PORT72), - GPIO_FN(MSIOF1_TSYNC_PORT73), GPIO_FN(MSIOF1_TXD_PORT74), - GPIO_FN(MSIOF1_RXD_PORT75), - GPIO_FN(MSIOF1_SS2_PORT202), /* MSEL4CR_10_1 */ - - /* GPIO */ - GPIO_FN(GPO0), GPIO_FN(GPI0), - GPIO_FN(GPO1), GPIO_FN(GPI1), - - /* USB0 */ - GPIO_FN(USB0_OCI), GPIO_FN(USB0_PPON), GPIO_FN(VBUS), - - /* USB1 */ - GPIO_FN(USB1_OCI), GPIO_FN(USB1_PPON), - - /* BBIF1 */ - GPIO_FN(BBIF1_RXD), GPIO_FN(BBIF1_TXD), GPIO_FN(BBIF1_TSYNC), - GPIO_FN(BBIF1_TSCK), GPIO_FN(BBIF1_RSCK), GPIO_FN(BBIF1_RSYNC), - GPIO_FN(BBIF1_FLOW), GPIO_FN(BBIF1_RX_FLOW_N), - - /* BBIF2 */ - GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */ - GPIO_FN(BBIF2_RXD2_PORT60), - GPIO_FN(BBIF2_TSYNC2_PORT6), - GPIO_FN(BBIF2_TSCK2_PORT59), - - GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */ - GPIO_FN(BBIF2_TXD2_PORT183), - GPIO_FN(BBIF2_TSCK2_PORT89), - GPIO_FN(BBIF2_TSYNC2_PORT184), - - /* BSC / FLCTL / PCMCIA */ - GPIO_FN(CS0), GPIO_FN(CS2), GPIO_FN(CS4), - GPIO_FN(CS5B), GPIO_FN(CS6A), - GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */ - GPIO_FN(CS5A_PORT19), - GPIO_FN(IOIS16), /* ? */ - - GPIO_FN(A0), GPIO_FN(A1), GPIO_FN(A2), GPIO_FN(A3), - GPIO_FN(A4_FOE), GPIO_FN(A5_FCDE), /* share with FLCTL */ - GPIO_FN(A6), GPIO_FN(A7), GPIO_FN(A8), GPIO_FN(A9), - GPIO_FN(A10), GPIO_FN(A11), GPIO_FN(A12), GPIO_FN(A13), - GPIO_FN(A14), GPIO_FN(A15), GPIO_FN(A16), GPIO_FN(A17), - GPIO_FN(A18), GPIO_FN(A19), GPIO_FN(A20), GPIO_FN(A21), - GPIO_FN(A22), GPIO_FN(A23), GPIO_FN(A24), GPIO_FN(A25), - GPIO_FN(A26), - - GPIO_FN(D0_NAF0), GPIO_FN(D1_NAF1), /* share with FLCTL */ - GPIO_FN(D2_NAF2), GPIO_FN(D3_NAF3), /* share with FLCTL */ - GPIO_FN(D4_NAF4), GPIO_FN(D5_NAF5), /* share with FLCTL */ - GPIO_FN(D6_NAF6), GPIO_FN(D7_NAF7), /* share with FLCTL */ - GPIO_FN(D8_NAF8), GPIO_FN(D9_NAF9), /* share with FLCTL */ - GPIO_FN(D10_NAF10), GPIO_FN(D11_NAF11), /* share with FLCTL */ - GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), /* share with FLCTL */ - GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), /* share with FLCTL */ - GPIO_FN(D16), GPIO_FN(D17), GPIO_FN(D18), GPIO_FN(D19), - GPIO_FN(D20), GPIO_FN(D21), GPIO_FN(D22), GPIO_FN(D23), - GPIO_FN(D24), GPIO_FN(D25), GPIO_FN(D26), GPIO_FN(D27), - GPIO_FN(D28), GPIO_FN(D29), GPIO_FN(D30), GPIO_FN(D31), - - GPIO_FN(WE0_FWE), /* share with FLCTL */ - GPIO_FN(WE1), - GPIO_FN(WE2_ICIORD), /* share with PCMCIA */ - GPIO_FN(WE3_ICIOWR), /* share with PCMCIA */ - GPIO_FN(CKO), GPIO_FN(BS), GPIO_FN(RDWR), - GPIO_FN(RD_FSC), /* share with FLCTL */ - GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */ - GPIO_FN(WAIT_PORT90), - - GPIO_FN(FCE0), GPIO_FN(FCE1), GPIO_FN(FRB), /* FLCTL */ - - /* IRDA */ - GPIO_FN(IRDA_FIRSEL), GPIO_FN(IRDA_IN), GPIO_FN(IRDA_OUT), - - /* ATAPI */ - GPIO_FN(IDE_D0), GPIO_FN(IDE_D1), GPIO_FN(IDE_D2), - GPIO_FN(IDE_D3), GPIO_FN(IDE_D4), GPIO_FN(IDE_D5), - GPIO_FN(IDE_D6), GPIO_FN(IDE_D7), GPIO_FN(IDE_D8), - GPIO_FN(IDE_D9), GPIO_FN(IDE_D10), GPIO_FN(IDE_D11), - GPIO_FN(IDE_D12), GPIO_FN(IDE_D13), GPIO_FN(IDE_D14), - GPIO_FN(IDE_D15), GPIO_FN(IDE_A0), GPIO_FN(IDE_A1), - GPIO_FN(IDE_A2), GPIO_FN(IDE_CS0), GPIO_FN(IDE_CS1), - GPIO_FN(IDE_IOWR), GPIO_FN(IDE_IORD), GPIO_FN(IDE_IORDY), - GPIO_FN(IDE_INT), GPIO_FN(IDE_RST), GPIO_FN(IDE_DIRECTION), - GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK), GPIO_FN(IDE_IODREQ), - - /* RMII */ - GPIO_FN(RMII_CRS_DV), GPIO_FN(RMII_RX_ER), GPIO_FN(RMII_RXD0), - GPIO_FN(RMII_RXD1), GPIO_FN(RMII_TX_EN), GPIO_FN(RMII_TXD0), - GPIO_FN(RMII_MDC), GPIO_FN(RMII_TXD1), GPIO_FN(RMII_MDIO), - GPIO_FN(RMII_REF50CK), GPIO_FN(RMII_REF125CK), /* for GMII */ - - /* GEther */ - GPIO_FN(ET_TX_CLK), GPIO_FN(ET_TX_EN), GPIO_FN(ET_ETXD0), - GPIO_FN(ET_ETXD1), GPIO_FN(ET_ETXD2), GPIO_FN(ET_ETXD3), - GPIO_FN(ET_ETXD4), GPIO_FN(ET_ETXD5), /* for GEther */ - GPIO_FN(ET_ETXD6), GPIO_FN(ET_ETXD7), /* for GEther */ - GPIO_FN(ET_COL), GPIO_FN(ET_TX_ER), GPIO_FN(ET_RX_CLK), - GPIO_FN(ET_RX_DV), GPIO_FN(ET_ERXD0), GPIO_FN(ET_ERXD1), - GPIO_FN(ET_ERXD2), GPIO_FN(ET_ERXD3), - GPIO_FN(ET_ERXD4), GPIO_FN(ET_ERXD5), /* for GEther */ - GPIO_FN(ET_ERXD6), GPIO_FN(ET_ERXD7), /* for GEther */ - GPIO_FN(ET_RX_ER), GPIO_FN(ET_CRS), GPIO_FN(ET_MDC), - GPIO_FN(ET_MDIO), GPIO_FN(ET_LINK), GPIO_FN(ET_PHY_INT), - GPIO_FN(ET_WOL), GPIO_FN(ET_GTX_CLK), - - /* DMA0 */ - GPIO_FN(DREQ0), GPIO_FN(DACK0), - - /* DMA1 */ - GPIO_FN(DREQ1), GPIO_FN(DACK1), - - /* SYSC */ - GPIO_FN(RESETOUTS), - - /* IRREM */ - GPIO_FN(IROUT), - - /* LCDC */ - GPIO_FN(LCDC0_SELECT), - GPIO_FN(LCDC1_SELECT), - - /* SDENC */ - GPIO_FN(SDENC_CPG), - GPIO_FN(SDENC_DV_CLKI), - - /* SYSC */ - GPIO_FN(RESETP_PULLUP), - GPIO_FN(RESETP_PLAIN), - - /* DEBUG */ - GPIO_FN(EDEBGREQ_PULLDOWN), - GPIO_FN(EDEBGREQ_PULLUP), - - GPIO_FN(TRACEAUD_FROM_VIO), - GPIO_FN(TRACEAUD_FROM_LCDC0), - GPIO_FN(TRACEAUD_FROM_MEMC), -}; - -static struct pinmux_cfg_reg pinmux_config_regs[] = { - PORTCR(0, 0xe6050000), /* PORT0CR */ - PORTCR(1, 0xe6050001), /* PORT1CR */ - PORTCR(2, 0xe6050002), /* PORT2CR */ - PORTCR(3, 0xe6050003), /* PORT3CR */ - PORTCR(4, 0xe6050004), /* PORT4CR */ - PORTCR(5, 0xe6050005), /* PORT5CR */ - PORTCR(6, 0xe6050006), /* PORT6CR */ - PORTCR(7, 0xe6050007), /* PORT7CR */ - PORTCR(8, 0xe6050008), /* PORT8CR */ - PORTCR(9, 0xe6050009), /* PORT9CR */ - PORTCR(10, 0xe605000a), /* PORT10CR */ - PORTCR(11, 0xe605000b), /* PORT11CR */ - PORTCR(12, 0xe605000c), /* PORT12CR */ - PORTCR(13, 0xe605000d), /* PORT13CR */ - PORTCR(14, 0xe605000e), /* PORT14CR */ - PORTCR(15, 0xe605000f), /* PORT15CR */ - PORTCR(16, 0xe6050010), /* PORT16CR */ - PORTCR(17, 0xe6050011), /* PORT17CR */ - PORTCR(18, 0xe6050012), /* PORT18CR */ - PORTCR(19, 0xe6050013), /* PORT19CR */ - PORTCR(20, 0xe6050014), /* PORT20CR */ - PORTCR(21, 0xe6050015), /* PORT21CR */ - PORTCR(22, 0xe6050016), /* PORT22CR */ - PORTCR(23, 0xe6050017), /* PORT23CR */ - PORTCR(24, 0xe6050018), /* PORT24CR */ - PORTCR(25, 0xe6050019), /* PORT25CR */ - PORTCR(26, 0xe605001a), /* PORT26CR */ - PORTCR(27, 0xe605001b), /* PORT27CR */ - PORTCR(28, 0xe605001c), /* PORT28CR */ - PORTCR(29, 0xe605001d), /* PORT29CR */ - PORTCR(30, 0xe605001e), /* PORT30CR */ - PORTCR(31, 0xe605001f), /* PORT31CR */ - PORTCR(32, 0xe6050020), /* PORT32CR */ - PORTCR(33, 0xe6050021), /* PORT33CR */ - PORTCR(34, 0xe6050022), /* PORT34CR */ - PORTCR(35, 0xe6050023), /* PORT35CR */ - PORTCR(36, 0xe6050024), /* PORT36CR */ - PORTCR(37, 0xe6050025), /* PORT37CR */ - PORTCR(38, 0xe6050026), /* PORT38CR */ - PORTCR(39, 0xe6050027), /* PORT39CR */ - PORTCR(40, 0xe6050028), /* PORT40CR */ - PORTCR(41, 0xe6050029), /* PORT41CR */ - PORTCR(42, 0xe605002a), /* PORT42CR */ - PORTCR(43, 0xe605002b), /* PORT43CR */ - PORTCR(44, 0xe605002c), /* PORT44CR */ - PORTCR(45, 0xe605002d), /* PORT45CR */ - PORTCR(46, 0xe605002e), /* PORT46CR */ - PORTCR(47, 0xe605002f), /* PORT47CR */ - PORTCR(48, 0xe6050030), /* PORT48CR */ - PORTCR(49, 0xe6050031), /* PORT49CR */ - PORTCR(50, 0xe6050032), /* PORT50CR */ - PORTCR(51, 0xe6050033), /* PORT51CR */ - PORTCR(52, 0xe6050034), /* PORT52CR */ - PORTCR(53, 0xe6050035), /* PORT53CR */ - PORTCR(54, 0xe6050036), /* PORT54CR */ - PORTCR(55, 0xe6050037), /* PORT55CR */ - PORTCR(56, 0xe6050038), /* PORT56CR */ - PORTCR(57, 0xe6050039), /* PORT57CR */ - PORTCR(58, 0xe605003a), /* PORT58CR */ - PORTCR(59, 0xe605003b), /* PORT59CR */ - PORTCR(60, 0xe605003c), /* PORT60CR */ - PORTCR(61, 0xe605003d), /* PORT61CR */ - PORTCR(62, 0xe605003e), /* PORT62CR */ - PORTCR(63, 0xe605003f), /* PORT63CR */ - PORTCR(64, 0xe6050040), /* PORT64CR */ - PORTCR(65, 0xe6050041), /* PORT65CR */ - PORTCR(66, 0xe6050042), /* PORT66CR */ - PORTCR(67, 0xe6050043), /* PORT67CR */ - PORTCR(68, 0xe6050044), /* PORT68CR */ - PORTCR(69, 0xe6050045), /* PORT69CR */ - PORTCR(70, 0xe6050046), /* PORT70CR */ - PORTCR(71, 0xe6050047), /* PORT71CR */ - PORTCR(72, 0xe6050048), /* PORT72CR */ - PORTCR(73, 0xe6050049), /* PORT73CR */ - PORTCR(74, 0xe605004a), /* PORT74CR */ - PORTCR(75, 0xe605004b), /* PORT75CR */ - PORTCR(76, 0xe605004c), /* PORT76CR */ - PORTCR(77, 0xe605004d), /* PORT77CR */ - PORTCR(78, 0xe605004e), /* PORT78CR */ - PORTCR(79, 0xe605004f), /* PORT79CR */ - PORTCR(80, 0xe6050050), /* PORT80CR */ - PORTCR(81, 0xe6050051), /* PORT81CR */ - PORTCR(82, 0xe6050052), /* PORT82CR */ - PORTCR(83, 0xe6050053), /* PORT83CR */ - - PORTCR(84, 0xe6051054), /* PORT84CR */ - PORTCR(85, 0xe6051055), /* PORT85CR */ - PORTCR(86, 0xe6051056), /* PORT86CR */ - PORTCR(87, 0xe6051057), /* PORT87CR */ - PORTCR(88, 0xe6051058), /* PORT88CR */ - PORTCR(89, 0xe6051059), /* PORT89CR */ - PORTCR(90, 0xe605105a), /* PORT90CR */ - PORTCR(91, 0xe605105b), /* PORT91CR */ - PORTCR(92, 0xe605105c), /* PORT92CR */ - PORTCR(93, 0xe605105d), /* PORT93CR */ - PORTCR(94, 0xe605105e), /* PORT94CR */ - PORTCR(95, 0xe605105f), /* PORT95CR */ - PORTCR(96, 0xe6051060), /* PORT96CR */ - PORTCR(97, 0xe6051061), /* PORT97CR */ - PORTCR(98, 0xe6051062), /* PORT98CR */ - PORTCR(99, 0xe6051063), /* PORT99CR */ - PORTCR(100, 0xe6051064), /* PORT100CR */ - PORTCR(101, 0xe6051065), /* PORT101CR */ - PORTCR(102, 0xe6051066), /* PORT102CR */ - PORTCR(103, 0xe6051067), /* PORT103CR */ - PORTCR(104, 0xe6051068), /* PORT104CR */ - PORTCR(105, 0xe6051069), /* PORT105CR */ - PORTCR(106, 0xe605106a), /* PORT106CR */ - PORTCR(107, 0xe605106b), /* PORT107CR */ - PORTCR(108, 0xe605106c), /* PORT108CR */ - PORTCR(109, 0xe605106d), /* PORT109CR */ - PORTCR(110, 0xe605106e), /* PORT110CR */ - PORTCR(111, 0xe605106f), /* PORT111CR */ - PORTCR(112, 0xe6051070), /* PORT112CR */ - PORTCR(113, 0xe6051071), /* PORT113CR */ - PORTCR(114, 0xe6051072), /* PORT114CR */ - - PORTCR(115, 0xe6052073), /* PORT115CR */ - PORTCR(116, 0xe6052074), /* PORT116CR */ - PORTCR(117, 0xe6052075), /* PORT117CR */ - PORTCR(118, 0xe6052076), /* PORT118CR */ - PORTCR(119, 0xe6052077), /* PORT119CR */ - PORTCR(120, 0xe6052078), /* PORT120CR */ - PORTCR(121, 0xe6052079), /* PORT121CR */ - PORTCR(122, 0xe605207a), /* PORT122CR */ - PORTCR(123, 0xe605207b), /* PORT123CR */ - PORTCR(124, 0xe605207c), /* PORT124CR */ - PORTCR(125, 0xe605207d), /* PORT125CR */ - PORTCR(126, 0xe605207e), /* PORT126CR */ - PORTCR(127, 0xe605207f), /* PORT127CR */ - PORTCR(128, 0xe6052080), /* PORT128CR */ - PORTCR(129, 0xe6052081), /* PORT129CR */ - PORTCR(130, 0xe6052082), /* PORT130CR */ - PORTCR(131, 0xe6052083), /* PORT131CR */ - PORTCR(132, 0xe6052084), /* PORT132CR */ - PORTCR(133, 0xe6052085), /* PORT133CR */ - PORTCR(134, 0xe6052086), /* PORT134CR */ - PORTCR(135, 0xe6052087), /* PORT135CR */ - PORTCR(136, 0xe6052088), /* PORT136CR */ - PORTCR(137, 0xe6052089), /* PORT137CR */ - PORTCR(138, 0xe605208a), /* PORT138CR */ - PORTCR(139, 0xe605208b), /* PORT139CR */ - PORTCR(140, 0xe605208c), /* PORT140CR */ - PORTCR(141, 0xe605208d), /* PORT141CR */ - PORTCR(142, 0xe605208e), /* PORT142CR */ - PORTCR(143, 0xe605208f), /* PORT143CR */ - PORTCR(144, 0xe6052090), /* PORT144CR */ - PORTCR(145, 0xe6052091), /* PORT145CR */ - PORTCR(146, 0xe6052092), /* PORT146CR */ - PORTCR(147, 0xe6052093), /* PORT147CR */ - PORTCR(148, 0xe6052094), /* PORT148CR */ - PORTCR(149, 0xe6052095), /* PORT149CR */ - PORTCR(150, 0xe6052096), /* PORT150CR */ - PORTCR(151, 0xe6052097), /* PORT151CR */ - PORTCR(152, 0xe6052098), /* PORT152CR */ - PORTCR(153, 0xe6052099), /* PORT153CR */ - PORTCR(154, 0xe605209a), /* PORT154CR */ - PORTCR(155, 0xe605209b), /* PORT155CR */ - PORTCR(156, 0xe605209c), /* PORT156CR */ - PORTCR(157, 0xe605209d), /* PORT157CR */ - PORTCR(158, 0xe605209e), /* PORT158CR */ - PORTCR(159, 0xe605209f), /* PORT159CR */ - PORTCR(160, 0xe60520a0), /* PORT160CR */ - PORTCR(161, 0xe60520a1), /* PORT161CR */ - PORTCR(162, 0xe60520a2), /* PORT162CR */ - PORTCR(163, 0xe60520a3), /* PORT163CR */ - PORTCR(164, 0xe60520a4), /* PORT164CR */ - PORTCR(165, 0xe60520a5), /* PORT165CR */ - PORTCR(166, 0xe60520a6), /* PORT166CR */ - PORTCR(167, 0xe60520a7), /* PORT167CR */ - PORTCR(168, 0xe60520a8), /* PORT168CR */ - PORTCR(169, 0xe60520a9), /* PORT169CR */ - PORTCR(170, 0xe60520aa), /* PORT170CR */ - PORTCR(171, 0xe60520ab), /* PORT171CR */ - PORTCR(172, 0xe60520ac), /* PORT172CR */ - PORTCR(173, 0xe60520ad), /* PORT173CR */ - PORTCR(174, 0xe60520ae), /* PORT174CR */ - PORTCR(175, 0xe60520af), /* PORT175CR */ - PORTCR(176, 0xe60520b0), /* PORT176CR */ - PORTCR(177, 0xe60520b1), /* PORT177CR */ - PORTCR(178, 0xe60520b2), /* PORT178CR */ - PORTCR(179, 0xe60520b3), /* PORT179CR */ - PORTCR(180, 0xe60520b4), /* PORT180CR */ - PORTCR(181, 0xe60520b5), /* PORT181CR */ - PORTCR(182, 0xe60520b6), /* PORT182CR */ - PORTCR(183, 0xe60520b7), /* PORT183CR */ - PORTCR(184, 0xe60520b8), /* PORT184CR */ - PORTCR(185, 0xe60520b9), /* PORT185CR */ - PORTCR(186, 0xe60520ba), /* PORT186CR */ - PORTCR(187, 0xe60520bb), /* PORT187CR */ - PORTCR(188, 0xe60520bc), /* PORT188CR */ - PORTCR(189, 0xe60520bd), /* PORT189CR */ - PORTCR(190, 0xe60520be), /* PORT190CR */ - PORTCR(191, 0xe60520bf), /* PORT191CR */ - PORTCR(192, 0xe60520c0), /* PORT192CR */ - PORTCR(193, 0xe60520c1), /* PORT193CR */ - PORTCR(194, 0xe60520c2), /* PORT194CR */ - PORTCR(195, 0xe60520c3), /* PORT195CR */ - PORTCR(196, 0xe60520c4), /* PORT196CR */ - PORTCR(197, 0xe60520c5), /* PORT197CR */ - PORTCR(198, 0xe60520c6), /* PORT198CR */ - PORTCR(199, 0xe60520c7), /* PORT199CR */ - PORTCR(200, 0xe60520c8), /* PORT200CR */ - PORTCR(201, 0xe60520c9), /* PORT201CR */ - PORTCR(202, 0xe60520ca), /* PORT202CR */ - PORTCR(203, 0xe60520cb), /* PORT203CR */ - PORTCR(204, 0xe60520cc), /* PORT204CR */ - PORTCR(205, 0xe60520cd), /* PORT205CR */ - PORTCR(206, 0xe60520ce), /* PORT206CR */ - PORTCR(207, 0xe60520cf), /* PORT207CR */ - PORTCR(208, 0xe60520d0), /* PORT208CR */ - PORTCR(209, 0xe60520d1), /* PORT209CR */ - - PORTCR(210, 0xe60530d2), /* PORT210CR */ - PORTCR(211, 0xe60530d3), /* PORT211CR */ - - { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) { - MSEL1CR_31_0, MSEL1CR_31_1, - MSEL1CR_30_0, MSEL1CR_30_1, - MSEL1CR_29_0, MSEL1CR_29_1, - MSEL1CR_28_0, MSEL1CR_28_1, - MSEL1CR_27_0, MSEL1CR_27_1, - MSEL1CR_26_0, MSEL1CR_26_1, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - MSEL1CR_16_0, MSEL1CR_16_1, - MSEL1CR_15_0, MSEL1CR_15_1, - MSEL1CR_14_0, MSEL1CR_14_1, - MSEL1CR_13_0, MSEL1CR_13_1, - MSEL1CR_12_0, MSEL1CR_12_1, - 0, 0, 0, 0, - MSEL1CR_9_0, MSEL1CR_9_1, - 0, 0, - MSEL1CR_7_0, MSEL1CR_7_1, - MSEL1CR_6_0, MSEL1CR_6_1, - MSEL1CR_5_0, MSEL1CR_5_1, - MSEL1CR_4_0, MSEL1CR_4_1, - MSEL1CR_3_0, MSEL1CR_3_1, - MSEL1CR_2_0, MSEL1CR_2_1, - 0, 0, - MSEL1CR_0_0, MSEL1CR_0_1, - } - }, - { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - MSEL3CR_15_0, MSEL3CR_15_1, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - MSEL3CR_6_0, MSEL3CR_6_1, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, - } - }, - { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) { - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, - MSEL4CR_19_0, MSEL4CR_19_1, - MSEL4CR_18_0, MSEL4CR_18_1, - 0, 0, 0, 0, - MSEL4CR_15_0, MSEL4CR_15_1, - 0, 0, 0, 0, 0, 0, 0, 0, - MSEL4CR_10_0, MSEL4CR_10_1, - 0, 0, 0, 0, 0, 0, - MSEL4CR_6_0, MSEL4CR_6_1, - 0, 0, - MSEL4CR_4_0, MSEL4CR_4_1, - 0, 0, 0, 0, - MSEL4CR_1_0, MSEL4CR_1_1, - 0, 0, - } - }, - { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) { - MSEL5CR_31_0, MSEL5CR_31_1, - MSEL5CR_30_0, MSEL5CR_30_1, - MSEL5CR_29_0, MSEL5CR_29_1, - 0, 0, - MSEL5CR_27_0, MSEL5CR_27_1, - 0, 0, - MSEL5CR_25_0, MSEL5CR_25_1, - 0, 0, - MSEL5CR_23_0, MSEL5CR_23_1, - 0, 0, - MSEL5CR_21_0, MSEL5CR_21_1, - 0, 0, - MSEL5CR_19_0, MSEL5CR_19_1, - 0, 0, - MSEL5CR_17_0, MSEL5CR_17_1, - 0, 0, - MSEL5CR_15_0, MSEL5CR_15_1, - MSEL5CR_14_0, MSEL5CR_14_1, - MSEL5CR_13_0, MSEL5CR_13_1, - MSEL5CR_12_0, MSEL5CR_12_1, - MSEL5CR_11_0, MSEL5CR_11_1, - MSEL5CR_10_0, MSEL5CR_10_1, - 0, 0, - MSEL5CR_8_0, MSEL5CR_8_1, - MSEL5CR_7_0, MSEL5CR_7_1, - MSEL5CR_6_0, MSEL5CR_6_1, - MSEL5CR_5_0, MSEL5CR_5_1, - MSEL5CR_4_0, MSEL5CR_4_1, - MSEL5CR_3_0, MSEL5CR_3_1, - MSEL5CR_2_0, MSEL5CR_2_1, - 0, 0, - MSEL5CR_0_0, MSEL5CR_0_1, - } - }, - { }, -}; - -static struct pinmux_data_reg pinmux_data_regs[] = { - { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) { - PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, - PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, - PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA, - PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA, - PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA, - PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA, - PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA, - PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA } - }, - { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) { - PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA, - PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA, - PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA, - PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA, - PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA, - PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA, - PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA, - PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA } - }, - { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA, - PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA, - PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA, - PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA, - PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA } - }, - { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) { - PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, - PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, - PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 } - }, - { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, PORT114_DATA, PORT113_DATA, PORT112_DATA, - PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA, - PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA, - PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA, - PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA } - }, - { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) { - PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA, - PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA, - PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA, - PORT115_DATA, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 } - }, - { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) { - PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA, - PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA, - PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA, - PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA, - PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA, - PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA, - PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA, - PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA } - }, - { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) { - PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA, - PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA, - PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA, - PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA, - PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA, - PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA, - PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA, - PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA } - }, - { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, PORT209_DATA, PORT208_DATA, - PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA, - PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA, - PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA, - PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA } - }, - { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) { - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - PORT211_DATA, PORT210_DATA, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0, - 0, 0, 0, 0 } - }, - { }, -}; - -static struct pinmux_irq pinmux_irqs[] = { - PINMUX_IRQ(evt2irq(0x0200), PORT2_FN0, PORT13_FN0), /* IRQ0A */ - PINMUX_IRQ(evt2irq(0x0220), PORT20_FN0), /* IRQ1A */ - PINMUX_IRQ(evt2irq(0x0240), PORT11_FN0, PORT12_FN0), /* IRQ2A */ - PINMUX_IRQ(evt2irq(0x0260), PORT10_FN0, PORT14_FN0), /* IRQ3A */ - PINMUX_IRQ(evt2irq(0x0280), PORT15_FN0, PORT172_FN0), /* IRQ4A */ - PINMUX_IRQ(evt2irq(0x02A0), PORT0_FN0, PORT1_FN0), /* IRQ5A */ - PINMUX_IRQ(evt2irq(0x02C0), PORT121_FN0, PORT173_FN0), /* IRQ6A */ - PINMUX_IRQ(evt2irq(0x02E0), PORT120_FN0, PORT209_FN0), /* IRQ7A */ - PINMUX_IRQ(evt2irq(0x0300), PORT119_FN0), /* IRQ8A */ - PINMUX_IRQ(evt2irq(0x0320), PORT118_FN0, PORT210_FN0), /* IRQ9A */ - PINMUX_IRQ(evt2irq(0x0340), PORT19_FN0), /* IRQ10A */ - PINMUX_IRQ(evt2irq(0x0360), PORT104_FN0), /* IRQ11A */ - PINMUX_IRQ(evt2irq(0x0380), PORT42_FN0, PORT97_FN0), /* IRQ12A */ - PINMUX_IRQ(evt2irq(0x03A0), PORT64_FN0, PORT98_FN0), /* IRQ13A */ - PINMUX_IRQ(evt2irq(0x03C0), PORT63_FN0, PORT99_FN0), /* IRQ14A */ - PINMUX_IRQ(evt2irq(0x03E0), PORT62_FN0, PORT100_FN0), /* IRQ15A */ - PINMUX_IRQ(evt2irq(0x3200), PORT68_FN0, PORT211_FN0), /* IRQ16A */ - PINMUX_IRQ(evt2irq(0x3220), PORT69_FN0), /* IRQ17A */ - PINMUX_IRQ(evt2irq(0x3240), PORT70_FN0), /* IRQ18A */ - PINMUX_IRQ(evt2irq(0x3260), PORT71_FN0), /* IRQ19A */ - PINMUX_IRQ(evt2irq(0x3280), PORT67_FN0), /* IRQ20A */ - PINMUX_IRQ(evt2irq(0x32A0), PORT202_FN0), /* IRQ21A */ - PINMUX_IRQ(evt2irq(0x32C0), PORT95_FN0), /* IRQ22A */ - PINMUX_IRQ(evt2irq(0x32E0), PORT96_FN0), /* IRQ23A */ - PINMUX_IRQ(evt2irq(0x3300), PORT180_FN0), /* IRQ24A */ - PINMUX_IRQ(evt2irq(0x3320), PORT38_FN0), /* IRQ25A */ - PINMUX_IRQ(evt2irq(0x3340), PORT58_FN0, PORT81_FN0), /* IRQ26A */ - PINMUX_IRQ(evt2irq(0x3360), PORT57_FN0, PORT168_FN0), /* IRQ27A */ - PINMUX_IRQ(evt2irq(0x3380), PORT56_FN0, PORT169_FN0), /* IRQ28A */ - PINMUX_IRQ(evt2irq(0x33A0), PORT50_FN0, PORT170_FN0), /* IRQ29A */ - PINMUX_IRQ(evt2irq(0x33C0), PORT49_FN0, PORT171_FN0), /* IRQ30A */ - PINMUX_IRQ(evt2irq(0x33E0), PORT41_FN0, PORT167_FN0), /* IRQ31A */ -}; - -static struct pinmux_info r8a7740_pinmux_info = { - .name = "r8a7740_pfc", - .reserved_id = PINMUX_RESERVED, - .data = { PINMUX_DATA_BEGIN, - PINMUX_DATA_END }, - .input = { PINMUX_INPUT_BEGIN, - PINMUX_INPUT_END }, - .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, - PINMUX_INPUT_PULLUP_END }, - .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, - PINMUX_INPUT_PULLDOWN_END }, - .output = { PINMUX_OUTPUT_BEGIN, - PINMUX_OUTPUT_END }, - .mark = { PINMUX_MARK_BEGIN, - PINMUX_MARK_END }, - .function = { PINMUX_FUNCTION_BEGIN, - PINMUX_FUNCTION_END }, - - .first_gpio = GPIO_PORT0, - .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC, - - .gpios = pinmux_gpios, - .cfg_regs = pinmux_config_regs, - .data_regs = pinmux_data_regs, - - .gpio_data = pinmux_data, - .gpio_data_size = ARRAY_SIZE(pinmux_data), - - .gpio_irq = pinmux_irqs, - .gpio_irq_size = ARRAY_SIZE(pinmux_irqs), -}; - -void r8a7740_pinmux_init(void) -{ - register_pinmux(&r8a7740_pinmux_info); -} diff --git a/arch/arm/mach-rmobile/pfc-r8a7790.h b/arch/arm/mach-rmobile/pfc-r8a7790.h deleted file mode 100644 index 3b36548..0000000 --- a/arch/arm/mach-rmobile/pfc-r8a7790.h +++ /dev/null @@ -1,139 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * arch/arm/cpu/armv7/rmobile/pfc-r8a7790.h - * - * Copyright (C) 2013 Renesas Electronics Corporation - */ - -#ifndef __PFC_R8A7790_H__ -#define __PFC_R8A7790_H__ - -#include <sh_pfc.h> -#include <asm/gpio.h> - -#define CPU_32_PORT(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_1(fn, pfx##31, sfx) - -#define CPU_32_PORT2(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) - -#if defined(CONFIG_R8A7790) -#define CPU_32_PORT1(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_10(fn, pfx##2, sfx) \ -/* GP_0_0_DATA -> GP_5_31_DATA (except for GP1[30],GP1[31],GP2[30],GP2[31]) */ -#define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT(fn, pfx##_0_, sfx), \ - CPU_32_PORT1(fn, pfx##_1_, sfx), \ - CPU_32_PORT2(fn, pfx##_2_, sfx), \ - CPU_32_PORT(fn, pfx##_3_, sfx), \ - CPU_32_PORT(fn, pfx##_4_, sfx), \ - CPU_32_PORT(fn, pfx##_5_, sfx) - -#elif defined(CONFIG_R8A7791) -#define CPU_32_PORT1(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx) - -/* - * GP_0_0_DATA -> GP_7_25_DATA - * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30]),GP1[31] - * GP7[26],GP7[27],GP7[28],GP7[29]),GP7[30]),GP7[31]) - */ -#define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT(fn, pfx##_0_, sfx), \ - CPU_32_PORT1(fn, pfx##_1_, sfx), \ - CPU_32_PORT(fn, pfx##_2_, sfx), \ - CPU_32_PORT(fn, pfx##_3_, sfx), \ - CPU_32_PORT(fn, pfx##_4_, sfx), \ - CPU_32_PORT(fn, pfx##_5_, sfx), \ - CPU_32_PORT(fn, pfx##_6_, sfx), \ - CPU_32_PORT1(fn, pfx##_7_, sfx) - -#elif defined(CONFIG_R8A7792) -/* - * GP_0_0_DATA -> GP_11_29_DATA - * (except for GP0[29..31],GP1[23..31],GP3[28..31],GP4[17..31],GP5[17..31] - * GP6[17..31],GP7[17..31],GP8[17..31],GP9[17..31],GP11[30..31]) - */ -#define CPU_32_PORT0_28(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \ - PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx), \ - PORT_1(fn, pfx##28, sfx) - -#define CPU_32_PORT0_22(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx) - -#define CPU_32_PORT0_27(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ - PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ - PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ - PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \ - PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx) - -#define CPU_32_PORT0_16(fn, pfx, sfx) \ - PORT_10(fn, pfx, sfx), \ - PORT_1(fn, pfx##10, sfx),PORT_1(fn, pfx##11, sfx), \ - PORT_1(fn, pfx##12, sfx), PORT_1(fn, pfx##13, sfx), \ - PORT_1(fn, pfx##14, sfx), PORT_1(fn, pfx##15, sfx), \ - PORT_1(fn, pfx##16, sfx) - -#define CPU_ALL_PORT(fn, pfx, sfx) \ - CPU_32_PORT0_28(fn, pfx##_0_, sfx), \ - CPU_32_PORT0_22(fn, pfx##_1_, sfx), \ - CPU_32_PORT(fn, pfx##_2_, sfx), \ - CPU_32_PORT0_27(fn, pfx##_3_, sfx), \ - CPU_32_PORT0_16(fn, pfx##_4_, sfx), \ - CPU_32_PORT0_16(fn, pfx##_5_, sfx), \ - CPU_32_PORT0_16(fn, pfx##_6_, sfx), \ - CPU_32_PORT0_16(fn, pfx##_7_, sfx), \ - CPU_32_PORT0_16(fn, pfx##_8_, sfx), \ - CPU_32_PORT0_16(fn, pfx##_9_, sfx), \ - CPU_32_PORT(fn, pfx##_10_, sfx), \ - CPU_32_PORT2(fn, pfx##_11_, sfx) - -#else -#error "NO support" -#endif - -#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) -#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ - GP##pfx##_IN, GP##pfx##_OUT) - -#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT -#define _GP_INDT(pfx, sfx) GP##pfx##_DATA - -#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) -#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) -#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) - -#define PORT_10_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ - PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ - PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ - PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ - PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) - -#define CPU_32_PORT_REV(fn, pfx, sfx) \ - PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ - PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ - PORT_10_REV(fn, pfx, sfx) - -#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) -#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) - -#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) -#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ - FN_##ipsr, FN_##fn) - -#endif /* __PFC_R8A7790_H__ */ diff --git a/arch/sh/lib/time.c b/arch/sh/lib/time.c index 366500d..19c8e3c 100644 --- a/arch/sh/lib/time.c +++ b/arch/sh/lib/time.c @@ -16,7 +16,7 @@ #include <asm/io.h> #include <linux/bitops.h> -#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RMOBILE) +#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_RENESAS) #define TSTR 0x4 #define TCR0 0x10 #endif /* CONFIG_CPU_SH4 */ diff --git a/board/beacon/beacon-rzg2m/Kconfig b/board/beacon/beacon-rzg2m/Kconfig index c03857c..1eb9e0d 100644 --- a/board/beacon/beacon-rzg2m/Kconfig +++ b/board/beacon/beacon-rzg2m/Kconfig @@ -1,7 +1,7 @@ if TARGET_BEACON_RZG2M config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "beacon-rzg2m" diff --git a/board/hoperun/hihope-rzg2/Kconfig b/board/hoperun/hihope-rzg2/Kconfig index ee422ba..e15b54a 100644 --- a/board/hoperun/hihope-rzg2/Kconfig +++ b/board/hoperun/hihope-rzg2/Kconfig @@ -1,7 +1,7 @@ if TARGET_HIHOPE_RZG2 config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "hihope-rzg2" diff --git a/board/hoperun/hihope-rzg2/hihope-rzg2.c b/board/hoperun/hihope-rzg2/hihope-rzg2.c index 3372290..68d3d30 100644 --- a/board/hoperun/hihope-rzg2/hihope-rzg2.c +++ b/board/hoperun/hihope-rzg2/hihope-rzg2.c @@ -10,7 +10,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <asm/processor.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> #include <linux/bitops.h> #include <linux/delay.h> diff --git a/board/renesas/alt/alt.c b/board/renesas/alt/alt.c index be77cad..d428320 100644 --- a/board/renesas/alt/alt.c +++ b/board/renesas/alt/alt.c @@ -22,10 +22,8 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <asm/arch/mmc.h> -#include <asm/arch/sh_sdhi.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> diff --git a/board/renesas/alt/alt_spl.c b/board/renesas/alt/alt_spl.c index fc9dac5..260863f 100644 --- a/board/renesas/alt/alt_spl.c +++ b/board/renesas/alt/alt_spl.c @@ -16,7 +16,7 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> #include <spl.h> diff --git a/board/renesas/alt/qos.c b/board/renesas/alt/qos.c index 38dfa64..b8edd54 100644 --- a/board/renesas/alt/qos.c +++ b/board/renesas/alt/qos.c @@ -9,9 +9,9 @@ #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) +#if defined(CONFIG_RENESAS_EXTRAM_BOOT) /* QoS version 0.311 for ES1 and version 0.321 for ES2 */ enum { @@ -991,8 +991,8 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); } -#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#else /* CONFIG_RENESAS_EXTRAM_BOOT */ void qos_init(void) { } -#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#endif /* CONFIG_RENESAS_EXTRAM_BOOT */ diff --git a/board/renesas/blanche/blanche.c b/board/renesas/blanche/blanche.c index c6ecea2..7f00d25 100644 --- a/board/renesas/blanche/blanche.c +++ b/board/renesas/blanche/blanche.c @@ -9,10 +9,8 @@ #include <cpu_func.h> #include <init.h> #include <net.h> -#include <asm/arch/mmc.h> #include <asm/arch/rcar-mstp.h> -#include <asm/arch/rmobile.h> -#include <asm/arch/sh_sdhi.h> +#include <asm/arch/renesas.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/gpio.h> @@ -51,7 +49,7 @@ static void blanche_init_sys(void) struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; u32 cpu_type; - cpu_type = rmobile_get_cpu_type(); + cpu_type = renesas_get_cpu_type(); if (cpu_type == 0x4A) { writel(0x4D000000, CPG_PLL1CR); writel(0x4F000000, CPG_PLL3CR); diff --git a/board/renesas/blanche/qos.c b/board/renesas/blanche/qos.c index 3134b36..f0bc7f7 100644 --- a/board/renesas/blanche/qos.c +++ b/board/renesas/blanche/qos.c @@ -8,9 +8,9 @@ #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> -#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +#if defined(CONFIG_RENESAS_EXTRAM_BOOT) enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, @@ -1357,8 +1357,8 @@ void qos_init(void) writel(0x0000F700, CCI_AXI_AX2ADDRMASK); } -#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +#else /* CONFIG_RENESAS_EXTRAM_BOOT */ void qos_init(void) { } -#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ +#endif /* CONFIG_RENESAS_EXTRAM_BOOT */ diff --git a/board/renesas/condor/Kconfig b/board/renesas/condor/Kconfig index 2286d88..fbfb12c 100644 --- a/board/renesas/condor/Kconfig +++ b/board/renesas/condor/Kconfig @@ -1,7 +1,7 @@ if TARGET_CONDOR config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "condor" diff --git a/board/renesas/draak/Kconfig b/board/renesas/draak/Kconfig index 9106387..8f3d904 100644 --- a/board/renesas/draak/Kconfig +++ b/board/renesas/draak/Kconfig @@ -1,7 +1,7 @@ if TARGET_DRAAK config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "draak" diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c index 06a3a83..a51bf65 100644 --- a/board/renesas/draak/draak.c +++ b/board/renesas/draak/draak.c @@ -22,9 +22,8 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <asm/arch/sh_sdhi.h> #include <i2c.h> #include <mmc.h> diff --git a/board/renesas/eagle/Kconfig b/board/renesas/eagle/Kconfig index 4d12843..04895d2 100644 --- a/board/renesas/eagle/Kconfig +++ b/board/renesas/eagle/Kconfig @@ -1,7 +1,7 @@ if TARGET_EAGLE config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "eagle" diff --git a/board/renesas/ebisu/Kconfig b/board/renesas/ebisu/Kconfig index f500a94..a9049b6 100644 --- a/board/renesas/ebisu/Kconfig +++ b/board/renesas/ebisu/Kconfig @@ -1,7 +1,7 @@ if TARGET_EBISU config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "ebisu" diff --git a/board/renesas/falcon/Kconfig b/board/renesas/falcon/Kconfig index 1fcefa7..44a2e56 100644 --- a/board/renesas/falcon/Kconfig +++ b/board/renesas/falcon/Kconfig @@ -1,7 +1,7 @@ if TARGET_FALCON config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "falcon" diff --git a/board/renesas/falcon/falcon.c b/board/renesas/falcon/falcon.c index cd86bb3..27fccac 100644 --- a/board/renesas/falcon/falcon.c +++ b/board/renesas/falcon/falcon.c @@ -6,7 +6,7 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/board/renesas/gose/gose.c b/board/renesas/gose/gose.c index 6edbdac..b4b70d3 100644 --- a/board/renesas/gose/gose.c +++ b/board/renesas/gose/gose.c @@ -23,9 +23,8 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <asm/arch/sh_sdhi.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> diff --git a/board/renesas/gose/gose_spl.c b/board/renesas/gose/gose_spl.c index 87126a0..f6fc96f 100644 --- a/board/renesas/gose/gose_spl.c +++ b/board/renesas/gose/gose_spl.c @@ -16,7 +16,7 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> #include <spl.h> diff --git a/board/renesas/gose/qos.c b/board/renesas/gose/qos.c index 9944df7..29817e1 100644 --- a/board/renesas/gose/qos.c +++ b/board/renesas/gose/qos.c @@ -9,9 +9,9 @@ #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) +#if defined(CONFIG_RENESAS_EXTRAM_BOOT) /* QoS version 0.311 */ enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, @@ -1194,8 +1194,8 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); } -#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#else /* CONFIG_RENESAS_EXTRAM_BOOT */ void qos_init(void) { } -#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#endif /* CONFIG_RENESAS_EXTRAM_BOOT */ diff --git a/board/renesas/grayhawk/Kconfig b/board/renesas/grayhawk/Kconfig index 97621a3..a6dbfb5 100644 --- a/board/renesas/grayhawk/Kconfig +++ b/board/renesas/grayhawk/Kconfig @@ -1,7 +1,7 @@ if TARGET_GRAYHAWK config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "grayhawk" diff --git a/board/renesas/grayhawk/grayhawk.c b/board/renesas/grayhawk/grayhawk.c index 6f2e73f..6c8fca8 100644 --- a/board/renesas/grayhawk/grayhawk.c +++ b/board/renesas/grayhawk/grayhawk.c @@ -6,7 +6,7 @@ * Copyright (C) 2023 Renesas Electronics Corp. */ -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c index ee5597a..78f3f90 100644 --- a/board/renesas/koelsch/koelsch.c +++ b/board/renesas/koelsch/koelsch.c @@ -24,9 +24,8 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <asm/arch/sh_sdhi.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> diff --git a/board/renesas/koelsch/koelsch_spl.c b/board/renesas/koelsch/koelsch_spl.c index 7581920..2950b8d 100644 --- a/board/renesas/koelsch/koelsch_spl.c +++ b/board/renesas/koelsch/koelsch_spl.c @@ -16,7 +16,7 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> #include <spl.h> diff --git a/board/renesas/koelsch/qos.c b/board/renesas/koelsch/qos.c index 70cd117..ee89351 100644 --- a/board/renesas/koelsch/qos.c +++ b/board/renesas/koelsch/qos.c @@ -9,10 +9,10 @@ #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> /* QoS version 0.240 for ES1 and version 0.411 for ES2 */ -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) +#if defined(CONFIG_RENESAS_EXTRAM_BOOT) enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, @@ -1382,8 +1382,8 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); } -#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#else /* CONFIG_RENESAS_EXTRAM_BOOT */ void qos_init(void) { } -#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#endif /* CONFIG_RENESAS_EXTRAM_BOOT */ diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c index 0daad0b..0ec8e3d 100644 --- a/board/renesas/lager/lager.c +++ b/board/renesas/lager/lager.c @@ -26,10 +26,8 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <asm/arch/mmc.h> -#include <asm/arch/sh_sdhi.h> #include <miiphy.h> #include <i2c.h> #include <mmc.h> @@ -48,7 +46,7 @@ void s_init(void) writel(0xA5A5A500, &swdt->swtcsra); /* CPU frequency setting. Set to 1.4GHz */ - if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { + if (renesas_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { u32 stat = 0; u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT; diff --git a/board/renesas/lager/lager_spl.c b/board/renesas/lager/lager_spl.c index df3e240..0799ba1 100644 --- a/board/renesas/lager/lager_spl.c +++ b/board/renesas/lager/lager_spl.c @@ -16,7 +16,7 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> #include <spl.h> diff --git a/board/renesas/lager/qos.c b/board/renesas/lager/qos.c index ddc831c..80e5710 100644 --- a/board/renesas/lager/qos.c +++ b/board/renesas/lager/qos.c @@ -8,10 +8,10 @@ #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> /* QoS version 0.955 for ES1 and version 0.973 for ES2 */ -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) +#if defined(CONFIG_RENESAS_EXTRAM_BOOT) enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, @@ -2419,13 +2419,13 @@ static void qos_init_es2(void) void qos_init(void) { - if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) + if (renesas_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) qos_init_es2(); else qos_init_es1(); } -#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#else /* CONFIG_RENESAS_EXTRAM_BOOT */ void qos_init(void) { } -#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#endif /* CONFIG_RENESAS_EXTRAM_BOOT */ diff --git a/board/renesas/porter/porter.c b/board/renesas/porter/porter.c index 2e6051a..f38263c 100644 --- a/board/renesas/porter/porter.c +++ b/board/renesas/porter/porter.c @@ -24,9 +24,8 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <asm/arch/sh_sdhi.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> diff --git a/board/renesas/porter/porter_spl.c b/board/renesas/porter/porter_spl.c index 039fc7b..1643446 100644 --- a/board/renesas/porter/porter_spl.c +++ b/board/renesas/porter/porter_spl.c @@ -16,7 +16,7 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> #include <spl.h> diff --git a/board/renesas/porter/qos.c b/board/renesas/porter/qos.c index e4d8f3d..87274ee 100644 --- a/board/renesas/porter/qos.c +++ b/board/renesas/porter/qos.c @@ -10,10 +10,10 @@ #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> /* QoS version 0.240 for ES1 and version 0.334 for ES2 */ -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) +#if defined(CONFIG_RENESAS_EXTRAM_BOOT) enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, @@ -1303,8 +1303,8 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); } -#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#else /* CONFIG_RENESAS_EXTRAM_BOOT */ void qos_init(void) { } -#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#endif /* CONFIG_RENESAS_EXTRAM_BOOT */ diff --git a/board/renesas/rcar-common/common.c b/board/renesas/rcar-common/common.c index 66eb6a2..499c314 100644 --- a/board/renesas/rcar-common/common.c +++ b/board/renesas/rcar-common/common.c @@ -14,7 +14,7 @@ #include <asm/global_data.h> #include <asm/io.h> #include <dm/uclass-internal.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <linux/libfdt.h> #ifdef CONFIG_RCAR_64 diff --git a/board/renesas/rcar-common/v3-common.c b/board/renesas/rcar-common/v3-common.c index 26c589d..5d057ed 100644 --- a/board/renesas/rcar-common/v3-common.c +++ b/board/renesas/rcar-common/v3-common.c @@ -4,7 +4,7 @@ */ #include <clock_legacy.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/io.h> #define CPGWPR 0xE6150900 diff --git a/board/renesas/rzg2l/Kconfig b/board/renesas/rzg2l/Kconfig index 1335fc7..c7b7570 100644 --- a/board/renesas/rzg2l/Kconfig +++ b/board/renesas/rzg2l/Kconfig @@ -4,7 +4,7 @@ if TARGET_RZG2L_SMARC_EVK config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "rzg2l" diff --git a/board/renesas/salvator-x/Kconfig b/board/renesas/salvator-x/Kconfig index ed4c479..52955e1 100644 --- a/board/renesas/salvator-x/Kconfig +++ b/board/renesas/salvator-x/Kconfig @@ -1,7 +1,7 @@ if TARGET_SALVATOR_X config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "salvator-x" diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c index d8312dd..8c47246 100644 --- a/board/renesas/salvator-x/salvator-x.c +++ b/board/renesas/salvator-x/salvator-x.c @@ -23,9 +23,8 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <asm/arch/sh_sdhi.h> #include <i2c.h> #include <mmc.h> @@ -77,17 +76,17 @@ void reset_cpu(void) int board_fit_config_name_match(const char *name) { /* PRR driver is not available yet */ - u32 cpu_type = rmobile_get_cpu_type(); + u32 cpu_type = renesas_get_cpu_type(); - if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) && + if ((cpu_type == RENESAS_CPU_TYPE_R8A7795) && !strcmp(name, "r8a77950-salvator-x-u-boot")) return 0; - if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) && + if ((cpu_type == RENESAS_CPU_TYPE_R8A7796) && !strcmp(name, "r8a77960-salvator-x-u-boot")) return 0; - if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) && + if ((cpu_type == RENESAS_CPU_TYPE_R8A77965) && !strcmp(name, "r8a77965-salvator-x-u-boot")) return 0; diff --git a/board/renesas/silk/qos.c b/board/renesas/silk/qos.c index bdd7646..00e5e79 100644 --- a/board/renesas/silk/qos.c +++ b/board/renesas/silk/qos.c @@ -10,9 +10,9 @@ #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) +#if defined(CONFIG_RENESAS_EXTRAM_BOOT) /* QoS version 0.11 */ enum { @@ -942,8 +942,8 @@ void qos_init(void) writel(0x00000001, &axi_qos->qosthres2); writel(0x00000001, &axi_qos->qosqon); } -#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#else /* CONFIG_RENESAS_EXTRAM_BOOT */ void qos_init(void) { } -#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#endif /* CONFIG_RENESAS_EXTRAM_BOOT */ diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c index 18ff759..cc64e44 100644 --- a/board/renesas/silk/silk.c +++ b/board/renesas/silk/silk.c @@ -23,10 +23,8 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <asm/arch/mmc.h> -#include <asm/arch/sh_sdhi.h> #include <netdev.h> #include <miiphy.h> #include <i2c.h> diff --git a/board/renesas/silk/silk_spl.c b/board/renesas/silk/silk_spl.c index b899442..19b2e5f 100644 --- a/board/renesas/silk/silk_spl.c +++ b/board/renesas/silk/silk_spl.c @@ -16,7 +16,7 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> #include <spl.h> diff --git a/board/renesas/spider/Kconfig b/board/renesas/spider/Kconfig index 8df2e85..bd5825e 100644 --- a/board/renesas/spider/Kconfig +++ b/board/renesas/spider/Kconfig @@ -1,7 +1,7 @@ if TARGET_SPIDER config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "spider" diff --git a/board/renesas/spider/spider.c b/board/renesas/spider/spider.c index 1eb75a6..414948f 100644 --- a/board/renesas/spider/spider.c +++ b/board/renesas/spider/spider.c @@ -6,7 +6,7 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/board/renesas/stout/qos.c b/board/renesas/stout/qos.c index 9030ba7..a3e512c 100644 --- a/board/renesas/stout/qos.c +++ b/board/renesas/stout/qos.c @@ -10,10 +10,10 @@ #include <asm/processor.h> #include <asm/mach-types.h> #include <asm/io.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> /* QoS version 0.955 for ES1 and version 0.973 for ES2 */ -#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) +#if defined(CONFIG_RENESAS_EXTRAM_BOOT) enum { DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, @@ -2421,13 +2421,13 @@ static void qos_init_es2(void) void qos_init(void) { - if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) + if (renesas_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) qos_init_es2(); else qos_init_es1(); } -#else /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#else /* CONFIG_RENESAS_EXTRAM_BOOT */ void qos_init(void) { } -#endif /* CONFIG_ARCH_RMOBILE_EXTRAM_BOOT */ +#endif /* CONFIG_RENESAS_EXTRAM_BOOT */ diff --git a/board/renesas/stout/stout.c b/board/renesas/stout/stout.c index 131deac..f1d84b5 100644 --- a/board/renesas/stout/stout.c +++ b/board/renesas/stout/stout.c @@ -25,10 +25,8 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <asm/arch/mmc.h> -#include <asm/arch/sh_sdhi.h> #include <miiphy.h> #include <i2c.h> #include <mmc.h> @@ -48,7 +46,7 @@ void s_init(void) writel(0xA5A5A500, &swdt->swtcsra); /* CPU frequency setting. Set to 1.4GHz */ - if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { + if (renesas_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { u32 stat = 0; u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT; diff --git a/board/renesas/stout/stout_spl.c b/board/renesas/stout/stout_spl.c index 8ec0216..3c7cac8 100644 --- a/board/renesas/stout/stout_spl.c +++ b/board/renesas/stout/stout_spl.c @@ -16,7 +16,7 @@ #include <linux/errno.h> #include <asm/arch/sys_proto.h> #include <asm/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> #include <spl.h> diff --git a/board/renesas/ulcb/Kconfig b/board/renesas/ulcb/Kconfig index 1e9a10d..3186036 100644 --- a/board/renesas/ulcb/Kconfig +++ b/board/renesas/ulcb/Kconfig @@ -1,7 +1,7 @@ if TARGET_ULCB config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "ulcb" diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c index b2a16b0..8f5de21 100644 --- a/board/renesas/ulcb/ulcb.c +++ b/board/renesas/ulcb/ulcb.c @@ -21,9 +21,8 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/arch/gpio.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/rcar-mstp.h> -#include <asm/arch/sh_sdhi.h> #include <i2c.h> #include <mmc.h> @@ -68,17 +67,17 @@ int board_init(void) int board_fit_config_name_match(const char *name) { /* PRR driver is not available yet */ - u32 cpu_type = rmobile_get_cpu_type(); + u32 cpu_type = renesas_get_cpu_type(); - if ((cpu_type == RMOBILE_CPU_TYPE_R8A7795) && + if ((cpu_type == RENESAS_CPU_TYPE_R8A7795) && !strcmp(name, "r8a77950-ulcb-u-boot")) return 0; - if ((cpu_type == RMOBILE_CPU_TYPE_R8A7796) && + if ((cpu_type == RENESAS_CPU_TYPE_R8A7796) && !strcmp(name, "r8a77960-ulcb-u-boot")) return 0; - if ((cpu_type == RMOBILE_CPU_TYPE_R8A77965) && + if ((cpu_type == RENESAS_CPU_TYPE_R8A77965) && !strcmp(name, "r8a77965-ulcb-u-boot")) return 0; diff --git a/board/renesas/v3hsk/Kconfig b/board/renesas/v3hsk/Kconfig index 531ceb7..da595a4 100644 --- a/board/renesas/v3hsk/Kconfig +++ b/board/renesas/v3hsk/Kconfig @@ -1,7 +1,7 @@ if TARGET_V3HSK config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "v3hsk" diff --git a/board/renesas/v3msk/Kconfig b/board/renesas/v3msk/Kconfig index fe037fd..8f42386 100644 --- a/board/renesas/v3msk/Kconfig +++ b/board/renesas/v3msk/Kconfig @@ -1,7 +1,7 @@ if TARGET_V3MSK config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "v3msk" diff --git a/board/renesas/whitehawk/Kconfig b/board/renesas/whitehawk/Kconfig index 05a8789..8adb24c 100644 --- a/board/renesas/whitehawk/Kconfig +++ b/board/renesas/whitehawk/Kconfig @@ -1,7 +1,7 @@ if TARGET_WHITEHAWK config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "whitehawk" diff --git a/board/renesas/whitehawk/whitehawk.c b/board/renesas/whitehawk/whitehawk.c index a72f5e0..3a10b02 100644 --- a/board/renesas/whitehawk/whitehawk.c +++ b/board/renesas/whitehawk/whitehawk.c @@ -6,7 +6,7 @@ * Copyright (C) 2021 Renesas Electronics Corp. */ -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/arch/sys_proto.h> #include <asm/global_data.h> #include <asm/io.h> diff --git a/board/silinux/ek874/Kconfig b/board/silinux/ek874/Kconfig index 60b390a..5b34087 100644 --- a/board/silinux/ek874/Kconfig +++ b/board/silinux/ek874/Kconfig @@ -1,7 +1,7 @@ if TARGET_SILINUX_EK874 config SYS_SOC - default "rmobile" + default "renesas" config SYS_BOARD default "ek874" diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 35707a6..e4007ab 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -18,7 +18,7 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7794-alt-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="Alt" +CONFIG_ARCH_RENESAS_BOARD_STRING="Alt" CONFIG_R8A7794=y CONFIG_TARGET_ALT=y CONFIG_SYS_MONITOR_LEN=262144 diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index f328af8..af7622a 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x00000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -13,7 +13,7 @@ CONFIG_ENV_OFFSET=0x40000 CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7792-blanche-u-boot" -CONFIG_ARCH_RMOBILE_BOARD_STRING="Blanche" +CONFIG_ARCH_RENESAS_BOARD_STRING="Blanche" CONFIG_R8A7792=y CONFIG_TARGET_BLANCHE=y CONFIG_SYS_MONITOR_LEN=262144 diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 92bb591..1eadf7c 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -18,7 +18,7 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7793-gose-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="Gose" +CONFIG_ARCH_RENESAS_BOARD_STRING="Gose" CONFIG_R8A7793=y CONFIG_TARGET_GOSE=y CONFIG_SYS_MONITOR_LEN=262144 diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index 6738424..eef3bad 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x18000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0x400 diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index 0fab055..a2c7e78 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x20000 diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index 8d9c3b9..963e02d 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -18,7 +18,7 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7791-koelsch-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="Koelsch" +CONFIG_ARCH_RENESAS_BOARD_STRING="Koelsch" CONFIG_R8A7791=y CONFIG_TARGET_KOELSCH=y CONFIG_SYS_MONITOR_LEN=262144 diff --git a/configs/lager_defconfig b/configs/lager_defconfig index d00314c..605909e 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -18,7 +18,7 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7790-lager-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="Lager" +CONFIG_ARCH_RENESAS_BOARD_STRING="Lager" CONFIG_R8A7790=y CONFIG_TARGET_LAGER=y CONFIG_SYS_MONITOR_LEN=262144 diff --git a/configs/porter_defconfig b/configs/porter_defconfig index a343c8e..021e521 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -18,7 +18,7 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7791-porter-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="Porter" +CONFIG_ARCH_RENESAS_BOARD_STRING="Porter" CONFIG_R8A7791=y CONFIG_TARGET_PORTER=y CONFIG_SYS_MONITOR_LEN=262144 diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index e6e70e0..62fa7e1 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a77970_v3msk_defconfig b/configs/r8a77970_v3msk_defconfig index a14d052..b340872 100644 --- a/configs/r8a77970_v3msk_defconfig +++ b/configs/r8a77970_v3msk_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 8649137..8a50195 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x40000 diff --git a/configs/r8a77980_v3hsk_defconfig b/configs/r8a77980_v3hsk_defconfig index 0f3f544..8d67b7f 100644 --- a/configs/r8a77980_v3hsk_defconfig +++ b/configs/r8a77980_v3hsk_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x40000 diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index 9e2e0d0..28fa30e 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 380b5f7..6443206 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index 7aed1fe..04a5600 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x40000 diff --git a/configs/r8a779f0_spider_defconfig b/configs/r8a779f0_spider_defconfig index a3a5aac..54e0928 100644 --- a/configs/r8a779f0_spider_defconfig +++ b/configs/r8a779f0_spider_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x40000 CONFIG_ENV_OFFSET=0xD00000 diff --git a/configs/r8a779g0_whitehawk_defconfig b/configs/r8a779g0_whitehawk_defconfig index c959ad1..1489c32 100644 --- a/configs/r8a779g0_whitehawk_defconfig +++ b/configs/r8a779g0_whitehawk_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 diff --git a/configs/r8a779h0_grayhawk_defconfig b/configs/r8a779h0_grayhawk_defconfig index 2c32a83..84401eb 100644 --- a/configs/r8a779h0_grayhawk_defconfig +++ b/configs/r8a779h0_grayhawk_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 3264088..a69bb43 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xFFFE0000 diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index b1814d7..5bd3697 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ENV_SIZE=0x20000 diff --git a/configs/renesas_rzg2l_smarc_defconfig b/configs/renesas_rzg2l_smarc_defconfig index 7f22795..e4e597f 100644 --- a/configs/renesas_rzg2l_smarc_defconfig +++ b/configs/renesas_rzg2l_smarc_defconfig @@ -2,7 +2,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_SYS_INIT_SP_BSS_OFFSET=1048576 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x80000 diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig index 1375938..f4b63ad 100644 --- a/configs/rzg2_beacon_defconfig +++ b/configs/rzg2_beacon_defconfig @@ -1,5 +1,5 @@ CONFIG_ARM=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/rzn1_snarc_defconfig b/configs/rzn1_snarc_defconfig index 5c65727..29a96d1 100644 --- a/configs/rzn1_snarc_defconfig +++ b/configs/rzn1_snarc_defconfig @@ -1,6 +1,6 @@ CONFIG_ARM=y CONFIG_SYS_ARCH_TIMER=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_SYS_MALLOC_LEN=0xb0000 CONFIG_SYS_MALLOC_F_LEN=0x800 CONFIG_NR_DRAM_BANKS=1 diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig index 25e3205..0f0aca3 100644 --- a/configs/silinux_ek874_defconfig +++ b/configs/silinux_ek874_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_COUNTER_FREQUENCY=16666666 CONFIG_ARCH_CPU_INIT=y -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x4000000 CONFIG_SYS_MALLOC_F_LEN=0x2000 diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 5f08ae0..939ccc9 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -18,7 +18,7 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7794-silk-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="Silk" +CONFIG_ARCH_RENESAS_BOARD_STRING="Silk" CONFIG_R8A7794=y CONFIG_TARGET_SILK=y CONFIG_SYS_MONITOR_LEN=262144 diff --git a/configs/stout_defconfig b/configs/stout_defconfig index 0375630..1022ee9 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -3,7 +3,7 @@ CONFIG_ARCH_CPU_INIT=y CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y # CONFIG_SPL_USE_ARCH_MEMCPY is not set # CONFIG_SPL_USE_ARCH_MEMSET is not set -CONFIG_ARCH_RMOBILE=y +CONFIG_ARCH_RENESAS=y CONFIG_TEXT_BASE=0x50000000 CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SYS_MALLOC_F_LEN=0x8000 @@ -18,7 +18,7 @@ CONFIG_ENV_SECT_SIZE=0x40000 CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="r8a7790-stout-u-boot" CONFIG_SPL_TEXT_BASE=0xe6300000 -CONFIG_ARCH_RMOBILE_BOARD_STRING="Stout" +CONFIG_ARCH_RENESAS_BOARD_STRING="Stout" CONFIG_R8A7790=y CONFIG_TARGET_STOUT=y CONFIG_SYS_MONITOR_LEN=262144 diff --git a/doc/git-mailrc b/doc/git-mailrc index 0ceb9eb..ca2f67a 100644 --- a/doc/git-mailrc +++ b/doc/git-mailrc @@ -66,7 +66,8 @@ alias imx uboot, sbabic alias kirkwood uboot, stroese alias omap ti alias pxa uboot, marex -alias rmobile uboot, iwamatsu +alias renesas uboot, marex, iwamatsu +alias rmobile uboot, marex, iwamatsu alias s3c samsung alias s5pc samsung alias samsung uboot, prom diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index e9296ed..a093027 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -1,6 +1,6 @@ config CLK_RENESAS bool "Renesas clock drivers" - depends on CLK && ARCH_RMOBILE + depends on CLK && ARCH_RENESAS help Enable support for clock present on Renesas SoCs. diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 27df5d8..2df3dc4 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -333,7 +333,7 @@ config PCF8575_GPIO config RCAR_GPIO bool "Renesas RCar GPIO driver" - depends on DM_GPIO && ARCH_RMOBILE + depends on DM_GPIO && ARCH_RENESAS help This driver supports the GPIO banks on Renesas RCar SoCs. diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig index d2a3a13..59c635a 100644 --- a/drivers/i2c/Kconfig +++ b/drivers/i2c/Kconfig @@ -551,7 +551,7 @@ config SPL_SYS_I2C_SANDBOX config SYS_I2C_SH bool "Legacy SuperH I2C interface" - depends on ARCH_RMOBILE && SYS_I2C_LEGACY + depends on ARCH_RENESAS && SYS_I2C_LEGACY help Enable the legacy SuperH I2C interface. diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 17618c3..cef0579 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -393,7 +393,7 @@ config HSMMC2_8BIT config SH_MMCIF bool "SuperH/Renesas ARM SoCs on-chip MMCIF host controller support" - depends on ARCH_RMOBILE || SH + depends on ARCH_RENESAS || SH help Support for the on-chip MMCIF host controller on SuperH/Renesas ARM SoCs platform @@ -408,7 +408,7 @@ config MMC_UNIPHIER config RENESAS_SDHI bool "Renesas R-Car SD/MMC Host Controller support" - depends on ARCH_RMOBILE + depends on ARCH_RENESAS depends on BLK && DM_MMC depends on OF_CONTROL select BOUNCE_BUFFER diff --git a/drivers/mmc/renesas-sdhi.c b/drivers/mmc/renesas-sdhi.c index a74559c..20b1e92 100644 --- a/drivers/mmc/renesas-sdhi.c +++ b/drivers/mmc/renesas-sdhi.c @@ -92,7 +92,7 @@ static const u8 r8a77990_calib_table[2][CALIB_TABLE_MAX] = { 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } }; -static int rmobile_is_gen3_mmc0(struct tmio_sd_priv *priv) +static int rcar_is_gen3_mmc0(struct tmio_sd_priv *priv) { /* On R-Car Gen3, MMC0 is at 0xee140000 */ return (uintptr_t)(priv->regbase) == 0xee140000; @@ -885,80 +885,80 @@ static void renesas_sdhi_filter_caps(struct udevice *dev) struct tmio_sd_plat *plat = dev_get_plat(dev); /* HS400 is not supported on H3 ES1.x, M3W ES1.[012], V3M, V3H ES1.x, D3 */ - if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && - (rmobile_get_cpu_rev_integer() <= 1)) || - ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && - (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() <= 2)) || - (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) || - ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77980) && - (rmobile_get_cpu_rev_integer() <= 1)) || - (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995)) + if (((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7795) && + (renesas_get_cpu_rev_integer() <= 1)) || + ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) && + (renesas_get_cpu_rev_integer() == 1) && + (renesas_get_cpu_rev_fraction() <= 2)) || + (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77970) || + ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77980) && + (renesas_get_cpu_rev_integer() <= 1)) || + (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77995)) plat->cfg.host_caps &= ~MMC_MODE_HS400; /* H3 ES2.0, ES3.0 and M3W ES1.2 and M3N bad taps */ - if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && - (rmobile_get_cpu_rev_integer() >= 2)) || - ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && - (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() == 2)) || - (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965)) + if (((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7795) && + (renesas_get_cpu_rev_integer() >= 2)) || + ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) && + (renesas_get_cpu_rev_integer() == 1) && + (renesas_get_cpu_rev_fraction() == 2)) || + (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77965)) priv->hs400_bad_tap = BIT(2) | BIT(3) | BIT(6) | BIT(7); /* M3W ES1.x for x>2 can use HS400 with manual adjustment and taps */ - if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && - (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() > 2)) { + if ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) && + (renesas_get_cpu_rev_integer() == 1) && + (renesas_get_cpu_rev_fraction() > 2)) { priv->adjust_hs400_enable = true; priv->adjust_hs400_offset = 3; priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7); priv->adjust_hs400_calib_table = - r8a7796_rev13_calib_table[!rmobile_is_gen3_mmc0(priv)]; + r8a7796_rev13_calib_table[!rcar_is_gen3_mmc0(priv)]; } /* M3W+ bad taps */ - if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && - (rmobile_get_cpu_rev_integer() == 3)) + if ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) && + (renesas_get_cpu_rev_integer() == 3)) priv->hs400_bad_tap = BIT(1) | BIT(3) | BIT(5) | BIT(7); /* M3N can use HS400 with manual adjustment */ - if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77965) { + if (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77965) { priv->adjust_hs400_enable = true; priv->adjust_hs400_offset = 3; priv->adjust_hs400_calib_table = - r8a77965_calib_table[!rmobile_is_gen3_mmc0(priv)]; + r8a77965_calib_table[!rcar_is_gen3_mmc0(priv)]; } /* E3 can use HS400 with manual adjustment */ - if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) { + if (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77990) { priv->adjust_hs400_enable = true; priv->adjust_hs400_offset = 3; priv->adjust_hs400_calib_table = - r8a77990_calib_table[!rmobile_is_gen3_mmc0(priv)]; + r8a77990_calib_table[!rcar_is_gen3_mmc0(priv)]; } /* H3 ES1.x, ES2.0 and M3W ES1.[0123] uses 4 tuning taps */ - if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && - (rmobile_get_cpu_rev_integer() <= 2)) || - ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && - (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() <= 3))) + if (((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7795) && + (renesas_get_cpu_rev_integer() <= 2)) || + ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) && + (renesas_get_cpu_rev_integer() == 1) && + (renesas_get_cpu_rev_fraction() <= 3))) priv->nrtaps = 4; else priv->nrtaps = 8; #endif /* H3 ES1.x and M3W ES1.0 uses bit 17 for DTRAEND */ - if (((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7795) && - (rmobile_get_cpu_rev_integer() <= 1)) || - ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A7796) && - (rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() == 0))) + if (((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7795) && + (renesas_get_cpu_rev_integer() <= 1)) || + ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A7796) && + (renesas_get_cpu_rev_integer() == 1) && + (renesas_get_cpu_rev_fraction() == 0))) priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD; else priv->read_poll_flag = TMIO_SD_DMA_INFO1_END_RD2; /* V3M handles SD0H differently than other Gen3 SoCs */ - if (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77970) + if (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77970) priv->needs_clkh_fallback = true; else priv->needs_clkh_fallback = false; diff --git a/drivers/mmc/sh_mmcif.h b/drivers/mmc/sh_mmcif.h index 66341e5..b131b8c 100644 --- a/drivers/mmc/sh_mmcif.h +++ b/drivers/mmc/sh_mmcif.h @@ -195,7 +195,7 @@ struct sh_mmcif_regs { #define SOFT_RST_OFF (0 << 31) #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ -#ifdef CONFIG_ARCH_RMOBILE +#ifdef CONFIG_ARCH_RENESAS #define MMC_CLK_DIV_MIN(clk) (clk / (1 << 9)) #define MMC_CLK_DIV_MAX(clk) (clk / (1 << 1)) #else diff --git a/drivers/net/ravb.c b/drivers/net/ravb.c index 0bcd6cf..4764bca 100644 --- a/drivers/net/ravb.c +++ b/drivers/net/ravb.c @@ -392,8 +392,8 @@ static int ravb_dmac_init(struct udevice *dev) writel(0x00222210, eth->iobase + RAVB_REG_TGC); /* Delay CLK: 2ns (not applicable on R-Car E3/D3) */ - if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) || - (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995)) + if ((renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77990) || + (renesas_get_cpu_type() == RENESAS_CPU_TYPE_R8A77995)) return 0; if (!dev_read_u32(dev, "rx-internal-delay-ps", &delay)) { diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 0e929d8..6d7b7cd 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -14,7 +14,7 @@ obj-$(CONFIG_PINCTRL_INTEL) += intel/ obj-$(CONFIG_ARCH_MTMIPS) += mtmips/ obj-$(CONFIG_ARCH_NPCM) += nuvoton/ obj-$(CONFIG_PINCTRL_QCOM) += qcom/ -obj-$(CONFIG_ARCH_RMOBILE) += renesas/ +obj-$(CONFIG_ARCH_RENESAS) += renesas/ obj-$(CONFIG_ARCH_RZN1) += renesas/ obj-$(CONFIG_PINCTRL_SANDBOX) += pinctrl-sandbox.o obj-$(CONFIG_PINCTRL_SUNXI) += sunxi/ diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index 171cd37..57e8860 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -1,8 +1,8 @@ -if ARCH_RMOBILE +if ARCH_RENESAS config PINCTRL_PFC bool "Renesas pin control drivers" - depends on DM && ARCH_RMOBILE + depends on DM && ARCH_RENESAS default n if CPU_RZA1 help Support pin multiplexing control on Renesas SoCs. diff --git a/drivers/pinctrl/renesas/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c index e1811c4..acd6b01 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7790.c +++ b/drivers/pinctrl/renesas/pfc-r8a7790.c @@ -6117,8 +6117,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { static int r8a7790_pinmux_soc_init(struct sh_pfc *pfc) { /* Initialize TDSEL on old revisions */ - if ((rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() == 0)) + if ((renesas_get_cpu_rev_integer() == 1) && + (renesas_get_cpu_rev_fraction() == 0)) sh_pfc_write(pfc, 0xe6060088, 0x00155554); return 0; diff --git a/drivers/pinctrl/renesas/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c index 29eab26..2f55021 100644 --- a/drivers/pinctrl/renesas/pfc-r8a7794.c +++ b/drivers/pinctrl/renesas/pfc-r8a7794.c @@ -5818,8 +5818,8 @@ static const struct pinmux_bias_reg pinmux_bias_regs[] = { static int r8a7794_pinmux_soc_init(struct sh_pfc *pfc) { /* Initialize TDSEL on old revisions */ - if ((rmobile_get_cpu_rev_integer() == 1) && - (rmobile_get_cpu_rev_fraction() == 0)) + if ((renesas_get_cpu_rev_integer() == 1) && + (renesas_get_cpu_rev_fraction() == 0)) sh_pfc_write(pfc, 0xe6060068, 0x55555500); return 0; diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index 985990a..c9c46cc 100644 --- a/drivers/ram/Makefile +++ b/drivers/ram/Makefile @@ -28,5 +28,5 @@ obj-$(CONFIG_DRAM_SUN20I_D1) += sunxi/ obj-$(CONFIG_ARCH_OCTEON) += octeon/ -obj-$(CONFIG_ARCH_RMOBILE) += renesas/ +obj-$(CONFIG_ARCH_RENESAS) += renesas/ obj-$(CONFIG_CADENCE_DDR_CTRL) += cadence/ diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 26460c4..88d6786 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -433,7 +433,7 @@ config DEBUG_UART_SEMIHOSTING config DEBUG_UART_SCIF bool "Renesas SCIF UART" - depends on SH || ARCH_RMOBILE + depends on SH || ARCH_RENESAS help Select this to enable a debug UART using the serial_sh driver. You will need to provide parameters to make this work. The driver will @@ -893,7 +893,7 @@ config SANDBOX_SERIAL config SCIF_CONSOLE bool "Renesas SCIF UART support" - depends on SH || ARCH_RMOBILE + depends on SH || ARCH_RENESAS help Select this to enable Renesas SCIF UART. To operate serial ports on systems with RCar or SH SoCs, say Y to this option. If unsure, diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c index 3eb1406..8aff223 100644 --- a/drivers/spi/renesas_rpc_spi.c +++ b/drivers/spi/renesas_rpc_spi.c @@ -203,7 +203,7 @@ static void rpc_spi_flush_read_cache(struct udevice *dev) static u32 rpc_spi_get_strobe_delay(void) { #ifndef CONFIG_RZA1 - u32 cpu_type = rmobile_get_cpu_type(); + u32 cpu_type = renesas_get_cpu_type(); /* * NOTE: RPC_PHYCNT_STRTIM value: @@ -212,11 +212,11 @@ static u32 rpc_spi_get_strobe_delay(void) * 7: On other R-Car Gen3 * 15: On R-Car Gen4 */ - if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && rmobile_get_cpu_rev_integer() == 1) + if (cpu_type == RENESAS_CPU_TYPE_R8A7796 && renesas_get_cpu_rev_integer() == 1) return RPC_PHYCNT_STRTIM(6); - else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 || - cpu_type == RMOBILE_CPU_TYPE_R8A779G0 || - cpu_type == RMOBILE_CPU_TYPE_R8A779H0) + else if (cpu_type == RENESAS_CPU_TYPE_R8A779F0 || + cpu_type == RENESAS_CPU_TYPE_R8A779G0 || + cpu_type == RENESAS_CPU_TYPE_R8A779H0) return RPC_PHYCNT_STRTIM2(15); else #endif diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c index 7dd1fe7..7259499 100644 --- a/drivers/spi/sh_qspi.c +++ b/drivers/spi/sh_qspi.c @@ -13,7 +13,7 @@ #include <malloc.h> #include <spi.h> #include <wait_bit.h> -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> #include <asm/io.h> #include <linux/bitops.h> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index f96027d..6e10b62 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -97,7 +97,7 @@ config USB_XHCI_PCI config USB_XHCI_RCAR bool "Renesas RCar USB 3.0 support" default y - depends on ARCH_RMOBILE + depends on ARCH_RENESAS help Choose this option to add support for USB 3.0 driver on Renesas RCar Gen3 SoCs. diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 291c2a4..67c9fae 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -8,7 +8,7 @@ #ifndef __RCAR_GEN2_COMMON_H #define __RCAR_GEN2_COMMON_H -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> /* console */ #define CFG_SYS_BAUDRATE_TABLE { 38400, 115200 } diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 213caa7..5f4d5ce 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -9,7 +9,7 @@ #ifndef __RCAR_GEN3_COMMON_H #define __RCAR_GEN3_COMMON_H -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> /* boot option */ diff --git a/include/configs/rcar-gen4-common.h b/include/configs/rcar-gen4-common.h index c4f506d..3465b4d 100644 --- a/include/configs/rcar-gen4-common.h +++ b/include/configs/rcar-gen4-common.h @@ -9,7 +9,7 @@ #ifndef __RCAR_GEN4_COMMON_H #define __RCAR_GEN4_COMMON_H -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> /* Console */ #define CFG_SYS_BAUDRATE_TABLE { 38400, 115200, 921600, 1843200 } diff --git a/include/configs/rzg2l-smarc.h b/include/configs/rzg2l-smarc.h index ea57d28..5806130 100644 --- a/include/configs/rzg2l-smarc.h +++ b/include/configs/rzg2l-smarc.h @@ -6,7 +6,7 @@ #ifndef __RENESAS_RZG2L_H #define __RENESAS_RZG2L_H -#include <asm/arch/rmobile.h> +#include <asm/arch/renesas.h> /* console */ #define CFG_SYS_BAUDRATE_TABLE { 115200, 38400 } |