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| author | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2023-01-26 21:01:55 +0100 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@gmail.com> | 2023-02-02 01:49:20 +0100 |
| commit | 4fc053f1e23239fd138b26516e0eee82f8d5fa2a (patch) | |
| tree | fb62e44087842d6bb177b3f7eb74e46d1edaa06e | |
| parent | 68a23c23453bbebef4ad61a4a5c4fcb6f48d728d (diff) | |
| download | u-boot-4fc053f1e23239fd138b26516e0eee82f8d5fa2a.zip u-boot-4fc053f1e23239fd138b26516e0eee82f8d5fa2a.tar.gz u-boot-4fc053f1e23239fd138b26516e0eee82f8d5fa2a.tar.bz2 | |
clk: renesas: Synchronize R8A77995 D3 clock tables with Linux 6.1.7
Synchronize R-Car R8A77995 D3 clock tables with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
| -rw-r--r-- | drivers/clk/renesas/r8a77995-cpg-mssr.c | 17 | ||||
| -rw-r--r-- | drivers/clk/renesas/rcar-gen3-cpg.h | 5 |
2 files changed, 14 insertions, 8 deletions
diff --git a/drivers/clk/renesas/r8a77995-cpg-mssr.c b/drivers/clk/renesas/r8a77995-cpg-mssr.c index 83e8e9b..ee4061f 100644 --- a/drivers/clk/renesas/r8a77995-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77995-cpg-mssr.c @@ -71,18 +71,14 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1), DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1), - DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), - - DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, - CLK_RPCSRC), - DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, - R8A77995_CLK_RPC), + DEF_FIXED_RPCSRC_D3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1), DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32), DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000), /* Core Clock Outputs */ + DEF_FIXED("za2", R8A77995_CLK_ZA2, CLK_PLL0D3, 2, 1), DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1), DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1), @@ -110,7 +106,11 @@ static const struct cpg_core_clk r8a77995_core_clks[] = { DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2), DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4), - DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268), + DEF_GEN3_SDH("sd0h", R8A77995_CLK_SD0H, CLK_SDSRC, 0x268), + DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, R8A77995_CLK_SD0H, 0x268), + + DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC), + DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2, R8A77995_CLK_RPC), DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244), DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014), @@ -166,6 +166,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { DEF_MOD("du1", 723, R8A77995_CLK_S1D1), DEF_MOD("du0", 724, R8A77995_CLK_S1D1), DEF_MOD("lvds", 727, R8A77995_CLK_S2D1), + DEF_MOD("mlp", 802, R8A77995_CLK_S2D1), DEF_MOD("vin4", 807, R8A77995_CLK_S1D2), DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2), DEF_MOD("imr0", 823, R8A77995_CLK_S1D2), @@ -179,7 +180,7 @@ static const struct mssr_mod_clk r8a77995_mod_clks[] = { DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2), DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4), DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4), - DEF_MOD("rpc", 917, R8A77995_CLK_RPC), + DEF_MOD("rpc-if", 917, R8A77995_CLK_RPCD2), DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2), DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2), DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2), diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index 9ca42c2..9159071 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -25,6 +25,7 @@ enum rcar_gen3_clk_types { CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ CLK_TYPE_GEN3_RPCSRC, + CLK_TYPE_GEN3_D3_RPCSRC, CLK_TYPE_GEN3_E3_RPCSRC, CLK_TYPE_GEN3_RPC, CLK_TYPE_GEN3_RPCD2, @@ -70,6 +71,10 @@ enum rcar_gen3_clk_types { #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) +#define DEF_FIXED_RPCSRC_D3(_name, _id, _parent0, _parent1) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN3_D3_RPCSRC, \ + (_parent0) << 16 | (_parent1), .div = 5) + #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \ (_parent0) << 16 | (_parent1), .div = 8) |