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authorTom Rini <trini@konsulko.com>2019-10-30 09:04:52 -0400
committerTom Rini <trini@konsulko.com>2019-10-30 09:04:52 -0400
commitcc64810dc6234a3537502a05988fa7a1a6fa5d55 (patch)
treec4fa2eb538e6805a6c6080dea5b8fc03a7a8dc15
parentffc379b42c85466e1dd4c8fee8268801f26d2ab8 (diff)
parent5f19c9302133cda54d5d1a6b1caa400260de9192 (diff)
downloadu-boot-cc64810dc6234a3537502a05988fa7a1a6fa5d55.zip
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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- H6 dts(i) sync (Clément) - H6 PIO (Icenowy) - Fix pll1 clock calculation (Stefan) - H6 dram, half DQ (Jernej) - A64 OLinuXino eMMC (Sunil)
-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/sun50i-a64-olinuxino-emmc.dts23
-rw-r--r--arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi12
-rw-r--r--arch/arm/dts/sun50i-h6-beelink-gs1.dts76
-rw-r--r--arch/arm/dts/sun50i-h6-pine-h64.dts12
-rw-r--r--arch/arm/dts/sun50i-h6.dtsi46
-rw-r--r--arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h1
-rw-r--r--arch/arm/include/asm/arch-sunxi/gpio.h3
-rw-r--r--arch/arm/mach-sunxi/Kconfig3
-rw-r--r--arch/arm/mach-sunxi/board.c9
-rw-r--r--arch/arm/mach-sunxi/clock_sun6i.c2
-rw-r--r--arch/arm/mach-sunxi/dram_sun50i_h6.c78
-rw-r--r--board/sunxi/MAINTAINERS5
-rw-r--r--cmd/Kconfig1
-rw-r--r--configs/a64-olinuxino-emmc_defconfig17
-rw-r--r--configs/aristainetos2_defconfig1
-rw-r--r--configs/aristainetos2b_defconfig1
-rw-r--r--configs/aristainetos_defconfig1
-rw-r--r--configs/cm_fx6_defconfig1
-rw-r--r--configs/socfpga_arria5_defconfig1
-rw-r--r--configs/socfpga_cyclone5_defconfig1
-rw-r--r--configs/socfpga_dbm_soc1_defconfig1
-rw-r--r--configs/socfpga_de0_nano_soc_defconfig1
-rw-r--r--configs/socfpga_de10_nano_defconfig1
-rw-r--r--configs/socfpga_is1_defconfig1
-rw-r--r--configs/socfpga_mcvevk_defconfig1
-rw-r--r--configs/socfpga_sockit_defconfig1
-rw-r--r--configs/socfpga_socrates_defconfig1
-rw-r--r--configs/socfpga_sr1500_defconfig1
-rw-r--r--configs/socfpga_vining_fpga_defconfig1
-rw-r--r--configs/sopine_baseboard_defconfig1
-rw-r--r--configs/stm32mp15_basic_defconfig1
-rw-r--r--doc/driver-model/spi-howto.rst8
-rw-r--r--drivers/mtd/spi/Kconfig14
-rw-r--r--drivers/mtd/spi/Makefile2
-rw-r--r--drivers/mtd/spi/sf_internal.h2
-rw-r--r--drivers/mtd/spi/sf_probe.c6
-rw-r--r--drivers/mtd/spi/spi-nor-core.c8
-rw-r--r--drivers/mtd/spi/spi-nor-ids.c19
-rw-r--r--drivers/spi/Kconfig18
-rw-r--r--drivers/spi/ath79_spi.c2
-rw-r--r--drivers/spi/bcm63xx_hsspi.c2
-rw-r--r--drivers/spi/bcm63xx_spi.c2
-rw-r--r--drivers/spi/designware_spi.c16
-rw-r--r--drivers/spi/sandbox_spi.c2
-rw-r--r--drivers/spi/spi-uclass.c7
-rw-r--r--drivers/spi/tegra20_sflash.c2
-rw-r--r--include/configs/aristainetos-common.h1
-rw-r--r--include/configs/cm_fx6.h7
-rw-r--r--include/configs/da850evm.h7
-rw-r--r--include/configs/dh_imx6.h1
-rw-r--r--include/configs/display5.h1
-rw-r--r--include/configs/gw_ventana.h10
-rw-r--r--include/configs/rcar-gen2-common.h4
-rw-r--r--include/configs/socfpga_common.h4
-rw-r--r--include/spi.h2
56 files changed, 359 insertions, 94 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 6a7dbb6..47978e7 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -540,6 +540,7 @@ dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-nanopi-a64.dtb \
sun50i-a64-oceanic-5205-5inmfd.dtb \
sun50i-a64-olinuxino.dtb \
+ sun50i-a64-olinuxino-emmc.dtb \
sun50i-a64-orangepi-win.dtb \
sun50i-a64-pine64-lts.dtb \
sun50i-a64-pine64-plus.dtb \
diff --git a/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts b/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts
new file mode 100644
index 0000000..96ab022
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-olinuxino-emmc.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2018 Martin Ayotte <martinayotte@gmail.com>
+ * Copyright (C) 2019 Sunil Mohan Adapa <sunil@medhas.org>
+ */
+
+#include "sun50i-a64-olinuxino.dts"
+
+/ {
+ model = "Olimex A64-Olinuxino-eMMC";
+ compatible = "olimex,a64-olinuxino-emmc", "allwinner,sun50i-a64";
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins>;
+ vmmc-supply = <&reg_dcdc1>;
+ vqmmc-supply = <&reg_dcdc1>;
+ bus-width = <8>;
+ non-removable;
+ cap-mmc-hw-reset;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi b/arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi
new file mode 100644
index 0000000..02b1ae0
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-sopine-baseboard-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Jagan Teki <jagan@amarulasolutions.com>
+ */
+
+#include "sunxi-u-boot.dtsi"
+
+/ {
+ aliases {
+ spi0 = &spi0;
+ };
+};
diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
index 54b0882..0dc33c9 100644
--- a/arch/arm/dts/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts
@@ -14,6 +14,7 @@
compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";
aliases {
+ ethernet0 = &emac;
serial0 = &uart0;
};
@@ -21,6 +22,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
leds {
compatible = "gpio-leds";
@@ -41,6 +53,40 @@
};
};
+&de {
+ status = "okay";
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ext_rgmii_pins>;
+ phy-mode = "rgmii";
+ phy-handle = <&ext_rgmii_phy>;
+ phy-supply = <&reg_aldo2>;
+ status = "okay";
+};
+
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+};
+
&mmc0 {
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
@@ -57,6 +103,15 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
+&pio {
+ vcc-pd-supply = <&reg_cldo1>;
+ vcc-pg-supply = <&reg_aldo1>;
+};
+
&r_i2c {
status = "okay";
@@ -177,8 +232,29 @@
};
};
+&r_pio {
+ /*
+ * PL0 and PL1 are used for PMIC I2C
+ * don't enable the pl-supply else
+ * it will fail at boot
+ *
+ * vcc-pl-supply = <&reg_aldo1>;
+ */
+ vcc-pm-supply = <&reg_aldo1>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usb2otg {
+ dr_mode = "host";
+ status = "okay";
+};
+
+&usb2phy {
+ usb0_vbus-supply = <&reg_vcc5v>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts
index 4802902..1898345 100644
--- a/arch/arm/dts/sun50i-h6-pine-h64.dts
+++ b/arch/arm/dts/sun50i-h6-pine-h64.dts
@@ -127,6 +127,12 @@
status = "okay";
};
+&pio {
+ vcc-pc-supply = <&reg_bldo2>;
+ vcc-pd-supply = <&reg_cldo1>;
+ vcc-pg-supply = <&reg_aldo1>;
+};
+
&r_i2c {
status = "okay";
@@ -243,10 +249,16 @@
pcf8563: rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
+ interrupt-parent = <&r_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
#clock-cells = <0>;
};
};
+&r_pio {
+ vcc-pm-supply = <&reg_aldo1>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_ph_pins>;
diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi
index e0dc4a0..a117f47 100644
--- a/arch/arm/dts/sun50i-h6.dtsi
+++ b/arch/arm/dts/sun50i-h6.dtsi
@@ -101,7 +101,7 @@
#size-cells = <1>;
ranges;
- display-engine@1000000 {
+ bus@1000000 {
compatible = "allwinner,sun50i-h6-de3",
"allwinner,sun50i-a64-de2";
reg = <0x1000000 0x400000>;
@@ -203,11 +203,32 @@
#reset-cells = <1>;
};
+ dma: dma-controller@3002000 {
+ compatible = "allwinner,sun50i-h6-dma";
+ reg = <0x03002000 0x1000>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>;
+ clock-names = "bus", "mbus";
+ dma-channels = <16>;
+ dma-requests = <46>;
+ resets = <&ccu RST_BUS_DMA>;
+ #dma-cells = <1>;
+ };
+
sid: sid@3006000 {
compatible = "allwinner,sun50i-h6-sid";
reg = <0x03006000 0x400>;
};
+ watchdog: watchdog@30090a0 {
+ compatible = "allwinner,sun50i-h6-wdt",
+ "allwinner,sun6i-a31-wdt";
+ reg = <0x030090a0 0x20>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ /* Broken on some H6 boards */
+ status = "disabled";
+ };
+
pio: pinctrl@300b000 {
compatible = "allwinner,sun50i-h6-pinctrl";
reg = <0x0300b000 0x400>;
@@ -243,6 +264,18 @@
bias-pull-up;
};
+ /*
+ * /omit-if-no-ref/ isn't supported by U-boot
+ * keep this comment to avoid bad sync with Linux
+ */
+ mmc1_pins: mmc1-pins {
+ pins = "PG0", "PG1", "PG2", "PG3",
+ "PG4", "PG5";
+ function = "mmc1";
+ drive-strength = <30>;
+ bias-pull-up;
+ };
+
mmc2_pins: mmc2-pins {
pins = "PC1", "PC4", "PC5", "PC6",
"PC7", "PC8", "PC9", "PC10",
@@ -294,6 +327,8 @@
resets = <&ccu RST_BUS_MMC1>;
reset-names = "ahb";
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins>;
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
@@ -445,7 +480,6 @@
resets = <&ccu RST_BUS_OHCI3>,
<&ccu RST_BUS_EHCI3>;
phys = <&usb2phy 3>;
- phy-names = "usb";
status = "disabled";
};
@@ -457,7 +491,6 @@
<&ccu CLK_USB_OHCI3>;
resets = <&ccu RST_BUS_OHCI3>;
phys = <&usb2phy 3>;
- phy-names = "usb";
status = "disabled";
};
@@ -613,6 +646,13 @@
#reset-cells = <1>;
};
+ r_watchdog: watchdog@7020400 {
+ compatible = "allwinner,sun50i-h6-wdt",
+ "allwinner,sun6i-a31-wdt";
+ reg = <0x07020400 0x20>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
r_intc: interrupt-controller@7021000 {
compatible = "allwinner,sun50i-h6-r-intc",
"allwinner,sun6i-a31-r-intc";
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
index 0a1da02..49a8a66 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h6.h
@@ -315,6 +315,7 @@ struct dram_para {
u8 cols;
u8 rows;
u8 ranks;
+ u8 bus_full_width;
const u8 dx_read_delays[NR_OF_BYTE_LANES][RD_LINES_PER_BYTE_LANE];
const u8 dx_write_delays[NR_OF_BYTE_LANES][WR_LINES_PER_BYTE_LANE];
};
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h
index 40a3f84..a646ea6 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -73,6 +73,9 @@ struct sunxi_gpio_reg {
struct sunxi_gpio_int gpio_int;
};
+#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
+#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
+
#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) - SUNXI_GPIO_L])
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index ffdf09f..16d41b8 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -275,7 +275,10 @@ config MACH_SUN9I
config MACH_SUN50I
bool "sun50i (Allwinner A64)"
select ARM64
+ select SPI
select DM_I2C
+ select DM_SPI if SPI
+ select DM_SPI_FLASH
select PHY_SUN4I_USB
select SUN6I_PRCM
select SUNXI_DE2
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 8e9bb63..db50636 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map;
static int gpio_init(void)
{
+ __maybe_unused uint val;
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
@@ -139,6 +140,14 @@ static int gpio_init(void)
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
+#ifdef CONFIG_MACH_SUN50I_H6
+ /* Update PIO power bias configuration by copy hardware detected value */
+ val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+ writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+ val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+ writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+#endif
+
return 0;
}
diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
index 1628f3a..6ca38f7 100644
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -118,7 +118,7 @@ void clock_set_pll1(unsigned int clk)
if (clk > 1152000000) {
k = 2;
} else if (clk > 768000000) {
- k = 3;
+ k = 4;
m = 2;
}
diff --git a/arch/arm/mach-sunxi/dram_sun50i_h6.c b/arch/arm/mach-sunxi/dram_sun50i_h6.c
index 2a8275d..9375db7 100644
--- a/arch/arm/mach-sunxi/dram_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/dram_sun50i_h6.c
@@ -201,6 +201,9 @@ static void mctl_set_addrmap(struct dram_para *para)
u8 rows = para->rows;
u8 ranks = para->ranks;
+ if (!para->bus_full_width)
+ cols -= 1;
+
/* Ranks */
if (ranks == 2)
mctl_ctl->addrmap[0] = rows + cols - 3;
@@ -213,6 +216,10 @@ static void mctl_set_addrmap(struct dram_para *para)
/* Columns */
mctl_ctl->addrmap[2] = 0;
switch (cols) {
+ case 7:
+ mctl_ctl->addrmap[3] = 0x1F1F1F00;
+ mctl_ctl->addrmap[4] = 0x1F1F;
+ break;
case 8:
mctl_ctl->addrmap[3] = 0x1F1F0000;
mctl_ctl->addrmap[4] = 0x1F1F;
@@ -300,13 +307,16 @@ static void mctl_com_init(struct dram_para *para)
reg_val = 0x3f00;
clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
- /* TODO: half DQ, DDR4 */
- reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) |
- MSTR_ACTIVE_RANKS(para->ranks);
+ /* TODO: DDR4 */
+ reg_val = MSTR_BURST_LENGTH(8) | MSTR_ACTIVE_RANKS(para->ranks);
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
reg_val |= MSTR_DEVICETYPE_LPDDR3;
if (para->type == SUNXI_DRAM_TYPE_DDR3)
reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
+ if (para->bus_full_width)
+ reg_val |= MSTR_BUSWIDTH_FULL;
+ else
+ reg_val |= MSTR_BUSWIDTH_HALF;
writel(reg_val | BIT(31), &mctl_ctl->mstr);
if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
@@ -333,7 +343,10 @@ static void mctl_com_init(struct dram_para *para)
}
writel(reg_val, &mctl_ctl->odtcfg);
- /* TODO: half DQ */
+ if (!para->bus_full_width) {
+ writel(0x0, &mctl_phy->dx[2].gcr[0]);
+ writel(0x0, &mctl_phy->dx[3].gcr[0]);
+ }
}
static void mctl_bit_delay_set(struct dram_para *para)
@@ -514,22 +527,35 @@ static void mctl_channel_init(struct dram_para *para)
if (readl(&mctl_phy->pgsr[0]) & 0x400000)
{
- /*
- * Detect single rank.
- * TODO: also detect half DQ.
- */
+ /* Check for single rank and optionally half DQ. */
if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
- (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 &&
- (readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 &&
- (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) {
+ (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2) {
para->ranks = 1;
+
+ if ((readl(&mctl_phy->dx[2].rsr[0]) & 0x3) != 2 ||
+ (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) != 2)
+ para->bus_full_width = 0;
+
/* Restart DRAM initialization from scratch. */
mctl_core_init(para);
return;
}
- else {
- panic("This DRAM setup is currently not supported.\n");
+
+ /*
+ * Check for dual rank and half DQ. NOTE: This combination
+ * is highly unlikely and was not tested. Condition is the
+ * same as in libdram, though.
+ */
+ if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 0 &&
+ (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 0) {
+ para->bus_full_width = 0;
+
+ /* Restart DRAM initialization from scratch. */
+ mctl_core_init(para);
+ return;
}
+
+ panic("This DRAM setup is currently not supported.\n");
}
if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
@@ -557,11 +583,8 @@ static void mctl_channel_init(struct dram_para *para)
static void mctl_auto_detect_dram_size(struct dram_para *para)
{
- /* TODO: non-LPDDR3, half DQ */
- /*
- * Detect rank number by the code in mctl_channel_init. Furtherly
- * when DQ detection is available it will also be executed there.
- */
+ /* TODO: non-(LP)DDR3 */
+ /* Detect rank number and half DQ by the code in mctl_channel_init. */
mctl_core_init(para);
/* detect row address bits */
@@ -570,8 +593,9 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
mctl_core_init(para);
for (para->rows = 13; para->rows < 18; para->rows++) {
- /* 8 banks, 8 bit per byte and 32 bit width */
- if (mctl_mem_matches((1 << (para->rows + para->cols + 5))))
+ /* 8 banks, 8 bit per byte and 16/32 bit width */
+ if (mctl_mem_matches((1 << (para->rows + para->cols +
+ 4 + para->bus_full_width))))
break;
}
@@ -580,18 +604,21 @@ static void mctl_auto_detect_dram_size(struct dram_para *para)
mctl_core_init(para);
for (para->cols = 8; para->cols < 11; para->cols++) {
- /* 8 bits per byte and 32 bit width */
- if (mctl_mem_matches(1 << (para->cols + 2)))
+ /* 8 bits per byte and 16/32 bit width */
+ if (mctl_mem_matches(1 << (para->cols + 1 +
+ para->bus_full_width)))
break;
}
}
unsigned long mctl_calc_size(struct dram_para *para)
{
- /* TODO: non-LPDDR3, half DQ */
+ u8 width = para->bus_full_width ? 4 : 2;
+
+ /* TODO: non-(LP)DDR3 */
- /* 8 banks, 32-bit (4 byte) data width */
- return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
+ /* 8 banks */
+ return (1ULL << (para->cols + para->rows + 3)) * width * para->ranks;
}
#define SUN50I_H6_LPDDR3_DX_WRITE_DELAYS \
@@ -625,6 +652,7 @@ unsigned long sunxi_dram_init(void)
.ranks = 2,
.cols = 11,
.rows = 14,
+ .bus_full_width = 1,
#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
.type = SUNXI_DRAM_TYPE_LPDDR3,
.dx_read_delays = SUN50I_H6_LPDDR3_DX_READ_DELAYS,
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS
index 88f1353..a2adf89 100644
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -106,6 +106,11 @@ M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
F: configs/a64-olinuxino_defconfig
+A64-OLINUXINO-EMMC BOARD
+M: Sunil Mohan Adapa <sunil@medhas.org>
+S: Maintained
+F: configs/a64-olinuxino-emmc_defconfig
+
A80 OPTIMUS BOARD
M: Chen-Yu Tsai <wens@csie.org>
S: Maintained
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 82b5d30..b08a709 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -1168,6 +1168,7 @@ config CMD_SDRAM
config CMD_SF
bool "sf"
depends on DM_SPI_FLASH || SPI_FLASH
+ default y if DM_SPI_FLASH
help
SPI Flash support
diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig
new file mode 100644
index 0000000..56153e3
--- /dev/null
+++ b/configs/a64-olinuxino-emmc_defconfig
@@ -0,0 +1,17 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I=y
+CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_USE_PREBOOT=y
+# CONFIG_CMD_FLASH is not set
+# CONFIG_SPL_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-olinuxino-emmc"
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE=y
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig
index 18ef5d2..0bfc117 100644
--- a/configs/aristainetos2_defconfig
+++ b/configs/aristainetos2_defconfig
@@ -44,6 +44,7 @@ CONFIG_SF_DEFAULT_CS=1
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHYLIB=y
diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig
index 1054c05..e2da747 100644
--- a/configs/aristainetos2b_defconfig
+++ b/configs/aristainetos2b_defconfig
@@ -42,6 +42,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHYLIB=y
diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig
index 4080a7b..5caf95c 100644
--- a/configs/aristainetos_defconfig
+++ b/configs/aristainetos_defconfig
@@ -43,6 +43,7 @@ CONFIG_SF_DEFAULT_BUS=3
CONFIG_SF_DEFAULT_MODE=0
CONFIG_SF_DEFAULT_SPEED=20000000
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
CONFIG_PHYLIB=y
diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig
index eed0558..fbaf79d 100644
--- a/configs/cm_fx6_defconfig
+++ b/configs/cm_fx6_defconfig
@@ -72,6 +72,7 @@ CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_SST=y
CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHYLIB=y
CONFIG_MII=y
CONFIG_DM_PMIC=y
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig
index 9325467..51f559c 100644
--- a/configs/socfpga_arria5_defconfig
+++ b/configs/socfpga_arria5_defconfig
@@ -47,6 +47,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig
index 8e5b2e2..c648113 100644
--- a/configs/socfpga_cyclone5_defconfig
+++ b/configs/socfpga_cyclone5_defconfig
@@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig
index c73f382..414f131 100644
--- a/configs/socfpga_dbm_soc1_defconfig
+++ b/configs/socfpga_dbm_soc1_defconfig
@@ -46,6 +46,7 @@ CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD_DEVICE=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig
index 80ccb33..6eb052e 100644
--- a/configs/socfpga_de0_nano_soc_defconfig
+++ b/configs/socfpga_de0_nano_soc_defconfig
@@ -43,6 +43,7 @@ CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD_DEVICE=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig
index 98e80b7..6b8b5b4 100644
--- a/configs/socfpga_de10_nano_defconfig
+++ b/configs/socfpga_de10_nano_defconfig
@@ -39,6 +39,7 @@ CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
CONFIG_MTD_DEVICE=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/socfpga_is1_defconfig b/configs/socfpga_is1_defconfig
index 99cdb26..38b9f6c 100644
--- a/configs/socfpga_is1_defconfig
+++ b/configs/socfpga_is1_defconfig
@@ -43,6 +43,7 @@ CONFIG_SYS_I2C_DW=y
CONFIG_MTD_DEVICE=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig
index e977cd7..605ffd7 100644
--- a/configs/socfpga_mcvevk_defconfig
+++ b/configs/socfpga_mcvevk_defconfig
@@ -42,6 +42,7 @@ CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_DM_MMC=y
CONFIG_MMC_DW=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
CONFIG_ETH_DESIGNWARE=y
diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig
index b570b9d..cae6f7b 100644
--- a/configs/socfpga_sockit_defconfig
+++ b/configs/socfpga_sockit_defconfig
@@ -48,6 +48,7 @@ CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig
index 9eac00e..9cb1daa 100644
--- a/configs/socfpga_socrates_defconfig
+++ b/configs/socfpga_socrates_defconfig
@@ -48,6 +48,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig
index 092347a..c48bbb0 100644
--- a/configs/socfpga_sr1500_defconfig
+++ b/configs/socfpga_sr1500_defconfig
@@ -49,6 +49,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SF_DEFAULT_SPEED=100000000
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
CONFIG_PHY_MARVELL=y
CONFIG_DM_ETH=y
CONFIG_PHY_GIGE=y
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig
index a9c594e..80733ba 100644
--- a/configs/socfpga_vining_fpga_defconfig
+++ b/configs/socfpga_vining_fpga_defconfig
@@ -72,6 +72,7 @@ CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_SPI_FLASH_MTD=y
CONFIG_MTD_UBI_FASTMAP=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ90X1=y
diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig
index 5833234..c9123fd 100644
--- a/configs/sopine_baseboard_defconfig
+++ b/configs/sopine_baseboard_defconfig
@@ -10,6 +10,7 @@ CONFIG_DRAM_ZQ=3881949
CONFIG_MMC0_CD_PIN=""
CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_SPL_SPI_SUNXI=y
+CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_USE_PREBOOT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x8000
diff --git a/configs/stm32mp15_basic_defconfig b/configs/stm32mp15_basic_defconfig
index c54feb0..2a54e71 100644
--- a/configs/stm32mp15_basic_defconfig
+++ b/configs/stm32mp15_basic_defconfig
@@ -90,6 +90,7 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_SPI_FLASH_MTD=y
+CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_DWC_ETH_QOS=y
CONFIG_PHY=y
diff --git a/doc/driver-model/spi-howto.rst b/doc/driver-model/spi-howto.rst
index 5540eb7..9631a50 100644
--- a/doc/driver-model/spi-howto.rst
+++ b/doc/driver-model/spi-howto.rst
@@ -116,7 +116,7 @@ Put this code at the bottom of your existing driver file:
static int exynos_cs_info(struct udevice *bus, uint cs,
struct spi_cs_info *info)
{
- return -ENODEV;
+ return -EINVAL;
}
static const struct dm_spi_ops exynos_spi_ops = {
@@ -633,9 +633,9 @@ is not obvious from outside the driver. In this case you can provide a
method for cs_info() to deal with this. If you don't provide it, then the
device tree will be used to determine what chip selects are valid.
-Return -ENODEV if the supplied chip select is invalid, or 0 if it is valid.
-If you don't provide the cs_info() method, -ENODEV is assumed for all
-chip selects that do not appear in the device tree.
+Return -EINVAL if the supplied chip select is invalid, or 0 if it is valid.
+If you don't provide the cs_info() method, 0 is assumed for all chip selects
+that do not appear in the device tree.
Test it
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index d3b007a..d77f818 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -3,6 +3,7 @@ menu "SPI Flash Support"
config DM_SPI_FLASH
bool "Enable Driver Model for SPI flash"
depends on DM && DM_SPI
+ imply SPI_FLASH
help
Enable driver model for SPI flash. This SPI flash interface
(spi_flash_probe(), spi_flash_write(), etc.) is then
@@ -26,11 +27,10 @@ config SPI_FLASH_SANDBOX
stored in a file on the host filesystem.
config SPI_FLASH
- bool "Legacy SPI Flash Interface support"
- depends on SPI
+ bool "SPI Flash Core Interface support"
select SPI_MEM
help
- Enable the legacy SPI flash support. This will include basic
+ Enable the SPI flash Core support. This will include basic
standard support for things like probing, read / write, and
erasing through cmd_sf interface.
@@ -196,4 +196,12 @@ config SPI_FLASH_MTD
If unsure, say N
+config SPL_SPI_FLASH_MTD
+ bool "SPI flash MTD support for SPL"
+ depends on SPI_FLASH
+ help
+ Enable the MTD support for the SPI flash layer in SPL.
+
+ If unsure, say N
+
endmenu # menu "SPI Flash Support"
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index 20db101..b5dfa30 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -19,5 +19,5 @@ endif
obj-$(CONFIG_SPI_FLASH) += spi-nor.o
obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
-obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
+obj-$(CONFIG_$(SPL_)SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index bb8c19a..5c64303 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -77,7 +77,7 @@ extern const struct flash_info spi_nor_ids[];
int spi_flash_cmd_get_sw_write_prot(struct spi_flash *flash);
-#ifdef CONFIG_SPI_FLASH_MTD
+#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
int spi_flash_mtd_register(struct spi_flash *flash);
void spi_flash_mtd_unregister(void);
#endif
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 73297e1..f051e47 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -44,7 +44,7 @@ static int spi_flash_probe_slave(struct spi_flash *flash)
if (ret)
goto err_read_id;
-#ifdef CONFIG_SPI_FLASH_MTD
+#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
ret = spi_flash_mtd_register(flash);
#endif
@@ -83,7 +83,7 @@ struct spi_flash *spi_flash_probe(unsigned int busnum, unsigned int cs,
void spi_flash_free(struct spi_flash *flash)
{
-#ifdef CONFIG_SPI_FLASH_MTD
+#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
spi_flash_mtd_unregister();
#endif
spi_free_slave(flash->spi);
@@ -152,7 +152,7 @@ static int spi_flash_std_probe(struct udevice *dev)
static int spi_flash_std_remove(struct udevice *dev)
{
-#ifdef CONFIG_SPI_FLASH_MTD
+#if CONFIG_IS_ENABLED(SPI_FLASH_MTD)
spi_flash_mtd_unregister();
#endif
return 0;
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 990e39d..5a8c084 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -380,12 +380,12 @@ static int spi_nor_fsr_ready(struct spi_nor *nor)
if (fsr & (FSR_E_ERR | FSR_P_ERR)) {
if (fsr & FSR_E_ERR)
- dev_dbg(nor->dev, "Erase operation failed.\n");
+ dev_err(nor->dev, "Erase operation failed.\n");
else
- dev_dbg(nor->dev, "Program operation failed.\n");
+ dev_err(nor->dev, "Program operation failed.\n");
if (fsr & FSR_PT_ERR)
- dev_dbg(nor->dev,
+ dev_err(nor->dev,
"Attempted to modify a protected sector.\n");
nor->write_reg(nor, SPINOR_OP_CLFSR, NULL, 0);
@@ -1916,7 +1916,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
erasesize = 1U << erasesize;
opcode = (half >> 8) & 0xff;
-#ifdef CONFIG_MTD_SPI_NOR_USE_4K_SECTORS
+#ifdef CONFIG_SPI_FLASH_USE_4K_SECTORS
if (erasesize == SZ_4K) {
nor->erase_opcode = opcode;
mtd->erasesize = erasesize;
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
index 6996c0a..d3b8457 100644
--- a/drivers/mtd/spi/spi-nor-ids.c
+++ b/drivers/mtd/spi/spi-nor-ids.c
@@ -58,7 +58,7 @@
* All newly added entries should describe *hardware* and should use SECT_4K
* (or SECT_4K_PMC) if hardware supports erasing 4 KiB sectors. For usage
* scenarios excluding small sectors there is config option that can be
- * disabled: CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
+ * disabled: CONFIG_SPI_FLASH_USE_4K_SECTORS.
* For historical (and compatibility) reasons (before we got above config) some
* old entries may be missing 4K flag.
*/
@@ -75,6 +75,7 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("at45db161d", 0x1f2600, 0, 64 * 1024, 32, SECT_4K) },
{ INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) },
{ INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) },
+ { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) },
{ INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_EON /* EON */
@@ -128,6 +129,8 @@ const struct flash_info spi_nor_ids[] = {
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ INFO("is25wp128", 0x9d7018, 0, 64 * 1024, 256,
SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
+ { INFO("is25wp256", 0x9d7019, 0, 64 * 1024, 512,
+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
#endif
#ifdef CONFIG_SPI_FLASH_MACRONIX /* MACRONIX */
/* Macronix */
@@ -161,12 +164,16 @@ const struct flash_info spi_nor_ids[] = {
{ INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
{ INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) },
- { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
- { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
+ { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) },
+ { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) },
+ { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) },
{ INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
- SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
- { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
- { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
+ USE_FSR) },
+ { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
+ { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
+ { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
{ INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
{ INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b8ca2bd..7be867d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -1,5 +1,22 @@
menuconfig SPI
bool "SPI Support"
+ help
+ The "Serial Peripheral Interface" is a low level synchronous
+ protocol. Chips that support SPI can have data transfer rates
+ up to several tens of Mbit/sec. Chips are addressed with a
+ controller and a chipselect. Most SPI slaves don't support
+ dynamic device discovery; some are even write-only or read-only.
+
+ SPI is widely used by microcontrollers to talk with sensors,
+ eeprom and flash memory, codecs and various other controller
+ chips, analog to digital (and d-to-a) converters, and more.
+ MMC and SD cards can be accessed using SPI protocol; and for
+ DataFlash cards used in MMC sockets, SPI must always be used.
+
+ SPI is one of a family of similar protocols using a four wire
+ interface (select, clock, data in, data out) including Microwire
+ (half duplex), SSP, SSI, and PSP. This driver framework should
+ work with most such devices and controllers.
if SPI
@@ -243,6 +260,7 @@ config SPI_SIFIVE
config SPI_SUNXI
bool "Allwinner SoC SPI controllers"
+ default ARCH_SUNXI
help
Enable the Allwinner SoC SPi controller driver.
diff --git a/drivers/spi/ath79_spi.c b/drivers/spi/ath79_spi.c
index 4fd3c05..2070692 100644
--- a/drivers/spi/ath79_spi.c
+++ b/drivers/spi/ath79_spi.c
@@ -198,7 +198,7 @@ static int ath79_cs_info(struct udevice *bus, uint cs,
{
/* Always allow activity on CS 0/1/2 */
if (cs >= 3)
- return -ENODEV;
+ return -EINVAL;
return 0;
}
diff --git a/drivers/spi/bcm63xx_hsspi.c b/drivers/spi/bcm63xx_hsspi.c
index e82b80c..529adfb 100644
--- a/drivers/spi/bcm63xx_hsspi.c
+++ b/drivers/spi/bcm63xx_hsspi.c
@@ -108,7 +108,7 @@ static int bcm63xx_hsspi_cs_info(struct udevice *bus, uint cs,
if (cs >= priv->num_cs) {
printf("no cs %u\n", cs);
- return -ENODEV;
+ return -EINVAL;
}
return 0;
diff --git a/drivers/spi/bcm63xx_spi.c b/drivers/spi/bcm63xx_spi.c
index 4d19e03..69f88c9 100644
--- a/drivers/spi/bcm63xx_spi.c
+++ b/drivers/spi/bcm63xx_spi.c
@@ -130,7 +130,7 @@ static int bcm63xx_spi_cs_info(struct udevice *bus, uint cs,
if (cs >= priv->num_cs) {
printf("no cs %u\n", cs);
- return -ENODEV;
+ return -EINVAL;
}
return 0;
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index 7d58cfa..91e613e 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -518,8 +518,22 @@ static int dw_spi_set_mode(struct udevice *bus, uint mode)
static int dw_spi_remove(struct udevice *bus)
{
struct dw_spi_priv *priv = dev_get_priv(bus);
+ int ret;
+
+ ret = reset_release_bulk(&priv->resets);
+ if (ret)
+ return ret;
- return reset_release_bulk(&priv->resets);
+#if CONFIG_IS_ENABLED(CLK)
+ ret = clk_disable(&priv->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_free(&priv->clk);
+ if (ret)
+ return ret;
+#endif
+ return 0;
}
static const struct dm_spi_ops dw_spi_ops = {
diff --git a/drivers/spi/sandbox_spi.c b/drivers/spi/sandbox_spi.c
index 906401e..16473ec 100644
--- a/drivers/spi/sandbox_spi.c
+++ b/drivers/spi/sandbox_spi.c
@@ -117,7 +117,7 @@ static int sandbox_cs_info(struct udevice *bus, uint cs,
{
/* Always allow activity on CS 0 */
if (cs >= 1)
- return -ENODEV;
+ return -EINVAL;
return 0;
}
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.c
index a4d1b65..9475160 100644
--- a/drivers/spi/spi-uclass.c
+++ b/drivers/spi/spi-uclass.c
@@ -261,11 +261,10 @@ int spi_cs_info(struct udevice *bus, uint cs, struct spi_cs_info *info)
return ops->cs_info(bus, cs, info);
/*
- * We could assume there is at least one valid chip select, but best
- * to be sure and return an error in this case. The driver didn't
- * care enough to tell us.
+ * We could assume there is at least one valid chip select.
+ * The driver didn't care enough to tell us.
*/
- return -ENODEV;
+ return 0;
}
int spi_find_bus_and_cs(int busnum, int cs, struct udevice **busp,
diff --git a/drivers/spi/tegra20_sflash.c b/drivers/spi/tegra20_sflash.c
index a54b10f..567e33f 100644
--- a/drivers/spi/tegra20_sflash.c
+++ b/drivers/spi/tegra20_sflash.c
@@ -78,7 +78,7 @@ int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
{
/* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
if (cs != 0)
- return -ENODEV;
+ return -EINVAL;
else
return 0;
}
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h
index e998d9b..b451c7e 100644
--- a/include/configs/aristainetos-common.h
+++ b/include/configs/aristainetos-common.h
@@ -30,7 +30,6 @@
#define CONFIG_ETHPRIME "FEC"
#define CONFIG_FEC_MXC_PHYADDR 0
-#define CONFIG_SPI_FLASH_MTD
#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
#define CONFIG_EXTRA_ENV_SETTINGS \
diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index b957e9c..c1a6625 100644
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -38,13 +38,6 @@
#define CONFIG_MXC_UART_BASE UART4_BASE
#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200}
-/* SPI flash */
-
-/* MTD support */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SPI_FLASH_MTD
-#endif
-
/* Environment */
#define CONFIG_ENV_SECT_SIZE (64 * 1024)
#define CONFIG_ENV_SIZE (8 * 1024)
diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index 41f0813..6876134 100644
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -190,16 +190,11 @@
#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
#endif
-#ifdef CONFIG_USE_SPIFLASH
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
+#if defined(CONFIG_USE_SPIFLASH) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
#define CONFIG_ENV_SIZE (64 << 10)
#define CONFIG_ENV_OFFSET (512 << 10)
#define CONFIG_ENV_SECT_SIZE (64 << 10)
#endif
-#ifdef CONFIG_SPL_BUILD
-#undef CONFIG_SPI_FLASH_MTD
-#endif
-#endif
/*
* U-Boot general configuration
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h
index a854d0b..86c1192 100644
--- a/include/configs/dh_imx6.h
+++ b/include/configs/dh_imx6.h
@@ -59,7 +59,6 @@
#if defined(CONFIG_SPL_BUILD)
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
-#undef CONFIG_SPI_FLASH_MTD
#endif
/* UART */
diff --git a/include/configs/display5.h b/include/configs/display5.h
index d806415..65dae1f 100644
--- a/include/configs/display5.h
+++ b/include/configs/display5.h
@@ -39,7 +39,6 @@
#if defined(CONFIG_SPL_BUILD)
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
-#undef CONFIG_SPI_FLASH_MTD
#endif
/* Below values are "dummy" - only to avoid build break */
diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index a27627e..e543061 100644
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -47,15 +47,7 @@
#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE UART2_BASE
-#ifdef CONFIG_SPI_FLASH
-
-/* SPI */
-#ifdef CONFIG_CMD_SF
- #define CONFIG_SPI_FLASH_MTD
- /* GPIO 3-19 (21248) */
-#endif
-
-#elif defined(CONFIG_SPL_NAND_SUPPORT)
+#if !defined(CONFIG_SPI_FLASH) && defined(CONFIG_SPL_NAND_SUPPORT)
/* Enable NAND support */
#ifdef CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE 1
diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h
index 71a5909..e940a8b 100644
--- a/include/configs/rcar-gen2-common.h
+++ b/include/configs/rcar-gen2-common.h
@@ -46,11 +46,9 @@
#define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
/* SF MTD */
-#if defined(CONFIG_SPI_FLASH_MTD) && !defined(CONFIG_SPL_BUILD)
-#else
+#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_SPI
#undef CONFIG_DM_SPI_FLASH
-#undef CONFIG_SPI_FLASH_MTD
#endif
/* Timer */
diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 94268ed..baa2143 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -132,10 +132,6 @@
/*
* QSPI support
*/
-/* Enable multiple SPI NOR flash manufacturers */
-#ifndef CONFIG_SPL_BUILD
-#define CONFIG_SPI_FLASH_MTD
-#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
unsigned int cm_get_qspi_controller_clk_hz(void);
diff --git a/include/spi.h b/include/spi.h
index 5eec0c4..3f79168 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -458,7 +458,7 @@ struct dm_spi_ops {
* @cs: The chip select (0..n-1)
* @info: Returns information about the chip select, if valid.
* On entry info->dev is NULL
- * @return 0 if OK (and @info is set up), -ENODEV if the chip select
+ * @return 0 if OK (and @info is set up), -EINVAL if the chip select
* is invalid, other -ve value on error
*/
int (*cs_info)(struct udevice *bus, uint cs, struct spi_cs_info *info);