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authorSamuel Holland <samuel@sholland.org>2021-09-12 09:47:24 -0500
committerAndre Przywara <andre.przywara@arm.com>2021-10-11 10:46:44 +0100
commitc61897bf029e86a46cdba53ced48889eae1cd468 (patch)
tree4b95b3e616cb94debc3a7fb6b8fd6cd053657e30
parent8fe8ff34110792f8a4ed4ab7a4f4e14c82feb452 (diff)
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clk: sunxi: Add support for I2C gates/resets
Currently, the I2C clocks are configured in the sunxi board code. Add the I2C clocks to the DM clock driver so they can be enabled from the DM I2C driver using the normal uclass methods. Signed-off-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat
-rw-r--r--drivers/clk/sunxi/clk_a10.c5
-rw-r--r--drivers/clk/sunxi/clk_a10s.c3
-rw-r--r--drivers/clk/sunxi/clk_a23.c6
-rw-r--r--drivers/clk/sunxi/clk_a31.c8
-rw-r--r--drivers/clk/sunxi/clk_a64.c6
-rw-r--r--drivers/clk/sunxi/clk_a80.c10
-rw-r--r--drivers/clk/sunxi/clk_a83t.c6
-rw-r--r--drivers/clk/sunxi/clk_h3.c6
-rw-r--r--drivers/clk/sunxi/clk_h6.c10
-rw-r--r--drivers/clk/sunxi/clk_h616.c12
-rw-r--r--drivers/clk/sunxi/clk_r40.c10
-rw-r--r--drivers/clk/sunxi/clk_v3s.c4
12 files changed, 86 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 1342a6c..90b929d 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -31,6 +31,11 @@ static struct ccu_clk_gate a10_gates[] = {
[CLK_AHB_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_APB1_I2C3] = GATE(0x06c, BIT(3)),
+ [CLK_APB1_I2C4] = GATE(0x06c, BIT(15)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index d30846a..addf4f4 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -25,6 +25,9 @@ static struct ccu_clk_gate a10s_gates[] = {
[CLK_AHB_SPI1] = GATE(0x060, BIT(21)),
[CLK_AHB_SPI2] = GATE(0x060, BIT(22)),
+ [CLK_APB1_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB1_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB1_I2C2] = GATE(0x06c, BIT(2)),
[CLK_APB1_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB1_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB1_UART2] = GATE(0x06c, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 52de1cb..c45d2c3 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -23,6 +23,9 @@ static struct ccu_clk_gate a23_gates[] = {
[CLK_BUS_EHCI] = GATE(0x060, BIT(26)),
[CLK_BUS_OHCI] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -53,6 +56,9 @@ static struct ccu_reset a23_resets[] = {
[RST_BUS_EHCI] = RESET(0x2c0, BIT(26)),
[RST_BUS_OHCI] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 28ff821..251fc3b 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -30,6 +30,10 @@ static struct ccu_clk_gate a31_gates[] = {
[CLK_AHB1_OHCI1] = GATE(0x060, BIT(30)),
[CLK_AHB1_OHCI2] = GATE(0x060, BIT(31)),
+ [CLK_APB2_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_APB2_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_APB2_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_APB2_I2C3] = GATE(0x06c, BIT(3)),
[CLK_APB2_UART0] = GATE(0x06c, BIT(16)),
[CLK_APB2_UART1] = GATE(0x06c, BIT(17)),
[CLK_APB2_UART2] = GATE(0x06c, BIT(18)),
@@ -71,6 +75,10 @@ static struct ccu_reset a31_resets[] = {
[RST_AHB1_OHCI1] = RESET(0x2c0, BIT(30)),
[RST_AHB1_OHCI2] = RESET(0x2c0, BIT(31)),
+ [RST_APB2_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_APB2_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_APB2_I2C2] = RESET(0x2d8, BIT(2)),
+ [RST_APB2_I2C3] = RESET(0x2d8, BIT(3)),
[RST_APB2_UART0] = RESET(0x2d8, BIT(16)),
[RST_APB2_UART1] = RESET(0x2d8, BIT(17)),
[RST_APB2_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index a46cb27..1004a79 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -26,6 +26,9 @@ static const struct ccu_clk_gate a64_gates[] = {
[CLK_BUS_OHCI0] = GATE(0x060, BIT(28)),
[CLK_BUS_OHCI1] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -60,6 +63,9 @@ static const struct ccu_reset a64_resets[] = {
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(28)),
[RST_BUS_OHCI1] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index bda7835..8a0834d 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -25,6 +25,11 @@ static const struct ccu_clk_gate a80_gates[] = {
[CLK_BUS_SPI2] = GATE(0x580, BIT(22)),
[CLK_BUS_SPI3] = GATE(0x580, BIT(23)),
+ [CLK_BUS_I2C0] = GATE(0x594, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x594, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x594, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x594, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x594, BIT(4)),
[CLK_BUS_UART0] = GATE(0x594, BIT(16)),
[CLK_BUS_UART1] = GATE(0x594, BIT(17)),
[CLK_BUS_UART2] = GATE(0x594, BIT(18)),
@@ -40,6 +45,11 @@ static const struct ccu_reset a80_resets[] = {
[RST_BUS_SPI2] = RESET(0x5a0, BIT(22)),
[RST_BUS_SPI3] = RESET(0x5a0, BIT(23)),
+ [RST_BUS_I2C0] = RESET(0x5b4, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x5b4, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x5b4, BIT(2)),
+ [RST_BUS_I2C3] = RESET(0x5b4, BIT(3)),
+ [RST_BUS_I2C4] = RESET(0x5b4, BIT(4)),
[RST_BUS_UART0] = RESET(0x5b4, BIT(16)),
[RST_BUS_UART1] = RESET(0x5b4, BIT(17)),
[RST_BUS_UART2] = RESET(0x5b4, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 5c3cc5b..8c6043f 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -25,6 +25,9 @@ static struct ccu_clk_gate a83t_gates[] = {
[CLK_BUS_EHCI1] = GATE(0x060, BIT(27)),
[CLK_BUS_OHCI0] = GATE(0x060, BIT(29)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -57,6 +60,9 @@ static struct ccu_reset a83t_resets[] = {
[RST_BUS_EHCI1] = RESET(0x2c0, BIT(27)),
[RST_BUS_OHCI0] = RESET(0x2c0, BIT(29)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index 3adc6a9..59afba5 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -30,6 +30,9 @@ static struct ccu_clk_gate h3_gates[] = {
[CLK_BUS_OHCI2] = GATE(0x060, BIT(30)),
[CLK_BUS_OHCI3] = GATE(0x060, BIT(31)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -74,6 +77,9 @@ static struct ccu_reset h3_resets[] = {
[RST_BUS_EPHY] = RESET(0x2c8, BIT(2)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index 86496ed..4a53788 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -22,6 +22,11 @@ static struct ccu_clk_gate h6_gates[] = {
[CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
[CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
@@ -57,6 +62,11 @@ static struct ccu_reset h6_resets[] = {
[RST_BUS_UART2] = RESET(0x90c, BIT(18)),
[RST_BUS_UART3] = RESET(0x90c, BIT(19)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index c39ba06..af97d3b 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -24,6 +24,12 @@ static struct ccu_clk_gate h616_gates[] = {
[CLK_BUS_UART4] = GATE(0x90c, BIT(4)),
[CLK_BUS_UART5] = GATE(0x90c, BIT(5)),
+ [CLK_BUS_I2C0] = GATE(0x91c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x91c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x91c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x91c, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x91c, BIT(4)),
+
[CLK_SPI0] = GATE(0x940, BIT(31)),
[CLK_SPI1] = GATE(0x944, BIT(31)),
@@ -68,6 +74,12 @@ static struct ccu_reset h616_resets[] = {
[RST_BUS_UART4] = RESET(0x90c, BIT(20)),
[RST_BUS_UART5] = RESET(0x90c, BIT(21)),
+ [RST_BUS_I2C0] = RESET(0x91c, BIT(16)),
+ [RST_BUS_I2C1] = RESET(0x91c, BIT(17)),
+ [RST_BUS_I2C2] = RESET(0x91c, BIT(18)),
+ [RST_BUS_I2C3] = RESET(0x91c, BIT(19)),
+ [RST_BUS_I2C4] = RESET(0x91c, BIT(20)),
+
[RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
[RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index a261296..4d5b69a 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -32,6 +32,11 @@ static struct ccu_clk_gate r40_gates[] = {
[CLK_BUS_GMAC] = GATE(0x064, BIT(17)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
+ [CLK_BUS_I2C2] = GATE(0x06c, BIT(2)),
+ [CLK_BUS_I2C3] = GATE(0x06c, BIT(3)),
+ [CLK_BUS_I2C4] = GATE(0x06c, BIT(15)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -77,6 +82,11 @@ static struct ccu_reset r40_resets[] = {
[RST_BUS_GMAC] = RESET(0x2c4, BIT(17)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
+ [RST_BUS_I2C2] = RESET(0x2d8, BIT(2)),
+ [RST_BUS_I2C3] = RESET(0x2d8, BIT(3)),
+ [RST_BUS_I2C4] = RESET(0x2d8, BIT(15)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 34ccda7..cce5c65 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -20,6 +20,8 @@ static struct ccu_clk_gate v3s_gates[] = {
[CLK_BUS_SPI0] = GATE(0x060, BIT(20)),
[CLK_BUS_OTG] = GATE(0x060, BIT(24)),
+ [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)),
+ [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)),
[CLK_BUS_UART0] = GATE(0x06c, BIT(16)),
[CLK_BUS_UART1] = GATE(0x06c, BIT(17)),
[CLK_BUS_UART2] = GATE(0x06c, BIT(18)),
@@ -38,6 +40,8 @@ static struct ccu_reset v3s_resets[] = {
[RST_BUS_SPI0] = RESET(0x2c0, BIT(20)),
[RST_BUS_OTG] = RESET(0x2c0, BIT(24)),
+ [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)),
+ [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)),
[RST_BUS_UART0] = RESET(0x2d8, BIT(16)),
[RST_BUS_UART1] = RESET(0x2d8, BIT(17)),
[RST_BUS_UART2] = RESET(0x2d8, BIT(18)),
generated by cgit v1.1 at 2024-07-10 20:35:51 +0000