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author | Tom Rini <trini@konsulko.com> | 2021-10-12 11:49:15 -0400 |
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committer | Tom Rini <trini@konsulko.com> | 2021-10-12 11:49:15 -0400 |
commit | 618c77d99a23c72b16e31a7380b6f3b96e6dfa40 (patch) | |
tree | 3c3c908810f0f7cc280e6279fdca5925a4d0c2f5 | |
parent | 2aab77f7263bb6e27120cfea82fc5efa4f625014 (diff) | |
parent | 1f83bda7886c0e3fbb9aaf1d36dcaac27a7c92ea (diff) | |
download | u-boot-618c77d99a23c72b16e31a7380b6f3b96e6dfa40.zip u-boot-618c77d99a23c72b16e31a7380b6f3b96e6dfa40.tar.gz u-boot-618c77d99a23c72b16e31a7380b6f3b96e6dfa40.tar.bz2 |
Merge tag 'u-boot-at91-2022.01-b' of https://source.denx.de/u-boot/custodians/u-boot-at91
Second set of u-boot-at91 features for the 2022.01 cycle:
This small feature set adds the support for PWM driver for the sama5d2
SoC. It also adds a node in the DT for this SoC.
-rw-r--r-- | arch/arm/dts/sama5d2.dtsi | 8 | ||||
-rw-r--r-- | doc/device-tree-bindings/pwm/pwm-at91.txt | 16 | ||||
-rw-r--r-- | drivers/pwm/Kconfig | 6 | ||||
-rw-r--r-- | drivers/pwm/Makefile | 1 | ||||
-rw-r--r-- | drivers/pwm/pwm-at91.c | 207 |
5 files changed, 238 insertions, 0 deletions
diff --git a/arch/arm/dts/sama5d2.dtsi b/arch/arm/dts/sama5d2.dtsi index d8a125b..038cd73 100644 --- a/arch/arm/dts/sama5d2.dtsi +++ b/arch/arm/dts/sama5d2.dtsi @@ -671,6 +671,14 @@ status = "disabled"; }; + pwm0: pwm@f802c000 { + compatible = "atmel,sama5d2-pwm"; + reg = <0xf802c000 0x4000>; + clocks = <&pwm_clk>; + #pwm-cells = <3>; + status = "disabled"; + }; + rstc@f8048000 { compatible = "atmel,sama5d3-rstc"; reg = <0xf8048000 0x10>; diff --git a/doc/device-tree-bindings/pwm/pwm-at91.txt b/doc/device-tree-bindings/pwm/pwm-at91.txt new file mode 100644 index 0000000..a03da40 --- /dev/null +++ b/doc/device-tree-bindings/pwm/pwm-at91.txt @@ -0,0 +1,16 @@ +Microchip AT91 PWM controller for SAMA5D2 + +Required properties: + - compatible: Should be "atmel,sama5d2-pwm" + - reg: Physical base address and length of the controller's registers. + - clocks: Should contain a clock identifier for the PWM's parent clock. + - #pwm-cells: Should be 3. + +Example: + +pwm0: pwm@f802c000 { + compatible = "atmel,sama5d2-pwm"; + reg = <0xf802c000 0x4000>; + clocks = <&pwm_clk>; + #pwm-cells = <3>; +}; diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index cf7f4c6..669d3fa 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -9,6 +9,12 @@ config DM_PWM frequency/period can be controlled along with the proportion of that time that the signal is high. +config PWM_AT91 + bool "Enable support for PWM found on AT91 SoC's" + depends on DM_PWM && ARCH_AT91 + help + Support for PWM hardware on AT91 based SoC. + config PWM_CROS_EC bool "Enable support for the Chrome OS EC PWM" depends on DM_PWM diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 10d244b..55f2bc0 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_DM_PWM) += pwm-uclass.o +obj-$(CONFIG_PWM_AT91) += pwm-at91.o obj-$(CONFIG_PWM_CROS_EC) += cros_ec_pwm.o obj-$(CONFIG_PWM_EXYNOS) += exynos_pwm.o obj-$(CONFIG_PWM_IMX) += pwm-imx.o pwm-imx-util.o diff --git a/drivers/pwm/pwm-at91.c b/drivers/pwm/pwm-at91.c new file mode 100644 index 0000000..95597aee --- /dev/null +++ b/drivers/pwm/pwm-at91.c @@ -0,0 +1,207 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PWM support for Microchip AT91 architectures. + * + * Copyright (C) 2021 Microchip Technology Inc. and its subsidiaries + * + * Author: Dan Sneddon <daniel.sneddon@microchip.com> + * + * Based on drivers/pwm/pwm-atmel.c from Linux. + */ +#include <clk.h> +#include <common.h> +#include <div64.h> +#include <dm.h> +#include <linux/bitops.h> +#include <linux/io.h> +#include <pwm.h> + +#define PERIOD_BITS 16 +#define PWM_MAX_PRES 10 +#define NSEC_PER_SEC 1000000000L + +#define PWM_ENA 0x04 +#define PWM_CHANNEL_OFFSET 0x20 +#define PWM_CMR 0x200 +#define PWM_CMR_CPRE_MSK GENMASK(3, 0) +#define PWM_CMR_CPOL BIT(9) +#define PWM_CDTY 0x204 +#define PWM_CPRD 0x20C + +struct at91_pwm_priv { + void __iomem *base; + struct clk pclk; + u32 clkrate; +}; + +static int at91_pwm_calculate_cprd_and_pres(struct udevice *dev, + unsigned long clkrate, + uint period_ns, uint duty_ns, + unsigned long *cprd, u32 *pres) +{ + u64 cycles = period_ns; + int shift; + + /* Calculate the period cycles and prescale value */ + cycles *= clkrate; + do_div(cycles, NSEC_PER_SEC); + + /* + * The register for the period length is period_bits bits wide. + * So for each bit the number of clock cycles is wider divide the input + * clock frequency by two using pres and shift cprd accordingly. + */ + shift = fls(cycles) - PERIOD_BITS; + + if (shift > PWM_MAX_PRES) { + return -EINVAL; + } else if (shift > 0) { + *pres = shift; + cycles >>= *pres; + } else { + *pres = 0; + } + + *cprd = cycles; + + return 0; +} + +static void at91_pwm_calculate_cdty(uint period_ns, uint duty_ns, + unsigned long clkrate, unsigned long cprd, + u32 pres, unsigned long *cdty) +{ + u64 cycles = duty_ns; + + cycles *= clkrate; + do_div(cycles, NSEC_PER_SEC); + cycles >>= pres; + *cdty = cprd - cycles; +} + +/** + * Returns: channel status after set operation + */ +static bool at91_pwm_set(void __iomem *base, uint channel, bool enable) +{ + u32 val, cur_status; + + val = ioread32(base + PWM_ENA); + cur_status = !!(val & BIT(channel)); + + /* if channel is already in that state, do nothing */ + if (!(enable ^ cur_status)) + return cur_status; + + if (enable) + val |= BIT(channel); + else + val &= ~(BIT(channel)); + + iowrite32(val, base + PWM_ENA); + + return cur_status; +} + +static int at91_pwm_set_enable(struct udevice *dev, uint channel, bool enable) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + + at91_pwm_set(priv->base, channel, enable); + + return 0; +} + +static int at91_pwm_set_config(struct udevice *dev, uint channel, + uint period_ns, uint duty_ns) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + unsigned long cprd, cdty; + u32 pres, val; + int channel_enabled; + int ret; + + ret = at91_pwm_calculate_cprd_and_pres(dev, priv->clkrate, period_ns, + duty_ns, &cprd, &pres); + if (ret) + return ret; + + at91_pwm_calculate_cdty(period_ns, duty_ns, priv->clkrate, cprd, pres, &cdty); + + /* disable the channel */ + channel_enabled = at91_pwm_set(priv->base, channel, false); + + /* It is necessary to preserve CPOL, inside CMR */ + val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + val = (val & ~PWM_CMR_CPRE_MSK) | (pres & PWM_CMR_CPRE_MSK); + iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + + iowrite32(cprd, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CPRD); + + iowrite32(cdty, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CDTY); + + /* renable the channel if needed */ + if (channel_enabled) + at91_pwm_set(priv->base, channel, true); + + return 0; +} + +static int at91_pwm_set_invert(struct udevice *dev, uint channel, + bool polarity) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + u32 val; + + val = ioread32(priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + if (polarity) + val |= PWM_CMR_CPOL; + else + val &= ~PWM_CMR_CPOL; + iowrite32(val, priv->base + (channel * PWM_CHANNEL_OFFSET) + PWM_CMR); + + return 0; +} + +static int at91_pwm_probe(struct udevice *dev) +{ + struct at91_pwm_priv *priv = dev_get_priv(dev); + int ret; + + priv->base = dev_read_addr_ptr(dev); + if (!priv->base) + return -EINVAL; + + ret = clk_get_by_index(dev, 0, &priv->pclk); + if (ret) + return ret; + + /* clocks aren't ref-counted so just enabled them once here */ + ret = clk_enable(&priv->pclk); + if (ret) + return ret; + + priv->clkrate = clk_get_rate(&priv->pclk); + + return ret; +} + +static const struct pwm_ops at91_pwm_ops = { + .set_config = at91_pwm_set_config, + .set_enable = at91_pwm_set_enable, + .set_invert = at91_pwm_set_invert, +}; + +static const struct udevice_id at91_pwm_of_match[] = { + { .compatible = "atmel,sama5d2-pwm" }, + { } +}; + +U_BOOT_DRIVER(at91_pwm) = { + .name = "at91_pwm", + .id = UCLASS_PWM, + .of_match = at91_pwm_of_match, + .probe = at91_pwm_probe, + .priv_auto = sizeof(struct at91_pwm_priv), + .ops = &at91_pwm_ops, +}; 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