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| author | Chris Packham <judge.packham@gmail.com> | 2023-10-27 13:23:52 +1300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-11-17 11:58:26 -0500 |
| commit | ee23d7466c77d01ee63efb76db2c5fd3b7cdd6f7 (patch) | |
| tree | cb383519c0ed6adee8e4d0fd77433506928dc9d3 | |
| parent | ac33a7976a5631e05fdb8f6c75be5f824dcf5229 (diff) | |
| download | u-boot-ee23d7466c77d01ee63efb76db2c5fd3b7cdd6f7.zip u-boot-ee23d7466c77d01ee63efb76db2c5fd3b7cdd6f7.tar.gz u-boot-ee23d7466c77d01ee63efb76db2c5fd3b7cdd6f7.tar.bz2 | |
Revert "armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present"
This reverts commit c1da6fdb5c239b432440721772d993e63cfdeb20. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
| -rw-r--r-- | arch/arm/cpu/armv8/cache_v8.c | 6 | ||||
| -rw-r--r-- | arch/arm/include/asm/armv8/mmu.h | 10 |
2 files changed, 3 insertions, 13 deletions
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index cb1131a..4c6a1b1 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -94,15 +94,11 @@ u64 get_tcr(u64 *pips, u64 *pva_bits) if (el == 1) { tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; if (gd->arch.has_hafdbs) - tcr |= TCR_EL1_HA | TCR_EL1_HD; + tcr |= TCR_HA | TCR_HD; } else if (el == 2) { tcr = TCR_EL2_RSVD | (ips << 16); - if (gd->arch.has_hafdbs) - tcr |= TCR_EL2_HA | TCR_EL2_HD; } else { tcr = TCR_EL3_RSVD | (ips << 16); - if (gd->arch.has_hafdbs) - tcr |= TCR_EL3_HA | TCR_EL3_HD; } /* PTWs cacheable, inner/outer WBWA and inner shareable */ diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 4f0adb0..27658e5 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -102,14 +102,8 @@ #define TCR_TG0_16K (2 << 14) #define TCR_EPD1_DISABLE (1 << 23) -#define TCR_EL1_HA BIT(39) -#define TCR_EL1_HD BIT(40) - -#define TCR_EL2_HA BIT(21) -#define TCR_EL2_HD BIT(22) - -#define TCR_EL3_HA BIT(21) -#define TCR_EL3_HD BIT(22) +#define TCR_HA BIT(39) +#define TCR_HD BIT(40) #define TCR_EL1_RSVD (1U << 31) #define TCR_EL2_RSVD (1U << 31 | 1 << 23) |