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| author | Chris Packham <judge.packham@gmail.com> | 2023-10-27 13:23:54 +1300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-11-17 11:58:26 -0500 |
| commit | 0585c28fda1007e4a90dea5f70723cff0b63dd98 (patch) | |
| tree | d3a20d0d2c1d336f2591190205af48a69c274cd8 | |
| parent | eed8294b75a5908a486945ff6655d4dc9aae5fed (diff) | |
| download | u-boot-0585c28fda1007e4a90dea5f70723cff0b63dd98.zip u-boot-0585c28fda1007e4a90dea5f70723cff0b63dd98.tar.gz u-boot-0585c28fda1007e4a90dea5f70723cff0b63dd98.tar.bz2 | |
Revert "arm64: Use FEAT_HAFDBS to track dirty pages when available"WIP/2023-11-17-assorted-important-fixes
This reverts commit 6cdf6b7a340db4ddd008516181de7e08e3f8c213. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
| -rw-r--r-- | arch/arm/cpu/armv8/cache_v8.c | 16 | ||||
| -rw-r--r-- | arch/arm/include/asm/armv8/mmu.h | 14 | ||||
| -rw-r--r-- | arch/arm/include/asm/global_data.h | 1 |
3 files changed, 5 insertions, 26 deletions
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index 4760064..6973340 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -93,8 +93,6 @@ u64 get_tcr(u64 *pips, u64 *pva_bits) if (el == 1) { tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE; - if (gd->arch.has_hafdbs) - tcr |= TCR_HA | TCR_HD; } else if (el == 2) { tcr = TCR_EL2_RSVD | (ips << 16); } else { @@ -202,9 +200,6 @@ static void __cmo_on_leaves(void (*cmo_fn)(unsigned long, unsigned long), attrs != PTE_BLOCK_MEMTYPE(MT_NORMAL_NC)) continue; - if (gd->arch.has_hafdbs && (pte & (PTE_RDONLY | PTE_DBM)) != PTE_DBM) - continue; - end = va + BIT(level2shift(level)) - 1; /* No intersection with RAM? */ @@ -353,9 +348,6 @@ static void add_map(struct mm_region *map) if (va_bits < 39) level = 1; - if (gd->arch.has_hafdbs) - attrs |= PTE_DBM | PTE_RDONLY; - map_range(map->virt, map->phys, map->size, level, (u64 *)gd->arch.tlb_addr, attrs); } @@ -407,13 +399,7 @@ static int count_ranges(void) __weak u64 get_page_table_size(void) { u64 one_pt = MAX_PTE_ENTRIES * sizeof(u64); - u64 size, mmfr1; - - asm volatile("mrs %0, id_aa64mmfr1_el1" : "=r" (mmfr1)); - if ((mmfr1 & 0xf) == 2) - gd->arch.has_hafdbs = true; - else - gd->arch.has_hafdbs = false; + u64 size; /* Account for all page tables we would need to cover our memory map */ size = one_pt * count_ranges(); diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h index 27658e5..ce655ce 100644 --- a/arch/arm/include/asm/armv8/mmu.h +++ b/arch/arm/include/asm/armv8/mmu.h @@ -49,13 +49,10 @@ #define PTE_TYPE_BLOCK (1 << 0) #define PTE_TYPE_VALID (1 << 0) -#define PTE_RDONLY BIT(7) -#define PTE_DBM BIT(51) - -#define PTE_TABLE_PXN BIT(59) -#define PTE_TABLE_XN BIT(60) -#define PTE_TABLE_AP BIT(61) -#define PTE_TABLE_NS BIT(63) +#define PTE_TABLE_PXN (1UL << 59) +#define PTE_TABLE_XN (1UL << 60) +#define PTE_TABLE_AP (1UL << 61) +#define PTE_TABLE_NS (1UL << 63) /* * Block @@ -102,9 +99,6 @@ #define TCR_TG0_16K (2 << 14) #define TCR_EPD1_DISABLE (1 << 23) -#define TCR_HA BIT(39) -#define TCR_HD BIT(40) - #define TCR_EL1_RSVD (1U << 31) #define TCR_EL2_RSVD (1U << 31 | 1 << 23) #define TCR_EL3_RSVD (1U << 31 | 1 << 23) diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 1325b06..75bd9d5 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -52,7 +52,6 @@ struct arch_global_data { #if defined(CONFIG_ARM64) unsigned long tlb_fillptr; unsigned long tlb_emerg; - bool has_hafdbs; #endif #endif #ifdef CFG_SYS_MEM_RESERVE_SECURE |