diff options
author | Tom Rini <trini@konsulko.com> | 2023-10-12 16:59:51 -0400 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2023-10-12 17:01:24 -0400 |
commit | 32abaf168713c5b4c87e70de01a0f76bf87f873b (patch) | |
tree | f3ac7f73768c9d5be046bc2887aeb8e18c57d5ac | |
parent | 1b0ef92444fadb726d1ba180699149d22696caa2 (diff) | |
download | u-boot-TEST/remove-common-h-part1.zip u-boot-TEST/remove-common-h-part1.tar.gz u-boot-TEST/remove-common-h-part1.tar.bz2 |
riscv: Remove common.h usageTEST/remove-common-h-part1
We can remove common.h from most cases of the code here, and only a few
places need an additional header instead.
Signed-off-by: Tom Rini <trini@konsulko.com>
---
Cc: Rick Chen <rick@andestech.com>
Cc: Leo <ycliang@andestech.com>
34 files changed, 9 insertions, 32 deletions
diff --git a/arch/riscv/cpu/andesv5/cache.c b/arch/riscv/cpu/andesv5/cache.c index 40d77f6..269bb27 100644 --- a/arch/riscv/cpu/andesv5/cache.c +++ b/arch/riscv/cpu/andesv5/cache.c @@ -6,7 +6,6 @@ #include <asm/csr.h> #include <asm/asm.h> -#include <common.h> #include <cache.h> #include <cpu_func.h> #include <dm.h> diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index 06e379b..63bc24c 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -5,7 +5,6 @@ */ /* CPU specific code */ -#include <common.h> #include <cpu_func.h> #include <irq_func.h> #include <asm/cache.h> diff --git a/arch/riscv/cpu/andesv5/spl.c b/arch/riscv/cpu/andesv5/spl.c index 4138490..a13dc40 100644 --- a/arch/riscv/cpu/andesv5/spl.c +++ b/arch/riscv/cpu/andesv5/spl.c @@ -3,7 +3,6 @@ * Copyright (C) 2023 Andes Technology Corporation * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ -#include <common.h> #include <cpu_func.h> #include <hang.h> #include <init.h> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index c1a9638..ebd39cb 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <cpu.h> #include <dm.h> #include <dm/lists.h> diff --git a/arch/riscv/cpu/fu540/dram.c b/arch/riscv/cpu/fu540/dram.c index 94d8018..7b5a347 100644 --- a/arch/riscv/cpu/fu540/dram.c +++ b/arch/riscv/cpu/fu540/dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <fdtdec.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c index 8657fcd..61f5517 100644 --- a/arch/riscv/cpu/fu740/dram.c +++ b/arch/riscv/cpu/fu740/dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <fdtdec.h> #include <init.h> #include <linux/sizes.h> diff --git a/arch/riscv/cpu/generic/cpu.c b/arch/riscv/cpu/generic/cpu.c index d78e1a3..f13c189 100644 --- a/arch/riscv/cpu/generic/cpu.c +++ b/arch/riscv/cpu/generic/cpu.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <irq_func.h> #include <asm/cache.h> diff --git a/arch/riscv/cpu/generic/dram.c b/arch/riscv/cpu/generic/dram.c index 94d8018..7b5a347 100644 --- a/arch/riscv/cpu/generic/dram.c +++ b/arch/riscv/cpu/generic/dram.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <fdtdec.h> #include <init.h> #include <asm/global_data.h> diff --git a/arch/riscv/cpu/jh7110/dram.c b/arch/riscv/cpu/jh7110/dram.c index 1a9fa46..664b9b9 100644 --- a/arch/riscv/cpu/jh7110/dram.c +++ b/arch/riscv/cpu/jh7110/dram.c @@ -4,7 +4,6 @@ * Author: Yanhong Wang <yanhong.wang@starfivetech.com> */ -#include <common.h> #include <fdtdec.h> #include <init.h> #include <linux/sizes.h> diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 4047b10..6bdf8b9 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -3,7 +3,6 @@ * Copyright (C) 2022 StarFive Technology Co., Ltd. * Author: Yanhong Wang<yanhong.wang@starfivetech.com> */ -#include <common.h> #include <asm/arch/eeprom.h> #include <asm/csr.h> #include <asm/sections.h> diff --git a/arch/riscv/cpu/mtrap.S b/arch/riscv/cpu/mtrap.S index e40c7bd..6eb3ed1 100644 --- a/arch/riscv/cpu/mtrap.S +++ b/arch/riscv/cpu/mtrap.S @@ -11,7 +11,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <asm/encoding.h> #ifdef CONFIG_32BIT diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 30cf674..6cecadf 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -11,7 +11,6 @@ #include <asm-offsets.h> #include <config.h> -#include <common.h> #include <elf.h> #include <system-constants.h> #include <asm/encoding.h> diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index c7ed920..393d51c 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -7,6 +7,7 @@ #define _ASM_ANDES_CSR_H #include <asm/asm.h> +#include <linux/bitops.h> #include <linux/const.h> #define CSR_MCACHE_CTL 0x7ca diff --git a/arch/riscv/include/asm/arch-jh7110/eeprom.h b/arch/riscv/include/asm/arch-jh7110/eeprom.h index f354d5c..d2776d5 100644 --- a/arch/riscv/include/asm/arch-jh7110/eeprom.h +++ b/arch/riscv/include/asm/arch-jh7110/eeprom.h @@ -7,6 +7,8 @@ #ifndef _ASM_RISCV_EEPROM_H #define _ASM_RISCV_EEPROM_H +#include <linux/types.h> + u8 get_pcb_revision_from_eeprom(void); u32 get_ddr_size_from_eeprom(void); diff --git a/arch/riscv/include/asm/dma-mapping.h b/arch/riscv/include/asm/dma-mapping.h index 6ecadab..d0cc5d7 100644 --- a/arch/riscv/include/asm/dma-mapping.h +++ b/arch/riscv/include/asm/dma-mapping.h @@ -9,7 +9,6 @@ #ifndef __ASM_RISCV_DMA_MAPPING_H #define __ASM_RISCV_DMA_MAPPING_H -#include <common.h> #include <linux/types.h> #include <asm/cache.h> #include <cpu_func.h> diff --git a/arch/riscv/include/asm/smp.h b/arch/riscv/include/asm/smp.h index 4284a33..ee749dd 100644 --- a/arch/riscv/include/asm/smp.h +++ b/arch/riscv/include/asm/smp.h @@ -7,6 +7,8 @@ #ifndef _ASM_RISCV_SMP_H #define _ASM_RISCV_SMP_H +#include <linux/types.h> + /** * struct ipi_data - Inter-processor interrupt (IPI) data structure * diff --git a/arch/riscv/lib/aclint_ipi.c b/arch/riscv/lib/aclint_ipi.c index 90b8e12..dcd7e5e 100644 --- a/arch/riscv/lib/aclint_ipi.c +++ b/arch/riscv/lib/aclint_ipi.c @@ -8,7 +8,6 @@ * associated with software and timer interrupts. */ -#include <common.h> #include <dm.h> #include <regmap.h> #include <syscon.h> diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c index 7518408..c188bff 100644 --- a/arch/riscv/lib/andes_plicsw.c +++ b/arch/riscv/lib/andes_plicsw.c @@ -8,7 +8,6 @@ * similar to RISC-V PLIC. */ -#include <common.h> #include <dm.h> #include <asm/global_data.h> #include <dm/device-internal.h> diff --git a/arch/riscv/lib/asm-offsets.c b/arch/riscv/lib/asm-offsets.c index 452dfce..875bb9a 100644 --- a/arch/riscv/lib/asm-offsets.c +++ b/arch/riscv/lib/asm-offsets.c @@ -8,7 +8,6 @@ * assembly language modules. */ -#include <common.h> #include <asm/global_data.h> #include <linux/kbuild.h> diff --git a/arch/riscv/lib/boot.c b/arch/riscv/lib/boot.c index 778d011..03014c5 100644 --- a/arch/riscv/lib/boot.c +++ b/arch/riscv/lib/boot.c @@ -4,8 +4,7 @@ * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ -#include <common.h> -#include <command.h> +#include <asm/u-boot.h> unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc, char *const argv[]) diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c index cc30efc..f9e1e18 100644 --- a/arch/riscv/lib/bootm.c +++ b/arch/riscv/lib/bootm.c @@ -6,7 +6,6 @@ * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ -#include <common.h> #include <bootstage.h> #include <command.h> #include <dm.h> diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c index 686e699..c46b49e 100644 --- a/arch/riscv/lib/cache.c +++ b/arch/riscv/lib/cache.c @@ -4,7 +4,6 @@ * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ -#include <common.h> #include <cpu_func.h> void invalidate_icache_all(void) diff --git a/arch/riscv/lib/fdt_fixup.c b/arch/riscv/lib/fdt_fixup.c index 36c16e9..c658e72 100644 --- a/arch/riscv/lib/fdt_fixup.c +++ b/arch/riscv/lib/fdt_fixup.c @@ -6,7 +6,6 @@ #define LOG_CATEGORY LOGC_ARCH -#include <common.h> #include <fdt_support.h> #include <log.h> #include <mapmem.h> diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c index a65a5b8d..a82f48e 100644 --- a/arch/riscv/lib/image.c +++ b/arch/riscv/lib/image.c @@ -6,7 +6,6 @@ * Based on arm/lib/image.c */ -#include <common.h> #include <image.h> #include <mapmem.h> #include <errno.h> diff --git a/arch/riscv/lib/interrupts.c b/arch/riscv/lib/interrupts.c index e966afa..02dbcfd 100644 --- a/arch/riscv/lib/interrupts.c +++ b/arch/riscv/lib/interrupts.c @@ -10,7 +10,6 @@ */ #include <linux/compat.h> -#include <common.h> #include <efi_loader.h> #include <hang.h> #include <irq_func.h> diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c index 8779c61..712e1bd 100644 --- a/arch/riscv/lib/reset.c +++ b/arch/riscv/lib/reset.c @@ -3,7 +3,6 @@ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com> */ -#include <common.h> #include <command.h> #include <hang.h> diff --git a/arch/riscv/lib/sbi.c b/arch/riscv/lib/sbi.c index 55a3bc3..35a7d3b 100644 --- a/arch/riscv/lib/sbi.c +++ b/arch/riscv/lib/sbi.c @@ -7,7 +7,7 @@ * Taken from Linux arch/riscv/kernel/sbi.c */ -#include <common.h> +#include <errno.h> #include <asm/encoding.h> #include <asm/sbi.h> diff --git a/arch/riscv/lib/sbi_ipi.c b/arch/riscv/lib/sbi_ipi.c index d02e2b4..511d381 100644 --- a/arch/riscv/lib/sbi_ipi.c +++ b/arch/riscv/lib/sbi_ipi.c @@ -4,7 +4,6 @@ * Lukas Auer <lukas.auer@aisec.fraunhofer.de> */ -#include <common.h> #include <asm/encoding.h> #include <asm/sbi.h> diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c index 2815487..39b0248 100644 --- a/arch/riscv/lib/sifive_cache.c +++ b/arch/riscv/lib/sifive_cache.c @@ -3,9 +3,9 @@ * Copyright (C) 2021 SiFive, Inc */ -#include <common.h> #include <cache.h> #include <cpu_func.h> +#include <log.h> #include <dm.h> void enable_caches(void) diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c index f3cd8b9..a692f06 100644 --- a/arch/riscv/lib/smp.c +++ b/arch/riscv/lib/smp.c @@ -4,7 +4,6 @@ * Lukas Auer <lukas.auer@aisec.fraunhofer.de> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <asm/barrier.h> diff --git a/arch/riscv/lib/spl.c b/arch/riscv/lib/spl.c index 9b242ed..9a7a4f6 100644 --- a/arch/riscv/lib/spl.c +++ b/arch/riscv/lib/spl.c @@ -3,7 +3,6 @@ * Copyright (C) 2019 Fraunhofer AISEC, * Lukas Auer <lukas.auer@aisec.fraunhofer.de> */ -#include <common.h> #include <cpu_func.h> #include <hang.h> #include <init.h> diff --git a/board/AndesTech/ae350/ae350.c b/board/AndesTech/ae350/ae350.c index 1c2288b..36375d9 100644 --- a/board/AndesTech/ae350/ae350.c +++ b/board/AndesTech/ae350/ae350.c @@ -4,7 +4,7 @@ * Rick Chen, Andes Technology Corporation <rick@andestech.com> */ -#include <common.h> +#include <config.h> #include <cpu_func.h> #include <flash.h> #include <image.h> diff --git a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c index 2b985b9..938cede 100644 --- a/board/sifive/unmatched/hifive-platform-i2c-eeprom.c +++ b/board/sifive/unmatched/hifive-platform-i2c-eeprom.c @@ -9,7 +9,6 @@ * Timur Tabi (timur@freescale.com) */ -#include <common.h> #include <command.h> #include <env.h> #include <i2c.h> diff --git a/board/sifive/unmatched/unmatched.c b/board/sifive/unmatched/unmatched.c index 6675548..c869627 100644 --- a/board/sifive/unmatched/unmatched.c +++ b/board/sifive/unmatched/unmatched.c @@ -6,7 +6,6 @@ * Pragnesh Patel <pragnesh.patel@sifive.com> */ -#include <common.h> #include <cpu_func.h> #include <dm.h> #include <asm/sections.h> |