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| author | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2023-09-17 16:11:29 +0200 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2023-10-01 00:08:28 +0200 |
| commit | 0b93899bfb548a9590cc7723afb97a1f38f5232f (patch) | |
| tree | 7438dbb525ed7fcaecdc751d9edb6148507553c1 | |
| parent | 3e997e2d7a7956b3b5fd669019d1c50090a07a32 (diff) | |
| download | u-boot-0b93899bfb548a9590cc7723afb97a1f38f5232f.zip u-boot-0b93899bfb548a9590cc7723afb97a1f38f5232f.tar.gz u-boot-0b93899bfb548a9590cc7723afb97a1f38f5232f.tar.bz2 | |
clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.5.3
Synchronize R-Car R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.5.3,
commit 238589d0f7b421aae18c5704dc931595019fa6c7 .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
| -rw-r--r-- | drivers/clk/renesas/r8a7796-cpg-mssr.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 27cf62e..ea1f6d6 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -52,7 +52,7 @@ enum clk_ids { MOD_CLK_BASE }; -static const struct cpg_core_clk r8a7796_core_clks[] = { +static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { /* External Clock Inputs */ DEF_INPUT("extal", CLK_EXTAL), DEF_INPUT("extalr", CLK_EXTALR), @@ -128,7 +128,7 @@ static const struct cpg_core_clk r8a7796_core_clks[] = { DEF_BASE("r", R8A7796_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT), }; -static const struct mssr_mod_clk r8a7796_mod_clks[] = { +static struct mssr_mod_clk r8a7796_mod_clks[] __initdata = { DEF_MOD("fdp1-0", 119, R8A7796_CLK_S0D1), DEF_MOD("tmu4", 121, R8A7796_CLK_S0D6), DEF_MOD("tmu3", 122, R8A7796_CLK_S3D2), @@ -299,7 +299,7 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] = { (((md) & BIT(19)) >> 18) | \ (((md) & BIT(17)) >> 17)) -static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = { +static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] __initconst = { /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */ { 1, 192, 1, 192, 1, 16, }, { 1, 192, 1, 128, 1, 16, }, |