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2023-10-11small cleanupsdevel2Helge Deller2-4/+5
2023-10-09fix lasi keyboard in graphics modeHelge Deller2-9/+18
2023-10-09move CPU to end of listHelge Deller1-17/+6
2023-10-09ohci workHelge Deller3-51/+56
2023-10-09Fix graphics output on B160LHelge Deller4-8/+33
2023-10-08add new command lineHelge Deller1-0/+1
2023-10-08default all PCI devices as FIOHelge Deller1-5/+2
2023-10-08allow USB (ohci)Helge Deller1-3/+3
2023-10-08add command lineHelge Deller1-0/+3
2023-10-08parisc: Serial port works, c3700 works, everything OK.Helge Deller5-132/+380
2023-10-05serial Diva card works, no autodetection yetHelge Deller5-43/+43
2023-10-03initial work on making PCI patchs correctHelge Deller2-37/+154
2023-09-29make B160L work againHelge Deller2-7/+12
2023-09-29Block TLB only for 32-bit CPUsHelge Deller1-3/+10
2023-09-29fix scsi card in pci slotHelge Deller1-0/+3
2023-09-28more fixesHelge Deller1-1/+3
2023-09-28fix building IRTHelge Deller1-0/+3
2023-09-27build IOSAPIC IRT tableHelge Deller3-27/+53
2023-09-27detect all PCI devices on the bussesHelge Deller6-22/+57
2023-09-26cleanups for HP-UX, keep LASI UART, fix CPUIDHelge Deller2-11/+17
2023-09-26allow up to 16 CPUs, change to /elroy-pcihostHelge Deller3-3/+3
2023-09-26fix LSI detection, PCI mapping, PDC_MODELHelge Deller3-10/+23
2023-09-26enhance debug output for mallocHelge Deller1-1/+1
2023-09-26Fix DebugOutputPort for PA-RISCHelge Deller1-2/+3
2023-09-26pci detection on astro worksHelge Deller5-16/+84
2023-09-25astro added in pciHelge Deller5-4/+40
2023-09-25irq routing tabelleHelge Deller1-3/+3
2023-09-25erster IRQ versiucheHelge Deller1-10/+43
2023-09-24fix machine handover via fw_cfgHelge Deller1-1/+1
2023-09-24add Astro RTCHelge Deller1-13/+13
2023-09-23set 64-bit OS-capable flagHelge Deller1-1/+4
2023-09-23nicer text for CPU/machineHelge Deller1-2/+2
2023-09-23show emulated machineHelge Deller1-2/+2
2023-09-23detect CPU bit widthHelge Deller1-3/+10
2023-09-22wire up c3700 machine info, auto-add devices to keep listHelge Deller2-13/+35
2023-09-22hack model type to B160L (to avoid kernel crash with old qemu which tries to ↵Helge Deller1-1/+4
run 64-bit instruction in sr_disable_hash)
2023-09-21fix pdc_modelHelge Deller1-2/+2
2023-09-21add c3700 fileHelge Deller1-0/+280
2023-09-21initial c3700 supportHelge Deller3-28/+84
2023-09-18parisc: Add PDC_CACHE_RET_SPID functionHelge Deller1-0/+5
Signed-off-by: Helge Deller <deller@gmx.de>
2023-09-18parisc: Some more PDC constantsHelge Deller1-2/+25
Signed-off-by: Helge Deller <deller@gmx.de>
2023-09-16parisc: Fix serial output at early bootupHelge Deller1-3/+11
If some bug happens during early bootup, the mem_cons might not have been initialized yet. In that case use default PARISC_SERIAL_CONSOLE to show something. Signed-off-by: Helge Deller <deller@gmx.de>
2023-09-16esp-scsi: handle non-DMA SCSI commands with no data phaseMark Cave-Ayland1-1/+10
The existing esp-scsi state machine checks for the STAT_TC bit to exit state 1 but in the case where there is no data phase, a non-DMA command is executed which doesn't set STAT_TC. This only works because QEMU currently always sets STAT_TC just after issuing every SCSI command. Update the esp-scsi state machine so that in the case where there is no data phase, we immediately execute CMD_ICCS instead of waiting for STAT_TC to be set which will never happen with a non-DMA CMD_SELATN command. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20230807065300.366070-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2023-09-16esp-scsi: check for INTR_BS/INTR_FC instead of STAT_TC for command completionMark Cave-Ayland1-14/+22
The ESP SELATN command used to send SCSI commands from the ESP to the SCSI bus is not a DMA command and therefore does not affect the STAT_TC bit. The only reason this works at all is due to a bug in QEMU which (currently) always updates the STAT_TC bit in ESP_RSTAT regardless of the state of the ESP_CMD_DMA bit. According to the NCR datasheet [1] the INTR_BS/INTR_FC bits are set when the SELATN command has completed, so update the existing logic to check for these bits in ESP_RINTR instead. Note that the read of ESP_RINTR needs to be restricted to state == 0 as reading ESP_RINTR resets the ESP_RSTAT register which breaks the STAT_TC check when state == 1. This commit also includes an extra read of ESP_INTR to clear all the interrupt bits before submitting the SELATN command to ensure that we don't accidentally immediately progress to the data phase handling logic where ESP_RINTR bits have already been set by a previous ESP command. [1] "NCR 53C94, 53C95, 53C96 Advanced SCSI Controller" NCR_53C94_53C95_53C96_Data_Sheet_Feb90.pdf Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20230807065300.366070-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2023-09-16esp-scsi: flush FIFO before sending SCSI commandMark Cave-Ayland1-0/+4
The ESP FIFO is used as a buffer for DMA requests and so isn't guaranteed to be empty in the case of SCSI errors or a mixed DMA/non-DMA request. Flush the FIFO before sending a SCSI command to guarantee that it is correctly positioned at the start of the FIFO. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230807065300.366070-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2023-09-13parisc: SEABIOS_HPPA_VERSION 9seabios-hppa-v9devel-btlb-2Helge Deller1-2/+2
Enhancements: - Support for Block-TLB (BTLB) on 32-bit CPUs Signed-off-by: Helge Deller <deller@gmx.de>
2023-09-13parisc: Implement Block-TLB (BTLB) support for 32-bit CPUsHelge Deller1-20/+11
SeaBIOS has no information about the lower implementation details for Block-TLB (or generic TLB) support, so it simply hands over the parameters in the CPU registers provided by the operating system to the PDC_BLOCK_TLB PDC function to QEMU. Calling QEMU happens via a diagnostics instruction (diag 0x100) which QEMU will respond to. Older QEMU versions without the BTLB support will simply log that they ignored the diag instruction, and SeaBIOS will return PDC_BAD_OPTION for this PDC call in that case. Signed-off-by: Helge Deller <deller@gmx.de>
2023-06-24parisc: SEABIOS_HPPA_VERSION 8seabios-hppa-v8hppa-reboot-fixHelge Deller1-2/+2
Fixes - boot of HP-UX with SMP, and - reboot of Linux and HP-UX with SMP Enhancements: - show qemu version in boot menu - adds exit menu entry in boot menu to quit emulation - allow to trace PCD_CHASSIS codes more specifically Signed-off-by: Helge Deller <deller@gmx.de>
2023-06-24parisc: Drop unnecessary SMP wake-up codeHelge Deller2-13/+1
Signed-off-by: Helge Deller <deller@gmx.de>
2023-06-24parisc: Enable PSW_Q bit at bootupHelge Deller1-1/+2
Qemu currently only supports PSW_Q handling, so enable it by default. Signed-off-by: Helge Deller <deller@gmx.de>
generated by cgit v1.1 at 2024-07-10 18:58:37 +0000