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When used to read characters from the terminal (e.g., when the SBI
console is used via ecall from linux with `console=hvc0`), we must
acknowledge receipt of each character to "pop" it off the LiteUART
hardware queue, and allow the next character to be made available.
Fixes: 52af6e4b ("lib: utils: Add LiteX UART support")
Suggested-by: Dolu1990 <charles.papon.90@gmail.com>
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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In DT, multiple reset devices may use the same driver, and they
may have different priorities. If rc is returned after the first
initialization, the highest priority device may be lost.
Fixes: a73ff043e991 (lib: utils/reset: Fix fdt_reset to search for more dt nodes)
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Save/restore sbi_trap_context during domain context switching to
ensure proper trap handling and isolation. This maintains correct
domain-specific state, avoiding context corruption.
Fixes: abea949721bc ("lib: sbi: Introduce trap context")
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Alvin Chang <alvinga@andestech.com>
Tested-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yong Li <yong.li@intel.com>
Tested-by: Yong Li <yong.li@intel.com>
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If there are multiple dt nodes, the previous code only tries to match
the first one, which may lose initialization.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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When the dt node has a status property and the value is not ok or
okay, skip initializing reset.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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If there are multiple dt nodes, the previous code only tries to match
the first one, which may lose initialization.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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When the dt node has a status property and the value is not ok or
okay, skip initializing serial.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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When the dt node has a status property and the value is not ok or
okay, skip initializing irqchip.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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When the dt node has a status property and the value is not ok or
okay, skip initializing timer.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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When the dt node has a status property and the value is not ok or
okay, skip initializing ipi.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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During Linux AIA driver review, the APLIC DT property for interrupt
delegation was renamed to "riscv,delegation" so let's use the new DT
property name and fallback to old DT property name if the new DT
property name is not available.
Fixes: 34612193af92 ("lib: utils/irqchip: Add FDT based driver for APLIC")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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"gpio-poweroff" and "gpio-restart" always set gpio to high to
active the function, but some chips need a low signal to active.
Fortunately, it can be achieved by setting GPIO_FLAG_ACTIVE_LOW
for the gpio. Implement this flag support for the gpio library
so the gpio reset can function well.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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The spec states that a6, a7, flags and sepc are writable but the
implementation was not allowing that. Add support for these 4 writable
attributes.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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imsic_get_target_file()
Add extra sanity checks to prevent the caller getting the invalid result from
imsic_get_data() or imsic_get_target_file() when imsic is not initialized
correctly.
Signed-off-by: Cyan Yang <cyan.yang@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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The current mlevel imsic check is only for the platform, which
may cause hart without imsic in the platform to trigger an
illegal instruction exception when initializing imsic. For
example, the platform contains a management hart that only
supports wired interrupts.
This patch will check if each hart supports Smaia extension
before doing imsic initialization to avoid triggering illegal
instruction exceptions.
Signed-off-by: Cheng Yang <yangcheng.work@foxmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Currently, the sbi_sse_exit() gets event in a loop but does not put
it back after use. This results in global events remaining locked
causing hangs on sub-sequent calls to sse_event_get() for global
events.
Fixes: c8cdf01d8f3a ("lib: sbi: Add support for Supervisor Software Events extension")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
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SG2042 uses an onboard MCU to provide reset function.
Add reset driver to support this onboard MCU.
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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The inline function can simplify the code by setting some call
restrictions. This ensures logical smoothness
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Modify the return value of the sbi_dbtr_shmem_disabled function to
bool to make the semantics clearer.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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The previous code detected shmem_phys_hi and shmem_phys_lo as two
addresses. fix this bug
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
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Obtaining a 64-bit address under rv64 does not require combining
32-bit registers
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
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After getting hart_shmem_base, dbtr_thishart_state_ptr cannot be
empty. So remove check code.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
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When only phys_hi is equal to SBI_DBTR_SHMEM_INVALID_ADDR, it may be
a legal address. The old code would modify the legal address.
Signed-off-by: Xiang W <wxjstz@126.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
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Add spinlock protection to avoid race condition on assigned_harts
during domain context switching. Also, rename/add variables for
accessing the corresponding domain of target/current context.
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Although Mstatus.MPV is set, before executing mret, access to VS mode
registers should use the actual register addresses, not the pseudonyms
of S registers.
Signed-off-by: Pope B.Lei <popeblei@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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When registering an SSE event, check for the handler_entry_pc to belong
to supervisor mode domain using sbi_domain_check_addr_range().
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reported-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Rather then passing 1 to sbi_domain_check_addr_range() for supervisor
mode, use PRV_S.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Move the enable callback call before sending the IPI. Even though the
event is locked and no race condition can happen, this is more logical.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reported-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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The list loop below that check is actually not looping if the list is
empty so there was no need for this check.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reported-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Rather than checking 32bits overflow with some absolute value, check the
value to be different from the cast itself.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reported-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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There was a naming incoherency between enabled events list lock/unlock.
Rename sse_hart_unlock() to sse_enabled_event_unlock() to be coherent
and reword comments above lock()/unlock() functions.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Fix some errors spotted by Samuel while reviewing the SSE implementation.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reported-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Implement the test which covers some of the functions from the
`riscv_locks.h` file. This test consists of 3 test cases:
1) For lock/unlock functions
2) Unsuccessful trylock (the lock was previously taken)
3) Successful trylock (the lock is free and can be taken)
Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Implement the test which covers some of the functions from the
`riscv_atomic.h` header file. The test contains 9 test cases:
1) atomic read/write test
2) add/return test
3) sub/return test
4) cmpxchg test
5) atomic_xchg test
6) atomic_raw_set_bit test
7) atomic_raw_clear_bit test
8) atomic_set_bit test
9) atomic_clear_bit test
Some of the test cases operate on the `test_atomic` variable. It gets
initialized in the suite init function.
Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Allow to define an init function for the test suite. It could help us
to initialize global variable once, and use them in multiple test cases
after the initialization.
For instance, if multiple test cases use the same atomic_t var, it
could be helpful to call ATOMIC_INIT once during the suite
initialization.
Signed-off-by: Ivan Orlov <ivan.orlov0322@gmail.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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After calling fdt_node_offset_by_compatible() we must check its return
value and not an unrelated value.
Addresses-Coverity-ID: 1584993 Logically dead code
Fixes: 67ce5a763cfb ("platform: generic: Add support for specify coldboot harts in DT")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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sse_event_get() may return NULL. We should not dereference the return value
in sbi_sse_exit() without checking.
Fixes: c8cdf01d8f3a ("lib: sbi: Add support for Supervisor Software Events extension")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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The sbi_hart_ext[] array is missing these two extensions ids. It is
expected that this array contains all the extensions declaration at the
same index of the SBI_HART_EXT_* define. Without this, when adding a new
extension, there is a mismatch between ids and extension names and it
can even display corrupted extension names.
Addresses-Coverity-ID: 1584994 Out-of-bounds read
Fixes: 6bb6b61c27eb ("lib: sbi: Add support for smcsrind and smcdeleg")
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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S-mode CSRs
SCOUNTEREN and SENVCFG may not be supported on certain RISC-V core,
so check the existence of these CSRs via privilege spec version to
prevent illegal instructions.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Signed-off-by: Alvin Chang <alvinga@andestech.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Currently, all non-coldboot HARTs busy spin in wait_for_coldboot()
until the entire coldboot init sequence is completed.
This means:
1) On QEMU, all non-coldboot HARTs will eat host CPU time and
also slow down the coldboot HART until the entire coldboot
init sequence is completed.
2) On real HW, all non-coldboot HARTs will consume more CPU
power until the entire coldboot init sequence is completed.
To address this, wake up all non-coldboot HARTs as early as
possible in the coldboot init sequence.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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On QEMU virt machine with large number of HARTs, some of the HARTs
randomly fail to come out of wait_for_coldboot() due to one of the
following race-conditions:
1) Failing HARTs are not able to acquire the coldboot_lock and
update the coldboot_hartmask in wait_for_coldboot() before
the coldboot HART acquires the coldboot_lock and sends IPI
in wake_coldboot_harts() hence the failing HARTs never
receive IPI from the coldboot HART.
2) Failing HARTs acquire the coldbood_lock and update the
coldboot_hartmask before coldboot HART does sbi_scratch_init()
so the sbi_hartmask_set_hartid() does not update the
coldboot_hartmask on the failing HARTs hence they never
receive IPI from the coldboot HART.
To address this, use a simple busy-loop in wait_for_coldboot() for
polling on coldboot_done flag.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
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The address of the local scratch area is stored in each hart's mscratch
CSR. It is more efficient to read the CSR than to compute the address
from the hart ID.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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Add SSE callbacks registration to PMU driver in order to disable
interrupt delegation for PMU interrupts. When interrupts are
undelegated send the PMU SSE event upon LCOFIP IRQ.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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The SBI SSE extension defines a set of function that can be called to
register and handle supervisor sofwtare events. This patch implements
all of the functionality defined in the specification.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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This extension [1] allows to deliver events from SBI to supervisor via
a software mechanism. This extension defines events (either local or
global) which are signaled by the SBI on specific signal sources (IRQ,
exceptions, etc) and are injected to be executed in supervisor mode.
[1] https://lists.riscv.org/g/tech-prs/message/798
Signed-off-by: Clément Léger <cleger@rivosinc.com>
Reviewed-by: Himanshu Chauhan <hchauhan@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
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The sbi_trap_error() should dump state of all in-flight traps upon
failure in a nested trap so extend it accordingly.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
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To be consistent with other trap handlers, pass trap context pointer
to sbi_ecall_handler().
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>
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The trap irq handling functions no longer require regs parameter
so remove it.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
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The irqchip handlers will typically not need pointer to trap registers
so remove regs parameter of sbi_irqchip_process().
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Clément Léger <cleger@rivosinc.com>
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The struct sbi_trap_context already has the information needed by
sbi_illegal_insn_handler() so directly pass struct sbi_trap_context
pointer to this function.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
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