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| author | Anup Patel <anup.patel@wdc.com> | 2019-01-22 11:06:31 +0530 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-01-22 11:40:15 +0530 |
| commit | 3fde8f3f644396bb2c664b474a4eaa4205acf639 (patch) | |
| tree | f3453e4a3ed3ad89d0d9ba301bfc2964ddbfe41b | |
| parent | f37f7e21e078187ac314fdb7339f5946d9cc426e (diff) | |
| download | opensbi-3fde8f3f644396bb2c664b474a4eaa4205acf639.zip opensbi-3fde8f3f644396bb2c664b474a4eaa4205acf639.tar.gz opensbi-3fde8f3f644396bb2c664b474a4eaa4205acf639.tar.bz2 | |
lib: Update documentation of sbi_init()
We don't need to pre-enable MSIP in MIE CSR when
calling sbi_init() from firmware. This patch updates
documentation accordingly.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
| -rw-r--r-- | lib/sbi_init.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/sbi_init.c b/lib/sbi_init.c index 1f1103c..35a543e 100644 --- a/lib/sbi_init.c +++ b/lib/sbi_init.c @@ -147,7 +147,7 @@ static atomic_t coldboot_lottery = ATOMIC_INITIALIZER(0); * 1. The 'mscratch' CSR is pointing to sbi_scratch of current HART * 2. Stack pointer (SP) is setup for current HART * 3. Interrupts are disabled in MSTATUS CSR - * 4. All interrupts are disabled in MIE CSR except MSIP + * 4. All interrupts are disabled in MIE CSR * * @param scratch pointer to sbi_scratch of current HART */ |