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| author | Atish Patra <atish.patra@wdc.com> | 2019-01-21 18:17:45 -0800 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2019-01-22 10:03:49 +0530 |
| commit | 023aa6bb043420cd215379a0b31b8aceef38807b (patch) | |
| tree | d01330ff6db909b3fa70ba35def32d99b9903a2e | |
| parent | bc545539d2f2842c12c8b16d898a21113ce70417 (diff) | |
| download | opensbi-023aa6bb043420cd215379a0b31b8aceef38807b.zip opensbi-023aa6bb043420cd215379a0b31b8aceef38807b.tar.gz opensbi-023aa6bb043420cd215379a0b31b8aceef38807b.tar.bz2 | |
lib: Do not access mi/edeleg register if S mode is not present.
As per the RISC-V ISA, mideleg and medeleg registers should not exist
if S-mode is not present for a hart.
We shouldn't access these CSRs if non S-mode harts.
Signed-off-by: Atish Patra <atish.patra@wdc.com>
| -rw-r--r-- | lib/sbi_hart.c | 28 |
1 files changed, 13 insertions, 15 deletions
diff --git a/lib/sbi_hart.c b/lib/sbi_hart.c index e12a546..7e5df72 100644 --- a/lib/sbi_hart.c +++ b/lib/sbi_hart.c @@ -82,21 +82,19 @@ static int delegate_traps(struct sbi_scratch *scratch, u32 hartid) struct sbi_platform *plat = sbi_platform_ptr(scratch); unsigned long interrupts, exceptions; - if (!misa_extension('S')) { - /* No delegation possible */ - interrupts = 0; - exceptions = 0; - } else { - /* Send M-mode interrupts and most exceptions to S-mode */ - interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP; - exceptions = (1U << CAUSE_MISALIGNED_FETCH) | - (1U << CAUSE_BREAKPOINT) | - (1U << CAUSE_USER_ECALL); - if (sbi_platform_has_mfaults_delegation(plat)) - exceptions |= (1U << CAUSE_FETCH_PAGE_FAULT) | - (1U << CAUSE_LOAD_PAGE_FAULT) | - (1U << CAUSE_STORE_PAGE_FAULT); - } + if (!misa_extension('S')) + /* No delegation possible as mideleg does not exist*/ + return 0; + + /* Send M-mode interrupts and most exceptions to S-mode */ + interrupts = MIP_SSIP | MIP_STIP | MIP_SEIP; + exceptions = (1U << CAUSE_MISALIGNED_FETCH) | + (1U << CAUSE_BREAKPOINT) | + (1U << CAUSE_USER_ECALL); + if (sbi_platform_has_mfaults_delegation(plat)) + exceptions |= (1U << CAUSE_FETCH_PAGE_FAULT) | + (1U << CAUSE_LOAD_PAGE_FAULT) | + (1U << CAUSE_STORE_PAGE_FAULT); csr_write(mideleg, interrupts); csr_write(medeleg, exceptions); |