From 39426bad550f340dcf2b544ae23f465fbbbc42f5 Mon Sep 17 00:00:00 2001
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Date: Fri, 3 Dec 2010 15:02:36 +1100
Subject: Initial qemu/KVM board support

Added a new board for SLOF running on KVM/qemu.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
---
 include/ppcp7/cache.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++
 include/ppcp7/cpu.h   | 50 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 112 insertions(+)
 create mode 100644 include/ppcp7/cache.h
 create mode 100644 include/ppcp7/cpu.h

(limited to 'include')

diff --git a/include/ppcp7/cache.h b/include/ppcp7/cache.h
new file mode 100644
index 0000000..ecbec1c
--- /dev/null
+++ b/include/ppcp7/cache.h
@@ -0,0 +1,62 @@
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#ifndef __CACHE_H
+#define __CACHE_H
+
+#include <cpu.h>
+#include <stdint.h>
+
+// XXX FIXME: Use proper CI load/store */
+#define cache_inhibited_access(type,name) 			\
+	static inline type ci_read_##name(type * addr)		\
+	{							\
+		type val;					\
+		val = *addr;					\
+		return val;					\
+	}							\
+	static inline void ci_write_##name(type * addr, type data)	\
+	{							\
+		*addr = data;					\
+	}
+
+cache_inhibited_access(uint8_t,  8)
+cache_inhibited_access(uint16_t, 16)
+cache_inhibited_access(uint32_t, 32)
+cache_inhibited_access(uint64_t, 64)
+
+static inline uint16_t bswap16_load(uint64_t addr)
+{
+	unsigned int val;
+	asm volatile ("lhbrx %0, 0, %1":"=r" (val):"r"(addr));
+	return val;
+}
+
+static inline uint32_t bswap32_load(uint64_t addr)
+{
+	unsigned int val;
+	asm volatile ("lwbrx %0, 0, %1":"=r" (val):"r"(addr));
+	return val;
+}
+
+static inline void bswap16_store(uint64_t addr, uint16_t val)
+{
+	asm volatile ("sthbrx %0, 0, %1"::"r" (val), "r"(addr));
+}
+
+static inline void bswap32_store(uint64_t addr, uint32_t val)
+{
+	asm volatile ("stwbrx %0, 0, %1"::"r" (val), "r"(addr));
+}
+
+#endif /* __CACHE_H */
+
diff --git a/include/ppcp7/cpu.h b/include/ppcp7/cpu.h
new file mode 100644
index 0000000..6de50d7
--- /dev/null
+++ b/include/ppcp7/cpu.h
@@ -0,0 +1,50 @@
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     IBM Corporation - initial implementation
+ *****************************************************************************/
+
+#ifndef __CPU_H
+#define __CPU_H
+
+/* Used in boot_abort.S, will need something better for KVM */
+#define HSPRG0  304
+
+/* XXX FIXME: Can be more efficient, no dcbst nor loop needed on P7 */
+/* This macro uses r0 */
+#define FLUSH_CACHE(r, n)	add	n, n, r; \
+				addi	n, n, 127; \
+				rlwinm	r, r, 0,0,24; \
+				rlwinm	n, n, 0,0,24; \
+				sub	n, n, r; \
+				srwi	n, n, 7; \
+				mtctr	n; \
+			0:	dcbst	0, r; \
+				sync; \
+				icbi	0, r; \
+				sync; \
+				isync; \
+				addi	r, r, 128; \
+				bdnz	0b;
+
+#ifndef __ASSEMBLER__
+#define STRINGIFY(x...) #x
+#define EXPAND(x) STRINGIFY(x)
+
+static inline void flush_cache(void* r, long n)
+{
+	asm volatile(EXPAND(FLUSH_CACHE(%0, %1))
+		     : "+r"(r), "+r"(n)
+		     :: "memory", "cc", "r0", "ctr");
+}
+
+
+#endif /* __ASSEMBLER__ */
+
+#endif
-- 
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