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| author | Thomas Huth <thuth@linux.vnet.ibm.com> | 2011-07-29 08:23:46 +0200 |
|---|---|---|
| committer | Thomas Huth <thuth@linux.vnet.ibm.com> | 2011-10-12 13:20:00 +0200 |
| commit | d38a1c54f519c5f23995bbe9341265cd56814d76 (patch) | |
| tree | fdccff94f71204151aab699b011c0f3371526ffd /include | |
| parent | c9d1203de087ad20d1ef115355129a1b1082d8ed (diff) | |
| download | SLOF-d38a1c54f519c5f23995bbe9341265cd56814d76.zip SLOF-d38a1c54f519c5f23995bbe9341265cd56814d76.tar.gz SLOF-d38a1c54f519c5f23995bbe9341265cd56814d76.tar.bz2 | |
Improved cache-inhibited access functions
Implemented the CI functions in cache.h (which are required by net-snk)
and fixed a bug in hv_logical_ci_store in libhvcall.
Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/ppcp7/cache.h | 37 |
1 files changed, 27 insertions, 10 deletions
diff --git a/include/ppcp7/cache.h b/include/ppcp7/cache.h index ecbec1c..64389ae 100644 --- a/include/ppcp7/cache.h +++ b/include/ppcp7/cache.h @@ -17,16 +17,33 @@ #include <stdint.h> // XXX FIXME: Use proper CI load/store */ -#define cache_inhibited_access(type,name) \ - static inline type ci_read_##name(type * addr) \ - { \ - type val; \ - val = *addr; \ - return val; \ - } \ - static inline void ci_write_##name(type * addr, type data) \ - { \ - *addr = data; \ +#define cache_inhibited_access(type,size) \ + static inline type ci_read_##size(type * addr) \ + { \ + type val; \ + register int bytes asm ("r4") = size / 8; \ + register uint64_t _addr asm ("r5") = (long)addr; \ + asm volatile(" li 3, 0x3c \n" /* H_LOGICAL_CI_LOAD */ \ + ".long 0x44000022 \n" /* HVCALL */ \ + " cmpdi cr0,3,0 \n" \ + " mr %0,4 \n" \ + " beq 0f \n" \ + " li %0,-1 \n" \ + "0:\n" \ + : "=r"(val) \ + : "r"(bytes), "r"(_addr) \ + : "r3", "memory", "cr0"); \ + return val; \ + } \ + static inline void ci_write_##size(type * addr, type data) \ + { \ + register int bytes asm ("r4") = size / 8; \ + register uint64_t _addr asm ("r5") = (uint64_t)addr; \ + register uint64_t _data asm ("r6") = (uint64_t)data; \ + asm volatile(" li 3, 0x40 \n" /* H_LOGICAL_CI_STORE */ \ + ".long 0x44000022 \n" /* HVCALL */ \ + : : "r"(bytes), "r"(_addr), "r"(_data) \ + : "r3", "memory"); \ } cache_inhibited_access(uint8_t, 8) |