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2025-07-25target/arm: Pass correct esize to sve_st1_z() for LD1Q, ST1QPeter Maydell1-4/+32
Our implementation of the helper functions for the LD1Q and ST1Q insns reused the existing DO_LD1_ZPZ_D and DO_ST1_ZPZ_D macros. This passes the wrong esize (8, not 16) to sve_ldl_z(). Create new macros DO_LD1_ZPZ_Q and DO_ST1_ZPZ_Q which pass the correct esize, and use them for the LD1Q and ST1Q helpers. Fixes: d2aa9a804ee ("target/arm: Implement LD1Q, ST1Q for SVE2p1") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250723165458.3509150-6-peter.maydell@linaro.org
2025-07-25target/arm: LD1Q, ST1Q are vector + scalar, not scalar + vectorPeter Maydell2-20/+57
Unlike the "LD1D (scalar + vector)" etc instructions, LD1Q is vector + scalar. This means that: * the vector and the scalar register are in opposite fields in the encoding * 31 in the scalar register field is XZR, not XSP The same applies for ST1Q. This means we can't reuse the trans_LD1_zprz() and trans_ST1_zprz() functions for LD1Q and ST1Q. Split them out to use their own trans functions. Note that the change made here to sve.decode requires the decodetree bugfix "decodetree: Infer argument set before inferring format" to avoid a spurious compile-time error about "dtype". Fixes: d2aa9a804ee678f ("target/arm: Implement LD1Q, ST1Q for SVE2p1") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250723165458.3509150-5-peter.maydell@linaro.org
2025-07-25decodetree: Infer argument set before inferring formatRichard Henderson3-3/+9
Failure to confirm an argument set first may result in the selection of a format which leaves extra arguments to be filled in by the pattern. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250723165458.3509150-4-peter.maydell@linaro.org Message-id: 20250722183343.273533-1-richard.henderson@linaro.org Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-25target/arm: Pack mtedesc into upper 32 bits of descriptorRichard Henderson4-51/+25
Instead of trying to pack mtedesc into the upper 17 bits of a 32-bit gvec descriptor, pass the gvec descriptor in the lower 32 bits and the mte descriptor in the upper 32 bits of a 64-bit operand. This fixes two bugs: (1) in gen_sve_ldr() and gen_sve_str() call gen_mte_checkN() with a length value which is the SVE vector length and can be up to 256 bytes. We don't assert there that it fits in the descriptor, so we would just fail to do the MTE checks on the right length of memory if the VL is more than 32 bytes (2) the new-in-SVE2p1 insns LD3Q, LD4Q, ST3Q, ST4Q also involve transfers of more than 32 bytes of memory. In this case we would assert at translate time. (Note for potential backporting: this commit depends on the previous "target/arm: Expand the descriptor for SME/SVE memory ops to i64".) Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250723165458.3509150-3-peter.maydell@linaro.org [PMM: expand commit message to clarify that we are fixing bugs here] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-25target/arm: Expand the descriptor for SME/SVE memory ops to i64Richard Henderson7-827/+828
We have run out of room attempting to pack both the gvec descriptor and the mte descriptor into 32 bits. Here, change nothing except the parameter type, which affects all declarations, the function typedefs, and the type used with tcg expansion. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20250723165458.3509150-2-peter.maydell@linaro.org
2025-07-25hw/display/qxl-render.c: fix qxl_unpack_chunks() chunk size calculationMichael Tokarev1-1/+10
In case of multiple chunks, code in qxl_unpack_chunks() takes size of the wrong (next in the chain) chunk, instead of using current chunk size. This leads to wrong number of bytes being copied, and to crashes if next chunk size is larger than the current one. Based on the code by Gao Yong. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1628 Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> Reviewed-by: Thomas Huth <thuth@redhat.com>
2025-07-24log: make '-msg timestamp=on' apply to all qemu_log usageDaniel P. Berrangé2-14/+20
Currently the tracing 'log' back emits special code to add timestamps to trace points sent via qemu_log(). This current impl is a bad design for a number of reasons. * It changes the QEMU headers, such that 'error-report.h' content is visible to all files using tracing, but only when the 'log' backend is enabled. This has led to build failure bugs as devs rarely test without the (default) 'log' backend enabled, and CI can't cover every scenario for every trace backend. * It bloats the trace points definitions which are inlined into every probe location due to repeated inlining of timestamp formatting code, adding MBs of overhead to QEMU. * The tracing subsystem should not be treated any differently from other users of qemu_log. They all would benefit from having timestamps present. * The timestamp emitted with the tracepoints is in a needlessly different format to that used by error_report() in response to '-msg timestamp=on'. This fixes all these issues simply by moving timestamp formatting into qemu_log, using the same approach as for error_report. The code before: static inline void _nocheck__trace_qcrypto_tls_creds_get_path(void * creds, const char * filename, const char * path) { if (trace_event_get_state(TRACE_QCRYPTO_TLS_CREDS_GET_PATH) && qemu_loglevel_mask(LOG_TRACE)) { if (message_with_timestamp) { struct timeval _now; gettimeofday(&_now, NULL); qemu_log("%d@%zu.%06zu:qcrypto_tls_creds_get_path " "TLS creds path creds=%p filename=%s path=%s" "\n", qemu_get_thread_id(), (size_t)_now.tv_sec, (size_t)_now.tv_usec , creds, filename, path); } else { qemu_log("qcrypto_tls_creds_get_path " "TLS creds path creds=%p filename=%s path=%s" "\n", creds, filename, path); } } } and after: static inline void _nocheck__trace_qcrypto_tls_creds_get_path(void * creds, const char * filename, const char * path) { if (trace_event_get_state(TRACE_QCRYPTO_TLS_CREDS_GET_PATH) && qemu_loglevel_mask(LOG_TRACE)) { qemu_log("qcrypto_tls_creds_get_path " "TLS creds path creds=%p filename=%s path=%s" "\n", creds, filename, path); } } The log and error messages before: $ qemu-system-x86_64 -trace qcrypto* -object tls-creds-x509,id=tls0,dir=$HOME/tls -msg timestamp=on 2986097@1753122905.917608:qcrypto_tls_creds_x509_load TLS creds x509 load creds=0x55d925bd9490 dir=/var/home/berrange/tls 2986097@1753122905.917621:qcrypto_tls_creds_get_path TLS creds path creds=0x55d925bd9490 filename=ca-cert.pem path=<none> 2025-07-21T18:35:05.917626Z qemu-system-x86_64: Unable to access credentials /var/home/berrange/tls/ca-cert.pem: No such file or directory and after: $ qemu-system-x86_64 -trace qcrypto* -object tls-creds-x509,id=tls0,dir=$HOME/tls -msg timestamp=on 2025-07-21T18:43:28.089797Z qcrypto_tls_creds_x509_load TLS creds x509 load creds=0x55bf5bf12380 dir=/var/home/berrange/tls 2025-07-21T18:43:28.089815Z qcrypto_tls_creds_get_path TLS creds path creds=0x55bf5bf12380 filename=ca-cert.pem path=<none> 2025-07-21T18:43:28.089819Z qemu-system-x86_64: Unable to access credentials /var/home/berrange/tls/ca-cert.pem: No such file or directory The binary size before: $ ls -alh qemu-system-x86_64 -rwxr-xr-x. 1 berrange berrange 87M Jul 21 19:39 qemu-system-x86_64 $ strip qemu-system-x86_64 $ ls -alh qemu-system-x86_64 -rwxr-xr-x. 1 berrange berrange 30M Jul 21 19:39 qemu-system-x86_64 and after: $ ls -alh qemu-system-x86_64 -rwxr-xr-x. 1 berrange berrange 85M Jul 21 19:41 qemu-system-x86_64 $ strip qemu-system-x86_64 $ ls -alh qemu-system-x86_64 -rwxr-xr-x. 1 berrange berrange 29M Jul 21 19:41 qemu-system-x86_64 Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Message-id: 20250721185452.3016488-1-berrange@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-07-24MAINTAINERS: remove myself as ppc maintainer/reviewerDaniel Henrique Barboza1-3/+0
It has been awhile since I actively did anything for qemu-ppc aside from reading the qemu-ppc inbox a couple of times each month. It's not enough to justify a reviewer role, let alone being a maintainer. Given that we're doing qemu-ppc maintainership changes across the board I'll take the opportunity and remove myself from the premises too. Feel free to reach out with questions about code I did in the past, but at this moment I'm no longer able to keep up with qemu-ppc activities. Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250724123416.3115941-1-danielhb413@gmail.com [ clg: Adjusted context ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-07-24MAINTAINERS: Remove Frédéric as reviewerCédric Le Goater1-2/+0
Frédéric has moved to other tasks within IBM and no longer does QEMU development. Cc: Frédéric Barrat <fbarrat@linux.ibm.com> Acked-by: Frédéric Barrat <fbarrat@linux.ibm.com> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Link: https://lore.kernel.org/qemu-devel/20250724075916.1593420-1-clg@redhat.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-07-24MAINTAINERS: Add myself as a reviewer for XIVEGautam Menghani1-0/+1
Proposing myself as a reviewer for XIVE on PPC. I have been looking at XIVE in context of KVM internally at IBM for some time in addition to testing a few XIVE upstream patches; and I'll be closely looking at XIVE going forward. Signed-off-by: Gautam Menghani <gautam@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250724100623.3071131-6-harshpb@linux.ibm.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-07-24MAINTAINERS: Add myself as a reviewer of PowerNV emulationAditya Gupta1-0/+1
Proposing myself as a reviewer in the PowerNV emulation in QEMU Have been working on PowerNV QEMU for sometime, with contributions in Power11, MPIPL and minor fixes and things such as dtb support Cc: Cédric Le Goater <clg@kaod.org> Cc: Frédéric Barrat <fbarrat@linux.ibm.com> Cc: Mahesh J Salgaonkar <mahesh@linux.ibm.com> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> Cc: Nicholas Piggin <npiggin@gmail.com> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250724100623.3071131-5-harshpb@linux.ibm.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-07-24MAINTAINERS: Add myself as reviewer for PowerPC TCG CPUsChinmay Rath1-0/+1
I have been working on Power ISA for a long time now and have mostly contributed in TCG instruction translation area (moved 300+ instructions to decodetree as of yet) and would like to continue contributing to PPC TCG in best possible ways I can. I think it's time to step up and assist in reviewing related patches to enable myself contribute more effectively in this direction. Signed-off-by: Chinmay Rath <rathc@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Link: https://lore.kernel.org/qemu-devel/20250724100623.3071131-4-harshpb@linux.ibm.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-07-24MAINTAINERS: Adding myself as reviewer for PPC KVM cpus.Harsh Prateek Bora1-0/+1
Have been contributing in ppc/spapr from tcg/kvm perspective, stepping up to help with patch reviews and get notified of incoming changes. Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250724100623.3071131-3-harshpb@linux.ibm.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-07-24MAINTAINERS: Adding myself as a co-maintainer for ppc/spaprHarsh Prateek Bora1-0/+1
Have been contributing in ppc/spapr and related areas for quite some time as a contributor and reviewer. I think its time to step up as a co-maintainer to help with maintainer activities. Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250724100623.3071131-2-harshpb@linux.ibm.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
2025-07-22crypto: add tracing & warning about GNUTLS countermeasuresDaniel P. Berrangé2-0/+13
We want some visibility on stderr when the GNUTLS thread safety countermeasures are activated, to encourage people to get the real fix deployed (once it exists). Some trace points will also help if we see any further wierd crash scenario we've not anticipated. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/20250718150514.2635338-5-berrange@redhat.com [add missing include] Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-07-22migration: activate TLS thread safety workaroundDaniel P. Berrangé1-0/+9
When either the postcopy or return path capabilities are enabled, the migration code will use the primary channel for bidirectional I/O. If either of those capabilities are enabled, the migration code needs to mark the channel as expecting concurrent I/O in order to activate the thread safety workarounds for GNUTLS bug 1717 Closes: https://gitlab.com/qemu-project/qemu/-/issues/1937 Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/20250718150514.2635338-4-berrange@redhat.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-07-22io: add support for activating TLS thread safety workaroundDaniel P. Berrangé2-0/+6
Add a QIO_CHANNEL_FEATURE_CONCURRENT_IO feature flag. If this is set on a QIOChannelTLS session object, the TLS session will be marked as requiring thread safety, which will activate the workaround for GNUTLS bug 1717 if needed. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/20250718150514.2635338-3-berrange@redhat.com Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-07-22crypto: implement workaround for GNUTLS thread safety problemsDaniel P. Berrangé5-3/+119
When TLS 1.3 is negotiated on a TLS session, GNUTLS will perform automatic rekeying of the session after 16 million records. This is done for all algorithms except CHACHA20_POLY1305 which does not require rekeying. Unfortunately the rekeying breaks GNUTLS' promise that it is safe to use a gnutls_session_t object concurrently from multiple threads if they are exclusively calling gnutls_record_send/recv. This patch implements a workaround for QEMU that adds a mutex lock around any gnutls_record_send/recv call to serialize execution within GNUTLS code. When GNUTLS calls into the push/pull functions we can release the lock so the OS level I/O calls can at least have some parallelism. The big downside of this is that the actual encryption/decryption code is fully serialized, which will halve performance of that cipher operations if two threads are contending. The workaround is not enabled by default, since most use of GNUTLS in QEMU does not tickle the problem, only non-multifd migration with a return path open is affected. Fortunately the migration code also won't trigger the halving of performance, since only the outbound channel diretion needs to sustain high data rates, the inbound direction is low volume. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/20250718150514.2635338-2-berrange@redhat.com [add stub for qcrypto_tls_session_require_thread_safety; fix unused var] Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-07-22migration: show error message when postcopy failsDaniel P. Berrangé1-1/+3
The 'info migrate' command only shows the error message when the migration state is 'failed'. When postcopy is used, however, the 'postcopy-paused' state is used instead of 'failed', so we must show the error message there too. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Fabiano Rosas <farosas@suse.de> Link: https://lore.kernel.org/qemu-devel/20250721133913.2914669-1-berrange@redhat.com [line break to satisfy checkpatch] Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-07-22migration: HMP: Fix postcopy latency distribution labelFabiano Rosas1-1/+1
Fix the loop condition to avoid having a label with "1000 us" instead of "1 ms". Reported-by: Prasad Pandit <ppandit@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/qemu-devel/20250716182648.30202-3-farosas@suse.de Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-07-22migration: HMP: Fix possible out-of-bounds accessFabiano Rosas1-4/+2
Coverity has caught a bug in the formatting of time intervals for postcopy latency distribution display in 'info migrate'. While bounds checking the labels array, sizeof is incorrectly being used. ARRAY_SIZE is the correct form of obtaining the size of an array. Fixes: 3345fb3b6d ("migration/postcopy: Add latency distribution report for blocktime") Resolves: Coverity CID 1612248 Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/qemu-devel/20250716182648.30202-2-farosas@suse.de Signed-off-by: Fabiano Rosas <farosas@suse.de>
2025-07-22Update version for the v10.1.0-rc0 releasev10.1.0-rc0Stefan Hajnoczi1-1/+1
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-07-22Merge tag 'tracing-pull-request' of https://gitlab.com/stefanha/qemu into ↵Stefan Hajnoczi4-16/+4
staging Pull request Tanish's removal of the remnants of the "vcpu" property. # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCgAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmh/p3sACgkQnKSrs4Gr # c8gmNgf/cyke7C/K3lb6Qtajb1KMp//kY2hnVms/tAJZxirY02UEfvrEd3AOX1+E # 5q6kpVWV18qVqoSZsdkukBVa7U3qWeJ6OL9MvlFYrUwg93yV10kHvD3Hwx7CdYS/ # OzVf75ryVw+TLwavDdyb2S1fUJC+4ou3NxhGN2AoIz+2agqw+klitPPOCkzLtKRv # CZbdT+fhFqoWkZ3eq3QvlPJISPAO0O6+pUc7rwiFO+Hv0VK1R7nUoiHK2yIwsn9R # BfCgPlQ4oecL8ZAakTXCuX8SiHFp9wwvxz+ZWlEam70GNKM+USr26CJEmwnT0+CF # LZAOFBEpimV2YGphYSnvcmcjVnP5BA== # =mXTq # -----END PGP SIGNATURE----- # gpg: Signature made Tue 22 Jul 2025 11:00:11 EDT # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [ultimate] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [ultimate] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * tag 'tracing-pull-request' of https://gitlab.com/stefanha/qemu: tracetool: removed the unused vcpu property Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-07-22tracetool: removed the unused vcpu propertytracingTanish Desai4-16/+4
The vcpu property is no longer used in these backends. Removing it avoids unnecessary checks and simplifies the code generation for these trace backends. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Tanish Desai <tanishdesai37@gmail.com> Message-id: 20250722114352.3624-1-tanishdesai37@gmail.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-07-22rust/pl011: merge device_class.rs into device.rsManos Pitsidianakis3-111/+96
The split was a relic of early development and is not necessary. Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Link: https://lore.kernel.org/r/20250718-rust-pl011-cleanup-v1-1-c71b1d6a69a5@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-07-22rust: devices are not staticlibsPaolo Bonzini2-6/+0
This is only cosmetic for now, but hopefully later on Meson will parse more of Cargo.toml. Devices are linked into a staticlib but are not staticlibs themselves. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-07-21Merge tag 'pull-ppc-20250721' of https://github.com/legoater/qemu into stagingStefan Hajnoczi12-492/+1146
ppc/xive queue: * Various bug fixes around lost interrupts particularly. * Major group interrupt work, in particular around redistributing interrupts. Upstream group support is not in a complete or usable state as it is. * Significant context push/pull improvements, particularly pool and phys context handling was quite incomplete beyond trivial OPAL case that pushes at boot. * Improved tracing and checking for unimp and guest error situations. * Various other missing feature support. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmh951cACgkQUaNDx8/7 # 7KFK6w//SAmZpNmE380UN4OxMBcjsT5m5Cf2hy+Wq9pSEcwWckBFT03HyR86JAv3 # QLR1d6yx7dY0aVWAHtFC24vlU2jpv0Io97wfX9VbgG7e4TY/i1vRMSXYYehXuU/Y # gLrwuJGxAMKWrd+4ymvHOyXHRAq3LMGQQYfqLCB77b8UJ18JyCL8FwAl/D6EsZ1y # nUW8WlDy6qQ/SJQHZZ664kyJEv7Qw4xd81ZnmoPsy3xVd7c4ASNBWvDTjRoUn2EN # sfJW76UqqFn3EqASaKsqoNPHu3kklQ/AX3KlE1wFCBjYoXwl/051wIX4RIb+b2S4 # SLtc/YSAie1n2Pp1sghfLRFiRpjrmnqaLlw04Buw1TXY2OaQbFc9zTkc9rvFSez1 # cNjdJcvm3myAWy2Pg//Nt3FgCqfMlrrdTlyGsdqmrEaplBy6pHnas+82o5tPGC3t # SBMgTDqNMq0v/V/gOIsmHc5/9f+FS5s+v/nvm0xJDfLkY39qP73W+YZllYyyuTHY # HiLVjD7x5BSGZAsP9EN6EnL7DPXKPIIQSfNwo2564tAhe3/IyJo8hpGhMeiZ83Hf # G9oPiLa4YljsHzP0UPRNhID5IYyngEDoh2j3AXnew1tkikHd5LIpNCdbtW5x52RR # kik4hBmqJU6sYpO0O9yCd6YWv/Bpm4bDs6tQOSWMc6uWqP0qN8M= # =65BL # -----END PGP SIGNATURE----- # gpg: Signature made Mon 21 Jul 2025 03:08:07 EDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full] # gpg: aka "Cédric Le Goater <clg@kaod.org>" [full] # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-ppc-20250721' of https://github.com/legoater/qemu: (50 commits) ppc/xive2: Enable lower level contexts on VP push ppc/xive: Split need_resend into restore_nvp ppc/xive2: Implement PHYS ring VP push TIMA op ppc/xive2: Implement POOL LGS push TIMA op ppc/xive2: Implement set_os_pending TIMA op ppc/xive2: redistribute group interrupts on context push ppc/xive2: Implement pool context push TIMA op ppc/xive: Check TIMA operations validity ppc/xive: Redistribute phys after pulling of pool context ppc/xive2: Prevent pulling of pool context losing phys interrupt ppc/xive2: implement NVP context save restore for POOL ring ppc/xive: Assert group interrupts were redistributed ppc/xive2: Avoid needless interrupt re-check on CPPR set ppc/xive2: Consolidate presentation processing in context push ppc/xive2: split tctx presentation processing from set CPPR ppc/xive: Add xive_tctx_pipr_set() helper function ppc/xive: tctx_accept only lower irq line if an interrupt was presented ppc/xive: tctx signaling registers rework ppc/xive: Split xive recompute from IPB function ppc/xive: Fix high prio group interrupt being preempted by low prio VP ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-07-21Merge tag 'display-20250718-pull-request' of https://gitlab.com/kraxel/qemu ↵Stefan Hajnoczi12-16/+55
into staging Load ramfb vgabios on x86 only. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEoDKM/7k6F6eZAf59TLbY7tPocTgFAmh6o80ACgkQTLbY7tPo # cTjxPBAAktTXxFK6loSMSWC1ul8RCl/4F7G84J4eT+Ui8/KIG8do5KcebTnXb9zo # keOG7n9HPk4fROWiAFgGnuBfw41DWmLDS34iuENrG3X26TQgSSgBveuwas67Pzqu # HpaFSxjh7BRLlkUWaNoll57cDM3kKLmx+Onw6m/7kbcVXAsy1N4wxfCT1faUU7ID # R1ggULG1WhB8q+YtQjac6EfOpdHe1BTBGLuxSwE3mNkce9ZP7C8uxZTCR5PXggZi # IXzJzGpFRDCHqrilWksiE62yF20Kem4ZcpO/GgLWmF+X+DYBDEWcajihvF20TGUL # n6dyT7MBxuvqFy0OtBPHNcnq2PZzOIKyxyMvBg9402xeD6goNbFKloAYeae4C9u0 # QuqQUpb8D3lVagVu55N5XfpdMHR0P8yefPAjaFL4o3rf2JSjyI6MRX/+2eA7aXcX # xiwHSx3iavEeNQNsPZsS3JhH5bKy/zkWRiBd+msGVAYMZGzhdEtLg/w8yUd6dQ5p # /3Y3F4fL6T6QSwhsiihcbdPtjhfVCP09MYK/P4cIFbWOzjfbndt1/UIXHQ54s8Jo # PShcE7QH7ttT2gK5nFPG5yeTqF70kKpSyhwF2pukf2fAgcU+0SNoj2zZNtHAvKeh # 8EHqAy8m1J4AlQeO5nT9tJj/v1CM0q6cljzIfV8hWWgM/hL/vLc= # =76m5 # -----END PGP SIGNATURE----- # gpg: Signature made Fri 18 Jul 2025 15:43:09 EDT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * tag 'display-20250718-pull-request' of https://gitlab.com/kraxel/qemu: hw/i386: Add the ramfb romfile compatibility vfio: Move the TYPE_* to hw/vfio/types.h ramfb: Add property to control if load the romfile Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Conflicts: hw/core/machine.c Context conflict because the vfio-pci "x-migration-load-config-after-iter" was added recently.
2025-07-21Merge tag 'pull-tcg-20250721' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi1-1/+1
tcg/optimize: Don't fold INDEX_op_and_vec to extract # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmh+WFMdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV+ieggAjnO41ApUWcRbuILy # MAUK9sU5Z5R7y/bsj5ZUAlqS83/p3ipwzu8ihQqQcRII+QwT4ry1QED2+JtZduwX # b20d3HKghr0dqN4ZKd07ftD8qDFlzzOhXKuKLEzDRRC1d5wgt7AOKxdvZ70IMhov # DUxN097VSmR3tX7VFOAweqFPQRPykl7/5g+fDSJhXRH1YffshlT6z7Gql5B4oBs4 # leKwYmpmOiNwKuKhBuWjPwbp/zJtcFFdNdsE9nMoRKil27G0z0dDL0fJ8U4cDuiT # cWqQB0pajT6XANmwchw0ADsvb7Uudsdu/W6jj/2KIPP7zlxnTW5p+igu217fGuIA # 7GQE5w== # =i/Vc # -----END PGP SIGNATURE----- # gpg: Signature made Mon 21 Jul 2025 11:10:11 EDT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20250721' of https://gitlab.com/rth7680/qemu: tcg/optimize: Don't fold INDEX_op_and_vec to extract Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-07-21Merge tag 'pull-target-arm-20250721' of https://gitlab.com/pm215/qemu into ↵Stefan Hajnoczi16-60/+285
staging target-arm queue: * hvf: arm: Remove $pc from trace_hvf_data_abort() * target/arm: Correct encoding of Debug Communications Channel registers * hw/misc/ivshmem-pci: Improve error handling * target/arm: Provide always-false kvm_arm_*_supported() stubs for usermode * host-utils: Drop workaround for buggy Apple Clang __builtin_subcll() * hw/misc/max78000_aes: Comment Internal Key Storage * docs: Fix Aspeed title * Implement a handful of missing FEAT_SVE_B16_B16 insns * Fix bugs in FMAXQV, FMINQV, etc * Fix assert in LD1Q decode * hvf: arm: Add permission check in GIC sysreg handlers * hvf: arm: Emulate ICC_RPR_EL1 accesses properly * accel/hvf: Display executable bit as 'X' # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmh+OlgZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3klRD/0QvWyi0z0wbBdIKGi8kury # VP/S1FcqP2w9l0jUAmINxsOYu/+ql8w3t6m2jxlTOYZc9rNauQrxRYGD1GdqfJVn # VCYN47OHRye+iMH6c5jdKyJTi3n2uvT2g8anh2Yt18xOey45Pwr2fTs8rje3N5sH # fvv1mNaeGyA7wgXEY9Z4tEvW19ZPsuKIBd4Ea7klDXwUpTmmQkJMVTKyz7/TefqK # YicpM9E4dMxwNvW/8zrsVH505E4s15OytIjhDci30v2M7Uh3tUIRKo+s44Kk7cEq # HIwO/ra1HEhp8xGU2UfRf643EF1k7A0VUgetHSxYbi1gIknjiSU8Ohnd268CgY7G # /UbjgjFu5mcJgBvoNCwGy0iuCkEfRZ+veq24OjL6GbMvt2utCm9Rumu5KLemLpvW # mB4RexjbT+FDldhz8Ub42sR96UpZ0TSEfwjOswHibA4Zk4o2S6fRv0OqaBMB2dKU # MhcMdBdPXe3SmecRlYoqde+RCUyIOMD46uiJYrBhG6Nfn6SgcnS+ZGB960veaH2r # p5lvyJIBn3/a1KwOET9z5Gp3C6l4TXgJjIaCB4qAWHxeBR/AIobRC71heCc0uPU+ # J3Nm5/p6rcz0vjzs1To0VuXM57qNpQJWu0Un+8CDjpXJ0piyBk4o2iu1dw26bsMs # yrgqlMfDsXNlK/yUdykAbw== # =rQ+N # -----END PGP SIGNATURE----- # gpg: Signature made Mon 21 Jul 2025 09:02:16 EDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] # gpg: aka "Peter Maydell <peter@archaic.org.uk>" [unknown] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * tag 'pull-target-arm-20250721' of https://gitlab.com/pm215/qemu: accel/hvf: Display executable bit as 'X' hvf: arm: Emulate ICC_RPR_EL1 accesses properly hvf: arm: Add permission check in GIC sysreg handlers target/arm: Make LD1Q decode and trans fn agree about a->u target/arm: Honour FPCR.AH=1 default NaN value in FMAXNMQV, FMINNMQV target/arm: Don't nest H() macro calls in SVE DO_REDUCE target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQV target/arm: Add BFMLA, BFMLS (indexed) target/arm: Add BFMLA, BFMLS (vectors) target/arm: Add BFMUL (indexed) target/arm: Add BFMIN, BFMAX (predicated) target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated) target/arm: Add BFADD, BFSUB, BFMUL (unpredicated) docs: Fix Aspeed title hw/misc/max78000_aes: Comment Internal Key Storage host-utils: Drop workaround for buggy Apple Clang __builtin_subcll() target/arm: Provide always-false kvm_arm_*_supported() stubs for usermode hw/misc/ivshmem-pci: Improve error handling target/arm: Correct encoding of Debug Communications Channel registers hvf: arm: Remove $pc from trace_hvf_data_abort() Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-07-21Merge tag 'misc-next-pull-request' of https://gitlab.com/berrange/qemu into ↵Stefan Hajnoczi4-13/+83
staging Misc crypto & UI patches * Fix endian defaults when no VNC pixel format message is set * Add more trace events for VNC messages * Fix checking of certificate loading * Eliminate cert limit on loading CA certificates # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE2vOm/bJrYpEtDo4/vobrtBUQT98FAmh+GhkACgkQvobrtBUQ # T995OBAAiET1Av3xoF9aAVO5Visy/yvDaSOkP4bDDr1KkpaDrqLpBhAoqIEdxU1O # c+SUwltp0dYe7RcYIWg9b5dTpJdWyYDo5LvPQBbwxbhOXMPFbGsMJMc0BaO3KPVV # dlfXHUyHZ1bLVE5mnM/5poZzhN7CE4qHGw35jr08VF7iPHrEEp+5OgxFddzi5vQq # Rt+PlWA2CT/U5AoQe3Pgc0sRoS4VWV35xhdDWRgNR52CGzdNR76GneXy1ByJ6CWd # mlbFkXE6Abnp/TN/IT3sefH099Mc23adxPZ3WJ0aDEWG6jLnlcrvxmag0HNNJmm/ # R+PRB5OkClYA1kntYbLqOZyNHkcWTGtCTIq7293N0hXTWzQw96Py+pDVMeoktqqO # yuhdykCmOETWbudbpdCpcQyEpu4TQdFDPPoHVh4H2XbJmgIkuU+MMoBaaN+OBphk # 40H/mvGPkrY1Gb/jvDpbg74tqzH/gmTfuZJ+b1CMku9T11ElVPdu2bCUgOTgnPfC # b7wvyH31qtbel3OA1zzJ69Lh0wCEVYiOoMT+O49PMndlDn/d6ssi2T/6SjdDKUSd # JyVqhjG6xKr3Mogp/HVVpAEVHncztVDBOPYJA69OG/hjfE63NtcTsbWUhwO0kYr3 # R8qtdq/IYYOPAzGjCzNsApJusrymhVRF/ZSQCnbO15RdERBMF5Y= # =sxKq # -----END PGP SIGNATURE----- # gpg: Signature made Mon 21 Jul 2025 06:44:41 EDT # gpg: using RSA key DAF3A6FDB26B62912D0E8E3FBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" [full] # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" [full] # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * tag 'misc-next-pull-request' of https://gitlab.com/berrange/qemu: crypto: load all certificates in X509 CA file crypto/x509-utils: Check for error from gnutls_x509_crt_init() ui: add trace events for all client messages ui: fix setting client_endian field defaults Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-07-21tcg/optimize: Don't fold INDEX_op_and_vec to extractRichard Henderson1-1/+1
There is no such thing as vector extract. Fixes: 932522a9ddc1 ("tcg/optimize: Fold and to extract during optimize") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3036 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Tested-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-21accel/hvf: Display executable bit as 'X'Philippe Mathieu-Daudé1-1/+1
Developers are accustomed to read RWX, not RWE. Replace E -> X. Reported-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Mads Ynddal <mads@ynddal.dk> Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-21Merge tag 'pull-request-2025-07-21' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi13-784/+12
staging * Remove unused 32-bit arm Linux headers * Fix some small issues in the functional tests and docs # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCgAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmh99uIRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbUxsQ//XlRxmO5iChFc68yFF/zy7iVgLa5mQDws # MeFQm5agBSRp7kK0zwb08FxE9nOzwh9OljdUUWfg858OWiHeFLiMyn85c/RM7SBn # qovku4TfmP7TyII/czU7KbejvJvA6xrV7Adm1ltiwmV/fAueJ/RTknzY7Omy0hgV # crRJP+xU1MWAg892QkRPrwOS1HfAsrJJs5XFkNJS9SzYhR1SSUwCGKl2qtADCUdP # Vik88CiwMWhHiyutbsqQX1AOo+UHcNq1r+IcabqZqLed2au4sChxTq9S9xEKTLQ5 # 3QEFG2vy/QkgIpWeOkpYBQt7kQyyo0XUMECL16CY8tLaDq6/sgooSGU4WK7TxgAU # 66GiV/VA0nJi2QkOdx9mH1BGcEjR9UMvjnvNdOUYZ2nwfg77vjHjDdI6+DFITf/W # 3EPCKGaZBijYqsLxK2kAzM21lj+6XGXcuYnUGVWw5xte+2J4pr7LRuj1ZgWgQo8i # qU9pS9HAz37IQumAz5ibi8/MeeyRqQkGjqyXvCL5v3PM4Ct6atgbpN0pW17GnUZ7 # oJQMxpnsie1l2VmdwbMZX8MOmnTA37AX2fMfhsjctGRtiF+Jd4XW7gAtDdsdhBtz # I56DxTt+2oe/P35xpggH7s75Xj9k78QpWcG4HQcCxEsXNbFk0kWf6+UMCGyP1H5F # 6kcO8zKrqBo= # =HPaT # -----END PGP SIGNATURE----- # gpg: Signature made Mon 21 Jul 2025 04:14:26 EDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2025-07-21' of https://gitlab.com/thuth/qemu: docs/devel: fix over-quoting of QEMU_TEST_KEEP_SCRATCH functional: always enable all python warnings functional: ensure sockets and files are closed functional: ensure log handlers are closed linux-headers: Remove the 32-bit arm headers Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-07-21Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into stagingStefan Hajnoczi4-40/+26
# -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEIV1G9IJGaJ7HfzVi7wSWWzmNYhEFAmh91p0ACgkQ7wSWWzmN # YhG+2wgAqw3G2TGRPT29ObyYDcd2Z54jdnNpX5gEND/UnqENprXfdD3PR58bnxe3 # uJGPRkMXgkIDit61lshsb8DF8x9ZEIlm/Ax5FM0ksBczWDYHiyEuXoyt2Uai1kWY # fLBkVfjFqCu1AGniboCZiC4ZawZXIqkx/+DI3J/XRqa+bSCQ18I15dsLD/yxU/pp # Hwxp07/d+UayANdxs0mZ5Lr7a1ktTgytCt0O2jQNHlMzfOvdBbVbF/WGclMWfNgI # 68HWPY7P8k8jRTRFx3H/0LyYQrPyseTpa3zHC+zW9jNskkPkhCwlAY4UDC8x8LII # OjsDc/0nre626rNCiJlifD3UJ7t86A== # =xj23 # -----END PGP SIGNATURE----- # gpg: Signature made Mon 21 Jul 2025 01:56:45 EDT # gpg: using RSA key 215D46F48246689EC77F3562EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [full] # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * tag 'net-pull-request' of https://github.com/jasowang/qemu: net/vhost-user: Remove unused "err" from chr_closed_bh() (CID 1612365) net/passt: Initialize "error" variable in net_passt_send() (CID 1612368) net/passt: Check return value of g_remove() in net_passt_cleanup() (CID 1612369) net/passt: Remove dead code in passt_vhost_user_start error path (CID 1612371) net/vhost-user: Remove unused "err" from net_vhost_user_event() (CID 1612372) net/passt: Remove unused "err" from passt_vhost_user_event() (CID 1612375) hw/net/npcm_gmac.c: Drop 'buf' local variable hw/net/npcm_gmac.c: Correct test for when to reallocate packet buffer hw/net/npcm_gmac.c: Unify length and prev_buf_size variables hw/net/npcm_gmac.c: Send the right data for second packet in a row tap: fix net_init_tap() return code net/tap: drop too small packets Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2025-07-21crypto: load all certificates in X509 CA fileHenry Kleynhans1-12/+11
Some CA files may contain multiple intermediaries and roots of trust. These may not fit into the hard-coded limit of 16. Extend the validation code to allocate enough space to load all of the certificates present in the CA file and ensure they are cleaned up. Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Henry Kleynhans <hkleynhans@fb.com> [DB: drop MAX_CERTS constant & whitespace tweaks] Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2025-07-21hvf: arm: Emulate ICC_RPR_EL1 accesses properlyZenghui Yu1-0/+2
Commit a2260983c655 ("hvf: arm: Add support for GICv3") added GICv3 support by implementing emulation for a few system registers. ICC_RPR_EL1 was defined but not plugged in the sysreg handlers (for no good reason). Fix it. Fixes: a2260983c655 ("hvf: arm: Add support for GICv3") Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250714160139.10404-3-zenghui.yu@linux.dev Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-21hvf: arm: Add permission check in GIC sysreg handlersZenghui Yu1-0/+6
Quoting Peter Maydell: " hvf_sysreg_read_cp() and hvf_sysreg_write_cp() do not check the .access field of the ARMCPRegInfo to ensure that they forbid writes to registers that are marked with a .access field that says they're read-only (and ditto reads to write-only registers). " Before we add more registers in GIC sysreg handlers, let's get it correct by adding the .access checks to hvf_sysreg_read_cp() and hvf_sysreg_write_cp(). With that, a sysreg access with invalid permission will result in an UNDEFINED exception. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Zenghui Yu <zenghui.yu@linux.dev> Message-id: 20250714160139.10404-2-zenghui.yu@linux.dev Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-21target/arm: Make LD1Q decode and trans fn agree about a->uPeter Maydell1-1/+1
For the LD1Q instruction (gather load of quadwords) we use the LD1_zprz pattern with MO_128 elements. At this element size there is no signed vs unsigned distinction, and we only set the 'u' bit in the arg_LD1_zprz struct because we share the code and decode struct with smaller element sizes. However, we set u=0 in the decode pattern line but then accidentally asserted that it was 1 in the trans function. Since our usual convention is that the "default" is unsigned and we only mark operations as signed when they really do need to extend, change the decode pattern line to set u=1 to match the assert. Fixes: d2aa9a804ee6 ("target/arm: Implement LD1Q, ST1Q for SVE2p1") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250718173032.2498900-11-peter.maydell@linaro.org
2025-07-21target/arm: Honour FPCR.AH=1 default NaN value in FMAXNMQV, FMINNMQVPeter Maydell1-12/+17
The FMAXNMQV and FMINNMQV insns use the default NaN as their identity value for inactive source vector elements. We open-coded this in sve_helper.c, hoping to avoid a function call. However, this fails to account for FPCR.AH=1 changing the default NaN value to set the sign bit. Use a call to floatN_default_nan() to obtain this value. Fixes: 1de7ecfc12d05 ("target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250718173032.2498900-10-peter.maydell@linaro.org
2025-07-21target/arm: Don't nest H() macro calls in SVE DO_REDUCEPeter Maydell1-1/+1
In the part of the SVE DO_REDUCE macro used by the SVE2p1 FMAXQV, FMINQV, etc insns, we incorrectly applied the H() macro twice when calculating an offset to add to the vn pointer. This has no effect on little-endian hosts but on big-endian hosts the two invocations will cancel each other out and we will access the wrong part of the array. The "s * 16" part of the expression is already aligned, so we only need to use the H macro on the "e". Correct the macro usage. Fixes: 1de7ecfc12d05 ("target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250718173032.2498900-9-peter.maydell@linaro.org
2025-07-21target/arm: Correct sense of FPCR.AH test for FMAXQV and FMINQVPeter Maydell1-2/+2
When we implemented the FMAXQV and FMINQV insns we accidentally inverted the sense of the FPCR.AH test, so we gave the AH=1 behaviour when FPCR.AH was zero, and vice-versa. (The difference is limited to handling of negative zero and NaN inputs.) Fixes: 1de7ecfc12d05 ("target/arm: Implement FADDQV, F{MIN, MAX}{NM}QV for SVE2p1") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20250718173032.2498900-8-peter.maydell@linaro.org
2025-07-21target/arm: Add BFMLA, BFMLS (indexed)Peter Maydell2-9/+18
FEAT_SVE_B16B16 adds bfloat16 versions of the FMLA and FMLS insns in the SVE floating-point multiply-add (indexed) insn group. Implement these. Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250718173032.2498900-7-peter.maydell@linaro.org
2025-07-21target/arm: Add BFMLA, BFMLS (vectors)Peter Maydell3-6/+98
FEAT_SVE_B16B16 adds bfloat16 versions of the FMLA and FMLS insns in the "SVE floating-point multiply-accumulate writing addend" group, encoded as sz=0b00. Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250718173032.2498900-6-peter.maydell@linaro.org
2025-07-21target/arm: Add BFMUL (indexed)Peter Maydell4-1/+5
FEAT_SVE_B16B16 adds a bfloat16 version of the FMUL insn in the floating-point multiply (indexed) instruction group. The encoding is slightly bespoke; in our implementation we use MO_8 to indicate bfloat16, as with the other B16B16 insns. Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250718173032.2498900-5-peter.maydell@linaro.org
2025-07-21target/arm: Add BFMIN, BFMAX (predicated)Peter Maydell3-2/+27
FEAT_SVE_B16B16 adds bfloat16 versions of the SVE floating point (predicated) instructions, which are encoded via sz=0b00. Add the BFMAX and BFMIN insns. These have separate behaviour for AH=1 and AH=0; we have already implemented the AH=1 helper for the SME2 versions of these insns. Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250718173032.2498900-4-peter.maydell@linaro.org
2025-07-21target/arm: Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM (predicated)Peter Maydell3-5/+32
FEAT_SVE_B16B16 adds bfloat16 versions of the SVE floating point (predicated) instructions, which are encoded via sz=0b00. Add BFADD, BFSUB, BFMUL, BFMAXNM, BFMINNM; these are all the insns in this group which do not change behaviour for AH=1. We will deal with BFMAX/BFMIN (which do have different AH=1 behaviour) in a following commit. Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250718173032.2498900-3-peter.maydell@linaro.org
2025-07-21target/arm: Add BFADD, BFSUB, BFMUL (unpredicated)Peter Maydell3-1/+11
FEAT_SVE_B16B16 adds bfloat16 versions of the SVE floating point (unpredicated) instructions, which are encoded via sz==0b00. Fixes: 7b1613a1020d2942 ("target/arm: Enable FEAT_SME2p1 on -cpu max") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20250718173032.2498900-2-peter.maydell@linaro.org
2025-07-21docs: Fix Aspeed titleCédric Le Goater1-0/+1
commit ad8e0e8a0088 removed the "======" underlining the file title which broke documentation rendering. Add it back. Fixes: ad8e0e8a0088 ("docs: add support for gb200-bmc") Cc: Ed Tanous <etanous@nvidia.com> Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Ed Tanous <etanous@nvidia.com> Message-id: 20250715061904.97540-1-clg@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2025-07-21hw/misc/max78000_aes: Comment Internal Key StorageJackson Donaldson1-0/+6
Coverity Scan noted an unusual pattern in the MAX78000 aes device, with duplicated calls to set_decrypt. This commit adds a comment noting why the implementation is correct. Signed-off-by: Jackson Donaldson <jcksn@duck.com> Message-id: 20250716002622.84685-1-jcksn@duck.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-09-19 23:15:18 +0000