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| author | Luc Michel <luc.michel@amd.com> | 2025-09-26 09:07:42 +0200 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2025-10-07 10:35:36 +0100 |
| commit | d95bf385567dc635f4cf275af118f3774e3b3d29 (patch) | |
| tree | 9d01ffef391393ce33a99d4baf7f3f42115ab716 /scripts/lib/kdoc/kdoc_files.py | |
| parent | 27493e5e687e65829f548bf0145dd44bc223fbe5 (diff) | |
| download | qemu-d95bf385567dc635f4cf275af118f3774e3b3d29.zip qemu-d95bf385567dc635f4cf275af118f3774e3b3d29.tar.gz qemu-d95bf385567dc635f4cf275af118f3774e3b3d29.tar.bz2 | |
hw/arm/xlnx-versal: add support for multiple GICs
The Versal SoC contains two GICs: one GICv3 in the APU and one GICv2 in
the RPU (currently not instantiated). To prepare for the GICv2
instantiation, add support for multiple GICs when connecting interrupts.
When a GIC is created, the first-cpu-index property is set on it, and a
pointer to the GIC is stored in the intc array. When connecting an IRQ,
a TYPE_SPLIT_IRQ device is created with its num-lines property set to
the number of GICs in the SoC. The split device is used to fan out the
IRQ to all the GICs.
Signed-off-by: Luc Michel <luc.michel@amd.com>
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250926070806.292065-25-luc.michel@amd.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'scripts/lib/kdoc/kdoc_files.py')
0 files changed, 0 insertions, 0 deletions