aboutsummaryrefslogtreecommitdiff
path: root/machine
AgeCommit message (Collapse)AuthorFilesLines
2024-02-15Zicfilp: Regenerate machine/encoding.hMing-Yi Lai1-12381/+4066
2023-03-27Revert "Revert "SBI emulation of reads and writes to perf counters and ↵Andrew Waterman1-0/+58
config (#98)"" This reverts commit 7ae86fb97b792586493255f935f2f12ff068b13f. This will continue to allow accesses to cycle/time via mcycle/mtime despite https://github.com/riscv-software-src/riscv-isa-sim/pull/1297. The hope is this will keep most people happy while doing the right thing with Spike.
2022-04-08Stub out sysinfo syscallAndrew Waterman1-260/+10460
2022-02-17Fix sbi_console_getchar return value if no UART is presentAndrew Waterman1-1/+1
The UART drivers all return -1 if no character is present, and so that's what we should do if there's no UART at all. See discussion on https://github.com/riscv-non-isa/riscv-sbi-doc/issues/82
2021-11-22Reduce tightness of mideleg register assertion (required for H-extension) (#256)Andreas Kuster1-1/+1
2021-09-20Fix fcsr save slot address calculationAndrew Waterman1-1/+1
h/t @jrtc27
2021-09-15Revert "SBI emulation of reads and writes to perf counters and config (#98)"Andrew Waterman1-58/+0
This reverts commit fd2ddce557a9085ccdba1a455eded4808e7466c6. The SBI took a different approach (explicit SBI call) to support writing the counters, rather than using traps.
2021-08-12Fix build break from recent merge conflictAndrew Waterman1-1/+1
Resolves #249
2021-08-04Use __builtin_frame_address() instead of "sp" directly.John Baldwin1-3/+3
Also use pointer arithmetic on char * instead of void *.
2021-08-04Revert "machine: fix a case of undefined behaviour with SP handling (#245)"Andrew Waterman1-8/+3
This reverts commit 5450c2f731f16abe3a4f244c383c55f559c97359.
2021-08-04Revert "Revert "Use a global 'tp' register.""Andrew Waterman1-5/+7
This reverts commit 717702ceec053afd424a41ef6a4078d3cbd755b8.
2021-08-04Revert "Use __builtin_frame_address() instead of "sp" directly."Andrew Waterman1-4/+9
This reverts commit 17bec41e9bd44c43901938b784680661b9b28a76.
2021-08-04Use __builtin_frame_address() instead of "sp" directly.John Baldwin1-9/+4
Also use pointer arithmetic on char * instead of void *.
2021-08-04Revert "Use a global 'tp' register."Andrew Waterman1-7/+5
This reverts commit 0d1fdc2e24b7b6247a55d24c13ae85dca7f45695.
2021-08-04Use a global 'tp' register.John Baldwin1-5/+7
clang only supports register variables if they are declared globally.
2021-08-04Revert "machine: correct some additional cases of UB (#246)"Andrew Waterman1-18/+4
This reverts commit e8d15a489fa76612707ff9e99feb0fb36acc9f14.
2021-06-16Set desired endianness at boot time (#247)Marcus Comstedt2-0/+27
2021-05-07machine: correct some additional cases of UB (#246)Saleem Abdulrasool1-4/+18
Use of asm aliased register variables in local scope can only be used for extended assembly parameters. This changes the few instances of this in the floating point emulation to use the GNU extended assembly syntax to access the `tp` register. This ensures that we do not rely on undefined behaviour. This was uncovered when building the Proxy kernel with clang and LLVM.
2021-05-07machine: fix a case of undefined behaviour with SP handling (#245)Saleem Abdulrasool1-3/+8
The use of `asm` for register aliasing is supported in two different contexts: - local variables (including GNU expression statements) where it may only be used for specifying registers for input and output operands to extended `asm` syntax. c.f. https://gcc.gnu.org/onlinedocs/gcc/Local-Register-Variables.html#Local-Register-Variables - global variables where it may be used to observe the contents of a register. c.f. https://gcc.gnu.org/onlinedocs/gcc/Global-Register-Variables.html#Global-Register-Variables The two options here is to either to hoist the variable out into a global variable, but then it should not be in a header due to fears of ODR in case the optimizer does not inline it away, and thus becomes a bit more tricky. The alternative that this change actually adopts is to explicitly use a move to copy the value out via the GNU extended assembly syntax. With this change, it is now possible to build the Proxy Kernel completely with clang/LLVM and link with LLD. The generated kernel also runs under SPIKE and behaves as expected in a simple smoke test (without any executable prints the expected message, and runs a trivial RVV example).
2021-05-06machine: manually perform assembler relaxation (#244)Saleem Abdulrasool1-1/+3
This is an equivalent rewrite of the existing code. When building with gas, the `bltu` would implicitly get relaxed to the `bgeu` + `j`. This relaxation is required as the `init_other_hart` is not guaranteed to be addressable in 12-bits. When building with the LLVM IAS instead of gas we fail to link as the branch is not relaxed. This change enables LLVM to build and link this code with the LLVM IAS and lld.
2021-05-05replace `spbtr` with `satp` (#241)Saleem Abdulrasool1-1/+1
The LLVM IAS currently does not support the older spelling for the CSR. Update the references to the modern name.
2021-05-05machine: replace `mbadaddr` with `mtval` (#242)Saleem Abdulrasool4-6/+6
The LLVM IAS does not support the older name for the `mtval` CSR. This updates the name to the current spelling, which is required to build with the LLVM IAS. This remains compatible with binutils as well.
2021-05-05replace `sbadaddr` with `stval` (#243)Saleem Abdulrasool1-1/+1
This replaces use of the old `sbadaddr` CSR name with the current `stval` name. The old spelling is not supported by the LLVM IAS, however, the modern spelling is supported by both LLVM and binutils.
2021-04-28pk: Fix __clear_cache() compilation issue with recent compilers (#240)Christoph Müllner1-0/+8
Using recent compilers we get the following error message: ../pk/pk.c: In function 'run_loaded_program.constprop': ../pk/pk.c:177:3: error: both arguments to '__builtin___clear_cache' must be pointers 177 | __clear_cache(0, 0); | ^~~~~~~~~~~~~~~~~~~ Let's use the existing function __riscv_flush_icache(), give it a header with a prototype and use it to emits the FENCE.I instruction directly. See #239 Suggested-by: Andrew Waterman <andrew@sifive.com> Signed-off-by: Christoph Muellner <cmuellner@linux.com>
2021-04-05LiteX UART: fix compatible property name (#237)gsomlo1-1/+2
The upstream LiteX project defaults to "litex,liteuart" as the value for the "compatible" property of the UART DT node, so let's add it to the current list of accepted strings. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2021-03-29M-mode code doesn't need access to pk's page tableAndrew Waterman2-2/+0
2021-03-29update encoding.hAndrew Waterman1-267/+1145
2020-12-15Add support for the UART interface on the LiteX SoC (#230)gsomlo5-1/+101
Tested using the RocketChip CPU option. (see https://github.com/enjoy-digital/litex) Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2020-11-23Fix emulation of misaligned access on big endian target (#224)Marcus Comstedt2-3/+32
2020-11-11fdt: Skip byteorder swap on big endianMarcus Comstedt1-0/+5
2020-10-31Disable device tree filter when load a dts from file (#219)Yan3-0/+25
* add device tree in elf, using --with-dts to add the absolute path of device tree * Disable device tree filter * Remove *.dtb dependence, when the --with-dts option is not used
2020-10-30Revert "Disable device tree filter when load a dts from file (#217)"Andrew Waterman3-22/+0
This reverts commit a161e6f3ef31004e47a5b94b85c2e84b764f8637. Resolves #218
2020-10-29Disable device tree filter when load a dts from file (#217)Yan3-0/+22
* add device tree in elf, using --with-dts to add the absolute path of device tree * Disable device tree filter
2020-08-07make htif_poweroff thread-safe (#211)Howard Mao1-2/+3
2020-07-31Don't perform 64-bit accesses to the PLIC (#205)Alexander Richardson3-7/+7
Recent QEMU will fault for 8-byte accesses. Use a uint32_t instead of uintptr_t to avoid those problems.
2020-07-18Fix UART register map (#208)Nicholas O'Brien1-1/+3
While it's unused upstream, according to the SiFive FU540 document, the UART divisor register is at offset 0x18. This also maps the interrupt enable and interrupt pending register offsets.
2020-06-07Consistently use fdt_string_list for FDT compatible property (#202)Jessica Clarke3-3/+3
QEMU's finisher is "sifive,test1\0sifive,test0\0syscon" so we fail to detect it currently. Instead, search the entire list, and for completeness do the same with the HTIF and SiFive UART drivers.
2020-03-29Update encoding.h from riscv-opcodes (#194)Kito Cheng1-246/+1573
- Update to riscv-opcodes/231c5d58940113b006aa9fa22f47c18d5fac4123
2020-02-02Support manually zeroing out BSS when booting (#188)James Clarke1-1/+15
Some ELF loaders, in particular gdb's load command for dynamically loading files into memory, which is often used to load binaries onto FPGAs over JTAG, do not zero out BSS, leaving the memory in whatever state it was previously in. Thus, introduce a new --enable-zero-bss configure flag, which will include code to zero out BSS when booting.
2020-01-13Enable vector unit if present (continuation of ↵Andrew Waterman2-2/+7
77a5df569451571d608650a34183d53df99790ec)
2020-01-11Enable vector unit if presentAndrew Waterman2-0/+5
2019-12-06Only prohibit float32-only when FP emulation is enabledAndrew Waterman3-7/+22
2019-11-06Support a subset of 16750 functionality, and improve baud rate selection (#182)Jonathan Kimmitt1-3/+15
2019-10-31fdt: allow mmu type "riscv,32" on rv32 systems (#177)Gokturk Yuksek1-0/+4
SV32 is presented in RISC-V Privileged Architecture Manual (version 20190608-Priv-MSU-Ratified) Section 4.3 for RV32 systems. However, BBL responds to sv32 with: hart_filter_mask saw unknown hart type: status="okay", mmu_type="riscv,sv32" and hangs. This patch is adopted from the original 'riscv-pk.diff' patch written by Fabrice Bellard, distributed as part of the following tarball: https://bellard.org/tinyemu/diskimage-linux-riscv-2018-09-23.tar.gz Closes: https://github.com/riscv/riscv-pk/issues/160
2019-08-12allow additional ns16550a config via device treeMichael Panzlaff3-14/+54
This commit makes bbl read some additional fields from the device tree if it detects an ns16550a: - reg-shift - reg-offset - clock-frequency For explanation of these check out the Linux Kernel doc: https://www.kernel.org/doc/Documentation/devicetree/bindings/serial/8250.txt In particular this allows the Xilinx AXI UART 16550 to act as serial console with bbl and the Linux early boot console. This also fixes a bug in which bbl will ignore any other than the first "compatible" string when iterating over the nodes. Previously this line would not have worked: compatible = "xlnx,xps-uart16550-2.00.a", "ns16550a"; Before bbl would have just checked the first field instead of checking all strings in the list.
2019-07-17Make illegal-instruction jump table entries relative to their baseAndrew Waterman2-77/+77
This supports bbl living above 4 GiB.
2019-07-17Use pointer-sized entries in trap tableAndrew Waterman1-19/+19
This allows bbl to be loaded above 4 GiB on RV64.
2019-07-05Report correct scause when faulting while fetching emulated instructionAndrew Waterman2-7/+26
2019-06-11Check for 'U' extension before accessing 'mcounteren' CSRGabriel L. Somlo1-1/+2
On 64-bit Rocket with 'DefaultFPGAConfig' (using 'WithNSmallCores'), the 'U' extension is not supported, and accessing 'mcounteren' would trigger an 'Illegal Instruction' trap. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
2019-01-04Set up PMP earlier, so it can be overridden laterAndrew Waterman2-5/+3
generated by cgit v1.1 at 2024-11-04 14:51:55 +0000