This commit was manufactured by cvs2svn to create branch 'gdb_5_2-branch'.

Sprout from binutils-2_12-branch 2002-02-09 22:54:17 UTC cvs2svn 'This commit was manufactured by cvs2svn to create branch 'binutils-'
Cherrypick from master 2002-03-01 00:52:59 UTC Alexandre Oliva <aoliva@redhat.com> '* configure.in (libstdcxx_flags): Don't add libstdc++-v3 flags for':
    ChangeLog
    Makefile.in
    config.guess
    config.sub
    configure.in
    etc/ChangeLog
    etc/fdl.texi
    etc/make-stds.texi
    etc/standards.texi
    include/ChangeLog
    include/bfdlink.h
    include/elf/ChangeLog
    include/elf/m68k.h
    include/elf/ppc.h
    include/opcode/ChangeLog
    include/opcode/i386.h
    include/opcode/ppc.h
    include/splay-tree.h
    texinfo/texinfo.tex
Cherrypick from master 2002-03-11 00:01:11 UTC Daniel Jacobowitz <drow@false.org> 'gdb/:':
    include/gdb/ChangeLog
    include/gdb/signals.h

11 files changed, 391 insertions, 55 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index c0fd95b..8ccea05 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,19 @@
+2002-02-21  Jim Blandy  <jimb@redhat.com>
+
+	Allow the user to specify functions for allocating memory for
+	splay tree roots and nodes.
+	* splay-tree.h (splay_tree_allocate_fn, splay_tree_deallocate_fn):
+	New types.
+	(splay_tree): New fields: `allocate', `deallocate', and
+	`allocate_data'.
+	(splay_tree_new_with_allocator): New function declaration.
+
+2002-02-15  Alan Modra  <amodra@bigpond.net.au>
+
+	Support arbitrary length fill patterns.
+	* bfdlink.h (enum bfd_link_order_type): Remove bfd_fill_link_order.
+	(struct bfd_link_order): Remove fill.  Add data.size.
+
 2002-02-08  Alexandre Oliva  <aoliva@redhat.com>
 
 	Contribute sh64-elf.
diff --git a/include/bfdlink.h b/include/bfdlink.h
index c02a1e8..a034547 100644
--- a/include/bfdlink.h
+++ b/include/bfdlink.h
@@ -1,5 +1,5 @@
 /* bfdlink.h -- header file for BFD link routines
-   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000
+   Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2002
    Free Software Foundation, Inc.
    Written by Steve Chamberlain and Ian Lance Taylor, Cygnus Support.
 
@@ -446,7 +446,6 @@ enum bfd_link_order_type
 {
   bfd_undefined_link_order,	/* Undefined.  */
   bfd_indirect_link_order,	/* Built from a section.  */
-  bfd_fill_link_order,		/* Fill with a 16 bit constant.  */
   bfd_data_link_order,		/* Set to explicit data.  */
   bfd_section_reloc_link_order,	/* Relocate against a section.  */
   bfd_symbol_reloc_link_order	/* Relocate against a symbol.  */
@@ -480,13 +479,12 @@ struct bfd_link_order
 	} indirect;
       struct
 	{
-	  /* Value to fill with.  */
-	  unsigned int value;
-	} fill;
-      struct
-	{
-	  /* Data to put into file.  The size field gives the number
-	     of bytes which this field points to.  */
+	  /* Size of contents, or zero when contents size == size
+	     within output section.
+	     A non-zero value allows filling of the output section
+	     with an arbitrary repeated pattern.  */
+	  unsigned int size;
+	  /* Data to put into file.  */
 	  bfd_byte *contents;
 	} data;
       struct
diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index 79f99ac..e70f7fd 100644
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,11 @@
+2002-02-13  Matt Fredette  <fredette@netbsd.org>
+
+	* m68k.h (EF_M68000): Define.
+
+2002-02-12  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (DT_PPC64_OPD, DT_PPC64_OPDSZ): Define.
+
 2002-02-09  Richard Henderson  <rth@redhat.com>
 
 	* alpha.h (R_ALPHA_BRSGP): New.
diff --git a/include/elf/m68k.h b/include/elf/m68k.h
index 03bf465..7769c59 100644
--- a/include/elf/m68k.h
+++ b/include/elf/m68k.h
@@ -53,5 +53,6 @@ START_RELOC_NUMBERS (elf_m68k_reloc_type)
 END_RELOC_NUMBERS (R_68K_max)
 
 #define EF_CPU32    0x00810000
+#define EF_M68000   0x01000000
 
 #endif
diff --git a/include/elf/ppc.h b/include/elf/ppc.h
index 8e4af62..dfb43f4 100644
--- a/include/elf/ppc.h
+++ b/include/elf/ppc.h
@@ -174,6 +174,10 @@ END_RELOC_NUMBERS (R_PPC_max)
 /* Specify the start of the .glink section.  */
 #define DT_PPC64_GLINK		DT_LOPROC
 
+/* Specify the start and size of the .opd section.  */
+#define DT_PPC64_OPD		(DT_LOPROC + 1)
+#define DT_PPC64_OPDSZ		(DT_LOPROC + 2)
+
 /* Processor specific flags for the ELF header e_flags field.  */
 
 #define	EF_PPC_EMB		0x80000000	/* PowerPC embedded flag.  */
diff --git a/include/gdb/ChangeLog b/include/gdb/ChangeLog
new file mode 100644
index 0000000..5d83a64
--- /dev/null
+++ b/include/gdb/ChangeLog
@@ -0,0 +1,11 @@
+2002-03-10  Daniel Jacobowitz  <drow@mvista.com>
+
+	* signals.h: New file, from gdb/defs.h.
+
+
+Local Variables:
+mode: change-log
+left-margin: 8
+fill-column: 74
+version-control: never
+End:
diff --git a/include/gdb/signals.h b/include/gdb/signals.h
new file mode 100644
index 0000000..1710750
--- /dev/null
+++ b/include/gdb/signals.h
@@ -0,0 +1,233 @@
+/* Target signal numbers for GDB and the GDB remote protocol.
+   Copyright 1986, 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996,
+   1997, 1998, 1999, 2000, 2001, 2002
+   Free Software Foundation, Inc.
+
+   This file is part of GDB.
+
+   This program is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 2 of the License, or
+   (at your option) any later version.
+
+   This program is distributed in the hope that it will be useful,
+   but WITHOUT ANY WARRANTY; without even the implied warranty of
+   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+   GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+#ifndef GDB_SIGNALS_H
+#define GDB_SIGNALS_H
+
+/* The numbering of these signals is chosen to match traditional unix
+   signals (insofar as various unices use the same numbers, anyway).
+   It is also the numbering of the GDB remote protocol.  Other remote
+   protocols, if they use a different numbering, should make sure to
+   translate appropriately.
+
+   Since these numbers have actually made it out into other software
+   (stubs, etc.), you mustn't disturb the assigned numbering.  If you
+   need to add new signals here, add them to the end of the explicitly
+   numbered signals.
+
+   This is based strongly on Unix/POSIX signals for several reasons:
+   (1) This set of signals represents a widely-accepted attempt to
+   represent events of this sort in a portable fashion, (2) we want a
+   signal to make it from wait to child_wait to the user intact, (3) many
+   remote protocols use a similar encoding.  However, it is
+   recognized that this set of signals has limitations (such as not
+   distinguishing between various kinds of SIGSEGV, or not
+   distinguishing hitting a breakpoint from finishing a single step).
+   So in the future we may get around this either by adding additional
+   signals for breakpoint, single-step, etc., or by adding signal
+   codes; the latter seems more in the spirit of what BSD, System V,
+   etc. are doing to address these issues.  */
+
+/* For an explanation of what each signal means, see
+   target_signal_to_string.  */
+
+enum target_signal
+  {
+    /* Used some places (e.g. stop_signal) to record the concept that
+       there is no signal.  */
+    TARGET_SIGNAL_0 = 0,
+    TARGET_SIGNAL_FIRST = 0,
+    TARGET_SIGNAL_HUP = 1,
+    TARGET_SIGNAL_INT = 2,
+    TARGET_SIGNAL_QUIT = 3,
+    TARGET_SIGNAL_ILL = 4,
+    TARGET_SIGNAL_TRAP = 5,
+    TARGET_SIGNAL_ABRT = 6,
+    TARGET_SIGNAL_EMT = 7,
+    TARGET_SIGNAL_FPE = 8,
+    TARGET_SIGNAL_KILL = 9,
+    TARGET_SIGNAL_BUS = 10,
+    TARGET_SIGNAL_SEGV = 11,
+    TARGET_SIGNAL_SYS = 12,
+    TARGET_SIGNAL_PIPE = 13,
+    TARGET_SIGNAL_ALRM = 14,
+    TARGET_SIGNAL_TERM = 15,
+    TARGET_SIGNAL_URG = 16,
+    TARGET_SIGNAL_STOP = 17,
+    TARGET_SIGNAL_TSTP = 18,
+    TARGET_SIGNAL_CONT = 19,
+    TARGET_SIGNAL_CHLD = 20,
+    TARGET_SIGNAL_TTIN = 21,
+    TARGET_SIGNAL_TTOU = 22,
+    TARGET_SIGNAL_IO = 23,
+    TARGET_SIGNAL_XCPU = 24,
+    TARGET_SIGNAL_XFSZ = 25,
+    TARGET_SIGNAL_VTALRM = 26,
+    TARGET_SIGNAL_PROF = 27,
+    TARGET_SIGNAL_WINCH = 28,
+    TARGET_SIGNAL_LOST = 29,
+    TARGET_SIGNAL_USR1 = 30,
+    TARGET_SIGNAL_USR2 = 31,
+    TARGET_SIGNAL_PWR = 32,
+    /* Similar to SIGIO.  Perhaps they should have the same number.  */
+    TARGET_SIGNAL_POLL = 33,
+    TARGET_SIGNAL_WIND = 34,
+    TARGET_SIGNAL_PHONE = 35,
+    TARGET_SIGNAL_WAITING = 36,
+    TARGET_SIGNAL_LWP = 37,
+    TARGET_SIGNAL_DANGER = 38,
+    TARGET_SIGNAL_GRANT = 39,
+    TARGET_SIGNAL_RETRACT = 40,
+    TARGET_SIGNAL_MSG = 41,
+    TARGET_SIGNAL_SOUND = 42,
+    TARGET_SIGNAL_SAK = 43,
+    TARGET_SIGNAL_PRIO = 44,
+    TARGET_SIGNAL_REALTIME_33 = 45,
+    TARGET_SIGNAL_REALTIME_34 = 46,
+    TARGET_SIGNAL_REALTIME_35 = 47,
+    TARGET_SIGNAL_REALTIME_36 = 48,
+    TARGET_SIGNAL_REALTIME_37 = 49,
+    TARGET_SIGNAL_REALTIME_38 = 50,
+    TARGET_SIGNAL_REALTIME_39 = 51,
+    TARGET_SIGNAL_REALTIME_40 = 52,
+    TARGET_SIGNAL_REALTIME_41 = 53,
+    TARGET_SIGNAL_REALTIME_42 = 54,
+    TARGET_SIGNAL_REALTIME_43 = 55,
+    TARGET_SIGNAL_REALTIME_44 = 56,
+    TARGET_SIGNAL_REALTIME_45 = 57,
+    TARGET_SIGNAL_REALTIME_46 = 58,
+    TARGET_SIGNAL_REALTIME_47 = 59,
+    TARGET_SIGNAL_REALTIME_48 = 60,
+    TARGET_SIGNAL_REALTIME_49 = 61,
+    TARGET_SIGNAL_REALTIME_50 = 62,
+    TARGET_SIGNAL_REALTIME_51 = 63,
+    TARGET_SIGNAL_REALTIME_52 = 64,
+    TARGET_SIGNAL_REALTIME_53 = 65,
+    TARGET_SIGNAL_REALTIME_54 = 66,
+    TARGET_SIGNAL_REALTIME_55 = 67,
+    TARGET_SIGNAL_REALTIME_56 = 68,
+    TARGET_SIGNAL_REALTIME_57 = 69,
+    TARGET_SIGNAL_REALTIME_58 = 70,
+    TARGET_SIGNAL_REALTIME_59 = 71,
+    TARGET_SIGNAL_REALTIME_60 = 72,
+    TARGET_SIGNAL_REALTIME_61 = 73,
+    TARGET_SIGNAL_REALTIME_62 = 74,
+    TARGET_SIGNAL_REALTIME_63 = 75,
+
+    /* Used internally by Solaris threads.  See signal(5) on Solaris.  */
+    TARGET_SIGNAL_CANCEL = 76,
+
+    /* Yes, this pains me, too.  But LynxOS didn't have SIG32, and now
+       GNU/Linux does, and we can't disturb the numbering, since it's
+       part of the remote protocol.  Note that in some GDB's
+       TARGET_SIGNAL_REALTIME_32 is number 76.  */
+    TARGET_SIGNAL_REALTIME_32,
+    /* Yet another pain, IRIX 6 has SIG64. */
+    TARGET_SIGNAL_REALTIME_64,
+    /* Yet another pain, GNU/Linux MIPS might go up to 128. */
+    TARGET_SIGNAL_REALTIME_65,
+    TARGET_SIGNAL_REALTIME_66,
+    TARGET_SIGNAL_REALTIME_67,
+    TARGET_SIGNAL_REALTIME_68,
+    TARGET_SIGNAL_REALTIME_69,
+    TARGET_SIGNAL_REALTIME_70,
+    TARGET_SIGNAL_REALTIME_71,
+    TARGET_SIGNAL_REALTIME_72,
+    TARGET_SIGNAL_REALTIME_73,
+    TARGET_SIGNAL_REALTIME_74,
+    TARGET_SIGNAL_REALTIME_75,
+    TARGET_SIGNAL_REALTIME_76,
+    TARGET_SIGNAL_REALTIME_77,
+    TARGET_SIGNAL_REALTIME_78,
+    TARGET_SIGNAL_REALTIME_79,
+    TARGET_SIGNAL_REALTIME_80,
+    TARGET_SIGNAL_REALTIME_81,
+    TARGET_SIGNAL_REALTIME_82,
+    TARGET_SIGNAL_REALTIME_83,
+    TARGET_SIGNAL_REALTIME_84,
+    TARGET_SIGNAL_REALTIME_85,
+    TARGET_SIGNAL_REALTIME_86,
+    TARGET_SIGNAL_REALTIME_87,
+    TARGET_SIGNAL_REALTIME_88,
+    TARGET_SIGNAL_REALTIME_89,
+    TARGET_SIGNAL_REALTIME_90,
+    TARGET_SIGNAL_REALTIME_91,
+    TARGET_SIGNAL_REALTIME_92,
+    TARGET_SIGNAL_REALTIME_93,
+    TARGET_SIGNAL_REALTIME_94,
+    TARGET_SIGNAL_REALTIME_95,
+    TARGET_SIGNAL_REALTIME_96,
+    TARGET_SIGNAL_REALTIME_97,
+    TARGET_SIGNAL_REALTIME_98,
+    TARGET_SIGNAL_REALTIME_99,
+    TARGET_SIGNAL_REALTIME_100,
+    TARGET_SIGNAL_REALTIME_101,
+    TARGET_SIGNAL_REALTIME_102,
+    TARGET_SIGNAL_REALTIME_103,
+    TARGET_SIGNAL_REALTIME_104,
+    TARGET_SIGNAL_REALTIME_105,
+    TARGET_SIGNAL_REALTIME_106,
+    TARGET_SIGNAL_REALTIME_107,
+    TARGET_SIGNAL_REALTIME_108,
+    TARGET_SIGNAL_REALTIME_109,
+    TARGET_SIGNAL_REALTIME_110,
+    TARGET_SIGNAL_REALTIME_111,
+    TARGET_SIGNAL_REALTIME_112,
+    TARGET_SIGNAL_REALTIME_113,
+    TARGET_SIGNAL_REALTIME_114,
+    TARGET_SIGNAL_REALTIME_115,
+    TARGET_SIGNAL_REALTIME_116,
+    TARGET_SIGNAL_REALTIME_117,
+    TARGET_SIGNAL_REALTIME_118,
+    TARGET_SIGNAL_REALTIME_119,
+    TARGET_SIGNAL_REALTIME_120,
+    TARGET_SIGNAL_REALTIME_121,
+    TARGET_SIGNAL_REALTIME_122,
+    TARGET_SIGNAL_REALTIME_123,
+    TARGET_SIGNAL_REALTIME_124,
+    TARGET_SIGNAL_REALTIME_125,
+    TARGET_SIGNAL_REALTIME_126,
+    TARGET_SIGNAL_REALTIME_127,
+
+#if defined(MACH) || defined(__MACH__)
+    /* Mach exceptions */
+    TARGET_EXC_BAD_ACCESS,
+    TARGET_EXC_BAD_INSTRUCTION,
+    TARGET_EXC_ARITHMETIC,
+    TARGET_EXC_EMULATION,
+    TARGET_EXC_SOFTWARE,
+    TARGET_EXC_BREAKPOINT,
+#endif
+    TARGET_SIGNAL_INFO,
+
+    /* Some signal we don't know about.  */
+    TARGET_SIGNAL_UNKNOWN,
+
+    /* Use whatever signal we use when one is not specifically specified
+       (for passing to proceed and so on).  */
+    TARGET_SIGNAL_DEFAULT,
+
+    /* Last and unused enum value, for sizing arrays, etc.  */
+    TARGET_SIGNAL_LAST
+  };
+
+#endif /* #ifndef GDB_SIGNALS_H */
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 3c367d3..8d63771 100644
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,22 @@
+2002-02-25  Alan Modra  <amodra@bigpond.net.au>
+
+	* ppc.h (PPC_OPCODE_POWER4, PPC_OPCODE_NOPOWER4): Define.
+
+Mon Feb 18 17:31:48 CET 2002  Jan Hubicka  <jh@suse.cz>
+
+	* i386.h (push,pop): Fix Reg64 to WordReg to allow 16bit operands.
+
+Mon Feb 11 12:53:19 CET 2002  Jan Hubicka  <jh@suse.cz>
+
+	* i386.h (push,pop): Allow 16bit operands in 64bit mode.
+	(xchg): Fix.
+	(in, out): Disable 64bit operands.
+	(call, jmp): Avoid REX prefixes.
+	(jcxz): Prohibit in 64bit mode
+	(jrcxz, loop): Add 64bit variants.
+	(movq): Fix patterns.
+	(movmskps, pextrw, pinstrw): Add 64bit variants.
+
 2002-01-31  Ivan Guzvinec  <ivang@opencores.org>
 
 	* or32.h: New file.
diff --git a/include/opcode/i386.h b/include/opcode/i386.h
index 571990e..43d7208 100644
--- a/include/opcode/i386.h
+++ b/include/opcode/i386.h
@@ -62,6 +62,7 @@ static const template i386_optab[] = {
 #define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf)
 #define wlq_Suf (No_bSuf|No_sSuf|No_xSuf)
 #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf)
+#define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf)
 #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf)
 #define sldx_Suf (No_bSuf|No_wSuf|No_qSuf)
 #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf)
@@ -148,12 +149,12 @@ static const template i386_optab[] = {
 {"push",   1,	0x06, X, 0|CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
 {"push",   1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
 /* In 64bit mode, the operand size is implicitly 64bit.  */
-{"push",   1,	0x50, X, Cpu64,	q_Suf|ShortForm|DefaultSize|NoRex64, { Reg64, 0, 0 } },
-{"push",   1,	0xff, 6, Cpu64,	q_Suf|Modrm|DefaultSize|NoRex64, { Reg64|WordMem, 0, 0 } },
-{"push",   1,	0x6a, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
-{"push",   1,	0x68, X, Cpu186|Cpu64, q_Suf|DefaultSize|NoRex64, { Imm32S, 0, 0} },
-{"push",   1,	0x06, X, Cpu64,	q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
-{"push",   1, 0x0fa0, X, Cpu386|Cpu64, q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
+{"push",   1,	0x50, X, Cpu64,	wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } },
+{"push",   1,	0xff, 6, Cpu64,	wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } },
+{"push",   1,	0x6a, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} },
+{"push",   1,	0x68, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} },
+{"push",   1,	0x06, X, Cpu64,	wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
+{"push",   1, 0x0fa0, X, Cpu386|Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
 
 {"pusha",  0,	0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,	{ 0, 0, 0 } },
 
@@ -164,10 +165,10 @@ static const template i386_optab[] = {
 {"pop",	   1,	0x07, X, CpuNo64,	 wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } },
 {"pop",	   1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } },
 /* In 64bit mode, the operand size is implicitly 64bit.  */
-{"pop",	   1,	0x58, X, Cpu64,	 q_Suf|ShortForm|DefaultSize|NoRex64,	{ Reg64, 0, 0 } },
-{"pop",	   1,	0x8f, 0, Cpu64,	 q_Suf|Modrm|DefaultSize|NoRex64,	{ Reg64|WordMem, 0, 0 } },
-{"pop",	   1,	0x07, X, Cpu64,	 q_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
-{"pop",	   1, 0x0fa1, X, Cpu64,  q_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
+{"pop",	   1,	0x58, X, Cpu64,	 wq_Suf|ShortForm|DefaultSize|NoRex64,	{ WordReg, 0, 0 } },
+{"pop",	   1,	0x8f, 0, Cpu64,	 wq_Suf|Modrm|DefaultSize|NoRex64,	{ WordReg|WordMem, 0, 0 } },
+{"pop",	   1,	0x07, X, Cpu64,	 wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } },
+{"pop",	   1, 0x0fa1, X, Cpu64,  wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } },
 
 {"popa",   0,	0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize,		{ 0, 0, 0 } },
 
@@ -176,20 +177,20 @@ static const template i386_optab[] = {
  
    In the 64bit code, xchg eax, eax is reused for new nop instruction.
  */
-{"xchg",   2,	0x90, X, CpuNo64, wl_Suf|ShortForm,	{ WordReg, Acc, 0 } },
-{"xchg",   2,	0x90, X, CpuNo64, wl_Suf|ShortForm,	{ Acc, WordReg, 0 } },
+{"xchg",   2,	0x90, X, 0,	 wlq_Suf|ShortForm,	{ WordReg, Acc, 0 } },
+{"xchg",   2,	0x90, X, 0,	 wlq_Suf|ShortForm,	{ Acc, WordReg, 0 } },
 {"xchg",   2,	0x86, X, 0,	 bwlq_Suf|W|Modrm,	{ Reg, Reg|AnyMem, 0 } },
 {"xchg",   2,	0x86, X, 0,	 bwlq_Suf|W|Modrm,	{ Reg|AnyMem, Reg, 0 } },
 
 /* In/out from ports.  */
-{"in",	   2,	0xe4, X, 0,	 bwlq_Suf|W,		{ Imm8, Acc, 0 } },
-{"in",	   2,	0xec, X, 0,	 bwlq_Suf|W,		{ InOutPortReg, Acc, 0 } },
-{"in",	   1,	0xe4, X, 0,	 bwlq_Suf|W,		{ Imm8, 0, 0 } },
-{"in",	   1,	0xec, X, 0,	 bwlq_Suf|W,		{ InOutPortReg, 0, 0 } },
-{"out",	   2,	0xe6, X, 0,	 bwlq_Suf|W,		{ Acc, Imm8, 0 } },
-{"out",	   2,	0xee, X, 0,	 bwlq_Suf|W,		{ Acc, InOutPortReg, 0 } },
-{"out",	   1,	0xe6, X, 0,	 bwlq_Suf|W,		{ Imm8, 0, 0 } },
-{"out",	   1,	0xee, X, 0,	 bwlq_Suf|W,		{ InOutPortReg, 0, 0 } },
+{"in",	   2,	0xe4, X, 0,	 bwl_Suf|W,		{ Imm8, Acc, 0 } },
+{"in",	   2,	0xec, X, 0,	 bwl_Suf|W,		{ InOutPortReg, Acc, 0 } },
+{"in",	   1,	0xe4, X, 0,	 bwl_Suf|W,		{ Imm8, 0, 0 } },
+{"in",	   1,	0xec, X, 0,	 bwl_Suf|W,		{ InOutPortReg, 0, 0 } },
+{"out",	   2,	0xe6, X, 0,	 bwl_Suf|W,		{ Acc, Imm8, 0 } },
+{"out",	   2,	0xee, X, 0,	 bwl_Suf|W,		{ Acc, InOutPortReg, 0 } },
+{"out",	   1,	0xe6, X, 0,	 bwl_Suf|W,		{ Imm8, 0, 0 } },
+{"out",	   1,	0xee, X, 0,	 bwl_Suf|W,		{ InOutPortReg, 0, 0 } },
 
 /* Load effective address.  */
 {"lea",	   2, 0x8d,   X, 0,	 wlq_Suf|Modrm,		{ WordMem, WordReg, 0 } },
@@ -210,9 +211,9 @@ static const template i386_optab[] = {
 {"lahf",   0,	0x9f, X, CpuNo64,NoSuf,			{ 0, 0, 0} },
 {"sahf",   0,	0x9e, X, CpuNo64,NoSuf,			{ 0, 0, 0} },
 {"pushf",  0,	0x9c, X, CpuNo64,wlq_Suf|DefaultSize,	{ 0, 0, 0} },
-{"pushf",  0,	0x9c, X, Cpu64,	 q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
+{"pushf",  0,	0x9c, X, Cpu64,	 wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
 {"popf",   0,	0x9d, X, CpuNo64,wlq_Suf|DefaultSize,	{ 0, 0, 0} },
-{"popf",   0,	0x9d, X, Cpu64,	 q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
+{"popf",   0,	0x9d, X, Cpu64,	 wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} },
 {"stc",	   0,	0xf9, X, 0,	 NoSuf,			{ 0, 0, 0} },
 {"std",	   0,	0xfd, X, 0,	 NoSuf,			{ 0, 0, 0} },
 {"sti",	   0,	0xfb, X, 0,	 NoSuf,			{ 0, 0, 0} },
@@ -370,7 +371,8 @@ static const template i386_optab[] = {
 
 /* Control transfer instructions.  */
 {"call",   1,	0xe8, X, 0,	 wlq_Suf|JumpDword|DefaultSize,	{ Disp16|Disp32, 0, 0} },
-{"call",   1,	0xff, 2, 0,	 wlq_Suf|Modrm|DefaultSize,	{ WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"call",   1,	0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize,	{ WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"call",   1,	0xff, 2, Cpu64,	 wq_Suf|Modrm|DefaultSize|NoRex64,{ WordReg|WordMem|JumpAbsolute, 0, 0} },
 /* Intel Syntax */
 {"call",   2,	0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} },
 /* Intel Syntax */
@@ -381,7 +383,8 @@ static const template i386_optab[] = {
 
 #define JUMP_PC_RELATIVE 0xeb
 {"jmp",	   1,	0xeb, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
-{"jmp",	   1,	0xff, 4, 0,	 wlq_Suf|Modrm,		{ WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"jmp",	   1,	0xff, 4, CpuNo64, wl_Suf|Modrm,		{ WordReg|WordMem|JumpAbsolute, 0, 0} },
+{"jmp",	   1,	0xff, 4, Cpu64,	 wq_Suf|Modrm|NoRex64,	{ WordReg|WordMem|JumpAbsolute, 0, 0} },
 /* Intel Syntax */
 {"jmp",    2,	0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} },
 /* Intel Syntax */
@@ -432,18 +435,25 @@ static const template i386_optab[] = {
 {"jg",	   1,	0x7f, X, 0,	 NoSuf|Jump,		{ Disp, 0, 0} },
 
 /* jcxz vs. jecxz is chosen on the basis of the address size prefix.  */
-{"jcxz",   1,	0xe3, X, 0,	 NoSuf|JumpByte|Size16, { Disp, 0, 0} },
-{"jecxz",  1,	0xe3, X, 0,	 NoSuf|JumpByte|Size32, { Disp, 0, 0} },
+{"jcxz",  1,	0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} },
+{"jecxz",  1,	0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
+{"jecxz",  1,	0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} },
+{"jrcxz",  1,	0xe3, X, Cpu64,  NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} },
 
 /* The loop instructions also use the address size prefix to select
    %cx rather than %ecx for the loop count, so the `w' form of these
    instructions emit an address size prefix rather than a data size
    prefix.  */
-{"loop",   1,	0xe2, X, 0,	 wlq_Suf|JumpByte,	{ Disp, 0, 0} },
-{"loopz",  1,	0xe1, X, 0,	 wlq_Suf|JumpByte,	{ Disp, 0, 0} },
-{"loope",  1,	0xe1, X, 0,	 wlq_Suf|JumpByte,	{ Disp, 0, 0} },
-{"loopnz", 1,	0xe0, X, 0,	 wlq_Suf|JumpByte,	{ Disp, 0, 0} },
-{"loopne", 1,	0xe0, X, 0,	 wlq_Suf|JumpByte,	{ Disp, 0, 0} },
+{"loop",   1,	0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loop",   1,	0xe2, X, Cpu64,	 lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loopz",  1,	0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loopz",  1,	0xe1, X, Cpu64,	 lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loope",  1,	0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loope",  1,	0xe1, X, Cpu64,	 lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loopnz", 1,	0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loopnz", 1,	0xe0, X, Cpu64,	 lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
+{"loopne", 1,	0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} },
+{"loopne", 1,	0xe0, X, Cpu64,	 lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} },
 
 /* Set byte on flag instructions.  */
 {"seto",   1, 0x0f90, 0, Cpu386, b_Suf|Modrm,		{ Reg8|ByteMem, 0, 0} },
@@ -482,10 +492,10 @@ static const template i386_optab[] = {
 {"cmps",   2,	0xa6, X, 0,	 bwlq_Suf|W|IsString,	{ AnyMem|EsSeg, AnyMem, 0} },
 {"scmp",   0,	0xa6, X, 0,	 bwlq_Suf|W|IsString,	{ 0, 0, 0} },
 {"scmp",   2,	0xa6, X, 0,	 bwlq_Suf|W|IsString,	{ AnyMem|EsSeg, AnyMem, 0} },
-{"ins",	   0,	0x6c, X, Cpu186, bwlq_Suf|W|IsString,	{ 0, 0, 0} },
-{"ins",	   2,	0x6c, X, Cpu186, bwlq_Suf|W|IsString,	{ InOutPortReg, AnyMem|EsSeg, 0} },
-{"outs",   0,	0x6e, X, Cpu186, bwlq_Suf|W|IsString,	{ 0, 0, 0} },
-{"outs",   2,	0x6e, X, Cpu186, bwlq_Suf|W|IsString,	{ AnyMem, InOutPortReg, 0} },
+{"ins",	   0,	0x6c, X, Cpu186, bwl_Suf|W|IsString,	{ 0, 0, 0} },
+{"ins",	   2,	0x6c, X, Cpu186, bwl_Suf|W|IsString,	{ InOutPortReg, AnyMem|EsSeg, 0} },
+{"outs",   0,	0x6e, X, Cpu186, bwl_Suf|W|IsString,	{ 0, 0, 0} },
+{"outs",   2,	0x6e, X, Cpu186, bwl_Suf|W|IsString,	{ AnyMem, InOutPortReg, 0} },
 {"lods",   0,	0xac, X, 0,	 bwlq_Suf|W|IsString,	{ 0, 0, 0} },
 {"lods",   1,	0xac, X, 0,	 bwlq_Suf|W|IsString,	{ AnyMem, 0, 0} },
 {"lods",   2,	0xac, X, 0,	 bwlq_Suf|W|IsString,	{ AnyMem, Acc, 0} },
@@ -971,12 +981,16 @@ static const template i386_optab[] = {
 {"movd",     2, 0x660f6e,X,CpuSSE2,FP|Modrm,		{ Reg32|LLongMem, RegXMM, 0 } },
 {"movd",     2, 0x660f7e,X,CpuSSE2,FP|Modrm,		{ RegXMM, Reg32|LLongMem, 0 } },
 /* Real MMX instructions.  */
+{"movd",     2, 0x0f6e, X, CpuMMX, FP|Modrm,		{ Reg64|LLongMem, RegMMX, 0 } },
+{"movd",     2, 0x0f7e, X, CpuMMX, FP|Modrm,		{ RegMMX, Reg64|LLongMem, 0 } },
+{"movd",     2, 0x660f6e,X,CpuSSE2,FP|Modrm,		{ Reg64|LLongMem, RegXMM, 0 } },
+{"movd",     2, 0x660f7e,X,CpuSSE2,FP|Modrm,		{ RegXMM, Reg64|LLongMem, 0 } },
+/* In the 64bit mode the short form mov immediate is redefined to have
+   64bit displacement value.  */
 {"movq",     2, 0x0f6f, X, CpuMMX, FP|Modrm,		{ RegMMX|LongMem, RegMMX, 0 } },
 {"movq",     2, 0x0f7f, X, CpuMMX, FP|Modrm,		{ RegMMX, RegMMX|LongMem, 0 } },
 {"movq",     2, 0xf30f7e,X,CpuSSE2,FP|Modrm,		{ RegXMM|LLongMem, RegXMM, 0 } },
 {"movq",     2, 0x660fd6,X,CpuSSE2,FP|Modrm,		{ RegXMM, RegXMM|LLongMem, 0 } },
-/* In the 64bit mode the short form mov immediate is redefined to have
-   64bit displacement value.  */
 {"movq",   2,	0x88, X, Cpu64,	 NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } },
 {"movq",   2,	0xc6, 0, Cpu64,	 NoSuf|W|Modrm|Size64,	{ Imm32S, Reg64|WordMem, 0 } },
 {"movq",   2,	0xb0, X, Cpu64,	 NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } },
@@ -1140,7 +1154,7 @@ static const template i386_optab[] = {
 {"movlhps",   2, 0x0f16,    X, CpuSSE, FP|Modrm,	{ RegXMM|InvMem, RegXMM, 0 } },
 {"movlps",    2, 0x0f12,    X, CpuSSE, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
 {"movlps",    2, 0x0f13,    X, CpuSSE, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
-{"movmskps",  2, 0x0f50,    X, CpuSSE, FP|Modrm,	{ RegXMM|InvMem, Reg32, 0 } },
+{"movmskps",  2, 0x0f50,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,	{ RegXMM|InvMem, Reg32|Reg64, 0 } },
 {"movntps",   2, 0x0f2b,    X, CpuSSE, FP|Modrm, 	{ RegXMM, LLongMem, 0 } },
 {"movntq",    2, 0x0fe7,    X, CpuSSE, FP|Modrm, 	{ RegMMX, LLongMem, 0 } },
 {"movntdq",   2, 0x660fe7,  X, CpuSSE2,FP|Modrm, 	{ RegXMM, LLongMem, 0 } },
@@ -1155,10 +1169,10 @@ static const template i386_optab[] = {
 {"pavgb",     2, 0x660fe0,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 {"pavgw",     2, 0x0fe3,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
 {"pavgw",     2, 0x660fe3,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pextrw",    3, 0x0fc5,    X, CpuSSE, FP|Modrm,	{ Imm8, RegMMX|InvMem, Reg32 } },
-{"pextrw",    3, 0x660fc5,  X, CpuSSE2,FP|Modrm,	{ Imm8, RegXMM|InvMem, Reg32 } },
-{"pinsrw",    3, 0x0fc4,    X, CpuSSE, FP|Modrm,	{ Imm8, Reg32|ShortMem, RegMMX } },
-{"pinsrw",    3, 0x660fc4,  X, CpuSSE2, FP|Modrm,	{ Imm8, Reg32|ShortMem, RegXMM } },
+{"pextrw",    3, 0x0fc5,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,	{ Imm8, RegMMX|InvMem, Reg32|Reg64 } },
+{"pextrw",    3, 0x660fc5,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,	{ Imm8, RegXMM|InvMem, Reg32|Reg64 } },
+{"pinsrw",    3, 0x0fc4,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,	{ Imm8, Reg32|Reg64|ShortMem, RegMMX } },
+{"pinsrw",    3, 0x660fc4,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } },
 {"pmaxsw",    2, 0x0fee,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
 {"pmaxsw",    2, 0x660fee,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 {"pmaxub",    2, 0x0fde,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
@@ -1167,8 +1181,8 @@ static const template i386_optab[] = {
 {"pminsw",    2, 0x660fea,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 {"pminub",    2, 0x0fda,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
 {"pminub",    2, 0x660fda,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
-{"pmovmskb",  2, 0x0fd7,    X, CpuSSE, FP|Modrm,	{ RegMMX|InvMem, Reg32, 0 } },
-{"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,FP|Modrm,	{ RegXMM|InvMem, Reg32, 0 } },
+{"pmovmskb",  2, 0x0fd7,    X, CpuSSE, lq_Suf|IgnoreSize|Modrm,	{ RegMMX|InvMem, Reg32|Reg64, 0 } },
+{"pmovmskb",  2, 0x660fd7,  X, CpuSSE2,lq_Suf|IgnoreSize|Modrm,	{ RegXMM|InvMem, Reg32|Reg64, 0 } },
 {"pmulhuw",   2, 0x0fe4,    X, CpuSSE, FP|Modrm,	{ RegMMX|LLongMem, RegMMX, 0 } },
 {"pmulhuw",   2, 0x660fe4,  X, CpuSSE2,FP|Modrm,	{ RegXMM|LLongMem, RegXMM, 0 } },
 {"prefetchnta", 1, 0x0f18,  0, CpuSSE, FP|Modrm, 	{ LLongMem, 0, 0 } },
@@ -1233,7 +1247,7 @@ static const template i386_optab[] = {
 {"movhpd",    2, 0x660f17,  X, CpuSSE2, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
 {"movlpd",    2, 0x660f12,  X, CpuSSE2, FP|Modrm,	{ LLongMem, RegXMM, 0 } },
 {"movlpd",    2, 0x660f13,  X, CpuSSE2, FP|Modrm,	{ RegXMM, LLongMem, 0 } },
-{"movmskpd",  2, 0x660f50,  X, CpuSSE2, FP|Modrm,	{ RegXMM|InvMem, Reg32, 0 } },
+{"movmskpd",  2, 0x660f50,  X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } },
 {"movntpd",   2, 0x660f2b,  X, CpuSSE2, FP|Modrm, 	{ RegXMM, LLongMem, 0 } },
 {"movsd",     2, 0xf20f10,  X, CpuSSE2, FP|Modrm,	{ RegXMM|LongMem, RegXMM, 0 } },
 {"movsd",     2, 0xf20f11,  X, CpuSSE2, FP|Modrm,	{ RegXMM, RegXMM|LongMem, 0 } },
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index dc3983e..f7db66f 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -1,5 +1,6 @@
 /* ppc.h -- Header file for PowerPC opcode table
-   Copyright 1994, 1995, 1999, 2000, 2001 Free Software Foundation, Inc.
+   Copyright 1994, 1995, 1999, 2000, 2001, 2002
+   Free Software Foundation, Inc.
    Written by Ian Lance Taylor, Cygnus Support
 
 This file is part of GDB, GAS, and the GNU binutils.
@@ -100,6 +101,12 @@ extern const int powerpc_num_opcodes;
 /* Opcode is only supported by 64-bit PowerPC BookE processor.  */
 #define PPC_OPCODE_BOOKE64 (010000)
 
+/* Opcode is only supported by Power4 architecture.  */
+#define PPC_OPCODE_POWER4 (020000)
+
+/* Opcode isn't supported by Power4 architecture.  */
+#define PPC_OPCODE_NOPOWER4 (040000)
+
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)
 
diff --git a/include/splay-tree.h b/include/splay-tree.h
index 6903969..4b7a7bf 100644
--- a/include/splay-tree.h
+++ b/include/splay-tree.h
@@ -61,6 +61,18 @@ typedef void (*splay_tree_delete_value_fn) PARAMS((splay_tree_value));
 /* The type of a function used to iterate over the tree.  */
 typedef int (*splay_tree_foreach_fn) PARAMS((splay_tree_node, void*));
 
+/* The type of a function used to allocate memory for tree root and
+   node structures.  The first argument is the number of bytes needed;
+   the second is a data pointer the splay tree functions pass through
+   to the allocator.  This function must never return zero.  */
+typedef void *(*splay_tree_allocate_fn) PARAMS((int, void *));
+
+/* The type of a function used to free memory allocated using the
+   corresponding splay_tree_allocate_fn.  The first argument is the
+   memory to be freed; the latter is a data pointer the splay tree
+   functions pass through to the freer.  */
+typedef void (*splay_tree_deallocate_fn) PARAMS((void *, void *));
+
 /* The nodes in the splay tree.  */
 struct splay_tree_node_s
 {
@@ -89,11 +101,24 @@ typedef struct splay_tree_s
 
   /* The deallocate-value function.  NULL if no cleanup is necessary.  */
   splay_tree_delete_value_fn delete_value;
+
+  /* Allocate/free functions, and a data pointer to pass to them.  */
+  splay_tree_allocate_fn allocate;
+  splay_tree_deallocate_fn deallocate;
+  void *allocate_data;
+
 } *splay_tree;
 
 extern splay_tree splay_tree_new        PARAMS((splay_tree_compare_fn,
 					        splay_tree_delete_key_fn,
 					        splay_tree_delete_value_fn));
+extern splay_tree splay_tree_new_with_allocator
+                                        PARAMS((splay_tree_compare_fn,
+					        splay_tree_delete_key_fn,
+					        splay_tree_delete_value_fn,
+                                                splay_tree_allocate_fn,
+                                                splay_tree_deallocate_fn,
+                                                void *));
 extern void splay_tree_delete           PARAMS((splay_tree));
 extern splay_tree_node splay_tree_insert          
 		                        PARAMS((splay_tree,