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| author | Rich Felker <dalias@aerifal.cx> | 2012-07-22 18:55:01 -0400 |
|---|---|---|
| committer | Rich Felker <dalias@aerifal.cx> | 2012-07-22 18:55:01 -0400 |
| commit | dc046f55bbff5f79d022882723c73a6b9af0bf86 (patch) | |
| tree | 5dad3839830e12534d77443868a1fc410f898c21 | |
| parent | 75fff40b9b536e0e6847d17ecc076894ca7b7068 (diff) | |
| download | musl-dc046f55bbff5f79d022882723c73a6b9af0bf86.zip musl-dc046f55bbff5f79d022882723c73a6b9af0bf86.tar.gz musl-dc046f55bbff5f79d022882723c73a6b9af0bf86.tar.bz2 | |
add floating point register saving/restoring to mips setjmp/longjmp
also fix the alignment of jmp_buf to meet the abi. linux always
emulates fpu on mips if it's not present, so enabling this code
unconditionally is "safe" but may be slow. in the long term it may be
preferable to find a way to disable it on soft float builds.
| -rw-r--r-- | arch/mips/bits/setjmp.h | 2 | ||||
| -rw-r--r-- | src/setjmp/mips/longjmp.s | 16 | ||||
| -rw-r--r-- | src/setjmp/mips/setjmp.s | 14 |
3 files changed, 30 insertions, 2 deletions
diff --git a/arch/mips/bits/setjmp.h b/arch/mips/bits/setjmp.h index c43ea2b..6bb1546 100644 --- a/arch/mips/bits/setjmp.h +++ b/arch/mips/bits/setjmp.h @@ -1 +1 @@ -typedef unsigned long jmp_buf [30]; +typedef unsigned long long jmp_buf [15]; diff --git a/src/setjmp/mips/longjmp.s b/src/setjmp/mips/longjmp.s index 9cf6f8d..fc8e726 100644 --- a/src/setjmp/mips/longjmp.s +++ b/src/setjmp/mips/longjmp.s @@ -10,7 +10,21 @@ longjmp: bne $2, $0, 1f nop addu $2, $2, 1 -1: lw $ra, 0($4) +1: lw $8, 48($4) + ctc1 $8, $31 + lwc1 $20, 56($4) + lwc1 $21, 60($4) + lwc1 $22, 64($4) + lwc1 $23, 68($4) + lwc1 $24, 72($4) + lwc1 $25, 76($4) + lwc1 $26, 80($4) + lwc1 $27, 84($4) + lwc1 $28, 88($4) + lwc1 $29, 92($4) + lwc1 $30, 96($4) + lwc1 $31, 100($4) + lw $ra, 0($4) lw $sp, 4($4) lw $16, 8($4) lw $17, 12($4) diff --git a/src/setjmp/mips/setjmp.s b/src/setjmp/mips/setjmp.s index 38ed5e0..1b79525 100644 --- a/src/setjmp/mips/setjmp.s +++ b/src/setjmp/mips/setjmp.s @@ -21,5 +21,19 @@ setjmp: sw $23, 36($4) sw $30, 40($4) sw $28, 44($4) + cfc1 $8, $31 + sw $8, 48($4) + swc1 $20, 56($4) + swc1 $21, 60($4) + swc1 $22, 64($4) + swc1 $23, 68($4) + swc1 $24, 72($4) + swc1 $25, 76($4) + swc1 $26, 80($4) + swc1 $27, 84($4) + swc1 $28, 88($4) + swc1 $29, 92($4) + swc1 $30, 96($4) + swc1 $31, 100($4) jr $ra li $2, 0 |