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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -S --passes=slp-vectorizer -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
define void @h() {
; CHECK-LABEL: define void @h() {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16
; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> <i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>, i32 0, i32 0
; CHECK-NEXT: [[TMP1:%.*]] = or <8 x i32> zeroinitializer, [[TMP0]]
; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i32> [[TMP1]], zeroinitializer
; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i32> [[TMP2]] to <8 x i16>
; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr [[ARRAYIDX2]], align 2
; CHECK-NEXT: ret void
;
entry:
%conv9 = zext i16 0 to i32
%arrayidx2 = getelementptr i8, ptr null, i64 16
%conv310 = zext i16 0 to i32
%add4 = or i32 %conv310, %conv9
%sub = or i32 %conv9, %conv310
%conv15 = sext i16 0 to i32
%shr = ashr i32 0, 0
%arrayidx18 = getelementptr i8, ptr null, i64 24
%conv19 = sext i16 0 to i32
%sub20 = or i32 %shr, %conv19
%shr29 = ashr i32 0, 0
%add30 = or i32 %shr29, %conv15
%sub39 = or i32 %sub, %sub20
%conv40 = trunc i32 %sub39 to i16
store i16 %conv40, ptr %arrayidx2, align 2
%sub44 = or i32 %add4, %add30
%conv45 = trunc i32 %sub44 to i16
store i16 %conv45, ptr %arrayidx18, align 2
%arrayidx2.1 = getelementptr i8, ptr null, i64 18
%conv3.112 = zext i16 0 to i32
%add4.1 = or i32 %conv3.112, 0
%sub.1 = or i32 0, %conv3.112
%conv15.1 = sext i16 0 to i32
%shr.1 = ashr i32 0, 0
%arrayidx18.1 = getelementptr i8, ptr null, i64 26
%conv19.1 = sext i16 0 to i32
%sub20.1 = or i32 %shr.1, %conv19.1
%shr29.1 = ashr i32 0, 0
%add30.1 = or i32 %shr29.1, %conv15.1
%sub39.1 = or i32 %sub.1, %sub20.1
%conv40.1 = trunc i32 %sub39.1 to i16
store i16 %conv40.1, ptr %arrayidx2.1, align 2
%sub44.1 = or i32 %add4.1, %add30.1
%conv45.1 = trunc i32 %sub44.1 to i16
store i16 %conv45.1, ptr %arrayidx18.1, align 2
%conv.213 = zext i16 0 to i32
%arrayidx2.2 = getelementptr i8, ptr null, i64 20
%conv3.214 = zext i16 0 to i32
%add4.2 = or i32 0, %conv.213
%sub.2 = or i32 0, %conv3.214
%conv15.2 = sext i16 0 to i32
%shr.2 = ashr i32 0, 0
%arrayidx18.2 = getelementptr i8, ptr null, i64 28
%conv19.2 = sext i16 0 to i32
%sub20.2 = or i32 %shr.2, %conv19.2
%shr29.2 = ashr i32 0, 0
%add30.2 = or i32 %shr29.2, %conv15.2
%sub39.2 = or i32 %sub.2, %sub20.2
%conv40.2 = trunc i32 %sub39.2 to i16
store i16 %conv40.2, ptr %arrayidx2.2, align 2
%sub44.2 = or i32 %add4.2, %add30.2
%conv45.2 = trunc i32 %sub44.2 to i16
store i16 %conv45.2, ptr %arrayidx18.2, align 2
%conv.315 = zext i16 0 to i32
%arrayidx2.3 = getelementptr i8, ptr null, i64 22
%conv3.316 = zext i16 0 to i32
%add4.3 = or i32 0, %conv.315
%sub.3 = or i32 0, %conv3.316
%conv15.3 = sext i16 0 to i32
%shr.3 = ashr i32 0, 0
%arrayidx18.3 = getelementptr i8, ptr null, i64 30
%conv19.3 = sext i16 0 to i32
%sub20.3 = or i32 %shr.3, %conv19.3
%shr29.3 = ashr i32 0, 0
%add30.3 = or i32 %shr29.3, %conv15.3
%sub39.3 = or i32 %sub.3, %sub20.3
%conv40.3 = trunc i32 %sub39.3 to i16
store i16 %conv40.3, ptr %arrayidx2.3, align 2
%sub44.3 = or i32 %add4.3, %add30.3
%conv45.3 = trunc i32 %sub44.3 to i16
store i16 %conv45.3, ptr %arrayidx18.3, align 2
ret void
}
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