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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+bmi -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
#
# Test that rules where multiple operands must be the same operand successfully
# match. Also test that the rules do not match when they're not the same
# operand.
---
name: test_blsr32rr
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
# G_ADD and G_AND both use %0 so we should match this.
body: |
bb.1:
liveins: $edi
; CHECK-LABEL: name: test_blsr32rr
; CHECK: liveins: $edi
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[COPY]], implicit-def dead $eflags
; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[DEC32r]], [[COPY]], implicit-def dead $eflags
; CHECK-NEXT: $edi = COPY [[AND32rr]]
%0(s32) = COPY $edi
%1(s32) = G_CONSTANT i32 -1
%2(s32) = G_ADD %0, %1
%3(s32) = G_AND %2, %0
$edi = COPY %3
...
---
name: test_blsr32rr_nomatch
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
- { id: 3, class: gpr }
# G_ADD and G_AND use different operands so we shouldn't match this.
body: |
bb.1:
liveins: $edi
; CHECK-LABEL: name: test_blsr32rr_nomatch
; CHECK: liveins: $edi
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri -1
; CHECK-NEXT: [[DEC32r:%[0-9]+]]:gr32 = DEC32r [[MOV32ri]], implicit-def dead $eflags
; CHECK-NEXT: [[AND32rr:%[0-9]+]]:gr32 = AND32rr [[DEC32r]], [[COPY]], implicit-def dead $eflags
; CHECK-NEXT: $edi = COPY [[AND32rr]]
%0(s32) = COPY $edi
%1(s32) = G_CONSTANT i32 -1
%2(s32) = G_ADD %1, %1
%3(s32) = G_AND %2, %0
$edi = COPY %3
...
|
