1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV32XTHEADMAC
; RUN: llc -mtriple=riscv64 -mattr=+xtheadmac -mattr=+m -verify-machineinstrs < %s \
; RUN: | FileCheck %s -check-prefix=RV64XTHEADMAC
define i32 @mula_i32(i32 %a, i32 %b, i32 %c) {
; RV32XTHEADMAC-LABEL: mula_i32:
; RV32XTHEADMAC: # %bb.0:
; RV32XTHEADMAC-NEXT: th.mula a0, a1, a2
; RV32XTHEADMAC-NEXT: ret
;
; RV64XTHEADMAC-LABEL: mula_i32:
; RV64XTHEADMAC: # %bb.0:
; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a2
; RV64XTHEADMAC-NEXT: ret
%d = mul i32 %b, %c
%e = add i32 %a, %d
ret i32 %e
}
define i32 @muls_i32(i32 %a, i32 %b, i32 %c) {
; RV32XTHEADMAC-LABEL: muls_i32:
; RV32XTHEADMAC: # %bb.0:
; RV32XTHEADMAC-NEXT: th.muls a0, a1, a2
; RV32XTHEADMAC-NEXT: ret
;
; RV64XTHEADMAC-LABEL: muls_i32:
; RV64XTHEADMAC: # %bb.0:
; RV64XTHEADMAC-NEXT: th.mulsw a0, a1, a2
; RV64XTHEADMAC-NEXT: ret
%d = mul i32 %b, %c
%e = sub i32 %a, %d
ret i32 %e
}
define i64 @mula_i64(i64 %a, i64 %b, i64 %c) {
; RV32XTHEADMAC-LABEL: mula_i64:
; RV32XTHEADMAC: # %bb.0:
; RV32XTHEADMAC-NEXT: mulhu a6, a2, a4
; RV32XTHEADMAC-NEXT: th.mula a6, a2, a5
; RV32XTHEADMAC-NEXT: th.mula a6, a3, a4
; RV32XTHEADMAC-NEXT: mv a3, a0
; RV32XTHEADMAC-NEXT: th.mula a3, a2, a4
; RV32XTHEADMAC-NEXT: sltu a0, a3, a0
; RV32XTHEADMAC-NEXT: add a0, a1, a0
; RV32XTHEADMAC-NEXT: add a1, a0, a6
; RV32XTHEADMAC-NEXT: mv a0, a3
; RV32XTHEADMAC-NEXT: ret
;
; RV64XTHEADMAC-LABEL: mula_i64:
; RV64XTHEADMAC: # %bb.0:
; RV64XTHEADMAC-NEXT: th.mula a0, a1, a2
; RV64XTHEADMAC-NEXT: ret
%d = mul i64 %b, %c
%f = add i64 %a, %d
ret i64 %f
}
define i64 @mulaw_i64(i32 %a, i32 %b, i32 %c) {
; RV32XTHEADMAC-LABEL: mulaw_i64:
; RV32XTHEADMAC: # %bb.0:
; RV32XTHEADMAC-NEXT: th.mula a0, a1, a2
; RV32XTHEADMAC-NEXT: srai a1, a0, 31
; RV32XTHEADMAC-NEXT: ret
;
; RV64XTHEADMAC-LABEL: mulaw_i64:
; RV64XTHEADMAC: # %bb.0:
; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a2
; RV64XTHEADMAC-NEXT: ret
%d = mul i32 %b, %c
%e = add i32 %a, %d
%f = sext i32 %e to i64
ret i64 %f
}
define i64 @mulah_i64(i32 %a, i16 %b, i16 %c) {
; RV32XTHEADMAC-LABEL: mulah_i64:
; RV32XTHEADMAC: # %bb.0:
; RV32XTHEADMAC-NEXT: th.mulah a0, a1, a2
; RV32XTHEADMAC-NEXT: srai a1, a0, 31
; RV32XTHEADMAC-NEXT: ret
;
; RV64XTHEADMAC-LABEL: mulah_i64:
; RV64XTHEADMAC: # %bb.0:
; RV64XTHEADMAC-NEXT: th.mulah a0, a1, a2
; RV64XTHEADMAC-NEXT: ret
%d = sext i16 %b to i32
%e = sext i16 %c to i32
%f = mul i32 %d, %e
%g = add i32 %a, %f
%h = sext i32 %g to i64
ret i64 %h
}
define i64 @muls_i64(i64 %a, i64 %b, i64 %c) {
; RV32XTHEADMAC-LABEL: muls_i64:
; RV32XTHEADMAC: # %bb.0:
; RV32XTHEADMAC-NEXT: mulhu a6, a2, a4
; RV32XTHEADMAC-NEXT: th.mula a6, a2, a5
; RV32XTHEADMAC-NEXT: th.mula a6, a3, a4
; RV32XTHEADMAC-NEXT: mul a3, a2, a4
; RV32XTHEADMAC-NEXT: sltu a3, a0, a3
; RV32XTHEADMAC-NEXT: th.muls a0, a2, a4
; RV32XTHEADMAC-NEXT: sub a1, a1, a3
; RV32XTHEADMAC-NEXT: sub a1, a1, a6
; RV32XTHEADMAC-NEXT: ret
;
; RV64XTHEADMAC-LABEL: muls_i64:
; RV64XTHEADMAC: # %bb.0:
; RV64XTHEADMAC-NEXT: th.muls a0, a1, a2
; RV64XTHEADMAC-NEXT: ret
%d = mul i64 %b, %c
%f = sub i64 %a, %d
ret i64 %f
}
define i64 @mulsw_i64(i32 %a, i32 %b, i32 %c) {
; RV32XTHEADMAC-LABEL: mulsw_i64:
; RV32XTHEADMAC: # %bb.0:
; RV32XTHEADMAC-NEXT: th.muls a0, a1, a2
; RV32XTHEADMAC-NEXT: srai a1, a0, 31
; RV32XTHEADMAC-NEXT: ret
;
; RV64XTHEADMAC-LABEL: mulsw_i64:
; RV64XTHEADMAC: # %bb.0:
; RV64XTHEADMAC-NEXT: th.mulsw a0, a1, a2
; RV64XTHEADMAC-NEXT: ret
%d = mul i32 %b, %c
%e = sub i32 %a, %d
%f = sext i32 %e to i64
ret i64 %f
}
define i64 @mulsh_i64(i32 %a, i16 %b, i16 %c) {
; RV32XTHEADMAC-LABEL: mulsh_i64:
; RV32XTHEADMAC: # %bb.0:
; RV32XTHEADMAC-NEXT: th.mulsh a0, a1, a2
; RV32XTHEADMAC-NEXT: srai a1, a0, 31
; RV32XTHEADMAC-NEXT: ret
;
; RV64XTHEADMAC-LABEL: mulsh_i64:
; RV64XTHEADMAC: # %bb.0:
; RV64XTHEADMAC-NEXT: th.mulsh a0, a1, a2
; RV64XTHEADMAC-NEXT: ret
%d = sext i16 %b to i32
%e = sext i16 %c to i32
%f = mul i32 %d, %e
%g = sub i32 %a, %f
%h = sext i32 %g to i64
ret i64 %h
}
define i32 @commutative1(i32 %A, i32 %B, i32 %C) {
; RV32XTHEADMAC-LABEL: commutative1:
; RV32XTHEADMAC: # %bb.0:
; RV32XTHEADMAC-NEXT: th.mula a2, a1, a0
; RV32XTHEADMAC-NEXT: mv a0, a2
; RV32XTHEADMAC-NEXT: ret
;
; RV64XTHEADMAC-LABEL: commutative1:
; RV64XTHEADMAC: # %bb.0:
; RV64XTHEADMAC-NEXT: th.mulaw a2, a1, a0
; RV64XTHEADMAC-NEXT: mv a0, a2
; RV64XTHEADMAC-NEXT: ret
%mul = mul nsw i32 %B, %A
%add = add i32 %mul, %C
ret i32 %add
}
define i32 @commutative2(i32 %A, i32 %B, i32 %C) {
; RV32XTHEADMAC-LABEL: commutative2:
; RV32XTHEADMAC: # %bb.0:
; RV32XTHEADMAC-NEXT: th.mula a0, a1, a2
; RV32XTHEADMAC-NEXT: ret
;
; RV64XTHEADMAC-LABEL: commutative2:
; RV64XTHEADMAC: # %bb.0:
; RV64XTHEADMAC-NEXT: th.mulaw a0, a1, a2
; RV64XTHEADMAC-NEXT: ret
%mul = mul nsw i32 %B, %C
%add = add i32 %mul, %A
ret i32 %add
}
define i32 @commutative3(i32 %A, i32 %B, i32 %C) {
; RV32XTHEADMAC-LABEL: commutative3:
; RV32XTHEADMAC: # %bb.0:
; RV32XTHEADMAC-NEXT: th.mula a1, a2, a0
; RV32XTHEADMAC-NEXT: mv a0, a1
; RV32XTHEADMAC-NEXT: ret
;
; RV64XTHEADMAC-LABEL: commutative3:
; RV64XTHEADMAC: # %bb.0:
; RV64XTHEADMAC-NEXT: th.mulaw a1, a2, a0
; RV64XTHEADMAC-NEXT: mv a0, a1
; RV64XTHEADMAC-NEXT: ret
%mul = mul nsw i32 %C, %A
%add = add i32 %mul, %B
ret i32 %add
}
|