llvm/test/CodeGen/RISCV/pr64772.ll


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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s

define void @f() {
; CHECK-LABEL: f:
; CHECK:       # %bb.0:
; CHECK-NEXT:    sb zero, 0(zero)
; CHECK-NEXT:    ret
  %B1 = shl i64 -9223372036854775808, 0
  %LGV6 = load i8, ptr null, align 1
  %G3 = getelementptr i32, ptr null, i64 %B1
  %B5 = ashr i64 -9223372036854775808, 0
  store i1 false, ptr %G3, align 1
  store i8 1, ptr null, align 1
  store i1 false, ptr null, align 1
  ret void
}