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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv64 -mattr='+d,+zfa' -verify-machineinstrs -run-pass=riscv-opt-w-instrs %s -o - | FileCheck %s --check-prefix=CHECK-ZFA
---
name: fcvtmod_w_d
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11
; CHECK-ZFA-LABEL: name: fcvtmod_w_d
; CHECK-ZFA: liveins: $x10, $x11
; CHECK-ZFA-NEXT: {{ $}}
; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $x10
; CHECK-ZFA-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
; CHECK-ZFA-NEXT: [[FCVTMOD_W_D:%[0-9]+]]:gpr = nofpexcept FCVTMOD_W_D [[COPY]], 1
; CHECK-ZFA-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY1]], [[FCVTMOD_W_D]]
; CHECK-ZFA-NEXT: $x10 = COPY [[ADD]]
; CHECK-ZFA-NEXT: $x11 = COPY [[FCVTMOD_W_D]]
; CHECK-ZFA-NEXT: PseudoRET
%0:fpr64 = COPY $x10
%1:gpr = COPY $x11
%2:gpr = nofpexcept FCVTMOD_W_D %0, 1
%3:gpr = ADD %1, %2
%4:gpr = ADDIW %2, 0
$x10 = COPY %3
$x11 = COPY %4
PseudoRET
...
---
name: physreg
tracksRegLiveness: true
body: |
bb.0.entry:
liveins: $x10, $x11
; CHECK-ZFA-LABEL: name: physreg
; CHECK-ZFA: liveins: $x10, $x11
; CHECK-ZFA-NEXT: {{ $}}
; CHECK-ZFA-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
; CHECK-ZFA-NEXT: [[ADDIW:%[0-9]+]]:gpr = ADDIW [[COPY]], 0
; CHECK-ZFA-NEXT: $x10 = COPY [[ADDIW]]
; CHECK-ZFA-NEXT: PseudoRET
%0:gpr = COPY $x10
%1:gpr = ADDIW %0, 0
$x10 = COPY %1
PseudoRET
...
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