1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: opt -S -mtriple=amdgcn-- -mcpu=tahiti -passes=atomic-expand < %s | FileCheck -check-prefix=IR %s
; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti < %s | FileCheck -check-prefix=GCN %s
define i32 @load_atomic_private_seq_cst_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @load_atomic_private_seq_cst_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0:[0-9]+]] {
; IR-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[LOAD]]
;
; GCN-LABEL: load_atomic_private_seq_cst_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%load = load atomic i32, ptr addrspace(5) %ptr seq_cst, align 4
ret i32 %load
}
define i64 @load_atomic_private_seq_cst_i64(ptr addrspace(5) %ptr) {
; IR-LABEL: define i64 @load_atomic_private_seq_cst_i64(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[LOAD:%.*]] = load i64, ptr addrspace(5) [[PTR]], align 8
; IR-NEXT: ret i64 [[LOAD]]
;
; GCN-LABEL: load_atomic_private_seq_cst_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_add_i32_e32 v1, vcc, 4, v0
; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
; GCN-NEXT: buffer_load_dword v1, v1, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%load = load atomic i64, ptr addrspace(5) %ptr seq_cst, align 8
ret i64 %load
}
define void @atomic_store_seq_cst_i32(ptr addrspace(5) %ptr, i32 %val) {
; IR-LABEL: define void @atomic_store_seq_cst_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] {
; IR-NEXT: store i32 [[VAL]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret void
;
; GCN-LABEL: atomic_store_seq_cst_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
store atomic i32 %val, ptr addrspace(5) %ptr seq_cst, align 4
ret void
}
define void @atomic_store_seq_cst_i64(ptr addrspace(5) %ptr, i64 %val) {
; IR-LABEL: define void @atomic_store_seq_cst_i64(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]], i64 [[VAL:%.*]]) #[[ATTR0]] {
; IR-NEXT: store i64 [[VAL]], ptr addrspace(5) [[PTR]], align 8
; IR-NEXT: ret void
;
; GCN-LABEL: atomic_store_seq_cst_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_add_i32_e32 v3, vcc, 4, v0
; GCN-NEXT: buffer_store_dword v2, v3, s[0:3], 0 offen
; GCN-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
store atomic i64 %val, ptr addrspace(5) %ptr seq_cst, align 8
ret void
}
define i32 @load_atomic_private_seq_cst_syncscope_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @load_atomic_private_seq_cst_syncscope_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[LOAD]]
;
; GCN-LABEL: load_atomic_private_seq_cst_syncscope_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%load = load atomic i32, ptr addrspace(5) %ptr syncscope("agent") seq_cst, align 4
ret i32 %load
}
define void @atomic_store_seq_cst_syncscope_i32(ptr addrspace(5) %ptr, i32 %val) {
; IR-LABEL: define void @atomic_store_seq_cst_syncscope_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] {
; IR-NEXT: store i32 [[VAL]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret void
;
; GCN-LABEL: atomic_store_seq_cst_syncscope_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
store atomic i32 %val, ptr addrspace(5) %ptr syncscope("agent") seq_cst, align 4
ret void
}
define i32 @cmpxchg_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @cmpxchg_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
; IR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 1, i32 [[TMP1]]
; IR-NEXT: store i32 [[TMP3]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[TMP4:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP1]], 0
; IR-NEXT: [[TMP5:%.*]] = insertvalue { i32, i1 } [[TMP4]], i1 [[TMP2]], 1
; IR-NEXT: [[RESULT_0:%.*]] = extractvalue { i32, i1 } [[TMP5]], 0
; IR-NEXT: [[RESULT_1:%.*]] = extractvalue { i32, i1 } [[TMP5]], 1
; IR-NEXT: store i1 [[RESULT_1]], ptr addrspace(1) poison, align 1
; IR-NEXT: ret i32 [[RESULT_0]]
;
; GCN-LABEL: cmpxchg_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN-NEXT: v_cndmask_b32_e64 v2, v1, 1, vcc
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GCN-NEXT: buffer_store_byte v0, off, s[4:7], 0
; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = cmpxchg ptr addrspace(5) %ptr, i32 0, i32 1 acq_rel monotonic
%result.0 = extractvalue { i32, i1 } %result, 0
%result.1 = extractvalue { i32, i1 } %result, 1
store i1 %result.1, ptr addrspace(1) poison
ret i32 %result.0
}
define i64 @cmpxchg_private_i64(ptr addrspace(5) %ptr) {
; IR-LABEL: define i64 @cmpxchg_private_i64(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i64, ptr addrspace(5) [[PTR]], align 8
; IR-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 0
; IR-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i64 1, i64 [[TMP1]]
; IR-NEXT: store i64 [[TMP3]], ptr addrspace(5) [[PTR]], align 8
; IR-NEXT: [[TMP4:%.*]] = insertvalue { i64, i1 } poison, i64 [[TMP1]], 0
; IR-NEXT: [[TMP5:%.*]] = insertvalue { i64, i1 } [[TMP4]], i1 [[TMP2]], 1
; IR-NEXT: [[RESULT_0:%.*]] = extractvalue { i64, i1 } [[TMP5]], 0
; IR-NEXT: [[RESULT_1:%.*]] = extractvalue { i64, i1 } [[TMP5]], 1
; IR-NEXT: store i1 [[RESULT_1]], ptr addrspace(1) poison, align 1
; IR-NEXT: ret i64 [[RESULT_0]]
;
; GCN-LABEL: cmpxchg_private_i64:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_mov_b32_e32 v2, v0
; GCN-NEXT: v_add_i32_e32 v3, vcc, 4, v2
; GCN-NEXT: buffer_load_dword v1, v3, s[0:3], 0 offen
; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], 0 offen
; GCN-NEXT: s_mov_b32 s7, 0xf000
; GCN-NEXT: s_mov_b32 s6, -1
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[0:1]
; GCN-NEXT: v_cndmask_b32_e64 v4, v1, 0, vcc
; GCN-NEXT: buffer_store_dword v4, v3, s[0:3], 0 offen
; GCN-NEXT: v_cndmask_b32_e64 v3, v0, 1, vcc
; GCN-NEXT: s_waitcnt expcnt(0)
; GCN-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GCN-NEXT: buffer_store_dword v3, v2, s[0:3], 0 offen
; GCN-NEXT: buffer_store_byte v4, off, s[4:7], 0
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = cmpxchg ptr addrspace(5) %ptr, i64 0, i64 1 acq_rel monotonic
%result.0 = extractvalue { i64, i1 } %result, 0
%result.1 = extractvalue { i64, i1 } %result, 1
store i1 %result.1, ptr addrspace(1) poison
ret i64 %result.0
}
define i32 @atomicrmw_xchg_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_xchg_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: store i32 4, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_xchg_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v2, 4
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(1)
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw xchg ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define i32 @atomicrmw_add_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_add_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[NEW:%.*]] = add i32 [[TMP1]], 4
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_add_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_i32_e32 v2, vcc, 4, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw add ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define i32 @atomicrmw_sub_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_sub_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[NEW:%.*]] = sub i32 [[TMP1]], 4
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_sub_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_i32_e32 v2, vcc, -4, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw sub ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define i32 @atomicrmw_and_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_and_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[NEW:%.*]] = and i32 [[TMP1]], 4
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_and_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_and_b32_e32 v2, 4, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw and ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define i32 @atomicrmw_nand_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_nand_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 4
; IR-NEXT: [[NEW:%.*]] = xor i32 [[TMP2]], -1
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_nand_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_not_b32_e32 v2, v1
; GCN-NEXT: v_or_b32_e32 v2, -5, v2
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw nand ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define i32 @atomicrmw_or_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_or_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[NEW:%.*]] = or i32 [[TMP1]], 4
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_or_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_or_b32_e32 v2, 4, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw or ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define i32 @atomicrmw_xor_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_xor_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[NEW:%.*]] = xor i32 [[TMP1]], 4
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_xor_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_xor_b32_e32 v2, 4, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw xor ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define i32 @atomicrmw_max_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_max_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[TMP2:%.*]] = icmp sgt i32 [[TMP1]], 4
; IR-NEXT: [[NEW:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 4
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_max_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_max_i32_e32 v2, 4, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw max ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define i32 @atomicrmw_min_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_min_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[TMP2:%.*]] = icmp sle i32 [[TMP1]], 4
; IR-NEXT: [[NEW:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 4
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_min_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_min_i32_e32 v2, 4, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw min ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define i32 @atomicrmw_umax_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_umax_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[TMP2:%.*]] = icmp ugt i32 [[TMP1]], 4
; IR-NEXT: [[NEW:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 4
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_umax_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_max_u32_e32 v2, 4, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw umax ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define i32 @atomicrmw_umin_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_umin_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[TMP2:%.*]] = icmp ule i32 [[TMP1]], 4
; IR-NEXT: [[NEW:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 4
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_umin_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_min_u32_e32 v2, 4, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw umin ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define float @atomicrmw_fadd_private_f32(ptr addrspace(5) %ptr) {
; IR-LABEL: define float @atomicrmw_fadd_private_f32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[NEW:%.*]] = fadd float [[TMP1]], 2.000000e+00
; IR-NEXT: store float [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret float [[TMP1]]
;
; GCN-LABEL: atomicrmw_fadd_private_f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_f32_e32 v2, 2.0, v1
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw fadd ptr addrspace(5) %ptr, float 2.0 seq_cst
ret float %result
}
define bfloat @atomicrmw_fadd_private_bf16(ptr addrspace(5) %ptr) {
; IR-LABEL: define bfloat @atomicrmw_fadd_private_bf16(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load bfloat, ptr addrspace(5) [[PTR]], align 2
; IR-NEXT: [[NEW:%.*]] = fadd bfloat [[TMP1]], 0xR4000
; IR-NEXT: store bfloat [[NEW]], ptr addrspace(5) [[PTR]], align 2
; IR-NEXT: ret bfloat [[TMP1]]
;
; GCN-LABEL: atomicrmw_fadd_private_bf16:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_ushort v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GCN-NEXT: v_add_f32_e32 v2, 2.0, v1
; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; GCN-NEXT: buffer_store_short v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw fadd ptr addrspace(5) %ptr, bfloat 2.0 seq_cst
ret bfloat %result
}
define float @atomicrmw_fsub_private_i32(ptr addrspace(5) %ptr, float %val) {
; IR-LABEL: define float @atomicrmw_fsub_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]], float [[VAL:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load float, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[NEW:%.*]] = fsub float [[TMP1]], [[VAL]]
; IR-NEXT: store float [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret float [[TMP1]]
;
; GCN-LABEL: atomicrmw_fsub_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_sub_f32_e32 v1, v2, v1
; GCN-NEXT: buffer_store_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v2
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw fsub ptr addrspace(5) %ptr, float %val seq_cst
ret float %result
}
define amdgpu_kernel void @alloca_promote_atomicrmw_private_lds_promote(ptr addrspace(1) %out, i32 %in) nounwind {
; IR-LABEL: define amdgpu_kernel void @alloca_promote_atomicrmw_private_lds_promote(
; IR-SAME: ptr addrspace(1) [[OUT:%.*]], i32 [[IN:%.*]]) #[[ATTR1:[0-9]+]] {
; IR-NEXT: entry:
; IR-NEXT: [[TMP:%.*]] = alloca [2 x i32], align 4, addrspace(5)
; IR-NEXT: [[GEP2:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(5) [[TMP]], i32 0, i32 1
; IR-NEXT: store i32 0, ptr addrspace(5) [[TMP]], align 4
; IR-NEXT: store i32 1, ptr addrspace(5) [[GEP2]], align 4
; IR-NEXT: [[GEP3:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(5) [[TMP]], i32 0, i32 [[IN]]
; IR-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[GEP3]], align 4
; IR-NEXT: [[NEW:%.*]] = add i32 [[TMP0]], 7
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[GEP3]], align 4
; IR-NEXT: store i32 [[TMP0]], ptr addrspace(1) [[OUT]], align 4
; IR-NEXT: ret void
;
; GCN-LABEL: alloca_promote_atomicrmw_private_lds_promote:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dword s6, s[4:5], 0xb
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_eq_u32 s6, 1
; GCN-NEXT: s_cselect_b32 s4, 1, 0
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm
entry:
%tmp = alloca [2 x i32], addrspace(5)
%gep2 = getelementptr inbounds [2 x i32], ptr addrspace(5) %tmp, i32 0, i32 1
store i32 0, ptr addrspace(5) %tmp
store i32 1, ptr addrspace(5) %gep2
%gep3 = getelementptr inbounds [2 x i32], ptr addrspace(5) %tmp, i32 0, i32 %in
%rmw = atomicrmw add ptr addrspace(5) %gep3, i32 7 acq_rel
store i32 %rmw, ptr addrspace(1) %out
ret void
}
define amdgpu_kernel void @alloca_promote_cmpxchg_private(ptr addrspace(1) %out, i32 %in) nounwind {
; IR-LABEL: define amdgpu_kernel void @alloca_promote_cmpxchg_private(
; IR-SAME: ptr addrspace(1) [[OUT:%.*]], i32 [[IN:%.*]]) #[[ATTR1]] {
; IR-NEXT: entry:
; IR-NEXT: [[TMP:%.*]] = alloca [2 x i32], align 4, addrspace(5)
; IR-NEXT: [[GEP2:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(5) [[TMP]], i32 0, i32 1
; IR-NEXT: store i32 0, ptr addrspace(5) [[TMP]], align 4
; IR-NEXT: store i32 1, ptr addrspace(5) [[GEP2]], align 4
; IR-NEXT: [[GEP3:%.*]] = getelementptr inbounds [2 x i32], ptr addrspace(5) [[TMP]], i32 0, i32 [[IN]]
; IR-NEXT: [[TMP0:%.*]] = load i32, ptr addrspace(5) [[GEP3]], align 4
; IR-NEXT: [[TMP1:%.*]] = icmp eq i32 [[TMP0]], 0
; IR-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 1, i32 [[TMP0]]
; IR-NEXT: store i32 [[TMP2]], ptr addrspace(5) [[GEP3]], align 4
; IR-NEXT: [[TMP3:%.*]] = insertvalue { i32, i1 } poison, i32 [[TMP0]], 0
; IR-NEXT: [[TMP4:%.*]] = insertvalue { i32, i1 } [[TMP3]], i1 [[TMP1]], 1
; IR-NEXT: [[VAL:%.*]] = extractvalue { i32, i1 } [[TMP4]], 0
; IR-NEXT: store i32 [[VAL]], ptr addrspace(1) [[OUT]], align 4
; IR-NEXT: ret void
;
; GCN-LABEL: alloca_promote_cmpxchg_private:
; GCN: ; %bb.0: ; %entry
; GCN-NEXT: s_load_dword s6, s[4:5], 0xb
; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; GCN-NEXT: s_mov_b32 s3, 0xf000
; GCN-NEXT: s_mov_b32 s2, -1
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: s_cmp_eq_u32 s6, 1
; GCN-NEXT: s_cselect_b32 s4, 1, 0
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
; GCN-NEXT: s_endpgm
entry:
%tmp = alloca [2 x i32], addrspace(5)
%gep2 = getelementptr inbounds [2 x i32], ptr addrspace(5) %tmp, i32 0, i32 1
store i32 0, ptr addrspace(5) %tmp
store i32 1, ptr addrspace(5) %gep2
%gep3 = getelementptr inbounds [2 x i32], ptr addrspace(5) %tmp, i32 0, i32 %in
%xchg = cmpxchg ptr addrspace(5) %gep3, i32 0, i32 1 acq_rel monotonic
%val = extractvalue { i32, i1 } %xchg, 0
store i32 %val, ptr addrspace(1) %out
ret void
}
define i32 @atomicrmw_inc_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_inc_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], 1
; IR-NEXT: [[TMP3:%.*]] = icmp uge i32 [[TMP1]], 4
; IR-NEXT: [[NEW:%.*]] = select i1 [[TMP3]], i32 0, i32 [[TMP2]]
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_inc_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_i32_e32 v2, vcc, 1, v1
; GCN-NEXT: v_cmp_gt_u32_e32 vcc, 4, v1
; GCN-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw uinc_wrap ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
define i32 @atomicrmw_dec_private_i32(ptr addrspace(5) %ptr) {
; IR-LABEL: define i32 @atomicrmw_dec_private_i32(
; IR-SAME: ptr addrspace(5) [[PTR:%.*]]) #[[ATTR0]] {
; IR-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: [[TMP2:%.*]] = sub i32 [[TMP1]], 1
; IR-NEXT: [[TMP3:%.*]] = icmp eq i32 [[TMP1]], 0
; IR-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP1]], 4
; IR-NEXT: [[TMP5:%.*]] = or i1 [[TMP3]], [[TMP4]]
; IR-NEXT: [[NEW:%.*]] = select i1 [[TMP5]], i32 4, i32 [[TMP2]]
; IR-NEXT: store i32 [[NEW]], ptr addrspace(5) [[PTR]], align 4
; IR-NEXT: ret i32 [[TMP1]]
;
; GCN-LABEL: atomicrmw_dec_private_i32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: buffer_load_dword v1, v0, s[0:3], 0 offen
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: v_add_i32_e32 v2, vcc, -1, v1
; GCN-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; GCN-NEXT: v_cmp_lt_u32_e64 s[4:5], 4, v1
; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
; GCN-NEXT: v_cndmask_b32_e64 v2, v2, 4, s[4:5]
; GCN-NEXT: buffer_store_dword v2, v0, s[0:3], 0 offen
; GCN-NEXT: v_mov_b32_e32 v0, v1
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; GCN-NEXT: s_setpc_b64 s[30:31]
%result = atomicrmw udec_wrap ptr addrspace(5) %ptr, i32 4 seq_cst
ret i32 %result
}
|
