llvm/test/CodeGen/AMDGPU/post-ra-sched-reset.mir


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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=post-RA-sched -verify-machineinstrs -debug-only=post-RA-sched -o - %s 2>&1 | FileCheck %s

# REQUIRES: asserts

# CHECK-NOT: Stall in cycle
---
name:            hazard_rec_reset
tracksRegLiveness: true
body:             |
  bb.0:
    successors: %bb.1

    $m0 = S_MOV_B32 0

  bb.1:
    liveins: $vgpr4

    S_SETREG_IMM32_B32 0, 1, implicit-def $mode, implicit $mode
    $vgpr0 = V_INTERP_P1_F32 killed $vgpr4, 0, 0, implicit $mode, implicit $m0, implicit $exec
    S_ENDPGM 0

...