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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -S < %s | FileCheck %s
define <16 x i8> @test_laneselect(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: @test_laneselect(
; CHECK-NEXT: [[RES:%.*]] = call <16 x i8> @llvm.wasm.relaxed.laneselect.v16i8(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i8> [[C:%.*]])
; CHECK-NEXT: ret <16 x i8> [[RES]]
;
%res = call <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c)
ret <16 x i8> %res
}
define <8 x i16> @test_dot(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: @test_dot(
; CHECK-NEXT: [[RES:%.*]] = call <8 x i16> @llvm.wasm.relaxed.dot.i8x16.i7x16.signed(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]])
; CHECK-NEXT: ret <8 x i16> [[RES]]
;
%res = call <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(<16 x i8> %a, <16 x i8> %b)
ret <8 x i16> %res
}
define <4 x i32> @test_dot_add(<16 x i8> %a, <16 x i8> %b, <4 x i32> %c) {
; CHECK-LABEL: @test_dot_add(
; CHECK-NEXT: [[RES:%.*]] = call <4 x i32> @llvm.wasm.relaxed.dot.i8x16.i7x16.add.signed(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <4 x i32> [[C:%.*]])
; CHECK-NEXT: ret <4 x i32> [[RES]]
;
%res = call <4 x i32> @llvm.wasm.dot.i8x16.i7x16.add.signed(<16 x i8> %a, <16 x i8> %b, <4 x i32> %c)
ret <4 x i32> %res
}
define <4 x float> @test_fma(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: @test_fma(
; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.wasm.relaxed.madd.v4f32(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]])
; CHECK-NEXT: ret <4 x float> [[RES]]
;
%res = call <4 x float> @llvm.wasm.fma.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)
ret <4 x float> %res
}
define <4 x float> @test_fms(<4 x float> %a, <4 x float> %b, <4 x float> %c) {
; CHECK-LABEL: @test_fms(
; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.wasm.relaxed.nmadd.v4f32(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]])
; CHECK-NEXT: ret <4 x float> [[RES]]
;
%res = call <4 x float> @llvm.wasm.fms.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c)
ret <4 x float> %res
}
declare <16 x i8> @llvm.wasm.laneselect.v16i8(<16 x i8>, <16 x i8>, <16 x i8>)
declare <8 x i16> @llvm.wasm.dot.i8x16.i7x16.signed(<16 x i8>, <16 x i8>)
declare <4 x i32> @llvm.wasm.dot.i8x16.i7x16.add.signed(<16 x i8>, <16 x i8>, <4 x i32>)
declare <4 x float> @llvm.wasm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>)
declare <4 x float> @llvm.wasm.fms.v4f32(<4 x float>, <4 x float>, <4 x float>)
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