aboutsummaryrefslogtreecommitdiff
path: root/llvm/lib/Target/PowerPC/PPCScheduleP10.td
blob: f922f8a7d9852b14a18a5ede5790c5081c9e7aac (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
//===--- PPCScheduleP10.td - P10 Scheduling Definitions -*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Automatically generated file, do not edit!
//
// This file defines the resources required by P10 instructions.
//===----------------------------------------------------------------------===//
// Modeling pipeline forwarding logic.
def P10BR_Read : SchedRead;
def P10DF_Read : SchedRead;
def P10DV_Read : SchedRead;
def P10DX_Read : SchedRead;
def P10F2_Read : SchedRead;
def P10FX_Read : SchedRead;
def P10LD_Read : SchedRead;
def P10MU_Read : SchedRead;
def P10PM_Read : SchedRead;
def P10ST_Read : SchedRead;
def P10SX_Read : SchedRead;
def P10vMU_Read : SchedRead;

def P10Model : SchedMachineModel {
  let IssueWidth = 8;
  let MicroOpBufferSize = 44;
  let LoopMicroOpBufferSize = 60;
  let CompleteModel = 1;

  // Power 10 does not support instructions from SPE, Book E and HTM.
  let UnsupportedFeatures = [HasSPE, IsE500, IsBookE, IsISAFuture, HasHTM];
}

let SchedModel = P10Model in {

  // ***************** Processor Resources *****************

  // Pipeline Groups

  def P10_BF : ProcResource<4>; // Four Binary Floating Point pipelines.
  def P10_BR : ProcResource<2>; // Two Branch pipelines.
  def P10_CY : ProcResource<4>; // Four Crypto pipelines.
  def P10_DF : ProcResource<1>; // One Decimal Floating Point pipelines.
  def P10_DV : ProcResource<2>; // Two Fixed-point divide (DIV) pipelines.
  def P10_DX : ProcResource<2>; // Two 128-bit fixed-point and BCD pipelines.
  def P10_FX : ProcResource<4>; // Four ALU pipelines.
  def P10_LD : ProcResource<2>; // Two Load pipelines.
  def P10_MM : ProcResource<2>; // Two 512-bit SIMD matrix multiply engine pipelines.
  def P10_PM : ProcResource<4>; // Four 128-bit permute (PM) pipelines.
  def P10_ST : ProcResource<2>; // Two ST-D pipelines.
  def P10_SX : ProcResource<2>; // Two Simple Fixed-point (SFX) pipelines.

  // Dispatch Groups

  // Dispatch to any slots
  def P10_ANY_SLOT : ProcResource<8>;

  let Super = P10_ANY_SLOT in {

    // Dispatch to even slots
    def P10_EVEN_SLOT : ProcResource<4>;

    // Dispatch to odd slots
    def P10_ODD_SLOT : ProcResource<4>;
  }

  // Dispatch Rules
  let NumMicroOps = 0, Latency = 1 in {
    // Dispatch Rule '-'
    def P10W_DISP_ANY : SchedWriteRes<[P10_ANY_SLOT]>;

    // Dispatch Rule '-', even slot
    def P10W_DISP_EVEN : SchedWriteRes<[P10_EVEN_SLOT]>;

    // Dispatch Rule 'P'
    def P10W_DISP_PAIR : SchedWriteRes<[P10_EVEN_SLOT, P10_ODD_SLOT]>;
  }

  // ***************** SchedWriteRes Definitions *****************

  // A BF pipeline may take from 7 to 36 cycles to complete.
  // Some BF operations may keep the pipeline busy for up to 10 cycles.
  def P10W_BF_7C : SchedWriteRes<[P10_BF]> {
    let Latency = 7;
  }

  def P10W_BF_22C : SchedWriteRes<[P10_BF]> {
    let ReleaseAtCycles = [ 5 ];
    let Latency = 22;
  }

  def P10W_BF_24C : SchedWriteRes<[P10_BF]> {
    let ReleaseAtCycles = [ 8 ];
    let Latency = 24;
  }

  def P10W_BF_26C : SchedWriteRes<[P10_BF]> {
    let ReleaseAtCycles = [ 5 ];
    let Latency = 26;
  }

  def P10W_BF_27C : SchedWriteRes<[P10_BF]> {
    let ReleaseAtCycles = [ 7 ];
    let Latency = 27;
  }

  def P10W_BF_36C : SchedWriteRes<[P10_BF]> {
    let ReleaseAtCycles = [ 10 ];
    let Latency = 36;
  }

  // A BR pipeline may take 2 cycles to complete.
  def P10W_BR_2C : SchedWriteRes<[P10_BR]> {
    let Latency = 2;
  }

  // A CY pipeline may take 7 cycles to complete.
  def P10W_CY_7C : SchedWriteRes<[P10_CY]> {
    let Latency = 7;
  }

  // A DF pipeline may take from 13 to 174 cycles to complete.
  // Some DF operations may keep the pipeline busy for up to 67 cycles.
  def P10W_DF_13C : SchedWriteRes<[P10_DF]> {
    let Latency = 13;
  }

  def P10W_DF_24C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 16 ];
    let Latency = 24;
  }

  def P10W_DF_25C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 17 ];
    let Latency = 25;
  }

  def P10W_DF_26C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 18 ];
    let Latency = 26;
  }

  def P10W_DF_32C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 22 ];
    let Latency = 32;
  }

  def P10W_DF_33C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 25 ];
    let Latency = 33;
  }

  def P10W_DF_34C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 25 ];
    let Latency = 34;
  }

  def P10W_DF_38C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 30 ];
    let Latency = 38;
  }

  def P10W_DF_40C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 17 ];
    let Latency = 40;
  }

  def P10W_DF_43C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 34 ];
    let Latency = 43;
  }

  def P10W_DF_59C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 49 ];
    let Latency = 59;
  }

  def P10W_DF_61C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 12 ];
    let Latency = 61;
  }

  def P10W_DF_68C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 15 ];
    let Latency = 68;
  }

  def P10W_DF_77C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 67 ];
    let Latency = 77;
  }

  def P10W_DF_87C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 12 ];
    let Latency = 87;
  }

  def P10W_DF_100C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 32 ];
    let Latency = 100;
  }

  def P10W_DF_174C : SchedWriteRes<[P10_DF]> {
    let ReleaseAtCycles = [ 33 ];
    let Latency = 174;
  }

  // A DV pipeline may take from 20 to 83 cycles to complete.
  // Some DV operations may keep the pipeline busy for up to 33 cycles.
  def P10W_DV_20C : SchedWriteRes<[P10_DV]> {
    let ReleaseAtCycles = [ 10 ];
    let Latency = 20;
  }

  def P10W_DV_25C : SchedWriteRes<[P10_DV]> {
    let ReleaseAtCycles = [ 10 ];
    let Latency = 25;
  }

  def P10W_DV_27C : SchedWriteRes<[P10_DV]> {
    let ReleaseAtCycles = [ 10 ];
    let Latency = 27;
  }

  def P10W_DV_41C : SchedWriteRes<[P10_DV]> {
    let ReleaseAtCycles = [ 10 ];
    let Latency = 41;
  }

  def P10W_DV_43C : SchedWriteRes<[P10_DV]> {
    let ReleaseAtCycles = [ 21 ];
    let Latency = 43;
  }

  def P10W_DV_47C : SchedWriteRes<[P10_DV]> {
    let ReleaseAtCycles = [ 21 ];
    let Latency = 47;
  }

  def P10W_DV_54C : SchedWriteRes<[P10_DV]> {
    let ReleaseAtCycles = [ 33 ];
    let Latency = 54;
  }

  def P10W_DV_60C : SchedWriteRes<[P10_DV]> {
    let ReleaseAtCycles = [ 33 ];
    let Latency = 60;
  }

  def P10W_DV_75C : SchedWriteRes<[P10_DV]> {
    let ReleaseAtCycles = [ 21 ];
    let Latency = 75;
  }

  def P10W_DV_83C : SchedWriteRes<[P10_DV]> {
    let ReleaseAtCycles = [ 33 ];
    let Latency = 83;
  }

  // A DX pipeline may take 5 cycles to complete.
  def P10W_DX_5C : SchedWriteRes<[P10_DX]> {
    let Latency = 5;
  }

  // A F2 pipeline may take 4 cycles to complete.
  def P10W_F2_4C : SchedWriteRes<[P10_FX]> {
    let Latency = 4;
  }

  // A FX pipeline may take from 2 to 3 cycles to complete.
  def P10W_FX_2C : SchedWriteRes<[P10_FX]> {
    let Latency = 2;
  }

  def P10W_FX_3C : SchedWriteRes<[P10_FX]> {
    let Latency = 3;
  }

  // A LD pipeline may take 6 cycles to complete.
  def P10W_LD_6C : SchedWriteRes<[P10_LD]> {
    let Latency = 6;
  }

  // A MF pipeline may take 13 cycles to complete.
  def P10W_MF_13C : SchedWriteRes<[P10_SX]> {
    let Latency = 13;
  }

  // A MFL pipeline may take 13 cycles to complete.
  def P10W_MFL_13C : SchedWriteRes<[P10_SX]> {
    let Latency = 13;
  }

  // A MM pipeline may take 10 cycles to complete.
  def P10W_MM_10C : SchedWriteRes<[P10_MM]> {
    let Latency = 10;
  }

  // A MU pipeline may take 5 cycles to complete.
  def P10W_MU_5C : SchedWriteRes<[P10_BF]> {
    let Latency = 5;
  }

  // A PM pipeline may take 4 cycles to complete.
  def P10W_PM_4C : SchedWriteRes<[P10_PM]> {
    let Latency = 4;
  }

  // A ST pipeline may take 3 cycles to complete.
  def P10W_ST_3C : SchedWriteRes<[P10_ST]> {
    let Latency = 3;
  }

  // A SX pipeline may take from 0 to 3 cycles to complete.
  def P10W_SX : SchedWriteRes<[P10_SX]> {
    let Latency = 0;
  }

  def P10W_SX_3C : SchedWriteRes<[P10_SX]> {
    let Latency = 3;
  }

  // A vMU pipeline may take 7 cycles to complete.
  def P10W_vMU_7C : SchedWriteRes<[P10_BF]> {
    let Latency = 7;
  }

  // ***************** Read Advance Definitions *****************

  // Modeling pipeline forwarding logic.
  def P10BF_Read_1C : SchedReadAdvance<1, [P10W_DX_5C, P10W_MU_5C, P10W_vMU_7C, P10W_CY_7C, P10W_DF_13C, P10W_MM_10C]>;
  def P10BF_Read_2C : SchedReadAdvance<2, [P10W_BF_7C]>;
  def P10BR_Read_1C : SchedReadAdvance<1, [P10W_FX_3C, P10W_F2_4C]>;
  def P10CY_Read_1C : SchedReadAdvance<1, [P10W_DX_5C, P10W_MU_5C, P10W_vMU_7C, P10W_BF_7C, P10W_DF_13C, P10W_MM_10C]>;
  def P10CY_Read_3C : SchedReadAdvance<3, [P10W_CY_7C]>;
  def P10DF_Read_1C : SchedReadAdvance<1, [P10W_DX_5C, P10W_MU_5C, P10W_vMU_7C, P10W_BF_7C, P10W_CY_7C, P10W_DF_13C, P10W_MM_10C]>;
  def P10DV_Read_1C : SchedReadAdvance<1, [P10W_DX_5C, P10W_MU_5C, P10W_vMU_7C, P10W_BF_7C, P10W_CY_7C, P10W_DF_13C, P10W_MM_10C]>;
  def P10DX_Read_1C : SchedReadAdvance<1, [P10W_DX_5C, P10W_MU_5C, P10W_vMU_7C, P10W_BF_7C, P10W_CY_7C, P10W_DF_13C, P10W_MM_10C]>;
  def P10F2_Read_1C : SchedReadAdvance<1, [P10W_ST_3C, P10W_SX_3C, P10W_FX_3C, P10W_F2_4C, P10W_PM_4C]>;
  def P10FX_Read_1C : SchedReadAdvance<1, [P10W_ST_3C, P10W_SX_3C, P10W_FX_3C, P10W_F2_4C, P10W_PM_4C]>;
  def P10LD_Read_1C : SchedReadAdvance<1, [P10W_ST_3C, P10W_SX_3C, P10W_FX_3C, P10W_F2_4C]>;
  def P10MM_Read_1C : SchedReadAdvance<1, [P10W_DX_5C, P10W_MU_5C, P10W_vMU_7C, P10W_BF_7C, P10W_CY_7C, P10W_DF_13C]>;
  def P10MM_Read_6C : SchedReadAdvance<6, [P10W_MM_10C]>;
  def P10MU_Read_1C : SchedReadAdvance<1, [P10W_DX_5C, P10W_MU_5C, P10W_DF_13C]>;
  def P10PM_Read_1C : SchedReadAdvance<1, [P10W_ST_3C, P10W_SX_3C, P10W_FX_3C, P10W_F2_4C, P10W_PM_4C]>;
  def P10ST_Read_1C : SchedReadAdvance<1, [P10W_ST_3C, P10W_SX_3C, P10W_FX_3C, P10W_F2_4C, P10W_PM_4C]>;
  def P10SX_Read_1C : SchedReadAdvance<1, [P10W_ST_3C, P10W_SX_3C, P10W_FX_3C, P10W_F2_4C, P10W_PM_4C, P10W_MM_10C]>;
  def P10vMU_Read_1C : SchedReadAdvance<1, [P10W_DX_5C, P10W_MU_5C, P10W_vMU_7C, P10W_BF_7C, P10W_CY_7C, P10W_DF_13C, P10W_MM_10C]>;

  // Save 1 cycles if pipeline BF reads the data from pipelines DX, MU, vMU, CY, DF, MM.
  // Save 2 cycles if pipeline BF reads the data from pipelines BF.
  def P10BF_Read : SchedReadVariant<[
        SchedVar<P10W_BF_7C_Pred, [P10BF_Read_2C]>,
        SchedVar<NoSchedPred,     [P10BF_Read_1C]>
  ]>;

  // Save 1 cycles if pipeline CY reads the data from pipelines DX, MU, vMU, BF, DF, MM.
  // Save 3 cycles if pipeline CY reads the data from pipelines CY.
  def P10CY_Read : SchedReadVariant<[
        SchedVar<P10W_CY_7C_Pred, [P10CY_Read_3C]>,
        SchedVar<NoSchedPred,     [P10CY_Read_1C]>
  ]>;

  // Save 1 cycles if pipeline MM reads the data from pipelines DX, MU, vMU, BF, CY, DF.
  // Save 6 cycles if pipeline MM reads the data from pipelines MM.
  def P10MM_Read : SchedReadVariant<[
        SchedVar<P10W_MM_10C_Pred, [P10MM_Read_6C]>,
        SchedVar<NoSchedPred,     [P10MM_Read_1C]>
  ]>;

  // Save 1 cycles if pipeline BR reads the data from pipelines FX, F2.
  def : SchedAlias<P10BR_Read, P10BR_Read_1C>;

  // Save 1 cycles if pipeline DF reads the data from pipelines DX, MU, vMU, BF, CY, DF, MM.
  def : SchedAlias<P10DF_Read, P10DF_Read_1C>;

  // Save 1 cycles if pipeline DV reads the data from pipelines DX, MU, vMU, BF, CY, DF, MM.
  def : SchedAlias<P10DV_Read, P10DV_Read_1C>;

  // Save 1 cycles if pipeline DX reads the data from pipelines DX, MU, vMU, BF, CY, DF, MM.
  def : SchedAlias<P10DX_Read, P10DX_Read_1C>;

  // Save 1 cycles if pipeline F2 reads the data from pipelines ST, SX, FX, F2, PM.
  def : SchedAlias<P10F2_Read, P10F2_Read_1C>;

  // Save 1 cycles if pipeline FX reads the data from pipelines ST, SX, FX, F2, PM.
  def : SchedAlias<P10FX_Read, P10FX_Read_1C>;

  // Save 1 cycles if pipeline LD reads the data from pipelines ST, SX, FX, F2.
  def : SchedAlias<P10LD_Read, P10LD_Read_1C>;

  // Save 1 cycles if pipeline MU reads the data from pipelines DX, MU, DF.
  def : SchedAlias<P10MU_Read, P10MU_Read_1C>;

  // Save 1 cycles if pipeline PM reads the data from pipelines ST, SX, FX, F2, PM.
  def : SchedAlias<P10PM_Read, P10PM_Read_1C>;

  // Save 1 cycles if pipeline ST reads the data from pipelines ST, SX, FX, F2, PM.
  def : SchedAlias<P10ST_Read, P10ST_Read_1C>;

  // Save 1 cycles if pipeline SX reads the data from pipelines ST, SX, FX, F2, PM, MM.
  def : SchedAlias<P10SX_Read, P10SX_Read_1C>;

  // Save 1 cycles if pipeline vMU reads the data from pipelines DX, MU, vMU, BF, CY, DF, MM.
  def : SchedAlias<P10vMU_Read, P10vMU_Read_1C>;

  include "P10InstrResources.td"
}