1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
|
//===-- MSP430InstrFormats.td - MSP430 Instruction Formats -*- tablegen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Describe MSP430 instructions format here
//
class SourceMode<bits<2> val> {
bits<2> Value = val;
}
def SrcReg : SourceMode<0>; // r
def SrcMem : SourceMode<1>; // m
def SrcIndReg : SourceMode<2>; // n
def SrcPostInc : SourceMode<3>; // p
def SrcImm : SourceMode<3>; // i
// SrcCGImm : SourceMode< >; // c
class DestMode<bit val> {
bit Value = val;
}
def DstReg : DestMode<0>; // r
def DstMem : DestMode<1>; // m
// Generic MSP430 Format
class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
field bits<48> Inst;
field bits<48> SoftFail = 0;
let Namespace = "MSP430";
dag OutOperandList = outs;
dag InOperandList = ins;
let AsmString = asmstr;
let Size = size;
}
// MSP430 Double Operand (Format I) Instructions
class IForm<bits<4> opcode, DestMode ad, bit bw, SourceMode as, int size,
dag outs, dag ins, string asmstr, list<dag> pattern>
: MSP430Inst<outs, ins, size, asmstr> {
let Pattern = pattern;
bits<4> rs;
bits<4> rd;
let Inst{15-12} = opcode;
let Inst{11-8} = rs;
let Inst{7} = ad.Value;
let Inst{6} = bw;
let Inst{5-4} = as.Value;
let Inst{3-0} = rd;
}
// 8 bit IForm instructions
class IForm8<bits<4> opcode, DestMode dest, SourceMode src, int size,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
class I8rr<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Alpha";
}
class I8ri<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Gamma";
bits<16> imm;
let Inst{31-16} = imm;
let rs = 0b0000;
}
class I8rc<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: MSP430Inst<outs, ins, 2, asmstr> {
let DecoderNamespace = "Beta";
let Pattern = pattern;
bits<6> imm;
bits<4> rd;
let Inst{15-12} = opcode;
let Inst{11-8} = imm{3-0};
let Inst{7} = DstReg.Value;
let Inst{6} = 1;
let Inst{5-4} = imm{5-4};
let Inst{3-0} = rd;
}
class I8rm<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm8<opcode, DstReg, SrcMem, 4, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Gamma";
bits<20> src;
let rs = src{3-0};
let Inst{31-16} = src{19-4};
}
class I8rn<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm8<opcode, DstReg, SrcIndReg, 2, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Delta";
}
class I8rp<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm8<opcode, DstReg, SrcPostInc, 2, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Delta";
}
class I8mr<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm8<opcode, DstMem, SrcReg, 4, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Alpha";
bits<20> dst;
let rd = dst{3-0};
let Inst{31-16} = dst{19-4};
}
class I8mi<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm8<opcode, DstMem, SrcImm, 6, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Gamma";
bits<16> imm;
bits<20> dst;
let rs = 0b0000;
let Inst{31-16} = imm;
let rd = dst{3-0};
let Inst{47-32} = dst{19-4};
}
class I8mc<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: MSP430Inst<outs, ins, 4, asmstr> {
let DecoderNamespace = "Beta";
let Pattern = pattern;
bits<6> imm;
bits<20> dst;
let Inst{31-16} = dst{19-4};
let Inst{15-12} = opcode;
let Inst{11-8} = imm{3-0};
let Inst{7} = DstMem.Value;
let Inst{6} = 1;
let Inst{5-4} = imm{5-4};
let Inst{3-0} = dst{3-0};
}
class I8mm<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm8<opcode, DstMem, SrcMem, 6, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Gamma";
bits<20> src;
bits<20> dst;
let rs = src{3-0};
let Inst{31-16} = src{19-4};
let rd = dst{3-0};
let Inst{47-32} = dst{19-4};
}
class I8mn<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm8<opcode, DstMem, SrcIndReg, 4, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Delta";
bits<20> dst;
let rd = dst{3-0};
let Inst{31-16} = dst{19-4};
}
class I8mp<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm8<opcode, DstMem, SrcPostInc, 4, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Delta";
bits<20> dst;
let rd = dst{3-0};
let Inst{31-16} = dst{19-4};
}
// 16 bit IForm instructions
class IForm16<bits<4> opcode, DestMode dest, SourceMode src, int size,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm<opcode, dest, 0, src, size, outs, ins, asmstr, pattern>;
class I16rr<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm16<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Alpha";
}
class I16ri<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm16<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Gamma";
bits<16> imm;
let Inst{31-16} = imm;
let rs = 0b0000;
}
class I16rc<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: MSP430Inst<outs, ins, 2, asmstr> {
let DecoderNamespace = "Beta";
let Pattern = pattern;
bits<6> imm;
bits<4> rd;
let Inst{15-12} = opcode;
let Inst{11-8} = imm{3-0};
let Inst{7} = DstReg.Value;
let Inst{6} = 0;
let Inst{5-4} = imm{5-4};
let Inst{3-0} = rd;
}
class I16rm<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm16<opcode, DstReg, SrcMem, 4, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Gamma";
bits<20> src;
let rs = src{3-0};
let Inst{31-16} = src{19-4};
}
class I16rn<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm16<opcode, DstReg, SrcIndReg, 2, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Delta";
}
class I16rp<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm16<opcode, DstReg, SrcPostInc, 2, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Delta";
}
class I16mr<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm16<opcode, DstMem, SrcReg, 4, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Alpha";
bits<20> dst;
let rd = dst{3-0};
let Inst{31-16} = dst{19-4};
}
class I16mi<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm16<opcode, DstMem, SrcImm, 6, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Gamma";
bits<16> imm;
bits<20> dst;
let Inst{31-16} = imm;
let rs = 0b0000;
let rd = dst{3-0};
let Inst{47-32} = dst{19-4};
}
class I16mc<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: MSP430Inst<outs, ins, 4, asmstr> {
let DecoderNamespace = "Beta";
let Pattern = pattern;
bits<6> imm;
bits<20> dst;
let Inst{31-16} = dst{19-4};
let Inst{15-12} = opcode;
let Inst{11-8} = imm{3-0};
let Inst{7} = DstMem.Value;
let Inst{6} = 0;
let Inst{5-4} = imm{5-4};
let Inst{3-0} = dst{3-0};
}
class I16mm<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm16<opcode, DstMem, SrcMem, 6, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Gamma";
bits<20> src;
bits<20> dst;
let rs = src{3-0};
let Inst{31-16} = src{19-4};
let rd = dst{3-0};
let Inst{47-32} = dst{19-4};
}
class I16mn<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm16<opcode, DstMem, SrcIndReg, 4, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Delta";
bits<20> dst;
let rd = dst{3-0};
let Inst{31-16} = dst{19-4};
}
class I16mp<bits<4> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IForm16<opcode, DstMem, SrcPostInc, 4, outs, ins, asmstr, pattern> {
let DecoderNamespace = "Delta";
bits<20> dst;
let rd = dst{3-0};
let Inst{31-16} = dst{19-4};
}
// MSP430 Single Operand (Format II) Instructions
class IIForm<bits<3> opcode, bit bw, SourceMode as, int size,
dag outs, dag ins, string asmstr, list<dag> pattern>
: MSP430Inst<outs, ins, size, asmstr> {
let Pattern = pattern;
bits<4> rs;
let Inst{15-10} = 0b000100;
let Inst{9-7} = opcode;
let Inst{6} = bw;
let Inst{5-4} = as.Value;
let Inst{3-0} = rs;
}
// 8 bit IIForm instructions
class IIForm8<bits<3> opcode, SourceMode src, int size,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm<opcode, 1, src, size, outs, ins, asmstr, pattern>;
class II8r<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm8<opcode, SrcReg, 2, outs, ins, asmstr, pattern>;
class II8m<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm8<opcode, SrcMem, 4, outs, ins, asmstr, pattern> {
bits<20> src;
let rs = src{3-0};
let Inst{31-16} = src{19-4};
}
class II8i<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm8<opcode, SrcImm, 4, outs, ins, asmstr, pattern> {
bits<16> imm;
let rs = 0b0000;
let Inst{31-16} = imm;
}
class II8c<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: MSP430Inst<outs, ins, 2, asmstr> {
let Pattern = pattern;
bits<6> imm;
let Inst{15-10} = 0b000100;
let Inst{9-7} = opcode;
let Inst{6} = 1;
let Inst{5-0} = imm;
}
class II8n<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm8<opcode, SrcIndReg, 2, outs, ins, asmstr, pattern>;
class II8p<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm8<opcode, SrcPostInc, 2, outs, ins, asmstr, pattern>;
// 16 bit IIForm instructions
class IIForm16<bits<3> opcode, SourceMode src, int size,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm<opcode, 0, src, size, outs, ins, asmstr, pattern>;
class II16r<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm16<opcode, SrcReg, 2, outs, ins, asmstr, pattern>;
class II16m<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm16<opcode, SrcMem, 4, outs, ins, asmstr, pattern> {
bits<20> src;
let rs = src{3-0};
let Inst{31-16} = src{19-4};
}
class II16i<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm16<opcode, SrcImm, 4, outs, ins, asmstr, pattern> {
bits<16> imm;
let rs = 0b0000;
let Inst{31-16} = imm;
}
class II16c<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: MSP430Inst<outs, ins, 2, asmstr> {
let Pattern = pattern;
bits<6> imm;
let Inst{15-10} = 0b000100;
let Inst{9-7} = opcode;
let Inst{6} = 0;
let Inst{5-0} = imm;
}
class II16n<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm16<opcode, SrcIndReg, 2, outs, ins, asmstr, pattern>;
class II16p<bits<3> opcode,
dag outs, dag ins, string asmstr, list<dag> pattern>
: IIForm16<opcode, SrcPostInc, 2, outs, ins, asmstr, pattern>;
// MSP430 Conditional Jumps Instructions
class CJForm<dag outs, dag ins, string asmstr, list<dag> pattern>
: MSP430Inst<outs, ins, 2, asmstr> {
let Pattern = pattern;
bits<3> cond;
bits<10> dst;
let Inst{15-13} = 0b001;
let Inst{12-10} = cond;
let Inst{9-0} = dst;
}
// Pseudo instructions
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
: MSP430Inst<outs, ins, 0, asmstr> {
let Pattern = pattern;
}
|
