; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
;; This test is really dependent on propagating a lot of memory info around, but in the end, not
;; screwing up a single add.
; RUN: opt < %s -passes=newgvn -S | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"

%struct.Letter = type { i32, i32, i32, i32 }

@alPhrase = external local_unnamed_addr global [26 x %struct.Letter], align 16
@aqMainMask = external local_unnamed_addr global [2 x i64], align 16
@aqMainSign = external local_unnamed_addr global [2 x i64], align 16
@cchPhraseLength = external local_unnamed_addr global i32, align 4
@auGlobalFrequency = external local_unnamed_addr global [26 x i32], align 16
@.str.7 = external hidden unnamed_addr constant [28 x i8], align 1

; Function Attrs: nounwind uwtable
declare void @Fatal(ptr, i32) local_unnamed_addr #0

; Function Attrs: nounwind readnone
declare ptr @__ctype_b_loc() local_unnamed_addr #1

; Function Attrs: nounwind uwtable
define void @BuildMask(ptr nocapture readonly) local_unnamed_addr #0 {
; CHECK-LABEL: define void @BuildMask(
; CHECK-SAME: ptr readonly captures(none) [[TMP0:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:    tail call void @llvm.memset.p0.i64(ptr align 16 @alPhrase, i8 0, i64 416, i1 false)
; CHECK-NEXT:    tail call void @llvm.memset.p0.i64(ptr align 16 @aqMainMask, i8 0, i64 16, i1 false)
; CHECK-NEXT:    tail call void @llvm.memset.p0.i64(ptr align 16 @aqMainSign, i8 0, i64 16, i1 false)
; CHECK-NEXT:    br label %[[DOTSINK_SPLIT:.*]]
; CHECK:       [[_SINK_SPLIT:.*:]]
; CHECK-NEXT:    [[DOT0:%.*]] = phi ptr [ [[TMP0]], [[TMP1:%.*]] ], [ [[TMP3:%.*]], %[[TMP14:.*]] ]
; CHECK-NEXT:    [[DOTSINK:%.*]] = phi i32 [ 0, [[TMP1]] ], [ [[TMP22:%.*]], %[[TMP14]] ]
; CHECK-NEXT:    store i32 [[DOTSINK]], ptr @cchPhraseLength, align 4, !tbaa [[INT_TBAA1:![0-9]+]]
; CHECK-NEXT:    br label %[[BB2:.*]]
; CHECK:       [[BB2]]:
; CHECK-NEXT:    [[DOT1:%.*]] = phi ptr [ [[DOT0]], %[[DOTSINK_SPLIT]] ], [ [[TMP3]], %[[TMP6:.*]] ]
; CHECK-NEXT:    [[TMP3]] = getelementptr inbounds i8, ptr [[DOT1]], i64 1
; CHECK-NEXT:    [[TMP4:%.*]] = load i8, ptr [[DOT1]], align 1, !tbaa [[CHAR_TBAA5:![0-9]+]]
; CHECK-NEXT:    [[TMP5:%.*]] = icmp eq i8 [[TMP4]], 0
; CHECK-NEXT:    br i1 [[TMP5]], label %[[DOTPREHEADER_PREHEADER:.*]], label %[[TMP6]]
; CHECK:       [[_PREHEADER_PREHEADER:.*:]]
; CHECK-NEXT:    br [[DOTPREHEADER:label %.*]]
; CHECK:       [[TMP6]]:
; CHECK-NEXT:    [[TMP7:%.*]] = tail call ptr @__ctype_b_loc() #[[ATTR4:[0-9]+]]
; CHECK-NEXT:    [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8, !tbaa [[ANYPTR_TBAA6:![0-9]+]]
; CHECK-NEXT:    [[TMP9:%.*]] = sext i8 [[TMP4]] to i64
; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr inbounds i16, ptr [[TMP8]], i64 [[TMP9]]
; CHECK-NEXT:    [[TMP11:%.*]] = load i16, ptr [[TMP10]], align 2, !tbaa [[SHORT_TBAA8:![0-9]+]]
; CHECK-NEXT:    [[TMP12:%.*]] = and i16 [[TMP11]], 1024
; CHECK-NEXT:    [[TMP13:%.*]] = icmp eq i16 [[TMP12]], 0
; CHECK-NEXT:    br i1 [[TMP13]], label %[[BB2]], label %[[TMP14]]
; CHECK:       [[TMP14]]:
; CHECK-NEXT:    [[TMP15:%.*]] = sext i8 [[TMP4]] to i32
; CHECK-NEXT:    [[TMP16:%.*]] = tail call i32 @tolower(i32 [[TMP15]]) #[[ATTR5:[0-9]+]]
; CHECK-NEXT:    [[TMP17:%.*]] = add nsw i32 [[TMP16]], -97
; CHECK-NEXT:    [[TMP18:%.*]] = sext i32 [[TMP17]] to i64
; CHECK-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [26 x %struct.Letter], ptr @alPhrase, i64 0, i64 [[TMP18]], i32 0
; CHECK-NEXT:    [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 16, !tbaa [[INT_TBAA10:![0-9]+]]
; CHECK-NEXT:    [[TMP21:%.*]] = add i32 [[TMP20]], 1
; CHECK-NEXT:    store i32 [[TMP21]], ptr [[TMP19]], align 16, !tbaa [[INT_TBAA10]]
; CHECK-NEXT:    [[TMP22]] = add nsw i32 [[DOTSINK]], 1
; CHECK-NEXT:    br label %[[DOTSINK_SPLIT]]
; CHECK:       [[_PREHEADER:.*:]]
; CHECK-NEXT:    [[INDVARS_IV:%.*]] = phi i64 [ 0, %[[DOTPREHEADER_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], %[[TMP57:.*]] ]
; CHECK-NEXT:    [[DOT04961:%.*]] = phi i32 [ [[DOT2:%.*]], %[[TMP57]] ], [ 0, %[[DOTPREHEADER_PREHEADER]] ]
; CHECK-NEXT:    [[DOT05160:%.*]] = phi i32 [ [[DOT253:%.*]], %[[TMP57]] ], [ 0, %[[DOTPREHEADER_PREHEADER]] ]
; CHECK-NEXT:    [[TMP23:%.*]] = getelementptr inbounds [26 x %struct.Letter], ptr @alPhrase, i64 0, i64 [[INDVARS_IV]], i32 0
; CHECK-NEXT:    [[TMP24:%.*]] = load i32, ptr [[TMP23]], align 16, !tbaa [[INT_TBAA10]]
; CHECK-NEXT:    [[TMP25:%.*]] = icmp eq i32 [[TMP24]], 0
; CHECK-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [26 x i32], ptr @auGlobalFrequency, i64 0, i64 [[INDVARS_IV]]
; CHECK-NEXT:    br i1 [[TMP25]], label %[[TMP27:.*]], label %[[TMP28:.*]]
; CHECK:       [[TMP27]]:
; CHECK-NEXT:    store i32 -1, ptr [[TMP26]], align 4, !tbaa [[INT_TBAA1]]
; CHECK-NEXT:    br label %[[TMP57]]
; CHECK:       [[TMP28]]:
; CHECK-NEXT:    store i32 0, ptr [[TMP26]], align 4, !tbaa [[INT_TBAA1]]
; CHECK-NEXT:    [[TMP29:%.*]] = zext i32 [[TMP24]] to i64
; CHECK-NEXT:    br i1 false, label %[[DOT_CRIT_EDGE:.*]], label %[[DOTLR_PH_PREHEADER:.*]]
; CHECK:       [[_LR_PH_PREHEADER:.*:]]
; CHECK-NEXT:    br label %[[DOTLR_PH:.*]]
; CHECK:       [[_LR_PH:.*:]]
; CHECK-NEXT:    [[DOT04658:%.*]] = phi i64 [ [[TMP31:%.*]], %[[DOTLR_PH]] ], [ 1, %[[DOTLR_PH_PREHEADER]] ]
; CHECK-NEXT:    [[DOT04857:%.*]] = phi i32 [ [[TMP30:%.*]], %[[DOTLR_PH]] ], [ 1, %[[DOTLR_PH_PREHEADER]] ]
; CHECK-NEXT:    [[TMP30]] = add nuw nsw i32 [[DOT04857]], 1
; CHECK-NEXT:    [[TMP31]] = shl i64 [[DOT04658]], 1
; CHECK-NEXT:    [[TMP32:%.*]] = icmp ult i64 [[TMP29]], [[TMP31]]
; CHECK-NEXT:    br i1 [[TMP32]], label %[[DOT_CRIT_EDGE_LOOPEXIT:.*]], label %[[DOTLR_PH]]
; CHECK:       [[__CRIT_EDGE_LOOPEXIT:.*:]]
; CHECK-NEXT:    br label %[[DOT_CRIT_EDGE]]
; CHECK:       [[__CRIT_EDGE:.*:]]
; CHECK-NEXT:    [[DOT048_LCSSA:%.*]] = phi i32 [ poison, %[[TMP28]] ], [ [[TMP30]], %[[DOT_CRIT_EDGE_LOOPEXIT]] ]
; CHECK-NEXT:    [[DOT046_LCSSA:%.*]] = phi i64 [ poison, %[[TMP28]] ], [ [[TMP31]], %[[DOT_CRIT_EDGE_LOOPEXIT]] ]
; CHECK-NEXT:    [[TMP33:%.*]] = add nsw i32 [[DOT048_LCSSA]], [[DOT04961]]
; CHECK-NEXT:    [[TMP34:%.*]] = icmp ugt i32 [[TMP33]], 64
; CHECK-NEXT:    br i1 [[TMP34]], label %[[TMP35:.*]], label %[[TMP39:.*]]
; CHECK:       [[TMP35]]:
; CHECK-NEXT:    [[TMP36:%.*]] = add i32 [[DOT05160]], 1
; CHECK-NEXT:    [[TMP37:%.*]] = icmp ugt i32 [[TMP36]], 1
; CHECK-NEXT:    br i1 [[TMP37]], label %[[TMP38:.*]], label %[[TMP39]]
; CHECK:       [[TMP38]]:
; CHECK-NEXT:    tail call void @Fatal(ptr @.str.7, i32 0)
; CHECK-NEXT:    br label %[[TMP39]]
; CHECK:       [[TMP39]]:
; CHECK-NEXT:    [[DOT152:%.*]] = phi i32 [ [[DOT05160]], %[[DOT_CRIT_EDGE]] ], [ [[TMP36]], %[[TMP38]] ], [ [[TMP36]], %[[TMP35]] ]
; CHECK-NEXT:    [[DOT150:%.*]] = phi i32 [ [[DOT04961]], %[[DOT_CRIT_EDGE]] ], [ 0, %[[TMP38]] ], [ 0, %[[TMP35]] ]
; CHECK-NEXT:    [[TMP40:%.*]] = add i64 [[DOT046_LCSSA]], 4294967295
; CHECK-NEXT:    [[TMP41:%.*]] = trunc i64 [[TMP40]] to i32
; CHECK-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [26 x %struct.Letter], ptr @alPhrase, i64 0, i64 [[INDVARS_IV]], i32 2
; CHECK-NEXT:    store i32 [[TMP41]], ptr [[TMP42]], align 8, !tbaa [[INT_TBAA12:![0-9]+]]
; CHECK-NEXT:    [[TMP43:%.*]] = zext i32 [[DOT150]] to i64
; CHECK-NEXT:    [[DOT046_:%.*]] = shl i64 [[DOT046_LCSSA]], [[TMP43]]
; CHECK-NEXT:    [[TMP44:%.*]] = zext i32 [[DOT152]] to i64
; CHECK-NEXT:    [[TMP45:%.*]] = getelementptr inbounds [2 x i64], ptr @aqMainSign, i64 0, i64 [[TMP44]]
; CHECK-NEXT:    [[TMP46:%.*]] = load i64, ptr [[TMP45]], align 8, !tbaa [[LONG_TBAA13:![0-9]+]]
; CHECK-NEXT:    [[TMP47:%.*]] = or i64 [[TMP46]], [[DOT046_]]
; CHECK-NEXT:    store i64 [[TMP47]], ptr [[TMP45]], align 8, !tbaa [[LONG_TBAA13]]
; CHECK-NEXT:    [[TMP48:%.*]] = load i32, ptr [[TMP23]], align 16, !tbaa [[INT_TBAA10]]
; CHECK-NEXT:    [[TMP49:%.*]] = zext i32 [[TMP48]] to i64
; CHECK-NEXT:    [[TMP50:%.*]] = shl i64 [[TMP49]], [[TMP43]]
; CHECK-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [2 x i64], ptr @aqMainMask, i64 0, i64 [[TMP44]]
; CHECK-NEXT:    [[TMP52:%.*]] = load i64, ptr [[TMP51]], align 8, !tbaa [[LONG_TBAA13]]
; CHECK-NEXT:    [[TMP53:%.*]] = or i64 [[TMP50]], [[TMP52]]
; CHECK-NEXT:    store i64 [[TMP53]], ptr [[TMP51]], align 8, !tbaa [[LONG_TBAA13]]
; CHECK-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [26 x %struct.Letter], ptr @alPhrase, i64 0, i64 [[INDVARS_IV]], i32 1
; CHECK-NEXT:    store i32 [[DOT150]], ptr [[TMP54]], align 4, !tbaa [[INT_TBAA15:![0-9]+]]
; CHECK-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [26 x %struct.Letter], ptr @alPhrase, i64 0, i64 [[INDVARS_IV]], i32 3
; CHECK-NEXT:    store i32 [[DOT152]], ptr [[TMP55]], align 4, !tbaa [[INT_TBAA16:![0-9]+]]
; CHECK-NEXT:    [[TMP56:%.*]] = add nsw i32 [[DOT150]], [[DOT048_LCSSA]]
; CHECK-NEXT:    br label %[[TMP57]]
; CHECK:       [[TMP57]]:
; CHECK-NEXT:    [[DOT253]] = phi i32 [ [[DOT05160]], %[[TMP27]] ], [ [[DOT152]], %[[TMP39]] ]
; CHECK-NEXT:    [[DOT2]] = phi i32 [ [[DOT04961]], %[[TMP27]] ], [ [[TMP56]], %[[TMP39]] ]
; CHECK-NEXT:    [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1
; CHECK-NEXT:    [[EXITCOND:%.*]] = icmp ne i64 [[INDVARS_IV_NEXT]], 26
; CHECK-NEXT:    br i1 [[EXITCOND]], [[DOTPREHEADER]], label %[[BB58:.*]]
; CHECK:       [[BB58]]:
; CHECK-NEXT:    ret void
;
  tail call void @llvm.memset.p0.i64(ptr align 16 @alPhrase, i8 0, i64 416, i1 false)
  tail call void @llvm.memset.p0.i64(ptr align 16 @aqMainMask, i8 0, i64 16, i1 false)
  tail call void @llvm.memset.p0.i64(ptr align 16 @aqMainSign, i8 0, i64 16, i1 false)
  br label %.sink.split

.sink.split:                                      ; preds = %14, %1
  %.0 = phi ptr [ %0, %1 ], [ %.lcssa67, %14 ]
  %.sink = phi i32 [ 0, %1 ], [ %23, %14 ]
  store i32 %.sink, ptr @cchPhraseLength, align 4, !tbaa !1
  br label %2

; <label>:2:                                      ; preds = %6, %.sink.split
  %.1 = phi ptr [ %.0, %.sink.split ], [ %3, %6 ]
  %3 = getelementptr inbounds i8, ptr %.1, i64 1
  %4 = load i8, ptr %.1, align 1, !tbaa !5
  %5 = icmp eq i8 %4, 0
  br i1 %5, label %.preheader.preheader, label %6

.preheader.preheader:                             ; preds = %2
  br label %.preheader

; <label>:6:                                      ; preds = %2
  %7 = tail call ptr @__ctype_b_loc() #4
  %8 = load ptr, ptr %7, align 8, !tbaa !6
  %9 = sext i8 %4 to i64
  %10 = getelementptr inbounds i16, ptr %8, i64 %9
  %11 = load i16, ptr %10, align 2, !tbaa !8
  %12 = and i16 %11, 1024
  %13 = icmp eq i16 %12, 0
  br i1 %13, label %2, label %14

; <label>:14:                                     ; preds = %6
  %.lcssa67 = phi ptr [ %3, %6 ]
  %.lcssa65 = phi i8 [ %4, %6 ]
  %15 = sext i8 %.lcssa65 to i32
  %16 = tail call i32 @tolower(i32 %15) #5
  %17 = add nsw i32 %16, -97
  %18 = sext i32 %17 to i64
  %19 = getelementptr inbounds [26 x %struct.Letter], ptr @alPhrase, i64 0, i64 %18, i32 0
  %20 = load i32, ptr %19, align 16, !tbaa !10
  %21 = add i32 %20, 1
  store i32 %21, ptr %19, align 16, !tbaa !10
  %22 = load i32, ptr @cchPhraseLength, align 4, !tbaa !1
  %23 = add nsw i32 %22, 1
  br label %.sink.split

.preheader:                                       ; preds = %58, %.preheader.preheader
  %indvars.iv = phi i64 [ 0, %.preheader.preheader ], [ %indvars.iv.next, %58 ]
  %.04961 = phi i32 [ %.2, %58 ], [ 0, %.preheader.preheader ]
  %.05160 = phi i32 [ %.253, %58 ], [ 0, %.preheader.preheader ]
  %24 = getelementptr inbounds [26 x %struct.Letter], ptr @alPhrase, i64 0, i64 %indvars.iv, i32 0
  %25 = load i32, ptr %24, align 16, !tbaa !10
  %26 = icmp eq i32 %25, 0
  %27 = getelementptr inbounds [26 x i32], ptr @auGlobalFrequency, i64 0, i64 %indvars.iv
  br i1 %26, label %28, label %29

; <label>:28:                                     ; preds = %.preheader
  store i32 -1, ptr %27, align 4, !tbaa !1
  br label %58

; <label>:29:                                     ; preds = %.preheader
  store i32 0, ptr %27, align 4, !tbaa !1
  %30 = zext i32 %25 to i64
  br i1 false, label %._crit_edge, label %.lr.ph.preheader

.lr.ph.preheader:                                 ; preds = %29
  br label %.lr.ph

.lr.ph:                                           ; preds = %.lr.ph, %.lr.ph.preheader
  %.04658 = phi i64 [ %32, %.lr.ph ], [ 1, %.lr.ph.preheader ]
  %.04857 = phi i32 [ %31, %.lr.ph ], [ 1, %.lr.ph.preheader ]
  %31 = add nuw nsw i32 %.04857, 1
  %32 = shl i64 %.04658, 1
  %33 = icmp ult i64 %30, %32
  br i1 %33, label %._crit_edge.loopexit, label %.lr.ph

._crit_edge.loopexit:                             ; preds = %.lr.ph
  %.lcssa63 = phi i32 [ %31, %.lr.ph ]
  %.lcssa = phi i64 [ %32, %.lr.ph ]
  br label %._crit_edge

._crit_edge:                                      ; preds = %._crit_edge.loopexit, %29
  %.048.lcssa = phi i32 [ 1, %29 ], [ %.lcssa63, %._crit_edge.loopexit ]
  %.046.lcssa = phi i64 [ 1, %29 ], [ %.lcssa, %._crit_edge.loopexit ]
  %34 = add nsw i32 %.048.lcssa, %.04961
  %35 = icmp ugt i32 %34, 64
  br i1 %35, label %36, label %40

; <label>:36:                                     ; preds = %._crit_edge
; This testcase essentially comes down to this little add.
; If we screw up the revisitation of the users of store of %sink above
; we will end up propagating and simplifying this to 1 in the final output
; because we keep an optimistic assumption we should not.
  %37 = add i32 %.05160, 1
  %38 = icmp ugt i32 %37, 1
  br i1 %38, label %39, label %40

; <label>:39:                                     ; preds = %36
  tail call void @Fatal(ptr @.str.7, i32 0)
  br label %40

; <label>:40:                                     ; preds = %39, %36, %._crit_edge
  %.152 = phi i32 [ %.05160, %._crit_edge ], [ %37, %39 ], [ %37, %36 ]
  %.150 = phi i32 [ %.04961, %._crit_edge ], [ 0, %39 ], [ 0, %36 ]
  %41 = add i64 %.046.lcssa, 4294967295
  %42 = trunc i64 %41 to i32
  %43 = getelementptr inbounds [26 x %struct.Letter], ptr @alPhrase, i64 0, i64 %indvars.iv, i32 2
  store i32 %42, ptr %43, align 8, !tbaa !12
  %44 = zext i32 %.150 to i64
  %.046. = shl i64 %.046.lcssa, %44
  %45 = zext i32 %.152 to i64
  %46 = getelementptr inbounds [2 x i64], ptr @aqMainSign, i64 0, i64 %45
  %47 = load i64, ptr %46, align 8, !tbaa !13
  %48 = or i64 %47, %.046.
  store i64 %48, ptr %46, align 8, !tbaa !13
  %49 = load i32, ptr %24, align 16, !tbaa !10
  %50 = zext i32 %49 to i64
  %51 = shl i64 %50, %44
  %52 = getelementptr inbounds [2 x i64], ptr @aqMainMask, i64 0, i64 %45
  %53 = load i64, ptr %52, align 8, !tbaa !13
  %54 = or i64 %51, %53
  store i64 %54, ptr %52, align 8, !tbaa !13
  %55 = getelementptr inbounds [26 x %struct.Letter], ptr @alPhrase, i64 0, i64 %indvars.iv, i32 1
  store i32 %.150, ptr %55, align 4, !tbaa !15
  %56 = getelementptr inbounds [26 x %struct.Letter], ptr @alPhrase, i64 0, i64 %indvars.iv, i32 3
  store i32 %.152, ptr %56, align 4, !tbaa !16
  %57 = add nsw i32 %.150, %.048.lcssa
  br label %58

; <label>:58:                                     ; preds = %40, %28
  %.253 = phi i32 [ %.05160, %28 ], [ %.152, %40 ]
  %.2 = phi i32 [ %.04961, %28 ], [ %57, %40 ]
  %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
  %exitcond = icmp ne i64 %indvars.iv.next, 26
  br i1 %exitcond, label %.preheader, label %59

; <label>:59:                                     ; preds = %58
  ret void
}

; Function Attrs: argmemonly nounwind
declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1) #2

; Function Attrs: inlinehint nounwind readonly uwtable
declare i32 @tolower(i32) local_unnamed_addr #3

attributes #0 = { nounwind uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #2 = { argmemonly nounwind }
attributes #3 = { inlinehint nounwind readonly uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+fxsr,+mmx,+sse,+sse2,+x87" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #4 = { nounwind readnone }
attributes #5 = { nounwind readonly }

!llvm.ident = !{!0}

!0 = !{!"clang version 4.0.0"}
!1 = !{!2, !2, i64 0}
!2 = !{!"int", !3, i64 0}
!3 = !{!"omnipotent char", !4, i64 0}
!4 = !{!"Simple C/C++ TBAA"}
!5 = !{!3, !3, i64 0}
!6 = !{!7, !7, i64 0}
!7 = !{!"any pointer", !3, i64 0}
!8 = !{!9, !9, i64 0}
!9 = !{!"short", !3, i64 0}
!10 = !{!11, !2, i64 0}
!11 = !{!"", !2, i64 0, !2, i64 4, !2, i64 8, !2, i64 12}
!12 = !{!11, !2, i64 8}
!13 = !{!14, !14, i64 0}
!14 = !{!"long", !3, i64 0}
!15 = !{!11, !2, i64 4}
!16 = !{!11, !2, i64 12}
;.
; CHECK: [[INT_TBAA1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
; CHECK: [[META2]] = !{!"int", [[META3:![0-9]+]], i64 0}
; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
; CHECK: [[META4]] = !{!"Simple C/C++ TBAA"}
; CHECK: [[CHAR_TBAA5]] = !{[[META3]], [[META3]], i64 0}
; CHECK: [[ANYPTR_TBAA6]] = !{[[META7:![0-9]+]], [[META7]], i64 0}
; CHECK: [[META7]] = !{!"any pointer", [[META3]], i64 0}
; CHECK: [[SHORT_TBAA8]] = !{[[META9:![0-9]+]], [[META9]], i64 0}
; CHECK: [[META9]] = !{!"short", [[META3]], i64 0}
; CHECK: [[INT_TBAA10]] = !{[[META11:![0-9]+]], [[META2]], i64 0}
; CHECK: [[META11]] = !{!"", [[META2]], i64 0, [[META2]], i64 4, [[META2]], i64 8, [[META2]], i64 12}
; CHECK: [[INT_TBAA12]] = !{[[META11]], [[META2]], i64 8}
; CHECK: [[LONG_TBAA13]] = !{[[META14:![0-9]+]], [[META14]], i64 0}
; CHECK: [[META14]] = !{!"long", [[META3]], i64 0}
; CHECK: [[INT_TBAA15]] = !{[[META11]], [[META2]], i64 4}
; CHECK: [[INT_TBAA16]] = !{[[META11]], [[META2]], i64 12}
;.