/llvm/test/Transforms/LoopVectorize/VPlan/
../
AArch64
PowerPC
RISCV
X86
conditional-scalar-assignment-vplan.ll
early_exit_with_stores_vplan.ll
first-order-recurrence-chains-vplan.ll
first-order-recurrence-sink-replicate-region.ll
icmp-uniforms.ll
interleave-and-scalarize-only.ll
lit.local.cfg
phi-with-fastflags-vplan.ll
predicator.ll
tail-folding.ll
uncountable-early-exit-vplan.ll
vplan-dot-printing.ll
vplan-force-tail-with-evl.ll
vplan-iv-transforms.ll
vplan-predicate-switch.ll
vplan-print-after-all.ll
vplan-printing-before-execute.ll
vplan-printing-metadata.ll
vplan-printing-outer-loop.ll
vplan-printing-reductions.ll
vplan-printing.ll
vplan-sink-scalars-and-merge-vf1.ll
vplan-sink-scalars-and-merge.ll
vplan-stress-test-no-explict-vf.ll
vplan-unused-interleave-group.ll
vplan-widen-struct-return.ll
vplan_hcfg_stress_test.ll