# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx               -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2              -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f           -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512

--- |
  define void @test_and_v64i8() {
    %ret = and <64 x i8> undef, undef
    ret void
  }

  define void @test_and_v32i16() {
    %ret = and <32 x i16> undef, undef
    ret void
  }

  define void @test_and_v16i32() {
    %ret = and <16 x i32> undef, undef
    ret void
  }

  define void @test_and_v8i64() {
    %ret = and <8 x i64> undef, undef
    ret void
  }

  define <64 x i8> @test_and_v64i8_2(<64 x i8> %arg1, <64 x i8> %arg2) #0 {
    %ret = and <64 x i8> %arg1, %arg2
    ret <64 x i8> %ret
  }
...
---
name:            test_and_v64i8
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $zmm0, $zmm1

    ; AVX-LABEL: name: test_and_v64i8
    ; AVX: liveins: $zmm0, $zmm1
    ; AVX-NEXT: {{  $}}
    ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
    ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
    ; AVX-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
    ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
    ; AVX-NEXT: [[AND:%[0-9]+]]:_(<32 x s8>) = G_AND [[UV]], [[UV2]]
    ; AVX-NEXT: [[AND1:%[0-9]+]]:_(<32 x s8>) = G_AND [[UV1]], [[UV3]]
    ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[AND]](<32 x s8>), [[AND1]](<32 x s8>)
    ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
    ; AVX-NEXT: RET 0
    ; AVX512-LABEL: name: test_and_v64i8
    ; AVX512: liveins: $zmm0, $zmm1
    ; AVX512-NEXT: {{  $}}
    ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
    ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
    ; AVX512-NEXT: [[AND:%[0-9]+]]:_(<64 x s8>) = G_AND [[DEF]], [[DEF1]]
    ; AVX512-NEXT: $zmm0 = COPY [[AND]](<64 x s8>)
    ; AVX512-NEXT: RET 0
    %0(<64 x s8>) = IMPLICIT_DEF
    %1(<64 x s8>) = IMPLICIT_DEF
    %2(<64 x s8>) = G_AND %0, %1
    $zmm0 = COPY %2
    RET 0
...
---
name:            test_and_v32i16
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $zmm0, $zmm1

    ; AVX-LABEL: name: test_and_v32i16
    ; AVX: liveins: $zmm0, $zmm1
    ; AVX-NEXT: {{  $}}
    ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
    ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
    ; AVX-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
    ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
    ; AVX-NEXT: [[AND:%[0-9]+]]:_(<16 x s16>) = G_AND [[UV]], [[UV2]]
    ; AVX-NEXT: [[AND1:%[0-9]+]]:_(<16 x s16>) = G_AND [[UV1]], [[UV3]]
    ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[AND]](<16 x s16>), [[AND1]](<16 x s16>)
    ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
    ; AVX-NEXT: RET 0
    ; AVX512-LABEL: name: test_and_v32i16
    ; AVX512: liveins: $zmm0, $zmm1
    ; AVX512-NEXT: {{  $}}
    ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
    ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
    ; AVX512-NEXT: [[AND:%[0-9]+]]:_(<32 x s16>) = G_AND [[DEF]], [[DEF1]]
    ; AVX512-NEXT: $zmm0 = COPY [[AND]](<32 x s16>)
    ; AVX512-NEXT: RET 0
    %0(<32 x s16>) = IMPLICIT_DEF
    %1(<32 x s16>) = IMPLICIT_DEF
    %2(<32 x s16>) = G_AND %0, %1
    $zmm0 = COPY %2
    RET 0
...
---
name:            test_and_v16i32
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $zmm0, $zmm1

    ; AVX-LABEL: name: test_and_v16i32
    ; AVX: liveins: $zmm0, $zmm1
    ; AVX-NEXT: {{  $}}
    ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
    ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
    ; AVX-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
    ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<8 x s32>), [[UV3:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
    ; AVX-NEXT: [[AND:%[0-9]+]]:_(<8 x s32>) = G_AND [[UV]], [[UV2]]
    ; AVX-NEXT: [[AND1:%[0-9]+]]:_(<8 x s32>) = G_AND [[UV1]], [[UV3]]
    ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[AND]](<8 x s32>), [[AND1]](<8 x s32>)
    ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)
    ; AVX-NEXT: RET 0
    ; AVX512-LABEL: name: test_and_v16i32
    ; AVX512: liveins: $zmm0, $zmm1
    ; AVX512-NEXT: {{  $}}
    ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
    ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
    ; AVX512-NEXT: [[AND:%[0-9]+]]:_(<16 x s32>) = G_AND [[DEF]], [[DEF1]]
    ; AVX512-NEXT: $zmm0 = COPY [[AND]](<16 x s32>)
    ; AVX512-NEXT: RET 0
    %0(<16 x s32>) = IMPLICIT_DEF
    %1(<16 x s32>) = IMPLICIT_DEF
    %2(<16 x s32>) = G_AND %0, %1
    $zmm0 = COPY %2
    RET 0
...
---
name:            test_and_v8i64
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $zmm0, $zmm1

    ; AVX-LABEL: name: test_and_v8i64
    ; AVX: liveins: $zmm0, $zmm1
    ; AVX-NEXT: {{  $}}
    ; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
    ; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
    ; AVX-NEXT: [[UV:%[0-9]+]]:_(<4 x s64>), [[UV1:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)
    ; AVX-NEXT: [[UV2:%[0-9]+]]:_(<4 x s64>), [[UV3:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)
    ; AVX-NEXT: [[AND:%[0-9]+]]:_(<4 x s64>) = G_AND [[UV]], [[UV2]]
    ; AVX-NEXT: [[AND1:%[0-9]+]]:_(<4 x s64>) = G_AND [[UV1]], [[UV3]]
    ; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[AND]](<4 x s64>), [[AND1]](<4 x s64>)
    ; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)
    ; AVX-NEXT: RET 0
    ; AVX512-LABEL: name: test_and_v8i64
    ; AVX512: liveins: $zmm0, $zmm1
    ; AVX512-NEXT: {{  $}}
    ; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
    ; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
    ; AVX512-NEXT: [[AND:%[0-9]+]]:_(<8 x s64>) = G_AND [[DEF]], [[DEF1]]
    ; AVX512-NEXT: $zmm0 = COPY [[AND]](<8 x s64>)
    ; AVX512-NEXT: RET 0
    %0(<8 x s64>) = IMPLICIT_DEF
    %1(<8 x s64>) = IMPLICIT_DEF
    %2(<8 x s64>) = G_AND %0, %1
    $zmm0 = COPY %2
    RET 0
...
---
name:            test_and_v64i8_2
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
  - { id: 6, class: _ }
  - { id: 7, class: _ }
  - { id: 8, class: _ }
#
#
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1, $ymm2, $ymm3
    ; AVX-LABEL: name: test_and_v64i8_2
    ; AVX: liveins: $ymm0, $ymm1, $ymm2, $ymm3
    ; AVX-NEXT: {{  $}}
    ; AVX-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
    ; AVX-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
    ; AVX-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
    ; AVX-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
    ; AVX-NEXT: [[AND:%[0-9]+]]:_(<32 x s8>) = G_AND [[COPY]], [[COPY2]]
    ; AVX-NEXT: [[AND1:%[0-9]+]]:_(<32 x s8>) = G_AND [[COPY1]], [[COPY3]]
    ; AVX-NEXT: $ymm0 = COPY [[AND]](<32 x s8>)
    ; AVX-NEXT: $ymm1 = COPY [[AND1]](<32 x s8>)
    ; AVX-NEXT: RET 0, implicit $ymm0, implicit $ymm1
    ; AVX512-LABEL: name: test_and_v64i8_2
    ; AVX512: liveins: $ymm0, $ymm1, $ymm2, $ymm3
    ; AVX512-NEXT: {{  $}}
    ; AVX512-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
    ; AVX512-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
    ; AVX512-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
    ; AVX512-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
    ; AVX512-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[COPY1]](<32 x s8>)
    ; AVX512-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY2]](<32 x s8>), [[COPY3]](<32 x s8>)
    ; AVX512-NEXT: [[AND:%[0-9]+]]:_(<64 x s8>) = G_AND [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
    ; AVX512-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[AND]](<64 x s8>)
    ; AVX512-NEXT: $ymm0 = COPY [[UV]](<32 x s8>)
    ; AVX512-NEXT: $ymm1 = COPY [[UV1]](<32 x s8>)
    ; AVX512-NEXT: RET 0, implicit $ymm0, implicit $ymm1
    %2(<32 x s8>) = COPY $ymm0
    %3(<32 x s8>) = COPY $ymm1
    %4(<32 x s8>) = COPY $ymm2
    %5(<32 x s8>) = COPY $ymm3
    %0(<64 x s8>) = G_CONCAT_VECTORS %2(<32 x s8>), %3(<32 x s8>)
    %1(<64 x s8>) = G_CONCAT_VECTORS %4(<32 x s8>), %5(<32 x s8>)
    %6(<64 x s8>) = G_AND %0, %1
    %7(<32 x s8>), %8(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)
    $ymm0 = COPY %7(<32 x s8>)
    $ymm1 = COPY %8(<32 x s8>)
    RET 0, implicit $ymm0, implicit $ymm1
...