; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:   -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN:   -mcpu=future -ppc-asm-full-reg-names < %s | FileCheck %s

declare <16 x i8> @llvm.ppc.xxmulmul(<16 x i8>, <16 x i8>, i32 immarg)
declare <16 x i8> @llvm.ppc.xxmulmulhiadd(<16 x i8>, <16 x i8>, i32 immarg, i32 immarg, i32 immarg)
declare <16 x i8> @llvm.ppc.xxmulmulloadd(<16 x i8>, <16 x i8>, i32 immarg, i32 immarg)
declare <16 x i8> @llvm.ppc.xxssumudm(<16 x i8>, <16 x i8>, i32 immarg)
declare <16 x i8> @llvm.ppc.xxssumudmc(<16 x i8>, <16 x i8>, i32 immarg)
declare <16 x i8> @llvm.ppc.xxssumudmcext(<16 x i8>, <16 x i8>, <16 x i8>, i32 immarg)
declare <16 x i8> @llvm.ppc.xsaddadduqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsaddaddsuqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsaddsubuqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsaddsubsuqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsmerge2t1uqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsmerge2t2uqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsmerge2t3uqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsmerge3t1uqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsrebase2t1uqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsrebase2t2uqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsrebase2t3uqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsrebase2t4uqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsrebase3t1uqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsrebase3t2uqm(<16 x i8>, <16 x i8>)
declare <16 x i8> @llvm.ppc.xsrebase3t3uqm(<16 x i8>, <16 x i8>)

define <16 x i8> @test_xxmulmul(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xxmulmul:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xxmulmul vs34, vs34, vs35, 3
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xxmulmul(<16 x i8> %a, <16 x i8> %b, i32 3)
  ret <16 x i8> %res
}

define <16 x i8> @test_xxmulmulhiadd(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xxmulmulhiadd:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xxmulmulhiadd vs34, vs34, vs35, 0, 1, 0
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xxmulmulhiadd(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, i32 0)
  ret <16 x i8> %res
}

define <16 x i8> @test_xxmulmulloadd(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xxmulmulloadd:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xxmulmulloadd vs34, vs34, vs35, 1, 0
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xxmulmulloadd(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0)
  ret <16 x i8> %res
}

define <16 x i8> @test_xxssumudm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xxssumudm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xxssumudm vs34, vs34, vs35, 1
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xxssumudm(<16 x i8> %a, <16 x i8> %b, i32 1)
  ret <16 x i8> %res
}

define <16 x i8> @test_xxssumudmc(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xxssumudmc:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xxssumudmc vs34, vs34, vs35, 0
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xxssumudmc(<16 x i8> %a, <16 x i8> %b, i32 0)
  ret <16 x i8> %res
}

define <16 x i8> @test_xxssumudmcext(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) {
; CHECK-LABEL: test_xxssumudmcext:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xxssumudmcext vs34, vs34, vs35, vs36, 1
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xxssumudmcext(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c, i32 1)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsaddadduqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsaddadduqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsaddadduqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsaddadduqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsaddaddsuqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsaddaddsuqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsaddaddsuqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsaddaddsuqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsaddsubuqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsaddsubuqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsaddsubuqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsaddsubuqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsaddsubsuqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsaddsubsuqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsaddsubsuqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsaddsubsuqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsmerge2t1uqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsmerge2t1uqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsmerge2t1uqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsmerge2t1uqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsmerge2t2uqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsmerge2t2uqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsmerge2t2uqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsmerge2t2uqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsmerge2t3uqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsmerge2t3uqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsmerge2t3uqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsmerge2t3uqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsmerge3t1uqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsmerge3t1uqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsmerge3t1uqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsmerge3t1uqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsrebase2t1uqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsrebase2t1uqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsrebase2t1uqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsrebase2t1uqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsrebase2t2uqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsrebase2t2uqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsrebase2t2uqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsrebase2t2uqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsrebase2t3uqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsrebase2t3uqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsrebase2t3uqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsrebase2t3uqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsrebase2t4uqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsrebase2t4uqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsrebase2t4uqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsrebase2t4uqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsrebase3t1uqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsrebase3t1uqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsrebase3t1uqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsrebase3t1uqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsrebase3t2uqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsrebase3t2uqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsrebase3t2uqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsrebase3t2uqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}

define <16 x i8> @test_xsrebase3t3uqm(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: test_xsrebase3t3uqm:
; CHECK:       # %bb.0:
; CHECK-NEXT:    xsrebase3t3uqm vs34, vs34, vs35
; CHECK-NEXT:    blr
  %res = call <16 x i8> @llvm.ppc.xsrebase3t3uqm(<16 x i8> %a, <16 x i8> %b)
  ret <16 x i8> %res
}