# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple arm-- -mattr=+v6 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

---
name:            get_inverted
legalized:       true
regBankSelected: true
selected:        false
tracksRegLiveness: true
registers:
  - { id: 0, class: gprb }
body:             |
  bb.0:
    liveins: $r0
    ; CHECK-LABEL: name: get_inverted
    ; CHECK: liveins: $r0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[MVNi:%[0-9]+]]:gpr = MVNi 0, 14 /* CC::al */, $noreg, $noreg
    ; CHECK-NEXT: $r0 = COPY [[MVNi]]
    ; CHECK-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0
    %0:gprb(s32) = G_CONSTANT i32 -1
    $r0 = COPY %0(s32)
    MOVPCLR 14 /* CC::al */, $noreg, implicit $r0

...